Академический Документы
Профессиональный Документы
Культура Документы
) 7 , 0 ( ) 6 , 3 , 2 (
, , , , Z Y X Z Y X
d F
15
14. For the Karnaugh map given in Figure 10, provide a minimum logic expression using groupings of maxterms.
Clearly show the groupings that you make.
A B
C D
d d
d
d
d
1
0 d 0
0 0 0
0
1
1 1
00
00
01 11 10
01
11
10
Figure 10 Karnaugh map
16
15. Expand the following Boolean expressions to both Canonical Sum-of-Products and Product-of-Sums forms.
Indicate clearly which expression is SOP and which one is POS.
f y x y z
17
16. Design a clocked synchronous state machine with the state/output table shown in Table 3, using D flip-flops.
Use two state variables, Q1 Q0 (where Q1 is the MSB), with the state assignment A=00, B=01, C=11, D=10 (that is
for D your state variables will be Q1 = 1 and Q0 = 0). Draw and label the designed circuit. Explain the steps you
take.
Table 3 State/output table
18
17. Given the excitation/output table in Table 4, derive the sum-of-products excitation equation for J2.
Table 4 Excitation/output table
19
18. Draw a 2-input gate, with a data input and a control input, which passes complemented data when the
control input is logic zero. Write down the truth-table for this gate. What is the name of the gate you have
drawn?
20
19. Prove the following equality:
W Y X X W Y X Y X ) ( ) (
Use the theorems of Boolean algebra listed below. At each step of your derivation state which theorem you are
using.
21
20. Prove the following theorem:
T10: ( ) ( ) X Y X Y X
Use the following theorems in your proof:
Distributivity theorem (T8): ( ) ( ) X Y X Z X Y Z ;
Complement theorem (T5): 0 X X ;
Identity theorem (T1): 0 X X .
Show and explain your work.
22
21. Prove the dual of theorem T10 from problem 20 using the duals of theorems T8, T5 and T1. Use the
Principle of Duality.
Principle of Duality: Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and
and + are swapped throughout.
Show and explain your work.
23
22. Prove the following theorem:
T1: X Y X Y X
Use the following theorems in your proof:
Distributivity theorem: X Y X Z X Y Z
Complements theorem: 1 X X
Show and explain your work.
24
23. Prove DeMorgans theorems using finite induction.
DeMorgans theorems:
DMT:
1 2 1 2
( )
n n
X X X X X X
DMT:
1 2 1 2
( )
n n
X X X X X X
25
24. Prove the following Shannons expansion theorem:
T15:
1 2 1 2 1 2
( , , , ) (1, , , ) (0, , , )
n n n
F X X X X F X X X F X X
Show and explain your work.
26
25. Prove that a twos complement number can be converted to a representation with more bits by sign
extension. That is, given an n-bit twos complement number X, show that the m-bit twos complement
representation of X, where m>n, can be obtained by appending m-n copies of Xs sign bit to the left of the n-
bit representation of X. Use the following formula in your derivation:
M
m
M
m
a
a
a
0
1
1
1
(Hint: Start by writing down the expressions for the values of X and Y. Continue by rewriting the value of X as a
function of Y (this may take a few steps). Finally, look at when the equation X = Y will hold.)
27
26. All the numbers below are unsigned. Perform the required conversions showing all your work.
a) (1 point) 0.5
10
= ?
2
b) (2 points) 34
10
= ?
2
c) (2 points) F1.2
16
= ?
10
(NOTE: 1/16 = 0.0625)
d) (2 points) 100.11
2
= ?
16
(Hint: remember the trick to convert between base-2 and base-16 numbers. You
have to group a certain number of the base-2 numbers)
28
27. The figure below shows four 27256 ROM devices connected to a three-state bus. The devices have chip-
select (CS) inputs as well as output-enable (OE) inputs, both of which must be asserted to enable the
outputs.
a) (5 points) How many 8-bit words (bytes) can each 27256 hold? (We know that the devices hold 8-bit words by
looking at the number of data outputs 8.)
b) (5 points) What is the size of the memory space of the microprocessor? (Hint: how many address lines are
there?)
c) (10 points) The memory map of the circuit is shown in Figure 13 on the following page. The memory map has
to indicate which addresses will access a given device. Complete the memory map by indicating where in this
memory space the four ROM devices (U2, U3, U4, and U5) are located. On the lines indicate the first address
that will access a given device. Use hexadecimal numbers. To determine the location of the ROM devices in
the memory map look at what address lines have to be active for a given ROM to be selected (use the truth table
for the 74x139 in Figure 12). Assume that A19 is the MSB of the address bus. Two addresses are shown in
Figure 13: 00000
16
, which is accessed when all of the microprocessors address lines are 0, and FFFFF
16
, which
is accessed when all address lines are 1. Note that FFFFF
16
is the last location in the memory space and that it
accesses U5.
Figure 11 Address decoding and ROM enabling in a microprocessor system
29
Figure 12 74x139 logic symbol and truth table
U5
U4
U3
U2
00000
16
FFFFF
16
Figure 13 Memory map
30
28. You are a Mayan first grade teacher. You are teaching your students addition. You assign the following
equation as a homework assignment.
+ = ?
One of your students submits the following work.
+ =
Is the students solution for the equation correct? If it is not, make the necessary correction(s). Explain your
answer and include the decimal version of the solution for the equation.
Hint: The Maya used a positional number system. The radix of their system was 20. They denoted numbers
using dots and bars. Each dot had a value of one and each bar had a value of five. The Maya also had a
symbol for zero: . The Maya wrote numbers in columns. The bottom position in a column was the least
significant position.
31
29. Figure 14 shows the logic symbol and state table for the 74x163 4-bit binary counter. Using this counter
and any gates of your choosing design a modulo-8 counter with the counting sequence
5,6,7,8,9,10,11,12,5,6, Explain the operation of your circuit in words.
Figure 14 74x163 logic symbol and state table
32
30. An n-bit shift register with the complement of the serial output fed back into the serial input is a counter
with 2n states and is called a twisted-ring, Moebius, or Johnson counter.
a) Using a 74x194 universal shift register and any number of external gates implement a simple 4-bit Johnson
counter. Your counter should not be self-correcting. Give a word explanation of the operation of your circuit.
b) Include a timing diagram showing the CLK, CLR, QD, QC, QB, and QA lines. Assume that the contents of the
74x194 are cleared by pulling the CLR line low and then setting it high at the beginning of your timing diagram.
c) Design a 4-bit self-correcting Johnson counter. In order to be self-correcting your circuit should load 0001 as
the next state whenever the current state is 0xx0. Give a word explanation of the operation of your circuit.
d) Draw the state diagram of the circuit to show that the circuit is indeed self-correcting. Give a short word
explanation of the state diagram and why it proves that the circuit is self-correcting. Note that there are 2
4
= 16
states in the state diagram.
Figure 15 Logic symbol for the 74x194 4-bit universal shift register
Table 5 Function table for the 74x194 4-bit universal shift register
33
31. The circuit shown in Figure 16 is a 3-bit counter with outputs Q1, Q2, and Q3. What is the counter output
sequence assuming an initial system clear? Provide your answer in .
CLK
Q3
Q3
D3
CLR
Q2
Q2
D2
CLR
Q1
Q1
D1
CLR
System
Clear
Count
Output
MSB
LSB
Figure 16 3-bit counter circuit
Clock Pulse
Counter Output
Q3 Q2 Q1
0 0 0 0
1
2
3
4
5
6
7
8
9
10
Table 6 Fill in the table with the counter output sequence
34
32. For the circuit given in question 31 complete the timing diagram in Figure 17 for a single complete counter
sequence. Cover as many clock cycles as necessary for the counter sequence to repeat.
CLK
Q
1
Q
2
Q
3
Figure 17 Complete the timing diagram
35
33. Obtain the timing diagram for the sequential circuit shown in Figure 18 for at least six clock cycles. Assume an
initial condition state of Q1Q2=00 for the flip-flop pair. The characteristic equation of the edge-triggered J-K
flip-flops used in the circuit is Q* = JQ + KQ.
CLK
J
K
Q1
Q1
J
K
Q2
Q2
CLK
Q
1
Q
2
Figure 18 Circuit diagram (top) and timing diagram to be filled in (bottom)
36
34. Assuming an initial condition of Q3Q2Q1 = 000 for the three flip flops, produce the state table for the counter
circuit shown below. Note: The MSB of the counter is Q3. The characteristic equation of the edge-triggered J-K
flip-flops used in the circuit is Q* = JQ + KQ.
CLK
J
K
Q1
Q1
J
K
Q2
Q2
J
K
Q3
Q3
+5V
37
35. Given the block diagram in Figure 19, draw the connections necessary to implement the shift right function and
a parallel load of data. Be sure to label the four blank boxes with the proper device name.
Clock
Q3
Q3
D3 Q2
Q2
D2 Q1
Q1
D1 Q4
Q4
D4
Input 0 Input 1 Input 2 Input 3
Shift Input
Load
or
Shift Right
Shift
Output
Figure 19 Complete the block diagram to implement the shift right and parallel load functions
38
36. One method to derive an n-bit Gray code is to write down the n-bit binary code and follow the steps below:
a) The bits of an n-bit binary or Gray-code code word are numbered from right to left, from 0 to n - 1.
b) Bit i of a Gray-code code word is 0 if bits i and i+1 of the corresponding binary code word are the same, else bit
i is 1. (When i + 1 = n, bit n of the binary code word is considered to be 0.)
Using this method complete Table 7.
Decimal number Binary code Gray code
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Table 7 Gray code