98

CIRCUIT DIAGRAM:
CALCULATIONS:
CURRENT LAW:
Ie=Il1+Il2

VOLTAGE LAW:
VS=VD1+VD2

V
+
(0-15)V
1k
A
+
(
0
-
1
0
0
)
m
A
0- 30V
A
+
(0-100)mA
A
+
(0-100)mA
V
+
(0-15)V
560 220
98
VERIFICATION OF KIRCHOFF S LAW
AIM:
To verify the kirchoffs current law and kirchoffs voltage law.
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1. Volteter !"#2$%V 2
2. &eter !"#2$%& '
'. (esistors 22")*$+")*1,) -ach 1
.. (egulated /ower su//ly !"#'"%V D0 1
STATEMENT:
KIRCHOFFS CURRENT LAW:
The su of the current flowing towards the 1unction is e2ual to the su of
the current leaving away fro the 1unction.
I
t =
3I
1
KIRCHOFFS VOLTAGE LAW:
In a closed circuit the su of the /otential dro/ is e2ual to the su of the
/otential rise.
VS=VD1+VD2
TAULAR COLOUMN:1:
98
S.NO SOURCE
VOLTAGE
ENTERING
CURRENT
LEAVING
CURRENT
DROP
VOLTAGE
LEAVING
CURRENT
DROP
VOLTAGE
!"#$ V% &'( I) &*A( I+1 &*A( V,1 &'( I+2 &*A( V,2 &'(
1.
2.
'.
..
$.
TAULAR COLOUMN:2
KIRCHOFFS LAW
CURRENTLAW VOLTAGE LAW
I
e
I
l1
+I
l2
V
S
V
D1
+V
D2
98
PROCEDURE:
1.0onnections are given as /er the circuit diagra.
2.The circuit is given to the circuit.
'.The readings of the aeter and volteter are noted various value of the su//ly.
..4inal readings are ta5ulated.
$.Verification of ,06 is done.
+.Verification of ,V6 is done.
98
RESULT:
Thus the kirchoff s law is verified.
CIRCUIT DIAGRAM:
TO FIND VTH 7
TO FIND RTH7
TO FIND I
L
:
0- 30V 330
100 220
V
+
(
0
-
2
5
)
V
560

3
3
0

100 220
R
T
H
98
VERIFICATION OF THEVININS THEOREM
AIM:
To verify the Thevinins theore for the circuit.
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1 Volteter !"#2$%V 1
2 &eter !"#1""%& 1
' (esistors 22")*$+")*''")*1"") -ach 1
. (egulated /ower su//ly !"#'"%V 1
$ 8ultieter 9999999 1
STATEMENT:
& linear 5ilateral electric circuit which contains one or ore voltage source can 5e
re/laced 5y single voltage resistance and series resistance and voltage is called thevinins
resistance or 5ase resistance .
FORMULA:
V
6
=V
T:
;!(
T:
+(
6
% in Volts
0- 30V

3
3
0

100 220
A
+
(0-100)mA
98
TAULAR COLUMN:
S.NO
RESISTANCE
OPEN
CIRCUIT
VOLTAGE
&VTH(
THVININS
RESISTANCE
&RTH(
-
LOAD
CURRENT
&IL(
*A
R1 R2 R. RL
1.
T:-<(ITI0&6
V&6=- 22") 1"") ''") $+")
2.
>(&0TI0&6
V&6=-
MODEL CALCULATIONS 7
TO FIND RTH7
(
T:
= !(
1
9(
2
;(
1
+(
2
%+(
'
)
TO FIND V
TH
:
V
T:
=V
<0
98
V
<0
=V<6T&?- &0(<SS (
'
V
dro/
(
'
=V
1
9(
'
;!(
1
+(
'
%V
TO FIND I
L
:
I
6
=V
T:
;!(
T:
+(
6
%&
PROCEDURE:
1.0onnections are given as /er the circuit diagra.
2.The su//ly is given to the circuit.
'.Thvinins voltage VT: is easured.
..Thevinins resistance (T: is easured.
$.The load current I6 is easured.
+. &ll the readings are noted.

98
RESULT:
Thus the Thevinins theore is verified.
CIRCUIT DIAGRAM:
TO FIND I
SC
:
TO FIND R
TH
:
I
S
C
+
(0-30)V
COMPLETE
ACTIVE
NETWORK
0- 30V

3
3
0

100 220
A
+
(0-100)mA
98
VERIFICATION OF THE NORTONS THEOREM
AIM:
To verify the @ortons theore for the given circuit.
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1. &eter !"#1""%& 1
2. (esistors 22")*$+")*1"")*''") -ach 1
'. (egulated /ower su//ly !"#'"%V D0 1
.. 8ulti eter 999999 1
$. Aread 5oard 999999 1


3
3
0

100 220
R
T
H
98
STATEMENT:
& linear 5ilateral active network which contains one or ore voltage source or current
source can 5e re/laced 5y the single current source and a /arallel resistance. This current source
is called short circuit current source and resistance is called thevinins resistance or 5ase
resistance.
FORMULA:
I
6
=!I
S09
(
T:
%;!(
T:
+(
6
%
TO FIND I
L
:
TAULARCOLUMN:
RESISTANCES
SHORT
CIRCUIT
CURRENT
&ISC( *A
THEVININS
RESISTANCE
&VTH( -
LOAD
CURRENT
&IL( *A
R1 R2 R. RL
0- 30V 330
100 220
A
+
(
0
-
1
0
0
)
m
A
560
98
T:-<(ITI0&6
V&6=- 22") 1"") ''") $+")
>(&0TI0&6
V&6=-
PROCEDURE:
1.0onnections are given as /er the circuit diagra.
2.The su//ly is given to the circuit.
'.Short circuit!Isc%is easured.
..Thevinins resistance !(T:%is easured.
$.The load current !I6% is easured.
+.&ll the readings are ta5ulated.

98
MODEL CALCULATIONS 7
TO FIND RTH:
(
T:
= !(
1
9(
2
;(
1
+(
2
%+(
'
)

(
T:
=(
@
TO FIND ISC:
I
SC
=V
TH
/R
TH
*A
TO FIND IL:
98
I
L
=&I
SC0
R
TH
(/&R
TH
+R
L
( *A

98
RESULT:
Thus the @ortons theore is verified.
CIRCUIT DIAGRAM:
CASE 1:
CASE 2:
560

3
3
0

220
A
+
(0-100)mA
V
+
(0-30)V
V
+
(0-30)V
0- 30V
0- 30V
98
VERIFICATION OF SUPER POSITION THEOREM
AIM:
To verify the Su/er >osition Theore for the given circuit..
APPARATUS REQUIRED:
S.NO NAMES RANGE QUANTITY
1. &eter !"#1""%& 1
2. (esistors 22")*''")*1"")*$+") -ach 1
560

3
3
0

220
A
+
(0-100)mA
V
+
(0-30)V
0- 30V
98

'. (egulated /ower su//ly !"#'"%V D0 2
..

Aread 5oard 9999999 1
STATEMENT:
& linear 5ilateral electric circuit which is energiBed 5y one or ore sources the
current at any /oint is e2ual to alge5raic su of the all the /oints. when each source are
re/laced 5y the internal resistance.
FORMULA:
I
6
=I
61
+I
62
in a/s
CASE .:
98
CASE 1:
1.0onnections are ade as /er the circuit diagra.
2.The su//ly is given to the circuit.
'.Then the voltage sourcesVS1*VS2 and corres/onding aeter readings
560

3
3
0

220
A
+
(0-100)mA
0- 30V
V
+
(0-30)V
98
are noted.
..The reading VS1*VS2and I6 are ta5ulated.



.
TAULAR COLUMN:
CASE:1
98
S.NO VOLTAGE SOURCE&VS1(
V1+$%
VOLTAGE
SOURCE&VS2( V1+$%
LOAD CURRENT&IL(
*A
CASE2:
S.NO VOLTAGE SOURCE
&VS1( V1+$%
LOAD CURRENT&IL1(
*A
98
CASE 2:
1.0onnections are ade as /er the circuit diagra.
2.The su//ly is given to the circuit
'.Then the voltage sourcesVS1 and corres/onding aeter readings
are noted.
..The reading VS1* and I61 are ta5ulated.
CASE .:
S.NO VOLTAGE SOURCE LOAD
CURRENT&I
L2
( *A
98
&V
S2
( V1+$%
VERIFICATION:
S.@< I
6
I
61
+I
62
CASE.:
98
1.0onnections are ade as /er the circuit diagra.
2.The su//ly is given to the circuit
'.Then the voltage sourcesVS2 and corres/onding aeter readings
are noted.
..The reading VS2* and I62 are ta5ulated
RESULT:
Thus the Su/er >osition Theore is verified.
CIRCUIT DIAGRAM:
98
TO FIND VTH :
TO FIND RTH7
VERIFICATION OF MA2IMUM POWER TRANSFER THEOREM
AIM:
560 470

5
6
0

V
+
(0-30)V
0- 30V
R
L

5
6
0

470 560
R
T
H
98
To easure the /ower a5sor5ed in a lead and to verify that the /ower a5sor5ed in
a load is aCiu only when load resistance is e2ual to the source resistance .
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1. Volteter !"#2$%V 1
2. &eter !"#1""%& 1
'. (esistance $+")*.D") 2
.. (egulated /ower su//ly !"#'"%V D0 1
$. Decade resistance 5oC 99999 1
THEORY:
The aCiu /ower transfer theore states that a load will receive aCiu /ower
for a linear 5ilateral D0 network when its total to the thevinins resistance of the network as
seen 5y the load. 4ro the network in fig!a% aCiu /ower will 5e delivered to the load when
(6=(th.
In the si/le for the circuit ay contain the voltage source Vs having the internal
resistance (" and connected across the load (6 to find /ower.
The aCiu /ower transfer theore tell us that the load should 5e e2ual in
agnitude to the source resistance for aCiu /ower to 5e a5sor5ed 5y the load.
TO FIND IL:
98
MODEL GRAPH:
R
L
0- 30V

5
6
0

470 560
V
+
(0-30)V
A
+
(0-25)mA
PMAX
6<&D (-SIST&@0-
POWER
98
PROCEDURE:
1. 8ake the connections as /er the circuit diagra.
2. Select at least five resistance (6 two of the having values less than (T: two having the
values higher than (T: and one having the values e2ual (T: ).
'. 0hange the resistance (6 one 5y one easure corres/onding V6*I6 and calculate the >6
and enter into the ta5le.
.. >lot the gra/h 5etween (6 and >6 and find the (6 corres/ondingthe aCiu /ower
$. Verified the easure values of (6 at a aCiu /ower transfer as sae as calculated
and found gra/hically.
TAULAR COLUMN:
98
CALCULATED VALUES:
S.NO
LOAD
RESISTANCE
&RL( -
LOAD
CURRENT &IL(
*A
LOAD
VOLTAGE &VL(
V
LOAD POWER
&PL( W3$$%
MEASURED VALUES:
S.NO LOAD
RESISTANCE
&R
L
( -
LOAD
CURRENT
&I
L
( *A
LOAD
VOLTAGE
&V
L
( V
LOAD
POWER &P
L
(
W3$$%
98
RESULT:
Thus aCiu /ower transfer theore was verified theoretically E /ractically.
CIRCUIT DIAGRAM:
98
+
V
R
1
R
1
A
+
ELECTRICAL
NETWORK
REVERSE
NETWORK
CASE 1:
VERIFICATION OF RECIPROCITY THEOREM
220 330 560 (0-30)V
A
+
(0-100)mA
98
AIM
To verify the reci/rocity theore for the given circuit.
EQUIPMENT REQUIRED
NAME RANGE QUANTITY
&eter
(esistors
(egulated
>ower
Su//ly
!"#1""%&
22")*''")
!"#'"%V
1 @os
-ach 1 @o
1 @o

STATEMENT
& linear 5ilateral network at a voltage V1 source in a 5ranch give rise in
current I. In another 5ranch ratio V;( is constant when the /osition of V and I are interchanged.
CASE 2:
98
TAULATION :
CASE &#(
S.NO VOLTAGE &VOLTS V( CURRENT &I( *A
PROCEDURE
1. 0onnections are ade as /er the circuit diagra.
220 330 560
(0-30)V
A
+
(0-100)mA
98
2. The su//ly is given to the circuit.
'. The circuit current I is easured fro the aeter readings.
CASE &##(
S.NO VOLTAGE &VOLTS V( CURRENT &I( *A
98
98
RESULT:
Thus the (eci/rocity theore is verified.
98
CIRCUIT DIAGRAM:
+
2V 1k
V
+
(0-5)V
1u
50m
MODEL GRAPH:
FREQUENCY RESONANCE IN RLC SERIES CIRCUIT
98
AIM:
To o5tain the resonance fre2uency of the given (60 Series electrical network.
APPARATUS REQUIRED:
S.@< 0<8><@-@TS TF>- &@D (&@?- G=&@TITF
1
2
'
.
$
+
4unction re2uired
(esistor
Decade Inductance 5oC
0a/acitor
Volteter
Aread Aoard E Hires
!"#'"%V
1 k)
$"
1 I4
80!"#$%V
99999999
1 @o
1 @o
1 @o
1 @o
1 @o
1 @o
THEORY:
&n a.c. circuit is said to 5e in resonance when the a//lied voltage and the
resulting current are in /hase. In an (60 Series circuit under the resonance J6=J0 where J6 is
inductive reactance and J0 is ca/acitive reactance &t to V0 and V6 are e2ual in agnitude and
o//osite in /hase.
The aCiu value of V6 occurs at a fre2uency lesser than 4o and the aCiu
value of V6 occurs at a 4re2uency greater than 4o
ANDWIDTH:
The distance 5etween the lower half /ower fre2uency 41 and the u//er half /ower
fre2uency 42 is called 5andwidth of the circuit.
98
OSERVATION:
S.NO FREQUENCY
KH4
VR
VOLTS
FORMULA :
98
Series resonance fre2uency *
FO=1/25LC
PROCEDURE:
0onnections are ade as /er the diagra.
Vary the fre2uency of the function generator.
8easure the corres/onding values of voltage * across (1 (esistor for Series (60 circuit.
(e/eat the sae /rocedure for different values of fre2uency.
Ta5ulate your o5servation.
@ote down the resonance fre2uency fro the ta5le.
RESULT:
Thus the resonance fre2uency of the electrical network is o5tained.
CIRCUIT DIAGRAM:
98
+
2V 1k
V
+
(0-5)V
1u

1
m
R
C
L
MODEL GRAPH:
]
FREQUENCY RESONANCE IN RLC PARALLEL CIRCUIT
98
AIM:
To o5tain the resonance fre2uency of the given (60 /arallel electrical network.
APPARATUS REQUIRED:
S.NO COMPONENTS TYPE AND RANGE QUANTITY
1
2
'
.
$
+
4unction re2uired
(esistor
Decade Inductance 5oC
0a/acitor
Volteter
Aread Aoard E Hires
!"#'"%V
1 k)
1
1 I4
80 !"#$%V
99999999999
1 @o
1 @o
1 @o
1 @o
1 @o
1 @o
THEORY:
&n a.c. circuit is said to 5e in resonance when the a//lied voltage and the
resulting current are in /hase. In an (60 Series circuit and /arallel circuit at resonance K=(*
J6=J0 where J6 is inductive reactance and J0 is ca/acitive reactance.
The difference 5etween the lower half /ower fre2uency 41 and the u//er half
/ower fre2uency 42 is called 5andwidth of the circuit.
PARALLEL:
The fre2uency at which the current in the /arallel (60 circuit is aCiu is
known as 4re2uency !4<%.
FO =1/25LC
&t 4< * Va and V6 are e2ual in agnitude and o//osite in /hase.
E2PERIMENTAL VALUE:
98
S.NO FREQUENCY
KH4
VR
VOLTS
THEORITICAL CALCULATIONS
PARALLEL
F
O
=1/25LC
FORMULA :
98
Series resonance fre2uency 6
FO =1/25LC
PROCEDURE:
0onnections are ade as /er the diagra.
Vary the fre2uency of the function generator.
8easure the corres/onding values of voltage * across (1 (esistor for Series (60 circuit
and /arallel circuit.
(e/eat the sae /rocedure for different values of fre2uency.
Ta5ulate your o5servation.
@ote down the resonance fre2uency fro the ta5le.
RESULT:
Thus the resonance fre2uency of (60 >arallel electrical network is o5tained.
98
CIRCUIT DIAGRAM
FORWARD IAS
REVERSE IAS
!22"
V
+
(0-10)V
A
+
(0-25)mA

1
k
0- 10V
CHARACTERISTICS OF PN 7UNCTION DIODE
98
AIM:
To study the characteristics of a >@ Lunction diode is forward and reverse 5ias and /lot
the gra/h.
COMPONENETS REQUIRED :
S.NO NAME RANGE QUANTITY
1
2
'
.
$
+
(egulated >ower Su//ly
Diode
Volteter
&eter
(esistor
Aread Aoard
&nd wires
!"#'"%v
I@.""D
!"#2"%v
!"#2$%&
!"#$""%&
1k)
##########
1 @<
1 @<
1 @<
1 @<
1 @<
##########
SYMOL
98

TAULATION:
FORWARD IAS
S.NO V#"

&V(
VF
&V(
IF
&*A(
IN 4007
A k
98
THEORY
Hhen a /#ty/e and n#ty/e seiconductor are 1oined a >@ Lunction diode is fored. & diode
in a two terinal * in 1unction device. It is directional which eans it conducts current in only
one direction. The current that flows under 5ias condition is called drift current. Drift current is a
/rocess in which the changes carries ore over one region to another due to a//lied voltage.
PROCEDURE
FORWARD IAS
Identify the anode and cathode ends of the diode and connect the circuit.
(ise the D0 >ower su//ly Voltage fro " to 1 V in ste/ ".1 V* therefore fro 1V to 1"V
in ste/ of 1V.
8easure and record the values of forward voltage V4 and forward current I4.
>lot the VI gra/h using the ta5ulated values.
REVERSE IAS
98
S.NO V#"
&V(
VR
&V(
IR
&*A(
MODEL GRAPH:
IF
CUT IN
VOLTAGE
VF
VR
IR
VBR
98
REVERSE IAS
(everse the anode and cathode ends of the diode and connect the circuits as shown in
the circuit diagra.
Vary the D0 >ower su//ly* voltage " to 1"V in ste/ of 1V Voltage easure and
record the values for V( and easure the reverse current I(.
>lot the VI gra/h using the ta5ulated values.
RESULT:
The forward and the reverse 5ias characteristics of >@ Lunction diode as studied
and gra/h is /lotted.

CIRCUIT DIAGRAM:
98
FORWARD IAS:
A
+
(0-25)mA
0- 10V
1k

1
N
2
"
0
4
V
+
(
0
-
1
0
)
V
REVERSE IAS:
A
+
(0-25)mA
0- 10V
1k

1
N
2
"
0
4
V
+
(
0
-
1
0
)
V
98
CHARACTERISTICS OF 4ENER DIODE
AIM:
To study the characteristics of a Kener diode is forward and reverse 5ias and /lot the
gra/h.
COMPONENETS REQUIRED:
S.NO NAME RANGE QUANTITY
1
2
.
8
9
:
R);!+3$), P1<)= S!>>+?
D#1,)
V1+$*)$)=
A**)$)=
R)%#%$1=
=)3, 13=,
A", <#=)%
&@A.@('
F4 9.1
&@A1@('
&@A29(*A
1B-
000000
1 NO
1 NO
1 NO
1 NO
1 NO
000000
98
SYMOL:

TAULATION:
FORWARD IAS
S.NO V#"
&V(
VF
&V(
IF
&*A(
THEORY
FZ 5.1
98
Kener diode is a s/ecially do/ed seiconductor diode to o/erate in the reverse 5reakdown
region. Hhen the Kener diode is forward 5iased* its characteristics is siilar to >@ Lunction
diode . Hhen the diode is reverse 5iased * a sall reversed current flows and reains constant
until the Kener 5reakdown region is reached . Thereafter the current increases ra/idly and the
voltage reains constant. Kener diode with reverse 5reakdown voltage of 'V and u/wards the
availa5le for coercial use.
PROCEDURE
FORWARD IAS
Identify the anode and cathode ends of the Kener diode and connect the circuit as shown
in the circuit diagra.
(ise the D0 >ower su//ly Voltage fro " to 1 V in ste/ ".1 V* thereafter fro 1V to 1"V
in ste/ of 1V.8easure and record the values of forward voltage V4 and forward current I4.
>lot the VI gra/h using the ta5ulated values.
MODEL GRAPH:
IF
98
REVERSE IAS
S.NO V#"
&V(
VR
&V(
IR
&*A(
CUT IN
VOLTAGE
VF
VR
IR
VBR
98
REVERSE IAS
(everse the anode and cathode ends of the diode and connect the circuits as shown in
the circuit diagra.
(ise the D0 >ower su//ly* voltage " to 1$V in ste/ of 1V. 8easure and record the
values of V( and I(.
>lot the VI gra/h using the ta5ulated values.
RESULT
The forward and the reverse 5ias characteristics of Kener diode as studied and gra/h is
/lotted.
SYMOL: TRANSISTOR:
98

CIRCUIT DIAGRAM:
CHARACTERISTICS OF COMMON EMITTER CONFIGURATION
V
+
(0-30)V
A
+
A
+
1k
V
+
C107
(0-30)V
(0-10)V
(0-500)#A
(0-100)mA
1k
(0-30)V

E
C
98
AIM:
To draw the in/ut and out/ut characteristics of the given transfer
COMPONENTS REQUIRED:
S.NO N3*) R3";) Q!3"$#$?
1 Transistor A01"D 1
2 (esistor 1kM 1
' Volteter !"#'"%V 2
. &eter !"#1""%&*!"#
$""%I&
-ach 1
$ (>S !"#'"%V 2
+ Aread 5oard # 1
D 0onnecting wires # &s re2uired
TC)1=?:
& transistor is a ' terinal device consisting of 1 N@ region sandwiched 5etween 2 N>
regions called @>@. It consists of 2 1unctions and the terinals naely eitter * 5ase * collector.
4or a noral o/eration of a transistor the collector #5ase region is reverse 5iased and the
5ase#eitter should 5e forward 5iased.
I">!$ DC3=3D$)=#%$#D%
The in/ut characteristics of a transistor ay 5e o5tained 5y /lotting 5ase# eitter
voltage VA- versus 5ase current IA kee/ing V0- constant. The characteristics curves are /lotted for
various values of collector to eitter voltage V0A .Threshold cut in voltage V@ 5elow which the IA
is very sall .The value of cut#in voltage is ".+v for Si.
O!$>!$ DC3=3D$)=#%$#D%:
The out/ut characteristic of a transistor ay 5e o5tained 5y /lotting V0- versus I0
for different values of IA.I0 varies with V0A initially* 5ut there after 5ecoes alost constant and
reaches saturation value. The transistor are o/erated in the region knee voltage. This region is
called as the &ctive region.
98
INPUT CHARACTERISTICS
TAULATION:
S.NO
VCE =9V VCE=1@V
VE&V( I&EA( VE&V( I&EA(
MODEL GRAPH:
I
B
(A)
V
BE
(V)
V
CE
=!V
V
CE
=!V
98
PROCEDURE:
I">!$ DC3=3D$)=#%$#D%:
0onnections are given as /er the circuit diagra
,ee/ing the V0- constant and varying V-A in the set of ".1V and IA is
noted
The /rocedure is re/eated for different values of V0- and gra/h is /lotted
98
OUTPUT CHARACTERISTICS:
TAULATION:
S.NO
I =1@EA I=2@EA
VCE&V( IC&*A( VCE&V( IC&*A(
MODEL GRAPH:
I
B
=5!A
V
CE
( V )
I
C
("A)
I
B
=1!!A
I
B
=#!A
98
O!$>!$ DC3=3D$)=#%$#D%:
0onnections are given as /er the circuit diagra
,ee/ing the IA constant and varying V0- and I0 is noted
The /rocedure is re/eated for different values of IA and gra/h is /lotted
R)%!+$:
Thus the in/ut and the out/ut characteristics of 0oon -itter Transistor is studied
and the gra/h is /lotted.
98
PIN DIAGRAM: SYMOL:
CIRCUIT DIAGRAM:
(0-30)V
V
+
(0-30)V
A
+
A
+
1k
V
+
C107
(0-30)V
(0-30)V
(0-10mA
(0-10mA
1k
98
CHARACTERISTICS OF COMMON ASE CONFIGURATION
AIM:
To draw the in/ut and out/ut characteristics of the given transfer
COMPONENTS REQUIRED :
S.NO N3*) R3";) Q!3"$#$?
1 Transistor A01"D 1
2 (esistor 1kM 1
' Volteter !"#'"%V 2
. &eter !"#1"%& 2
$ (>S !"#'"%V 2
+ Aread 5oard # 1
D 0onnecting wires # &s re2uired
THEORY:
& transistor is a ' terinal device consisting of 1 N@ region sandwiched 5etween 2 N>
regions called @>@. It consists of 2 1unctions and the terinals naely eitter * 5ase * collector.
4or a noral o/eration of a transistor the collector #5ase region is reverse 5iased and the
5ase#eitter should 5e forward 5iased
I">!$ DC3=3D$)=#%$#D%:
The in/ut characteristics of a transistor ay 5e o5tained 5y /lotting 5ase# eitter voltage
VA- versus eitter current I- kee/ing V0A constant. The characteristics curves are /lotted for
various values of collector to 5ase voltage V0A .
O!$>!$ DC3=3D$)=#%$#D%:
The out/ut characteristic of a transistor ay 5e o5tained 5y /lotting V0A versus I0 for
different values of I-.I0 varies with V0A initially* 5ut there after 5ecoes alost constant and
reaches saturation value. The transistor are o/erated in the region knee voltage. This region is
called as the &ctive region
To deterine the out/ut characteristics I- is ke/t constant and the gra/h is /lotted
5etween V0A and I0 .
98
INPUT CHARACTERISTICS
TAULATION:
S.NO
VC =1@V VC=9V
VE&V( IE&*A( VE&V( IE&*A(
MODEL GRAPH:
98
PROCEDURE:
I">!$ DC3=3D$)=#%$#D%:
0onnections are given as /er the circuit diagra
,ee/ing the V0A constant and varying V-A and I- is noted
The /rocedure is re/eated for different values of V0A and gra/h is /lotted
I
E
&*A(

V
BE
(V)
V
CB
=!V
V
CB
=1!V
98
OUTPUT CHARACTERISTICS
T3F!+3$#1":
S.NO
IE =. *A IE=G *A
VC&V( IC&*A( VC&V( IC&*A(
98
MODEL GRAPH:
O!$>!$ DC3=3D$)=#%$#D%:
0onnections are given as /er the circuit diagra
,ee/ing the IA constant and varying V0A and I0 is noted
The /rocedure is re/eated for different values of IA and gra/h is /lotted
I
-
=1 &
V
BC
( V )
I
0
!&%
I
-
=1" &
I
-
=$ &
98
R)%!+$:
Thus the in/ut and the out/ut characteristics of coon 5ase transistor is studied and
the gra/h is /lotted.
PIN DIAGRAM: SYMOL:
98

CIRCUIT DIAGRAM:
CHARACTERISTICS OF U7T
AIM:
To study the characteristics of the given =LT.
1k
V
+
A
+
V
+
2N 2646
(0-50)mA
2$2K
(0-30)V
(0-30)V
(0-30)V
(0-30)V
98
EQUIPMENTS REQUIRED :
S.NO COMPONENTS RANGE QUANTITY
1 =LT 2@ 2+.+ 1
2 (esistor 2.2,M 1
' Volteter !"#'"%V*!"#1$%V 1 each
. &eter !"#$"%& 1
$ (>S !"#'"%V 1
+ 0onnecting wires # #
D Aread 5oard # 1
FORMULA:
Intrinsic stand off ratio of =LT is H=& VP I VD (/ V12
Hhere
V> /eak voltage in volts
V0 drain voltage
VA1A2 voltage 5etween A1 E A2 in volts
TAULATION:
98
S.NO
V12=9V V12=1@V
VE1&V( IE&*A( VE2&V( IE&*A(
THEORY:
& /lot of V-A versus I- gives =LT eitter characteristics . refer to the =LT terinal
voltages and current identified and to the e2uivalent circuit. In that note that when VA1A2 ="*IA2="
and V1=".If I-A1 is now increased fro "* the resultant /oint of V-A1 and I- is si/ly the
98
characteristic of a forward 5iased diode with soe series resistance. This is the characteristics for
IA2=".
Hhen VA1A2 is 2" V the level of V1 ight 5e around 1$V*deoending u/on the resistance
of A1 E A2 with VA1A2=2"V E V-="* the eitter 1unction is reverse 5iased and the eitter
reverse current I-" flows * as shown at /oint 1 on the VA1A2=2"V.increasing the level of V-A1 until
it e2uals V1 gives I-="O/oint 2 on the characteristics. 4urther increase in V-A1 forward 5iases the
eitter 1unction* and it gives the /eak /oint on the characteristics. &s the /eak /oint*V-A1 is
identified as the /eak voltage V> and I> tered as the /eak current until the /eak /oint is said to
5e in the cut off region of the characteristics . when V-A1 arrives at the /eak voltage * charge
carriers are in1ected fro the eitter to decrease the resistance of VA1* as already eC/lained. The
device enters the negative resistance region.VA1 falls ra/idly to saturation resistance and V-A
fall to the valley voltage VV.I- also increases to the IV at this tie further increase in I- causes
he device to enter the saturation region where V- e2uals the su of VD and I-. starting with VA1A2
lower than 2"V gives a lower /eak /oint voltage *and a different characteristics. Thus using
various levels of VA1A2* a faily of gra/h can 5e /lotted.
M1,)+ ;=3>C:
98
VE
IE
PROCEDURE:
0onnections are given as /er the circuit diagra
PEAK POINT
98
The voltage VA1A2 are ke/t as constant
The voltage V- should 5e varied and the corres/onding I- reading should
5e taken
(e/eat the sae /rocedure for various values of VA1A2 and V-
?ra/h is /lotted 5;w V- E I-
RESULT:
Thus the study of =LT is studied E verified.
SYMOL:
98
CIRCUIT DIAGRAM:
MEASUREMENT OF SCR CHARACTERISTICS
V2 5
(0-30)V
(0-30)V
LOA%
SCR
T!N 604
RESISTOR
98
AIM:
To easure the S0( characteristics fro the gra/h
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1 S0( TF@ +". 1
2 (esistor .D"M ; 1 ,M.* P
H&TTS
2
' &eter !"#1"" % ; !"#1""%& 2
. Volteter !"#'"%V 1
$ (/s !"#'"%V 2
THEORY:
It has a . layer and ' terinal device @#layer acts as a anode and >#layer acts as cathode
>1@1*>2@2 &re sei conductors * L1 L2 L' &re >@ 1unctions
FORWARD CHARACTERISTICS:
S0( acts as a switch when it is forward 5iased when the gate is ke/t o/en. when Ig Q"
aount of reverse 5ias a//lied to L2 increases and so the 5reak over voltage VA< also increases.
IgR" the aount of reverse 5ias a//lied to L2 is decreased and so the VA< decreases with large +ve
gate current* 5reak over ay occur at low voltage such that the characteristic of S0( is switched
<@ can 5e controlled 5y the varying gate current Ig.
<nce the S0( is turned <@ * the gate losses current control the gate cant 5e used to
switch the device off is lowering the anode current 5elow the holding current I:

5y reduce su//ly
V: kee/ing gate o/en.

98
TAULATION:
S.NO IA&*A( VAK&V(
MODEL GRAPH:
IA&*A(
VH
I
VAK&V(
REVERSE CHARACTERISTICS:
Hhen the anode is Sve with res/ect to cathode the curve 5etween VEI is known as the
reverse characteristics. Hhen a reverse voltage is a//lied to S0( the current through the S0( is
very sall. Hhen the reverse voltage is increased gradually a stage is reached at the avalanche
5reakdown occurs and S0( starts conducting heavily in reverse direction. The aCiu
98
reverse voltage at which the S0( conducts heavily in reverse direction is known as reverse
5reakdown voltage.
PROCEDURE
0onnections are given as /er the circuit diagra
,ee/ing I& constant * vary V&, and the corres/onding readings are noted
(e/eat the eC/erient for various of Ig
Ta5ulate the values and /lot the gra/h 5;w V&, E I&
RESULT:
Thus the characteristics of S0( is deterined.
SYMOL:
98
CIRCUIT DIAGRAM:
1k
V
+
V
+
A
+
& W11
6"K
(0-15)V
(0-30)V
(0-30)V
(0-15)V
(!$
5!)"A
98
CHARACTERISTICS OF 7FET
AIM:
To study the drain and transfer characteristics of the given L4-T.
EQUIPMENTS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1 L4-T >4 H1" ; A4 H11 1
2 (esistor +TM*1,M 1 each
' Volteter !"#1$%V 2
. &eter !"#$"%& 1
$ (>S !"#'"%V 1
+ 0onnecting wires # #
D Aread 5oard # 1
TC)1=?:
& 1unction field effect transistor!L4-T% is a uni S/olar device. It conducts on only one
ty/e of charge carrier either holes or electrons. The device has . terinals in which the field or
/otential at the gate terinals in which the field or the current flow is controlled 5;w the source
and the drain terinals hence is called field S effect transistor . the fourth terinal is called
su5strate and is either connected to ground /otential or left unconnected. the figure shows the
5asis structure of of an n#channel L4-T . wire leads are connected to each end of the lower
end. The two >#ty/e regions are diffused in the Sty/e aterial to for a channel* and 5oth >#
ty/e regions are connected to the gate lead.
The drain characteristics are the current curves drawn 5etween drain to source voltage
VDS and the drain current Id with the constant gate to source to voltage a5ove which the current
5ecoes constant is /inch#off voltage. &fter which the channel width 5ecoes narrow and the
de/letion layer alost touches each other. The drain current /asses through the sall /assage
5;w these layers. :ence the increase in drain current is very sall with VDS a5ove which /inch#
off voltage . conse2uently* the drain current reains constant.
98
DRAIN CHARACTERISTICS
TAULATION:
SNO
VGS=@V VGS=@V
VDS&V( I&*A( VDS&V( I&*A(
MODEL GRAPH:
I
%
("A)
V
G&
=1V
V
%&
(V)
V
G&

=!V
V
G&
='V
V
G&
= V
G&
(OFF)
98
PROCEDURE:
DRAIN CHARACTERISTICS:
0onnect the circuit as shown in the circuit diagra
Set the gate voltage V?S to constant say "V vary VDS in ste/ of ".$ V. and record the value
of ID for each value of VDS
re/eat the /rocedure for various settings of V?S say 1V*2V etc.*
/lot the drain characteristics gra/h * VDS versus ID for constant V?S.
98
TRANSFER CHARACTERISTICS
TAULATION:
SNO
VDS=9V VDS=1@V
VGS&V( ID&*A( VGS&V( ID&*A(
MODEL GRAPH:
V
%&
(V)
I
%

("A)
V
G&
(V)
98
TRANSFER CHARACTERISTICS:
0onnect the circuit as shown in the circuit diagra
Set the drain voltage VDS to constant say $V *vary VDS in ste/ of 1 V. and record the value
of ID for each value of V?S
re/eat the /rocedure for various settings of VDS say 1"V*2"V etc.*
/lot the drain characteristics gra/h * V?S versus ID for constant VDS.
RESULT:
The drain and transfer characteristics of the given L4-T are studied and the gra/hs are
/lotted.
98
CIRCUIT DIAGRAM:
V2 5
(0-30)V
(0-30)V
LOA%
'OS&ET
SH(NT RESISTOR
98
CHARACTERISTICS OF MOSFET
AIM:
To study the characteristics of 8<S4-T and o5serve the wave for.
EQUIPMENTS REQUIRED:
NAME RANGE QUANTITY
>ower su//ly !"#'"%v 1
8<S4-T /in odule ########## ##########
>atch cards ########## ##########
(esistor load ########## ##########
98
DRAIN CHARACTERISTICS
TAULATION:
VGS = J..V
VDS&V( ID&*A(
MODEL GRAPH:
98
THEORY :
The drain current I< is /lotted with res/ect to drain to source voltage VDS the
characteristics are /lotted for various values of gate source voltage V?S .
There are ' region in the characteristics
<hic region
&ctive region
0utoff region
The cutoff region * the drain current is neglected and the 8<S4-T is set to 5e in off state. In
the ohic region * the 8<S4-T conducts heavily hence it is said to 5e in the ohic region. In
the active region iot acts as an a/lifier . the 8<S4-T is daaged it s drain to source voltage is
increased.
V
G&
=()V
V
%&
(V)
I
%
("A)
V
G&

=(9V
V
G&

=('V
98
TRANSFER CHARACTERISTICS
TAULATION:
VDS = V
VGS&V( ID&*A(
98
MODEL GRAPH:
PROCEDURE:
0onnect the D.0 su//ly to the load
0onnect the one end to the source of 8<S4-T
0onnect the other end to the load to shunt resistance
0onnect the other end of the shunt resistance to the 8<S4-T drain
The 12 V D0 su//ly is connected across the gate and the source terinal of the
8<S4-T.
I
%
("A)
V
%&
(V)
V
G&
(V)
98
RESULT:
Thus the characteristics of the 8<S4-T was verified and the gra/h was drawn..
CIRCUIT DIAGRAM:
MODEL GRAPH:
98
CHARACTERISTICS OF TRIAC
AIM:
To study and verify the characteristics of T(I&0.
COMPONENTS REQUIRED:
!"#'"%V /ower su//ly
T(I&0 kit odulus
>atch cards
(esistive load
THEORY:
98
The current I is /lotted with res/ect to voltage V* here I> is forward 5iased * V4 is voltage
current and initially I( is the reverse current and V( is the reverse voltage VD is the 5reakdown
voltage over the T(I&0.
Hhen the gate drive is a//lied* the T(I&0 turns U<@V ay the lower voltage then VD.such
characteristics is shown 5y center line . the dotted line in the characteristics indicate the
switching off of the T(I&0 is turned U<@V the voltage across it dro/s and current increases
ra/idly and o5serve that the characteristics are eCactly siilar on the forward E reverse
directions.
TAULATION:
FORWARD IAS:
VD = 9 V
VF&V( IF&*A(
98
REVERSE IAS:
VD = 1@ V
VR&V( IR&*A(
PROCEDURE:
0onnect the /ositive D0 su//ly to the load
0onnect the negative end of the terinal !8T2% of the T(I&0
0onnect the other end of the load to the terinal 8T1 of the T(I&0
The 12 V D0 su//ly is connected across the gate and the terinals of 8T2 of the
T(I&0.
98
RESULT:
:ence we studied the characteristics of the T(I&0.
CIRCUIT DIAGRAM:

1k
V
+
V'1
A
+
V1
(0-30)V
(0-5)V
(0-50)mA
)*+,+-.+-/
98
MODEL GRAPH:
CHARACTERISTICS OF PHOTODIODE
AIM:
To study the characteristics of /hotodiode.
APPARATUS REQUIRED:
NAME RANGE QUANTITY
&eter !"#$"%& 1
Volteter !"#$%V 1
(>S !"#'"%V 1
I (mA)
V
(V*+,-)
D
1
D
2
98
(esistor 1") 1
>hotodiode # 1
Aread 5oard # 1
THEORY:
Silicon /hotodiode is a light sensitive device also called /hoto detector which converts
light signals to electrical signals. The diode is ade of seiconductors >@ 1unction diode ke/t
in a sealed /aste or glass casing.
The cover is so designed that the light rays are allowed to fall on one surface across the
1unction. The reaining sides of the casing are /ointed to restrict the /enetration of light rays. &
lens /erit light to fall on the 1unction when light falls on the reverse 5iased >@ 1unction diode*
hole electron /airs are created. The oveent of these electron /airs in a /ro/erly connected
circuit results in current flow. The agnitude of the /hoto current de/ends on the nu5er of
charge carriers generated and hence on the illuination on the diode eleent.
TAULAR COLUMN:
D1=JJ.D* D2=JJ.D*
V &V( I &A( V &V( I &A(
98
PROCEDURE:
98
1. 0onnect the circuit as /er the circuit diagra.
2. Set a resistance 5etween the /hotodiode and light source as sae value.
'. &//ly In/ut voltage and note down I different in/ut voltage.
.. >lot the gra/h 5etween voltage and current and find the resistance of /hoto diode.
RESULT:
Thus the characteristics of /hotodiode was studied
D1 = WWWWc
D2= WWWW.c
CIRCUIT DIAGRAM:
98
MODEL GRAPH:
10k
V
+
A
+
A
'
1
(0-30)V
(0-10)V
(0-50)mA
)*+,+-.+-/
D
1
D
2
Ic (mA)
Vc (V)
98
CHARACTERISTICS OF PHOTOTRANSISTOR
AIM:
To study the characteristics of /hototransistor.
APPARATUS REQUIRED:
NAME RANGE QUANTITY
&eter !"#$"%& 1
Volteter !"#$%V 1
(>S !"#'"%V 1
(esistor 1") 1
>hototransistor # 1
Aread 5oard # 1
THEORY:
>hototransistor or /hotodiode is a uch ore resistive seiconductor /hotodiode than
>@ /hotodiode. The current /roduced 5y a /hotodiode is very low which cannot 5e directly used
in control a//lication.
Therefor the current should 5e a/lified 5efore a//lying to control circuit. The
/hototransistor is a light detector which co5ines a /hotodiode and transistor a/lified when
the /hototransistor is illuinated* it /erit a greater flow of current.
98
TAULAR COLUMN:
D1=JJ.D* D2=JJ.D*
VD&V( ID&A( VD&V( ID&A(
98
PROCEDURE:
1. 0onnections are ade as /er the circuit diagra.
2. Set the resistance 5etween the /hotodiode and light source as sae value.
'. &//ly in/ut voltage and note down I for different out/ut voltage.
.. >lot the gra/h 5etween voltage and current* and find resistance of /hotodiode.
RESULT:
Thus the characteristics of /hototransistor has 5een studied and the results are o5tained as
R = JJJ-
SYMOL:
98
CIRCUIT DIAGRAM:
MODEL GRAPH:

CHARACTERISTICS OF DIAC
98
AIM:
To study and verify the characteristics of DI&0.
COMPONENTS REQUIRED:
!"#'"%V /ower su//ly
DI&0 kit odulus
>atch cards
(esistive load
THEORY:

Hhen T1 is /ositive and voltage is less than VA<1 only a sall leakage current flows
through the device. Hhen voltage eCceeds VA<1 it starts conducting and current 5ecoes large.
&s the current increases* the voltage dro/ across diac decreases. Thus it eChi5it negative
resistance characteristics. The characteristics in the reverse direction!when T2 is /ositive%lies in
the third 2uadrant and is eCactly siilar to that in the first 2uadrant. The 5reakover voltage
VA<1 and VA<2 are eCactly e2ual in agnitude. In 5oth the cases* the device eChi5its negative
resistance 5ehavior during conduction region.
98
TAULATION:
FORWARD IAS:
VD = 9 V
VF&V( IF&*A(
REVERSE IAS:
VD = 1@ V
VR&V( IR&*A(
98
PROCEDURE:
0onnect the /ositive D0 su//ly to the load
0onnect the negative end of the terinal !T2% of the DI&0
0onnect the other end of the load to the terinal T1 of the DI&0
The 12 V D0 su//ly is connected across the gate and the terinals of T2 of the DI&0.
RESULT:
:ence we studied the characteristics of the DI&0.