Assignment No.

Instructions: Copy and answer the following questions. For questions requiring explanations, discuss
your answer as briefly as possible, right after the question. For problem solving type, show your
complete solutions after the question and box your final answers. Use at least one sheet of paper for
each of the items. Have the last page of this document printed and fill it up with your answers.

For items requiring simulations, use SPICE to simulate the circuit. Provide the SPICE netlist for each of
your simulation.

Note: Consider all devices ideal unless otherwise specified.

1. Describe a simple common-source MOSFET circuit with an n-channel enhancement-mode device

and discuss the relation between the drain-to-source voltage and gate-to-source. (5 points)
2. What are the steps in the dc analysis of a MOSFET circuit? (5 points)
3. How do you prove that a MOSFET is biased in the saturation region? (5 points)
4. In the dc analysis of some MOSFET circuits, quadratic equations in gate-to-source voltage are
developed. How do you determine which of the two possible solutions is the correct one? (5
points)
5. Consider the circuit in the figure below. The transistor parameters are VTH = -2 V and kp = 200
uA/V2. Determine ID, VSG, and VSD. Simulate this circuit using SPICE. (10 points)

6. Redesign the MOSFET circuit shown in item number 5. The transistor parameters are VTH = -2 V,
kp’ = 40 uA/V2, and λ = 0. The circuit bias is ± 10 V, the drain current is to be 0.8 mA, the drain-to-
source voltage is to be approximately 10 V, and the voltage across RS is to be approximately
equal to VGS. In addition, the current through the bias resistors is to be no more than 10 percent
of the drain current. Using these parameters, simulate the circuit and determine VGS, VDS, ID and
the current through the bias transistors.(10 points)
7. Design the circuit in the figure below such that ID = 0.8 mA and VD = 1 V. The transistor
parameters are kn = 400 uA/V2 and VTH = 1.7 V. Using SPICE, determine the values of VGS and VDS.
(10 points)

8. The PMOS transistor in the figure below has parameters VTH = -1.5 V, kp’ = 25 uA/V2, L = 4 um
and λ = 0. Determine the values of W and R such that I D = 0.1 mA and VSD = 2.5 V. (10 points)
9. Design the circuit in the figure below such that ID = 0.5 mA and VD = -3 V. The transistor
parameters are kp’ = 30 uA/V2, W/L = 20 and VTH = -1.2 V. (10 points)

10. The parameters of the transistor in the circuit in the figure below are VTH = -1.75 V and kp = 3
mA/V2. Design the circuit such that ID = 5 mA, VSD = 6 V, and Rin = 80 kohms. (10 points)
11. The transistors in the circuit below both have parameters VTH = 0.8 V and kn’ = 30 uA/V2. (a) If
the width-to-length ratios of M1 and M2 are (W/L)1 = (W/L)2 = 40, determine VGS1, VGS2, VO, and ID.
(b) Repeat part (a) if the width-to-length ratios are changed to (W/L)1 = 40 and (W/L)2 = 15.
Verify your answers using SPICE simulation. (10 points)

12. Consider the circuit in the figure below. The transistor parameters are VTH = 1 V and kn’ = 36
uA/V2. Design the width-to-length ratio required in each transistor such that ID = 0.5 mA, V1 = 2 V
and V2 = 5 V. (10 points)
Summary of Answers (For items 5 – 12 only)

Item Answers
ID Computed: Simulated:
5 VSG Computed: Simulated:
VSD Computed: Simulated:
W/L
R1
R2
RD
6 RS
VGS (simulated)
VDS (simulated)
ID (simulated)
I (simulated)
RD
RS
7
VGS (simulated)
VDS (simulated)
W
8
R
W/L
9 RS
RD
R1
10 R2
RD
VGS1 Computed: Simulated:
VGS2 Computed: Simulated:
a
VO Computed: Simulated:
ID Computed: Simulated:
11
VGS1 Computed: Simulated:
VGS2 Computed: Simulated:
b
VO Computed: Simulated:
ID Computed: Simulated:
(W/L)1
12 (W/L)2
(W/L)3