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Appendix A

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W e

SECRETARY
CUMMISSION

Appe ndixA
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
February OS, 2002
THIS IS TO CERTIFY THAT ANNEXED IS A TRUE COPY FROM THE
IRECORDS OF THIS OFFICE OF THE FILE WRAPPER AND CONTENTS
OF:
APPLICATION NUMBER: 08/265,535
FILING DATE: June 24,1994
PATENT NUMBER: 5,452,261
ISSUE DATE: September 19,1995
IW 507655
By Authority of the
'COMMISSIONER OF PATENTS AND TRADEMARKS
P. R. GRANT
Certifying Officer
E R l A L N U M B E R F I L I N G D A T E C L A S S G R O U P A R T l . - l N | T >
e : 3 x 2 5 5 , 5 3 5 - as/2 4/94 . . . . . 2 5 1 1









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T I T L E
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n A \ ub c
P R l M 7 \ R Y E XA M I N E
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. P fi mar y E x ami n e r
W A R N I N G : T h e I n fo r mat i o n d i sc r o sd h '
b y t h e U n i t e d S t at e s C o d e I
U.S. DEPARTMENT OF COMMERCE
PATENT AND TRADEMARK OFFICE
FEE RECORD SHEET
9132 07/12/74 08245535 19-2306 020 101 710.00CH M- 2595 US
' - 1555
87)
.. I
At t y. Docket No. : M- 2595 US
081265535
.AW OFFI CES OF
J une 24, 1994
Our Case Docket No. M- 2595 US
Commi ssi oner of Pat ent s and Tr ademar ks
Washi ngt on, D. C. 20231
Tr ansmi t t ed her ewi t h f or f i l i ng i s a pat ent appl i cat i on, as f ol l ows:
I nventor(s) : ET. &,L, Li gxosg Bung and Mi chael A. Murray
Ti t l e :
- 0 0
SERI ALAPDRESS . GENERATOR .. FO R... BVR..M.~-OR~
. Encl osed. al so ar e:
2 Sheet s of dr awi ngs: - ( Formal ) X ( I nf ormal )
- An Assi gnment of the I nvent i on t o
- A cert i f i ed copy of a Appl i cat i on.
CLAI MS AS FI LED
Number Number
E a Filed Rate
Basi c Fee
$ 710. 00
Tot al Cl ai ms 10 - 20 - 0 x $22 - 00. 00
Gl ai ms 3 - 3 - 0 x $74 - 00.00
dependent cl ai ms ( $230 t ot al f ee) - 00, oo
Tot al fi l i ns! f ee: $ 710. 00
I ndependent
-
Appl i cat i on cont ai ns one or more mul t i pl e
Pl ease make t he f ol l owi ng char ges to Deposi t Account 19- 2386:
XX Fee f or f i l i ng the pat ent appl i cat i on i n t he amount of $ 710. 00
2 The Commi ssi oner i s her eby aut hor i zed to charge any addi t i onal
f ees whi ch may be r equi r ed, or cr edi t any over payment to Deposi t
Account 19- 2386.
A Ret ur n Post Card and t hi s sheet i n t ri pl i cat e are encl osed.
I hereby certify that this correspondence is being
deposited with he United States Postal Service a6 expresa
mail In an enveloDe addressed to: Comnissioner of Patents
Respect f ul l y submi t t ed,
32 Pw-dA4 R. I4L.%Y(/-
Nor man R. Kl i vans
Reg. No. 33, 003
At t or ney f or Appl i cant(s)
. I :
' A '
...
5
10
15
20
25
30
35
: r/.-
# ., I
SERI AL ADDRESS GENEWmF OR BURSTMEMORY
___.
J i nyong chung /
./
Mi chael A. Mur r ay
BACKGROUND OF THE I NVENTI ON
Fi el d of t he I nvent i oq
Thi s di scl osur e r el at es t o r andomaccess memor y
and speci f i cal l y t o a ser i al addr ess gener at or f or a
bur st - t ype r andomaccess memor y.
Descr i pt i on of t he Pr i or Ar t
Vi deo RAM ( r andomaccess memor y) , synchr onous RAM
and bur st RAM each r equi r e a sequence of i nt er nal l y
gener at ed addr esses f or f ast er cycl i ng and pr event i on
of t he ext er nal addr ess bus l i nes f r omf ast swi t chi ng
t o suppr ess swi t chi ng noi se i n t he syst em. Typi cal l y
t he st ar t addr ess of a par t i cul ar addr ess bur st i s
pr ovi ded f r oman ext er nal sour ce (a host comput er or a
pr ocessor ) and as subsequent cl ock si gnal s ar r i ve at
t he addr ess gener at or , t he f ol l owi ng addr esses i n t he
bur st ar e gener at ed cont i nuousl y i n sequence f or t he
dur at i on of t he burst .
addr ess sequencer ( t ypi cal l y a count er ) t o t he
ext er nal l y pr ovi ded st ar t addr ess (A,) i n r esponse t o a
PRESET si gnal . The addr ess sequencer out put i s updat ed
wi t h each @clock r i si ng edge, and t he out put s of t he
addr ess gener at or ar e sequent i al l y A,, An+l , An,p , et c.
Such a pr i or ar t addr ess gener at or i s shown i n
Fi g. 1A i ncl udi ng addr ess sequencer 12 out put t i ng t he
sequence of addr esses t o an out put buf f er 14. The
t hr ee i nput si gnal s t o t he addr ess sequencer 12 ar e t he
i nput addr ess si gnal ( t he st ar t addr ess A,), t he @clock
si gnal , and t he PRESET si gnal . Addi t i onal l y, a
The pr i or ar t pr eset s t he
-1-
sequence cont r ol si gnal cont r ol s whet her t he addr ess
sequencer 12 count s up or down. I n most appl i cat i ons,
upcount i ng i s used, and t hi s f unct i on i s bui l t i n,
r at her t han bei ng a cont r ol f unct i on. The associ at ed
5 t i mi ng di agr ami s shown i n Fi g. 2A.
Typi cal l y t he addr ess sequencer 12 ( Count er )
i ncl udes a mast er si de and a sl ave si de, each i ni t i al l y
set t o t he st ar t addr ess A,,.
t hat t he devi ce of Fi g. 1A i s a par al l el devi ce, wher e
t he st ar t addr ess A, i s a mul t i - bi t addr ess pr ovi ded by
a pl ur al i t y of l i nes, i . e. an addr ess bus. The addr ess
out si gnal i s al so pr ovi ded on a mul t i - l i ne bus.
out put t o buf f er 14 when t he Pr eset si gnal i s appl i ed,
second addr ess out A,+1 i s out put t o buf f er 14 at t he
t r ai l i ng edge of @clock and t he f ol l owi ng addr esses ar e
updat ed at ever y t r ai l i ng edge of t he @clock si gnal .
The addr ess gener at or of Fi g. 1A f unct i ons
20 adequat el y; however i t i s sl ower t han desi r ed. Fast er
oper at i on i s desi r abl e t o i mpr ove syst emper f or mance
such as needed i n a t ypi cal bur st DRAM ( dynami c r andom
access memor y) chi p. The Fi g. 1A addr ess gener at or
del i ver s t he f i r st addr ess l at e, due t o t he pr opagat i on
sequencer . Thi s means a shor t er st ar t addr ess dur at i on
t i me .
To i mpr ove t he st ar t addr ess del i ver y, i n a second
pr i or ar t addr ess gener at or t he st ar t addr ess i s
30 pr ovi ded f r omt he Addr ess I nput di r ect l y, i nst ead of
goi ng t hr ough t he count er s. ( See Fi g. lB, and
cor r espondi ng t i mi ng di agr amFi g. 2B).
Rat her t han pr ovi di ng t he st ar t addr ess A, t o t he
addr ess sequencer as i n Fi g. 1A, t he addr ess sequencer
12 of Fi g. 1B i s bypassed bef or e and dur i ng t he pr eset
per i od by means of ext er nal addr ess enabl e swi t ch 24
I t i s t o be under st ood
10
As seen i n Fi g. 2A, t he f i r st addr ess out A,, i s
15 and kept unt i l l eadi ng edge of @=lock ar r i ves. The
25 del ay t hr ough t he count er s i nsi de t he addr ess
35
-2-
and i nt er nal addr ess enabl e swi t ch 26, and t he st ar t
addr ess i s pr ovi ded di r ect l y t o t he out put buf f er vi a
ext er nal addr ess enabl e swi t ch 2 4 . Thi s ( st ar t )
addr ess A, i s t her ef or e avai l abl e al most i mmedi at el y as
5 t he addr ess out at buf f er 1 4 , wi t hout pr ocessi ng by t he
addr ess sequencer 12.
hi gher speed) i s desi r abl e i n t er ms of addr ess out put .
However , f ur t her per f or mance i mpr ovement (i . e. ,
10 SUMMARY OF THE I NVENTI ON
I n t he above descr i bed pr i or ar t , t he second
addr ess A,+1 i s del i ver ed by t he addr ess sequencer t o
t he out put buf f er at t he t i me of t he t r ai l i ng edge of
t he f i r st Gclock cycl e.
t o t he out put buf f er at t he l eadi ng edge of t he @clock
si gnal . Thus one hal f of a cl ock cycl e i s gai ned or
each addr ess bur st .
I n accor dance wi t h t he
15 i nvent i on, i nst ead t he second addr ess A,+1 i s del i ver ed
Af t er pr ovi si on t o t he out put buf f er of t he f i r st
2 0 addr ess A, ( whi ch i s ext er nal l y suppl i ed as i n Fi g. 1B)
t he ext er nal addr ess l i ne i s di sconnect ed f r omt he
out put buf f er by an ext er nal addr ess enabl e swi t ch, and
an i nt er nal addr ess enabl e swi t ch whi ch connect s t he
addr ess sequencer t o t he out put buf f er i s cl osed,
subsequent i nt er nal l y gener at ed addr ess A,+1 t o t he
' out put buf f er , al so as i n Fi g. 1B. Then, dur i ng t he
t i me t hat t he st ar t addr ess A, i s bei ng pr ovi ded t o t he
out put buf f er , t he addr ess sequencer oper at es t o
addr esses of each bur st ar e t her eby each pr ovi ded t o
t he out put buf f er appr oxi mat el y 1/ 2 of a cl ock cycl e
ear l i er t han i n t he pr i or ar t of Fi g. IB.
The ext er nal l y pr ovi ded addr ess and t he addr ess
out bot h begi n wi t h t he same addr ess A, whi ch i s t he
i ni t i al addr ess i n t he bur st , whi l e usi ng t he pr eset
25 al l owi ng t he addr ess sequencer t o pr ovi de t he
30 cal cul at e t he subsequent addr ess A,+1. The out put
35
-3-
si gnal t o advance t he count i ng of t he sequence by one
count .
Ther ef or e, t he addr ess sequencer i s pr eset t o
addr ess A,+1 ( t he second addr ess i n t he bur st ) f ol l owi ng
f i r st cl ock si gnal ar r i ves at t he addr ess sequencer ,
t he addr ess sequencer out put i s sampl ed by enabl i ng t he
i nt er nal addr ess enabl e ( second) swi t ch and di sabl i ng
t he ext er nal addr ess enabl e ( f i r st ) swi t ch. The
10 addr ess sequencer out put i s updat ed wi t h each r i si ng
edge of t he cl ock si gnal @clock. Ther eby t he addr ess
sequencer gener at es each addr ess one cl ock cycl e ahead
of t he t i me t hat addr ess woul d have been gener at ed i n
t he pr i or ar t , and t he addr ess out put i s suppl i ed t o
t he out put buf f er 1/2 cl ock cycl e ahead of t he pr i or
ar t ( Fi g. 2B) t i mi ng. As i n t he pr i or ar t , t he addr ess
sequencer i ncl udes a mast er / sl ave count er . However , i n
accor dance wi t h t he i nvent i on and i n or der t o set t he
addr ess sequencer i ni t i al l y t o t he second addr ess An+l,
t he mast er si de of t he count er i s i ni t i al l y set t o
val ue An, and t he sl ave si de of t he count er i s
i ni t i al l y set t o val ue A,+1.
i ncr ement al t i mi ng advant age over t he pr i or art .
5 t he ext er nal l y pr ovi ded st ar t addr ess A,. When t he
15
20
Thi s pr ovi des t he desi r ed
The pr esent i nvent i on i s appl i cabl e speci f i cal l y
25 t o bur st DRAM ( dynami c RAM) oper at i ng i n page mode, and
i s al so appl i cabl e t o ot her t ypes of bur st memor y usi ng
sequent i al t ype addr essi ng.
I n accor dance wi t h t he i nvent i on, oper at i on of t he
addr ess gener at or i s t he same as i n t he pr i or ar t
30 except dur i ng t he pr eset cycl e. Thus t he per f or mance
advant age i s gai ned dur i ng t he pr eset por t i on of t he
addr ess bur st .
cycl e ahead of t hat pr ovi ded i n t he pr i or ar t , t hi s
i mpr oves t he oper at i onal per f or mance of t he syst emi n
whi ch t he bur st memor y is i nst al l ed.
Si nce t he addr esses ar e out put one- hal f
35
-4-
BRI EF DESCRI PTI ON OF THE DRAWI NGS
Fi gs. I A, I B showpr i or ar t addr ess gener at or s.
Fi gs. 2A, 2B showt i mi ng di agr ams f or t he pr i or "
ar t addr ess gener at or s of r espect i vel y Fi gs. l A, 1B.
wi t h t he pr esent i nvent i on.
gener at or of Fi g. 3 .
an
v 5 Fi g. 3' shows f l Aaddr ess gener at or i n accor dance
. /
Fi g. 4 shows a t i mi ng di agr amf or t he addr ess
Fi g. 5 shows a schemat i c of t he i nt er nal addr ess
10 enabl e swi t ch, ext er nal addr ess enabl e swi t ch, and
out put buf f er i n accor dance wi t h t he pr esent i nvent i on.
Fi g. 6 shows a count er i n accor dance wi t h t he
pr esent i nvent i on.
Fi g. 7 shows det ai l of one cel l of t he count er of
Fi gs. 8, 9 , and 10 showci r cui t r y or gener at i on
15 Fi g. 6.
of t he t i mi ng si gnal s f or t he addr ess gener at or i n
accor dance wi t h he r esent i nvent i on.
Fi qs 11 show$ a t i mi ng di agr amf or an addr ess
C d enst 11Pb)
A
20 gener at or i n accor dance wi t h t he pr esent i nvent i on.
DETAI LED DESCRI PTI ON OF THE I NVENTI ON
Fi g. 3 shows i n a bl ock di agr amser i al addr ess
gener at or 18 i n accor dance wi t h t he i nvent i on. Addr ess
buffer 2 2 , ext er nal addr ess enabl e swi t ch 24 (as i n
Fi g. 1B) act uat ed by an ext er nal addr ess enabl e cont r ol
si gnal 2 8 , and i nt er nal addr ess enabl e swi t ch 26 (as i n
Fi g. 1B) act uat ed by an i nt er nal addr ess enabl e cont r ol
30 si gnal 30. Thus t he ser i al addr ess gener at or of Fi g. 3
appear s i n t he bl ock di agr amt o be si mi l ar t o t he
ser i al addr ess gener at or of Fi g. 1B; t he di st i nct i on i s
i n t he i nt er nal st r uct ur e and oper at i on of addr ess
sequencer 20, whi ch di f f er s si gni f i cant l y from addr ess
25 gener at or 18 i ncl udes addr ess sequencer 20, out put
35 sequencer 12 of Fi gs. 1A and 1B.
/
i //
. I ,
-5-
5
10
15
20
25
i
30
J
35
Sequence cont r ol si gnal 32 ( as i n t he pr i or art )
det er mi nes whet her addr ess sequencer 20 i s an up or
down count er . I nput si gnal s on l i nes 34, 36 and 38 ar e
convent i onal ( as i n t he pr i or art). The out put addr ess
( I f addr ess out t l ) i s pr ovi ded on l i ne 40. Thi s ci r cui t ,
l i ke t hat of Fi gs. 1A and 1B, i s a par al l el devi ce
pr ovi di ng a mul t i - bi t addr ess. Hence addr ess l i ne 34,
t he out put f r omt he addr ess sequencer on l i ne 42, and
t he addr ess out l i ne 40 each r epr esent mul t i - l i ne
busses wi t h as many l i nes as t her e ar e addr ess bi t s i n
t he par t i cul ar appl i cat i on.
Fi g. 4 i l l ust r at es t i mi ng f or t he addr ess
gener at or of Fi g. 3 , and speci f i cal l y t he t i mi ng f or
ext er nal addr ess swi t ch 24 and i nt er nal addr ess swi t ch
26 as cont r ol l ed r espect i vel y by t hei r cont r ol si gnal s
28, 30 of Fi gur e 3 . I ni t i al l y, ext er nal addr ess enabl e
swi t ch 24 i s cl osed ( t he ext er nal addr ess enabl e
cont r ol si gnal 28 i s hi gh) t hus pr ovi di ng t he
ext er nal l y pr ovi ded addr ess on l i ne 34 di r ect l y t o
buf f er 2 2 . Af t er t he i ni t i al addr ess A, ( whi ch i s
ext er nal l y pr ovi ded) i s pr ovi ded t o buf f er 22, t he
si gnal @clock goes l ow, and t he ext er nal addr ess enabl e
cont r ol si gnal 2 8 goes l ow, t hen t he i nt er nal addr ess
enabl e si gnal 30 goes hi gh, cl osi ng swi t ch 26. At t hi s
t i me t he addr ess sequencer 20 has gener at ed t he second
address A,+1.
As seen i n t he t i mi ng di agr amof Fi g. 4 ,
gener at i on of t he second addr ess A,+1 over l aps wi t h
pr ovi si on of t he st ar t addr ess A,. Thus wi t hi n t he
f i r st t wo @clockkar al l of st ar t addr ess A, and
second addr ess A,+1 ar e out put t o buf f er 22, i n cont r ast
to t he pr i or ar t of Fi g. 2B i n whi ch onl y 1 1/2
addr esses ar e out put t ed i t hi n t he f i r st t wo
occur r ences of cl ock&% * @clock- Thi s hal f - cl ock
cycl e advant age i s t he chi ef benef i t of t he pr esent
i nvent i on. Thus t he gener at i on of addr esses ( Addr ess
-6-
?
sequencer out " i n Fi g. 4 ) i s one cl ock cycl e ahead of
t hat i n t he pr i or ar t , and t her e i s al so a hal f cl ock
t i mi ng advant age i n t he out put addr esses ( "Addr ess
out ") i n cont r ast t o t he pr i or ar t of Fi g. 2B.
I n one embodi ment t he ser i al addr ess gener at or of
Fi g. 3 i s f or use i n a bur st RAM oper at i ng i n page
mode, wi t h t he ext er nal l y pr ovi ded addr ess bei ng t he
f i r st ( st ar t ) addr ess f or each page. Ther ef or e f or
exampl e a RAMchi p havi ng 512 wor ds per page r equi r es
sequencer i s a ni ne- bi t count er .
gener at or i n accor dance wi t h t he i nvent i on i s al so be
sui t abl e f or ot her ( non- page mode) t ypes of ser i al l y
gener at ed addr esses, wi t h t he addi t i on of convent i onal
st op ci r cui t r y t o t er mi nat e a bur st of pr edet er mi ned
l engt h.
I t i s t o be appr eci at ed t hat t he ser i al addr ess
gener at or of Fi g. 3 i s used i n pl ace of convent i onal
ser i al addr ess gener at or of Fi gs. 1A, 1B as a por t i on
pr ovi ded on l i ne 40 i s convent i onal l y connect ed t o an
addr ess decoder whi ch sel ect s t he desi r ed memor y cel l
or cel l s t o be wr i t t en t o or r ead f rom.
of t he RAM chi p i s not i l l ust r at ed her ei n as bei ng
5
10 ni ne bi t addr esses, i . e. , 29 =512. Thus, t he addr ess
The ser i al addr ess
15
20 t ypi cal l y of a chi p. The addr ess out si gnal
( The r emai nder
25 convent i onal . )
Fi gs. 5 t hr ough 10 showa det ai l ed schemat i c of
one embodi ment of t he pr esent i nvent i on, cor r espondi ng
t o t hat shown i n t he bl ock di agr amof Fi g. 3 except
t hat t he sequence cont r ol i s not shown, due t o onl y
30 upcount i ng bei ng avai l abl e. I n Fi gs. 5 t hr ough 10 t he
Smal l number s adj acent each l ogi c gat e i ndi cat e t he
wi dt h ( i n mi cr omet er s) of each t r ansi st or gat e of t he
l ogi c gat e. Thus, llPlr i ndi cat es t he wi dt h of a P
channel t r ansi st or gat e and llN1l i ndi cat es t he wi dt h of
35 an N channel t r ansi st or gat e. The gat e l engt h i s equal
for al l t r ansi st or s except wher e a t wo number not at i on
-7-
5
10
BLOCK DI AGRAM
- FI G. 3
St ar t addr ess
( An)
PRESET
Ext er nal
Addr ess
I nt er nal
Addr ess
i s used i . e. , t t 48/ 211 means t he t r ansi st or gat e wi dt h i s
48 mi cr omet er s and t he t r ansi st or gat e l engt h i s 2
mi cr omet er s. The st andar d ( def aul t ) t r ansi st or gat e
l engt h i s 1.2 mi cr omet er s, f or t hi s embodi ment .
di agr amFi g. 3 and t he cor r espondi ng si gnal
desi gnat i ons i n schemat i c Fi gs. 5 t o I O, and i n t he
cor r espondi ng t i mi ng di agr amof Fi gs 1s;
t her e i s no schemat i c equi val ent t o t he sequence
cont r ol si gnal i n Fi g. 3 , si nce as expl ai ned above t he
ci r cui t shown i n t he schemat i c of Fi gs. 5 t o I O uses
"up count i ng" onl y and does not have a down count i ng
mode opt i on.
Tabl e 1 shows t he si gnal desi gnat i ons i n t he bl ock
(AI, 1:: L :
I n Tabl e 1
SCHEMATI C - FI GS. 5-10 TI MI NG CHART
- FI G. 11
Same Yn
Same Same
Addr ess
BN, ( Bur st Addr ess N) Addr ess
An
Sequencer
15
Sequence
cont r ol
Ext er na 1
Addr ess
Enabl e
I nt er nal
Addr ess
Enabl e
Addr ess Out
25
( up count i ng i s i nher ent
so t hi s cont r ol i s not
r equi r ed)
AH ( addr ess Hol d) AH
[ f unct i ons as ext er nal
addr ess l at chi ng and
di sabl e at same t i me]
BAEN- ( Bur st Addr ess BAEN-
Enabl e- )
Y,-L, YmLl Y,-R, YmR ( t wo Addr ess Out
pai r s per si ngl e
addr ess) , i
30
( Not Shown)
Tabl e 2 shows t he ext er nal l y pr ovi ded i nput
5 si gnal s/ l i nes f or t he ci r cui t of Fi gs. 5 t o 10.
TABLE 2
-- - - -
BCn ( Bur st Count er Car r y
- Out put ) BCN- 1 ( Bur st
10
NAME DESCRI PTI ON
A, Ext er nal addr ess
vcc power
L l ef t decoder addr ess enabl e
R r i ght decoder addr ess
YS
AS Addr ess Sense
enabl e
col umn addr ess power up
f -
c.
BE/ OE
AH
ATDOE
WE-
WE1
15
~-
mu 1 t i pl ex
Bur st enabl e/ out put enabl e
i nput
Ext er nal addr ess enabl e
Out put enabl e cont r ol
Wr i t e Enabl e-
Wr i t e Enabl e
20
I
! ROW- col umn addr ess
25
-9-
i
--
- b
L
\ 5
,\
\
UAm DESCRI PTI ON
Ym-r, l ef t addr ess bi t i nver t ed
Ymr, l ef t addr ess bi t
Ym-R r i ght addr ess bi t i nver t ed
YmR r i ght addr ess bi t
&
exempl ar y embodi ment of t he i nvent i on.
Wi t h r ef er ence t o Fi g. 5 , i nput si gnal dw
cor r esponds t o t he ext er nal Addr ess A, on l i ne 34 i n
ext er nal addr ess l at chi ng and di sabl e. Thi s i s t he
35 Fi g. 3 . Si gnal AH ( addr ess hol d) f unct i ons as t he
-10-
ext er nal addr ess enabl e si gnal , cont r ol l i ng swi t ch 50
i n Fi g. 5 whi ch cor r esponds t o swi t ch 24 i n Fi g. 3.
42 of Fi g. 3 i s desi gnat ed si gnal BN i n Fi g. 5, and i s
swi t ch 26 i n Fi g. 3 . Swi t ch 52 i s cont r ol l ed by t he
i nt er nal addr ess enabl e si gnal whi ch i n Fi g. 5 i s
desi gnat ed BAEN- . ( The i nver se of si gnal BAEN. ) It i s
t o be under st ood t hat t he si gnal BN i s pr ovi ded f r om
bel ow.
Buf f er 22 of Fi g. 3 cor r esponds t o t he buf f er
ci r cui t r y 56 of Fi g. 5. The out put s of t he buf f er
ci r cui t r y of Fi g. 5 ar e desi gnat ed as a ' t l ef t l l and
(Yn-=, Y,, Yn-R and YmR) . ( Not e t her e ar e t wo decoder s,
one f or t he l ef t memor y bl ock and t he ot her f or t he
r i ght memor y bl ock. ) The out put of buf f er 56
cor r esponds t o one bi t of t he addr ess out si gnal of
Si mi l ar l y, t he i nt er nal addr ess suppl i ed on l i ne
5 pr ovi ded as an i nput t o swi t ch 52 cor r espondi ng to
10 t he count er por t i on of t he addr ess gener at or , descr i bed
15 "r i ght " Y ( col umn addr ess) and t he i nver ses t her eof
2 0 Fig. 3.
The l ef t and r i ght (L, R) si gnal s of Fi g. 5
cont r ol t he buf f er 56 out put s, t o pr ovi de addr ess
si gnal s t o l ef t or r i ght decoder s r espect i vel y.
pr ovi ded i s col umn addr ess power up si gnal YS, whi ch
di sabl es t he i nput addr ess pass when t he chi p i s i n t he
pr echar ge st at e.
t he ci r cui t of Fi g. 5 ( desi gnat ed BA,) i s an i nput t o
t he associ at ed Count er Cel l , as descr i bed bel ow.
30 addr ess sequencer 20 of Fi g. 3 ) pr ovi di ng a ni ne- bi t
Al so
25
The i nt er nal st ar t addr ess out put by
Fi g. 6 shows t he count er ( cor r espondi ng t o t he
count .
60-2, ..., 60- 9 connect ed as shown. Each cel l has as a
f i r st i nput t he i nt er nal st ar t addr ess BA,. The second
cel l i nput i s t he Car r y si gnal desi gnat ed BC,,l f r omt he
si gnal PRESET, and a second t i mi ng si gnal qclock.
The count er has ni ne i dent i cal cel l s 60-1,
35 pr i or cel l . Each Cel l al so r ecei ves a f i r st t i mi ng
The
-11-
cv
out put of each count er cel l i s an out put addr ess bi t BN
( whi ch i s t he addr ess out) whi ch t hen goes t o buf f er 56
of Fi g. 5, and a second out put BC, whi ch i s t he car r y
val ue t o t he subsequent cel l .
occur s onl y once i n t he addr ess sequencer 20 and
ser vi ces al l ni ne addr ess buf f er ci r cui t s, of whi ch
onl y one i s shown i n Fi g.
5.
5 I t i s t o be under st ood t hat t he count er of Fi g. 6
Fi g. 7 shows det ai l s of one of t he cel l s of Fi g.
10 6. Si gnal BC,,l i s t he car r y i nput si gnal , whi l e si gnal
BA, i s t he ext er nal addr ess si gnal .
ar e @clock and PRESET ( and t hei r i nverses) . The cel l
out put i s t he t t r eal l t addr ess BN and a car r y val ue Bc,
t o t he next cel l . The cel l of Fi g. 7 i ncl udes
15 convent i onal l y a l ef t - hand si de whi ch i s t he 9t sl ave11
si de 70 and a r i ght hand si de whi ch i s t he 9nast er t 9
si de 72 ( i ndi cat ed by t he br oken l i ne). Thus, t her e
are t wo l at ches 70a, 72a one or each si de of t he
count er cel l , wi t h one l at ch at any one t i me updat i ng
i t s val ue whi l e t he second l at ch i s hol di ng t he
pr evi ousl y cal cul at ed dat a and t r ansmi t t i ng i t as
out put .
Fi gs. 8 , 9 and 10 showci r cui t r y for gener at i ng
t he t i mi ng si gnal s f or t he ser i al addr ess gener at or .
The t wo ext er nal l y pr ovi ded t i mi ng si gnal s ar e RAS and
CAS-PAD. These i n t ur n gener at e as shown t he i nt er nal
t i mi ng si gnal s. The sequence i s t hat t he i nput cl ock
si gnal CAS-PAD gener at es t i mi ng si gnal CASlb whi ch i n
t ur n gener at es si gnal BAEN- whi ch i n t ur n gener at es
30 si gnal @clock. The @clock si gnal of Fi g. 3 i s shown i n
t he t i mi ng di agr amof Fi g& 1 1 .
t i mi ng si gnal CAS1b whi ch i s a t i mi ng si gnal f or t he
above- descr i bed count er ci r cui t r y. Not e t hat si gnal
CASlb i s i n par t det er mi ned by t he si gnal BM ( bur st
The t i mi ng si gnal s
20
25
&)J / l ( b l
Fi g. 8 shows t he ci r cui t r y whi ch pr ovi des t he
35
-12-
mode) and by t he si gnal WE1 whi ch i n t hi s case i s t he
bur st wr i t e i nput si gnal .
of Fi gs. 5 t o 10.
Fi g. 3) i s desi gnat ed Y, i n t he t i mi ng di agr amof Fi gs.
1l a and 1lb. The out put si gnal of t he count er i s
desi gnat ed Y ~ + ~ , Y,+2r ... i n t he t i mi ng di agr am. I t
can be seen t hat when t he cl ock si gnal AS goes hi gh,
and af t er a par t i cul ar per i od, t he PRESET si gnal goes
det er mi ned by t he si gnal CAS- PAD goi ng l ow.
addr ess gener at i on i s det er mi ned by t he si gnal CAS- PAD;
i n one embodi ment t hi s si gnal has a 15 nanosecond
Fi gs. l l a and l l b showt he t i mi ng f or t he si gnal s
The st ar t addr ess ( desi gnat ed A, i n
5
10 hi gh. I n t ur n, t he PRESET si gnal goi ng l ow i s
The over al l cl ock speed of t he chi p i n t er ms of
15 per i od, pr ovi di ng a 66 MHz oper at i ng speed.
~t i s t o be under st ood t hat i n a t ypi cal oper at i on
of t he ser i al addr ess gener at or , t he associ at ed memor y
ar r ay i s consi der ed t o be an ar r ay of memor y cel l s
ar r anged i n r ows and col umns. Each "page11 i s one r ow,
f i r st memor y cel l i n t he col umn. Si gnal BE/ m, ( bur st
enabl e out put enabl e) at t he r i si ng edge of AS
det er mi nes whet her one i s t o be i n bur st mode or i n
nor mal page mode. si gnal BE/ ^ i s det er mi ned by t he
of Fi g. 5 i s connect ed t ypi cal l y t o a col umn pr edecoder
f or det er mi ni ng t he par t i cul ar col umn of a memor y ar r ay
to be addr essed. A pr edecoder buf f er s t he addr ess
si gnal s pr i or t o pr ovi si on t her eof t o t he decoder
i ncr eases oper at i ng speed, by ser vi ng as a buf f er f or
t he decoder pr oper .
l i mi t i ng; f ur t her modi f i cat i ons wi l l be appar ent t o one
ski l l ed i n t he ar t and ar e i nt ended t o be cover ed by
t he appended cl ai ms.
20 wi t h t he f i r st addr ess on t he page bei ng t hat of t he
25 host comput er . The out put of buf f er 56 of t he ci r cui t
30 i t sel f . The pr edecoder i n t hi s case saves power and
The above descr i pt i on i s i l l ust r at i ve and not
35
-13-
CLAIMS
.. -. .
We claim:
5
i
10
15
20
25
30
35
generator; and
inal of the address
generates a second
+rile a first
generator;
switch.
comprising:
enable switch; and
enable switch, wherein
duration o f the first: a
addresses, and
enable switch is closed
addresses.
-14-
,,
3 . The addr ess gener at or of Cl ai m1, wher ei n t he
second addr ess i s out put t o t he out put t er mi nal of t he
addr ess sequencer onl y when t he i nt er nal addr ess enabl e
swi t ch i s cl osed.
5
4. The addr ess gener at or of Cl ai m1, f ur t her
compr i si ng a buf f er ser i al l y connect ed bet ween t he
out put t er mi nal of t he addr ess sequencer and t he out put
t er mi nal of t he addr ess gener at or .
10 .
I
Cl ai m2 , f ur t her
7. The addr ess gener at or of Cl ai m2 , wher ei n t he
25 addr ess sequencer i ncl udes a count er havi ng a mast er
por t i on and a sl ave por t i on.
8. The addr ess gener at or of Cl ai m1, f ur t her
compr i si ng means f or pr ovi di ng an ext er nal l y gener at ed
ext er nal l y gener at ed addr ess i s a f i r st addr ess of a
page of t he r andomaccess memor y.
30 addr ess t o t he addr ess i nput t er mi nal , wher ei n t he
f o r a ser i al l y addr essed
-15-
5
10
pr ovi ded f r om
addr ess ;
subsequent addr e e sequence of addr esses,
a second addr ess i n ence bei ng pr ovi ded as
an out put addr ess
gener at i on of t h
er nal sour ce as an out put
encer f or gener at i ng t he an addr ess
s sequencer t o
e t i me t hat
t he f i r st addr es r ovi ded f r omt he
ext er nal sour ce.
20
addr esses f or addr essi ng a r andom
addr ess, t he second
at l east a par t of a
pr ovi di ng t he f i r st addr ess.
-.
15
compr i si ng t he st eps of :
25
-16-
* ,
. _I
*. .
5
10
15
20
25
i
SERIAL ADDRESS GENERATOR FOR BURST. MEMORY
J i nyong Chung
Mi chael A. Mur r ay
J
ABSTRACT
A ser i al addr ess gener at or f or a sequent i al ( bur st
mode) r andomaccess memor y gener at es a sequence of
i nt er nal l y gener at ed addr esses f or f ast cycl i ng.
st ar t addr ess i s ext er nal l y pr ovi ded. Then, as t he
cl ock si gnal s ar r i ve, t he subsequent addr esses ar e
geher at ed i n sequence by t he addr ess sequencer . The
addr ess sequencer i s pr eset t o t he second addr ess i n
t he sequence f ol l owi ng t he st ar t addr ess.
Si mul t aneousl y, t he st ar t addr ess i s connect ed by an
ext er nal addr ess enabl e swi t ch t o an out put t er mi nal of
t he addr ess gener at or , bypassi ng t he addr ess sequencer .
When t he f i r st cl ock si gnal ar r i ves at t he addr ess
sequencer , t he addr ess sequencer out put i s sampl ed by
cl osi ng an i nt er nal addr ess enabl e swi t ch and openi ng
t he ext er nal addr ess enabl e swi t ch. Thus t he
i nt er nal l y gener at ed addr esses ar e pr ovi ded i mmedi at el y
f ol l owi ng t he st ar t addr ess.
t her eby gener at es each addr ess one cl ock cycl e ahead of
t hat i n t he pr i or ar t , and t he out put addr ess i s
pr ovi ded one hal f cl ock cycl e ahead of t hat i n t he
pr i or art .
The
The addr ess sequencer
-17-
Atty. Docket NO. M-2595 US
DECLARATION FOR PATENT APPLICATION
As a below named inventor, I hereby declare that:
My residence, post office address and citizenship are as stated below adjacent to my name.
I believe I am the original, first and sole inventor (if only one name is listed below) or
an original, first and joint inventor (if plural names are listed below) of subject matter
(process, machine, manufacture, or composition of matter, or an improvement thereof) which
is claimed and for which a patent is sought by way of the application entitled SERIAL
WDRESS GENERATOR FOR BURST MEMORY
which (check) [ X) is attached hereto.
[ ) and is amended by the Preliminary Amendment attached hereto.
[ J was filed on as
Application Serial No.
[ ] and was amended on (if applicable).
I hereby state that I have reviewed and understand the contents of the above identified
specification, including the claims, as amended by any amendment referred to above.
I acknowledge the duty to disclose information known to me to be material to the examination
of this application in accordance with Title 37, Code of Federal Regulations, S1.56(a).
I hereby claim foreign priority benefits under Title 35, United States Code, 5119 of any
foreign application(s) for patent or inventor's certificate listed below and have also
identified below any foreign application for patent or inventor's certificate having a
filing date before that of the application on which priority is claimed:
Prior Foreign Application(a) Priority Claimed
(Number ) (country) (DayfMonth/Year Filed)
(Number (Country) (Day/Month/Year Filed)
(Number) (Country ) (Day/Month/Year Filed)
Yes No
Yes No
Ye5 No
I hereby claim the benefit under Title 35, United States Code, 5120 of any United States
application(s) listed below and, insofar as any subject matter of this application is not
disclosed in the prior United States application in the manner provided by the first
paragraph of Title 35, United States Code, 5112, I acknowledge the duty to disclose material
information as defined in Title 37, Code of Federal Regulations, 51.56(a) which occurred
between the filing date of the prior application(s) and the national or PCT international
filing date of this application:
(Application Serial No.) (Filing Date) (Status-patented, pending, abandoned)
(Application Serial No.) (Filing Date) (Status-patented, pending, abandoned)
Rev. 931109 - 1 -
Atty. Docket No. M-2595 US
I hereby appoint the following attorney(s) and/or agent(s) to prosecute this application anc
to transact all businesa in the United States Patent and Trademark Office connected
therewitht
Alan H. MacPherson (24,425); Thomas S. MacDonald (17,774); Richard Franklin
(19,128)r Kenneth E. Leeds (30,566); Paul J . Winters (25,246); Brian D. Ogonowsky
(31,988); David W. Heid (25,875); Guy W. Shoup (26,805); Forrest E. Gunnison
(32,899)~ Norman R. Klivans ( 3 3 . 0 0 3 ) ; David I. Carroll (29,903); Edward c. Kwok
(33,938); Patrick T. Bever (33,834); David E. Steuber (25,557); Michael Shenker
(34,250); Laura Terlizzi (31,307); T. Lester Wallace (.34,748)1 Ronald J. Meetin
(29,089); James D. Ivey (37,016); Andrew C. Graham (36,531); Ken John Koestner
(33,004); Hark P. Kahlar (29,178); and Stephen A. Terrile (32,946).
Address all telephone calls to porman R. Klivans at telephone no. (408) 283-1222
Address all correspondence to Norman R. Klivans
SKJERVEN, MORRILL, MacPHERSON, FRANKLIN & FRIEL
25 METRO DRIVE. SUITE 700
SAN JOSE, CALIFORNIA 95110
I hereby declare that all statements made herein of my own knowledge are true and that all
statements made on information and belief are believed to be true; and further that these
Statements were made with the knowledge that willful false statements and the like so made
are punishable by fine or imprisonment, or both, under Title 18, United States Code, s 1001
and that such willful false statements may jeopardize the validity of the application or any
patent issued thereon.
Full name of sole or first inventor Jinvonq Chuna
Inventor's signature Date
Residence LOB Altos Hills.
Post Office Address 12445 Robleda Road
California U.S.A. Citizenship U.S.A.
Los Altos Hills. CA 94022
Full name of second joint inventor, if any Michael A. Murrav
Inventor's signature Date
Post Office Addrese 16432 NE 1 8th Street
Citizenship U.S.A. Residence 2
Bellevue. Waehinaton 98002
Rev. 931109 - 2 -
1
F
Fig. 2A (prior art)
Fig. 2B (prior art)
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N . 0 _ u _ m n z
UNKED STATES DEPARMENT OF COMMERCE
Pat ent and Trademark Office
Address: COMMISSIONER OF PATENTS
Washington. D.C. 20231
FIRSTMEDAFPUCANT I ATN. DocKkko lllRE
APPLlCATlONMJMBER RUNGDATE
03B1/0729
SKJERVEN, MORRILLI MRCPHERBON.
FRANKLIN L FRKEL
25 METRO DR., STE. 700
SFiN .JOSE, CA 95110
NOTICE TO FEE MISSIh'G PARTS OF APP&ICATION
FILING DATE GRANTED
AnApplicationNumberarrdFilingDatehave beenassignedtothis application. However, theitemindicated
below are missing, The required items and fees identified below must be timely Bubmitted ALONG WITH
THE PAYMENT OF A SURCHARGE for items 1 and 3-6 only of 1 . % 0 *06 for large entities or
$ 6'5 - Oafor small entitles who havefiled a verifiedstatement claiming s u i status. The surcharge is set forth in
37 CFR l.l6(e).
.
If all required items on this formm fi led withinthe period set below, the total amountowedbyapplicant as a l3farge
entity, O entity (verified statement fi ed), is $ 1 04
Applicant is givenONE MONTH FROM THE DATE OF TEIS LETI1ER, OR TWO MONTHS FROM THE
FILING DATE of this application, WHICHEVER IS LATER, witbin which to file al l reqkimj items and pay any fees
q u i d aboveto avoidabandonment Extensions of time maybe. obtai nedby fi li ng a petitionaccompaniedby tbe
extensionfee under the provisions of 37 Cmc 1.13qa).
1.0 The statutory basic f i l i ng fee is: 0 missing 0 insufIident. Applicant as a 0 Iarge entity Dsmall
entity, must submit $ to complete the basic filing fee.
2.0 Additional claimfees of $
as a 0 large entity, mall entity, including any
required multiple dependent claim fee, are required. Applicant must submit the additional claim
fees or cancel the additional claims for which fees are due.
3.0 The oath or declaration:
0 is missing.
0 does not cover item omitted at time of execution.
An oath or declaration incompliance with 37 CFR 1.63, identifging the application by the above
Application Number and Filing Date is required.
4.0 The oath or declaration does not identifr the application to which it applies. An oath m declaration
in compliance with 37 CFR 1.63, identifying the application by the above Application Number and
Filing Date, is required.
6. dThe signature(s) to the oath or declaration idare. Mmissing; D by a person other than the inventor
or a person qualitied under 37 CFR 1.42,1.43, or 1.47. A properly signed oath or declaration in
compliance with 37 CFR 1.83. identifying the application by the above Application Number and
Filing Date, is required.
6.0 The signature of the following joint inventor(s) is missing fromthe oath or declaration:
An oath m declaration listing the names of al l inventom and signed by
the omitted inventor(s), identifying this application by t he above Application Number and Filing
Date; ia requi red
7. 0 The application was t iled in a language other than English. Applicant must file a veritied English
under 37 CFR 1.17&), unless this fee has
translation of the application and a fee of $
already been paid
&CIA$
processing fee h required since your check waa returned without payment.
(37 CFFt 1.21(m)).
9. U Your filing receipt was mailed in error because your check was returned without payment.
19.13 The appUcation does not camply with the Sequence Rules. See attached Notice to Comply with
11.0 Other.
Direct the response and any questions about this notice to, Attention: Application Process& Division,
Special Processing and Correspondence Branch (703) 308-1202.
Sequence Rules 37 CFR 1.821-1.825.
/ E/ 5. Ahrn- d
I N THE UNI TED STBTJ S' PATENT AND TRADEMARK OFFI CE
Appl i cant ( s) :
Assi gnee : Mosel Vi t el i c Cor por at i on
Ti t l e:
J i nyong Chung et al .
I .
SERI AL ADDRESS GENERATOR FOR BURST MEMORY
Ser i al No. : 08/265,535 Fi l i ng Dat e: J une 24, 1994
Exami ner : unknown Ar t Uni t : unknown
At t or ney Docket No.: M- 2595 US
San J ose, Cal i f or ni a
August 29, 1994
COMMI SSI ONER OF PATENTS & TRADEMARKS
Washi ngt on, D. C. 20231
Attention: Application Processina Division, Sneaial
s-ikGEIV,
Piicessing and Cor r espondenc e Branch
- - - - -
EEsPoN SE TONOT1 CE TO FI LE M I M G PARTS,
SEP 121!
OF APPLI CATI ON - FI LI NG DATE GRANTED
Dear Si r: WPLICATION[
I n r esponse t o t he "Not i ce t o Fi l e Mi ssi ng Par t s of
Appl i cat i on - Fi l i ng Dat e Gr ant ed" mai l ed by t he Uni t ed St at es
Pat ent and Tr ademar k Of f i ce on J ul y 29, 1994, t he f ol l owi ng
document s ar e encl osed t o compl et e t he f i l i ng of t he above-
i dent i f i ed pat ent appl i cat i on:
1. A decl ar at i on si gned by t he i nvent or s i n compl i ance
wi t h 37 CFR 1.63.
2. Copy of Not i ce t o Fi l e Mi ssi ng Par t s of Appl i cat i on -
Fi l i ng Dat e Gr ant ed.
The Uni t ed St at es Pat ent and Tr ademar k Of f i ce i s her eby
aut hor i zed t o char ge t he f ol l owi ng f ees t o Deposi t Account No.
19-2386:
1. Sur char ge f or f i l i ng decl ar at i on
on a dat e l at er t han t he f i l i ng dat e
of t he appl i cat i on. $130.00
The Commi ssi oner i s her eby aut hor i zed t o char ge any
nddi t i onal f ees whi ch may be r equi r ed, or cr edi t any
nr er payment t o Deposi t Account No. 19-2386.
I t i s her eby r espect f ul l y submi t t ed t hat t he encl osed
l ocument s compl et e t he f i l i ng of t he above pat ent appl i cat i on
i nd j ust i f y t he f i l i ng dat e of J une 24, 1994. Pl ease t el ephone
- 1 -
the undersigned at (408: 283-1222, if there are any questions.
This form is being submitted in triplicate.
Respectfully submitted,
Norman % + P . D w - d R. livans
Attorney for Applicants
Reg. NO. 33,003
1 hereby certify that this correspondence is being deposited with the
United States Postal Service ae flrst class mail In en envelope
cddressed to: Commissioner of Patents and Trademarks, Washington,
D.C., 20231, on
- 2 -
My residency,-& office address and citizenship are as stated below adjacent to my name.
I believ I am the original, first and sole inventor (if only one name is listed below) or
an orig nal, first and joint inventor (if plural names are listed below) of subject matter
OR FOR BURST ME MORY
is claimed and for which a patent is sought by way of the application entitled SERI-
BppRSSS GElOERAT
which (check) [ ] is attached hereto.
(procee c , machine, manufacture, or composition of matter, or an improvement thereof) which
I 1 and is amended bv the Preliminarv Amendment attached hereto.
I hereby state that I have reviewed a n d s t a n d the contents of the above identified
I acknowledge the duty todisclose informatiop known to me to be material to the examination
of this application in accordance with T i p s 37, Code of Federal Regulations, S1,56(a).
' specification, including the claims, as amended by any amendment referred to above.
/
/
I hereby claim foreign
reign application(8)
Title 35, United States Code, 8119 of any
certificate listed below and have also
entified below any foreign application for patent or inventor's certificate having a
ling date before that of the application on which priority is claimed:
Prior Foreign Application(s) Priority Claimed
Yes No
(Number) (Country) (Day/Month/Year Filed)
(Day/Month/Year Filed) Yes No
(Number ) (Country)
Yes No
(Number ) (Country) (Day/Konth/Year Filed) -
I hereby claim the benefit under Title 35, United States Code, 8120 of any United States
application(s) listed below and, insofar as any subject matter of this application is not
disclosed in the prior United States application in the manner provided by the first
paragraph of Title 35, United States Code, 5112, I acknowledge the duty to disclose material
informBtion as defined in Title 37, Code of Federal Regulations, S1.56(a) which occurred
between the filing date of the prior application(s) and the national or PCT international
filing date of this application:
(Application Serial No.) (Filing Date) (Status-patented, pending, abandoned)
(Application serial NO.) (Filing Date) (Status-patented, pending, abandoned)
- 1 - Rev. 931109
. .
Atty. Docket No. M-2595 US
I 'hereby appoint the following attorney( s) and/or agent(s) to prosecute this' application and
to transact all business i n the United States Patent and Trademark Office connected
therewithr
Alan H. MacPherson (24 423 ; Thomas 5 . MacDonald (17,7741; Richard Franklin
(19,128); Kenneth E. & ($0,5661; Paul J. Winters ( w ) t Brian D. Ogonoweky
(31,988)j David W. Held (25, 75); Guy W. Shoup ( 26, 805) t Forrest E. Gunnison
(32,899); Norman R. Klivana J;003 ; David H. Carroll -3); Edward C. Kwok
(33,938); Patrick T. Bever 33 834); David E. Steuber t u ) ; Michael Shenker
' /d (34,250); Laura Terlizzi ,J & 307); T. Lester Wallace (w); Ronald J. Meetin
(29,089); James D. Ivey ( 3 m ; Andrew C. Graham (-1 Ken John Koestner
(33,004); Mark P. Kahler m) ; and Stephen A. Terrile (-6),.
I -
.,
one no. (408) 283-1222
..-
A' - - . -
the like so made
Full name of sole or first inventor w.
- - -,..-.
or's
nce
ffic
3v. 931109
- 2 -
UNITED STAl Eb DEPARTMENT OF CO
Patent and Trademark Offica
Washington. D.C. 20231
/I I I
" I i v
UNITED STAl Eb DEPARTMENT OF CO
Patent and Trademark Of f i ca
Washington. DC. 20231
DATE MAILED 07/29/94
NOTICE TO FILE MISSING PARTS OF APP&ICATION
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'1 I
Direct the response and any questions about this notice to, Attention: Application Processing Diviajon,
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A
Ser i al Number : 08/ 265, 535
Ar t Uni t : 2511
Part 111 DETAILED ACTION
. n.
. ,. .
-2-
Drawi ngs
1.
ar e accept abl e f or exami nat i on purposes onl y. For mal dr awi ngs
wi l l be r equi r ed when t he appl i ca~r on L S al l owed.
Thi s appl i cat i on has been f i ed wi t h i nf or mal dr awi ngs whi ch
Specifica tion
2. The di scl osur e LS obj ect ed t i becx:jse of t he f ol l owi ng
i nf or mal i t i es: On paqe 5, l i ne 5, a addr ess shoul d cor r ect l y be
- - an addr ess- - and at l i ne :9, F. r ; . l J shoul d be changed t o --
Fi gs. l l ( a ) and l l ( b ! - - t o cor r esymd t c t he dr awi ngs; on page 6,
l i nes 30 and 34, t he wor d si gnal s shoul d be changed t o --
cycl es- - t o be mor e accur at e.
r equi r ed.
Apor opr i at e cor r ect i on i s
Claim Rejections - 35 USC 112
3 . Cl ai ms 9 and 10 ar e re; ected under 35 U. S. C. 112, second
par agr aph, as bei ng i ndef i ni t e f oi f ai l i ng t o par t i cul ar 1
out and di st i nct l y cl ai mt hc subject mat t er whi ch appl i cant
r egar ds as t he i nven i on. : t i r: l . $J I T ~R Q and 10, t he ser i al addr ess
gener at or woul d not fcnc:tioii as i l i t rAndod wi t hout an i nt er nal
addr ess enabl e swi t ch and ar L t.xtc-*-.al address enabl e swi t ch.
Ser i al Number : 08/ 265, 535
Ar t Uni t : 2511
- 3-
Claim Ii ej ecti ons - 35 USC 102
4. The f ol l owi ng i s a quot at i on of t he appr opr i at e par agr aphs
of 35 U. S. C. 102 t hat form t he basi s f or t he r ej ect i ons under
t hi s sect i on made i n t hi s Of f i ce act i on:
A per son shal l be ent i t l ed t o a pat ent unl ess --
( a) t he i nvent i on was known or used by ot her s i n t hi s
count r y, or pat ent ed or descr i bed i n a pr i nt ed publ i cat i on
i n t hi s or a f or ei gn count r y, bef or e t he i nvent i on t her eof
by t he appl i cant f or a pat ent .
5. Cl ai ms 1-4, 8-10 ar e r ej ect ea under 35 U. S. C. 102(a) as
bei ng ant i ci pat ed by t he Pr i or arr !as shown i n Fi gs. 1B and 2B).
The Pr i or art di s c l os e a ser i al il ic!i e s s yener at or havi ng al l t he
f eat ur es as r eci t ed i n cl ai m 1- 4, 9- 9 and met hod of gener at i ng a
sequence of addr ess as r e c i i - 4 i r i cl ai l ? 10.
Allowable Subj ect Matter
6.
r ej ect ed base cl ai m, but would be al l ovabl e i f r ewr i t t en i n
i ndependent f or mi ncl udi ng a i l of. t he l i mi t at i ons o f t he base
cl ai mand any i nt er veni nq cl ai ms.
Cl ai ms 5- 7 ar e obj ect ed t o a s bei ng dependent upon a
Conclusion
7 . The pr i or ar t made of r ecor d dnd r:ot r el i ed upon i s
consi der ed per t i nent t o appl i cant ' s di scl osur e.
Ogawa (5,097,4471, Ehy c- t a!. [ 5, : 46, 431) and Mor i (5,260,905)
di scl ose semi conduct or i wmor y de-^I rv: : I I ~ I V I ny ser i al access
memor y.
.----- - -
Serial Number: 08/265,535 -4-
Art Unit: 2511
8.
t o S. Ma i at telephone number (703) 305-3497.
Any inquiry concerning this communlcation should be directed
S .M. PRMARY EXAMINER
December 4, 1994
GROUP 2500
UNITED STATES DEPARTMENT OF COMMERCE
Pat ent and Trademar& offi w
Address: COMMlssloNER OF PATENTS ANDmAoEMARKS
Washinnton. D.C. 2w31
I SERIAL NUMBER I FILING DATE I FIRST NAMED INVENTOR I AlTORNEY DOCKET NO. 1
25M1/3215
NORMAN R KLI VANS
SKJ ERVEN MORRI LL MACPHERSON
FRANKLI N P, FRI EL
25 METRO DRI VE SUI TE 700
SAN JOSE Ch 95110
Thls is a communlcatlon fromthe examiner In charge of your appllcation.
COMMISSIONER OF PATENTS AND TRADEMARKS
3 M2595l J S
~ MAMINER
Y I
ARTUNIT I PAPER NUMBER I
251 1
DATE MAILED: /!$L5,94
dI Sepptlcatlon has been examlned Responsive to communlcalbn Hled on his action IS made finat.
A shortened statutory perlod for response to thls actlon is set to explre 3 month(@, - days from the date of thls letter.
Fallure to respondwlthln the pedod for response wlll cause the appllcatton to become Bbandoned. 35U.S.C. 133
Palt I THE FourrwlNQ AITACHMENT(S) ARE PART OF THISACTION
1. NoHCeof References Cbd by Examlner, PT0-892.
3. Notice of Art Clted by Appllcant. PTO-1449.
5. 0 Intormatton on ow to ~~e c t ~rawing Changes, PTO-1474.
2. dNoUce of Draftsmans Patent Drawing Revlew. PTO-948.
4. 0 Notlce of Informal Patent Appllcatlon. PTO-152.
6.
d
Part II SUMMARY OF ACTION
pendlng In the appllcation. 1. CdCI alm \ + \o
20ashns have been cancelled.
3 . 0 claim are allowed.
are rejected.
4.daakns e c
5. d c t m 5 -7 are objected lo.
6 . 0 clalms
7. B(Thls epprrcatron has been ffled Mth infDrmal drawlngs under 37 C.F.R. 1.85 whlch are acceptable for exambation purposes.
8 . 0 Formal clmwlngs are requlred In response Lo thls of f f c e actlon.
9 . 0 The coneded or substiMe draMw have been received on
are subjact to mi r t di on M electton requirement.
. Under 37 C.F.R. 1.84 these drawings
are 0 amepteble; 0 not scceptable (see explanation or Notlca 01Draftsmans Patent DraMngR em, PTO-948).
examiner; Ddisappmved by the examiner (see explanallon).
10. [7 TtwpFoposed addltiDnal or subsUiule sheet@) of drawlngs. filed on
it. 0 The proposeddrawing mrrectlon. nied
120 Admowledgement is made ofthe claim for pdorlty under 35 U.S.C. 119. The certlfled copy has 0 been received 0 not been recehred
1 3 . 0 si nce thh, appt~tion epppears to be in mndltlon tor attowam except for torrnai matters. prosemtion as to the merlts 1sclosed in
14001her
. has (have) been napproved by the
, has been Oapproved; 0 nMppmved (see explanatton).
D been riled In parent appikatlon, serial no. ; nted on
acc4rdsnce wi ththe practice under Ex parte Ouayle, 1935 C.D. 11; 453 O.G. 213.
FmL-3% (Rev. us3)
EXAMINERS ACIlON
Og/26 5 535
TO SEPARATE, HOLD TOP AND BOTTOM EDGES, SNAP-APART AND DI SCARD CARBON
RoUPART
ATTACHMENT
TO
PAPER
FORM PTQBO2 US. DEPARTMENT OF COMMERCE SERI AL No.
(REV. 2-92)
PATENT AND TRADEMARK OFFICE
NUMBER 4
NOTICE OF REFERENCES CITED
I lll~I1111111111111111 llllllIlIIllllI 11111111111111111111IlIIlfllllltll II
2 ,
USCQ5D97447A
United States Patent 119) [II] Patent Number: 5,097,44:
Ogawa et al. [is) Date of Patent: Mar. 17, 199:
[U] SLWCOXDUCTOR MEMORY DEVI CE
HAVISG A SfRlAL ACCESS MEMORY
[75] Inventors: HIrorld Ogmrr, Nagoy.; Mrurld
1731 Auignm: Fujitsu b i t t d , Kawasaki: FuJilru
4.823.x)2 411989 Christopher .._...._......-_.... 3 6 5 ~ 2 1
4.831.192 111919 Tauumi et a. .- ..........-...... 365/2a
4.870.621 9/1989 N W a ........................ 3651230,s
4.885.720 1211969 Hiller ct d. ........................ 3 6 5 1 2 ~
4 . 8 8 m 1211989 Ksumwkr ........................ 36312m
4.891.794 1/1990 Hush e t d. ......._...."...... 365R30.09
Nosuch& %io. both of Japan
4,890.262 12/1989 Hrrhimoio CT d. ._ ............. 3651200
MS I bit4 Kasugd. both of
J a m Primary Lrominrr-Joxph E. Clawson J r.
f21) Appl. KO.: 408,028
.._ 122) Filed: Sep. 15,1989
I301 - Foreign Appllatlon Pri~rlty thu
Scp. 20. 1988 [IF') Japm ................................ 63.235697
IS11 Lt. Q.' ................................................ GllC 7/00
us. a. .................................... 365/200; 365/221;
36mm.09; ~s n 3 6 ; mm9; 36~241;
371/10.2
[Sa] Field of Surcb ................... 365/230.09. 203. 236,
365/241, 239,221; 371110.2
1561 Refercoca Cited
1521
US. PATEh'T DOCUMEhTS
4292.6'14 911981 Scheunemin .................. 363fl30.09
4.Bll.036 311989 Fumuni et J . .................... 365/203
AI:OGW& Agcn:. or F+n- Armstrong, Niksido.
Mamxlstein, Kubovcik k Murray
ABSTRACT
A semiconductor memory device includn a RAM and
a wrial access memory (SAM). The SAM includn M
address counter which generates a slave address and a
rnmtcr address. Tne slave address p r d a thc master
address by half the period of a rerial access strobe sig-
nal. A redundancy decision is made by comparing the
slave address with a redundancy address. When the
master address is supplied I O a dau register provided in
the SAM, the decision result is available. That is. the
SAM can be & immediately after the master
address h supplied thereto.
L57l
20 Claims, 12 Drnring Sheets
4s
L6 40
/
=5W.L
* DOES5
SIGNAL
i'
.......... I ?
U.S. Patent
Mar. 17, 1992
Sheet 1 of 12 5,097,Wi
PRIOR ART
FI G. 1
ROW ADoRESSl
COLUMN 1
ADDRESS
/
I I I I
SAS
I
U.S. Patent
Mar. 17, 1992
Sheet 2 of 12 5,097,447
...
FI G. 2
12 13
REDUNDANCY S A { F , S O M [ - - - - Y I
I
I
I
LATCH I
ADDRES S DECISION
...
F I G.3A
F I G.3B
r
SAS
SAS
SAT
SAD
MAD
SA
SOM
-
Sbeet 3. of 12, 5, Q97. , $47
I
I I
I
I I
. ...
CAD n - l x n X n+l .
I I
i !
I I
t
I
SA t I '
I I 1 1
SOM I
2 LAt
U.S. Patent
ADDRESS DECl S10 N
Mar. 17; 1992
- SOM
LATCH
Sheet 4 of 12
SAD --
(n bits)
...
MAD
I:
. (n bits)
5,097,447
1st 2 ND
10 1 '
FIG. 4
11
13
CAD f >COUNTER cam
-
,--. 20
US. Patent
Sheet 5 of 12 5,097,447
-
m
U.S. Patent
Mar. 13, 1992
...
Sheet 6 of 12 5,097,447
U.S. Patent Mar. 17, 1992 Sheet 7 of 12 5,097,447
I
--
U.S. Patent Mar. it, 1992 Sheet 8 of 12 5,097,447
-..
EXTERNAL
ADDRESS
SI GNAL
I l k w f
.45
" 40
/
49b
U.S. Patent
Mar: 17, 1992 Sheet 9 of 12 5,097,447
FIG. 9
TOFROM MEMORY CELL ARRAY 43
TO/FROM
BUFFER 56
58
%a DECODER
MAD SOM
U.S. Patent M~: 1 7 , 1992 Sheet 10 of 12
5,097,447
... .
0
P
.. .
U.S. Patent
P
P
cj
w
LL
Mar. 17, 1992 Sheet 11 of 12 5,097,447
---
US. Patent Mar. 17,1992 Sheet 12 of 12 5,097,447
2
5 $9 7,44 7
, .
.. ' . * . a
... I I
1
compared with the redundancy address which is pro-
SEMICOSDUCTOR MEMORY DEVICE HAVING grammed infomation indicative of defective cells. and
A SERIAL ACCESS MEMORY a decision is made based on whether both the addr-
are the same. It is noted that the above-mentioned re-
BACKGROUND OF THE WVEN'TION 5 dundancy decision procedure cannot be done until the
The prewnt invention generally relates to a semicon. address of cells requested for accasing. that is, the
ductor memory device, and more particularly to a semi- serial access address S Ami s settled. In the above-men-
conductor memory device having a serial access mem. tioned manner, the serial access cannot be done until the
serial access address SAADis settled and then the redun-
OW.
Generally. an image memory used in the field of Io dancy decision procedure is executed. Even when the
image processing has r wo pons: a random port and a length of a peri od of the serial access strobe 6ignal SAS
serial port. T h e random port is connected to a central is reduced in order to speed up the serial a m % there i S
processing unit fiereinafter simply referred t o as a a limit on the possible length of period due to a t h e
CPU), and the serial ponis connected to a display de- n-ry for the settlement of the serial a - address
vice such as a cathode-ray tube display device. The '' SA^^ and the rfdundancy decision procedure. The
&zess s p d at the serial port is desired to be BSfast tis-- .-mve ~~~f , ~o i j ~d l & j ' e [br & jil&mative in which
possible since it directly influences the image displaying the co~umn addr- c ADi S input in the &drcss mu t e r
%Fed. Particularly, there is a need 10 U X a higher- synchro,,ism with a fall ofthe =rial -strobe
access speed image memory as an image memory used signal SA^.
for high-speed image processing for drawing pictures at Zo
high srueds. , SUMMARY OF THE INVENTION
...
j ,
~
Referring to FIG. 1. there is illustrated a conven-
tional semiconductor memory device having a serial
access memory. Referring to FIG. 1. a semiconductor
memory device 1 includes a random access memory
(hereinafter simply referred to as a RAM) 2. and a serial
access memory (hereinafter simply referred to as a
SAM) 3. The RAM 2 includes memory cells located at
intersecting points where word lines and bit lines inter--
sect. One of the word lines is selected by a row address
supplied from an external device such as a CPU, and
one of the bit lines is selected by a column address sup-
plied thercfrom. The SAM 3 is made UD o f an address
25
3P
-
Abr di ngi y, a general object of the pr mnt inven-
tion is t o provide an improved semiconductor memory
device having a serial access 3emory in which the
aforementioned disadvantages arc eliminated.
Another object of the present invention is to provide
a higher-sped semiconductor memory device having a
serial access memory in which serial access is done
immediately after the serial access signal falls or rises. or
in other words, the column address is inpuf in the ad-
dress counter so that the length of a period of the serial
access signal can be reduced and serial access speed can
...~~. ~~~~
counter 3a. a redundancy decision circuit 3b, a data bc increased. . '
register 3c. and an input/output buffer 3d. The address 35 The above objects of the present invention a n be
counter 30 inputs, as an initial address value for serial achieved by a semiconductor memory device compris-
access, the column address in synchronism with a rise of ing a random access memory including a plurality Of
a serial access strobe signal SAS, and generates a come- memory cells and parallel rcad/writc means for writing
rponding serial access address SAAD The redundancy data and reading data into and from the memory cells
decision circuit 3b compares the serial access address 40 on the basis of address information, and a serial access
SAAD with a predetermined redundancy address, and memory coupled to the random access memory. The
outputs a redundancy switching signal SOM when the serial access memory comprixs a data register device
compared addresses are identical 10 each other. The for storing data 10 be written i nto ot m d from the
data register Jc has storage (register) cells and redun- random access memory and to be input from or output
dancy cells amounting ro one line of the RAM 2. The 45 form; ne data rebslcr
storage cells arc acccsscd one by one in ~r i e in syn- device includs a fint group of reginer cells and a sec-
chronism with Ihe
When
ond group of redundancy cells, fi rst address generating
the redundancy switching signal SOM is supplied to the
dat a register k, t hc redundancy cells are accessed. The
an signal line in
for generating a first addras
buffer 3d wnnects the data
from an initial addr m S U P P ~ ~ ~ from ex t mv d
Jc and input,output in bidirection. devi=. and W n d address generahg device. mupled
However, the mnventional device Is
in
to the fi st address generating device. for inputting the
3 prcscnu the rolio,,,+,g diwrdvaotages. me addrcss f i t serial WO% address and generating a second S e d
addrrrs labelled cAD in
- a d d r a 10 be SUPPfid to the re&m device-
synchronism with a rise ofthe serial acecssstrobe signal 55 The first
coDteDc( 6 5
SAS, .s shown in FIG. 3@). In other words, a timing he second
with which the column address is input corresponds to
Ond serial acCcss address by a predetermind he. The
&e ri wof the serial vccss strobe signal SAS. me n the s e d .CMI memory further comprises a rdundsncy
d d r M counter 30 outpu& the
decision device, COUPlbd I O the fVSr address generating
SA^^and then &e r&u&an~y decision circuit 3b 60 device, for determining whether &e f i t 4 lcctss
outputs the redundancy switching signal SOM to the address the -e as a r duda nc y address. A selecting
da b register k, Thus, the
8- sped of :he device is Coupled tO the dundanc y decision device for
device is not so high.
selecting one of the first and second groups of the data
It is inevitable that a large storage capacity memory register device on the basis of the comparison result
device is conftgured .so as to have a redundancy s t n~c - 65 supplied from the redundancy decision device. The data
lure and therefore redundancy decision procedure is registered in the dam rebster device is .tcesscd in serial
necessarily required. In the redundancy decision proce- form by the m n d serial access address. When the
durc. an address for cells requested 10 be -sed is second serial 8- address is supplied to the data regis-
34 inpuls the
acfcss %Idrcss bas
lcctsL address and Pmg the
address
5, 097, 441
3 4
ter device, the data is input in or output from the data and output device, coupled t o the data register and the
register device in seria. redundancy register, for outputting the data stored in
The aforementioned objects of the prescnt invention the redundancy register in place of data stored in the
a n also be achieved by a semiconductor memory de- data register when the device detects the coincidence.
rice comprising a random access memory including a 5 The aforementioned objects of the present invention
plurality of memory cells and parallel read/writc device can also be achieved by a semiconductor memory de-
for writing data and reading data into and from the vice comprising a register including a plurality of data
memory cells on the basis o f address information, and a registers and storing data composed of a plurality o f bits
serial acccs~ memory coupled to the random access to be output in serial form, output device for sequen-
memory. The address information is divided into IO tially designating the plurality o f data registers and
groups each composed of a predetermined number of sequentially outputting the plurality of bits, a redun-
address bits. The serial access memory comprises a data dancy register replaceable by one of the plurality of
register device for storing data to be written into or data registen, address generating device for simulta-
read from the random a m memory and to be input neously generating a fmt address for scquentialIy desig-
from or output to an external signal line in serial form. I 5 nating the plurality of data registers and a second ad-
The data register device includes a fint group of regis- dress corresponding to an address obtained by incre-
ter cells and 8 second group of redundancy cells, f i s t menting the first address by +1, detecting device for
address generating device, provided for each of the detecting the coincidence of the second address and a
groups of address bits. for generating a part of a first predetermined address, and switching device fw re-
serial acces5 address starting from an initial address for 20 sponding to the detected coincidence and selecting data
corresponding one of the groups of address bits s u p stored in the redundancy register in place of the one of
plied from an external device. and second address gen- the data registers.
crating device, provided for each of the groups of ad- Additional objects. features and advantages of the
dress bits and coupled to the related first address gener- present invention will be apparent from the following
sting device, for inputting the related pan of the fint 25 detailed description when read in conjunction with the
serial access address and generating a part of a second accompanying drawings.
..
. . -
serial access address to b;supplied-to ihe data register
device. The fint serial access address has the Same con-
DESCRIFT*oN OF THE
~~ ~~ ~.
tents BS the second serial access address and precedes FIG. 1 is a block diagram of a conventional semicon-
the second serial access address by a predetermined 30 ductor memory device having a serial access memory;
time. The serial access memory further comprises re- FI G. 2 is a block diagram of the principle of the
dundancy decision device, provided for each of the present invention;
groups of address bits and coupled to the first address FIGS. 3(A)-3(B) arc timing chart5 of signals ob.
generating device. for determining whether the pan of served in the configuration shown in FIG. 2 and the
the firrt serial access address is the same as a come- 35 conventional device shown in FI G. 1;
sponding pan of a redundancy address. A selecting FIG. 4 is a block diagram o f a fundamental structure
device is coupled to the redundancy decision device, of the invention which handles a plurality of address
for selecting one of the firs! and second groups of the bits;
data register device on the basis of the comparison re- FIGS. S(A), S(B), S(C): 5@). S(E), 5 0 , 5(G), and
sults supplied from the redundancy decision device 10 5(H) are timing c ham of signah observed in the config-
provided for the groups of address bits. The data regis- uration shown in FIG. 4;
cered in the data register device is accared in serial FIG. 6 is a block diagram of a fundamental structure
form by the second serial access address. When the of the present invention where an address signal is di-
second serial access address is supplied to the data regis- vided into groups each consisting of birr,
ter device, the data is input in or output from the data 45 FIGS. 7(A). 7(8), 7( 9, . 7( D) , 7(E), 7 0 , 7 ( G) , 7(H),
register device in series. 7(I), 7(J), and 7(K) are ttming c ham of signals observed
T h e aforementioned objects of the present invention in the configuration shown in FIG. 6;
can also be achieved by a semiconductor memory de- FIG. 8 is a block diagram of the entire stmcture of a
rice comprising a memory cell array including a plural- semiconductor memory device according to 8 prefemed
ity of memory cells redundancy memory cells replace- 50 embodiment of the present invention;
able by defective memory cells contained in the mem- FIG. 9 is 8 block dingram of a d d e r , a dab register
ory cell array, a dam register coupled IO the memory and a peripheral circuit thereof;
cell ma y and including i plurality of register cells. the . FIG. 10 is a circuit diagram of M address wunter
dat a register storing a plurality of bits read out from the used in Lbe embodiment shown in FIG. 8;
memory cel l ma y , a redundancy register coupled to 55 ' FIG. 11 is a circuit diagram of a flip-flop uwd in the
the redundancy memory cells and storing dat a Md out ddr t r s counter shown in FIG. 10; and
from the redundancy memory cells, selecting device for FIG. U is a circuit diagram ora redundancy deision
selecting one register cell from among the plurality of &cui1 and a gate and latch circuit used ia the embodj.
register cells on the basis ora serial a m address, frsl men1 shown in FIG. 8.
DESCRIFTION OF THE PREFERRED
EMBODIMENTS
address genernting device, coupled to the selecting 60
device. for sequentially generating (he send a m
&dress, second address nrneratina device. C O U D ~C ~ t o
the fint address generailing de&. for -scqu;ntially A description is given of the principle of the present
generating the serial 8CCeSS address prior to the first invention with reference lo FIG. 2. The configuration
address generating device, device for determining 65 shown in FIG. 2 corresponds to a seriai a m memory
whether the serial access address generated by the sec- provided in a semiconductor memory device according
ond address generating device coincides with an ad- io the present invention. The illustrated configuration
dress indicative of one of the redundancy memory cells, includcs a f i t counter IO, a second counter 11, a redun-
5
5, 097, 447
6
signal SAS which is supplied to the &and countes 11
and the gate and latch circuit 13. The signal
the same time as the signal falls o r vice versa. The
:, ,.first andsewrid count'en.l.0 b d fl'configure amaster-
":. .3a<+, t ype IXp-floph:which'the'fi&t andsecondvunt-
ers 10 and 11 scrvc as a master counter and a slave'
vided for each of the n bits. The address counter 20
rise at .10 outputs the serial access strobe signal S AD consisting of
n Mts' hd ?he master address MAD consisting of n bits.
,&cIock generator 21 generates a c l q ~k si 5al . m having
$bc same &jug ' k. theJerial ~ccess stp& signal SAS,
and a clock signal @ obrained by inverting the clock
Counter. respectively. When the invened serial acccss I S signal @.
strobe signal SAS rim while the iniu+l counfccaddress &. . $mw&' , , FTG.S:~~~?t5~):.5Cc~,.5@?s(E), 50%
sertinn sinnal SATi r "H. the fint Counter 10 idnuts thi'. _ . . &Wand g&\. the slave address%&) conststtng of n
.
_ I . y _ ~ .... . ~ , ~ ~ ~~ ~~ ~ ~.
column address CAD
input column address
as a slave address sig
inputs ihc slave add
with the rise of the serial access strobe signal SAS, and
then outputs the slave address signal S AD as a master
. _ . address signal MAD. As will be described later, the
9, that is, the rise of the h a l access strobe signal SAS.
Thus, it is possible to sun a necessary internal operation
including the redundancy decision proced
serial access strobe signal SAS rim.. As
.j$sible to reduce the pcriod of the serial
signal SAS and thus speed up accessing.
'
and outputs the slave address signal SAD each time the In the aforementioned operation, the master address
.r. 'invened serial address strpbc signal rises . . - MAD to be supplied to the data registu..& settled in
Referring t o a timing chart of FIG. 3(A). the slave 30 synchronism with each ri se of the seria1,access strobe
ddress signal SAD derived from the first counter 10 is signal SAS. Alternatively, it is possible'to supply the
renewed each time the inverted serial access strobe master address MAD lo the data register in synchro-
signal s7is rises, that is, each time the serial access nism with each fall o f the serial access strobe signal
SAS.
rived from the second counter 11 is renewed each time 35 In some of conventional memory devices. the column
the serial access strobe signal SAS rises. T h e redun- address (initial setting address) supplied t o the serial
dancy decision circuit 12 makes a decision on redun- access memory is predecoded by a column decoder
dancy on the basis of the slave address S AD and the provided on the side of the RAM, and is divided into
redundancy address supplied from a read only memory groups. A configuration shown in FIG. 6 is suitable for
(not shown in FIG. 2) provided in the semiconductor 43 such cases.
memory device. T h e redundancy decision procedure is Referring to FIG. 6, an address counter 30 includes a
sulned before the serial access strobe signal SAS rises. group-A counter 300 for lowsrder address bits and a
The redundancy decision circuit I f outputs a signal SA group-B counter 30b for high-order address bits. lhat
which i ndi um the decision result when both the input is, the column address is divided into two groups of
addresses are the same. When the seri al access strobe 45 group A and group B. The number of groups is not
signal SAS rises, the gate and latch circuit 13 is made limited to two. The group-A counter 300 include mas-
open whereby it parses the signal SA as the redundancy ter-slave type flip-flops 31031n which amount to the
switching signal SOM. At almost the same time. the number of bits contained in the group A, and a carry
master address MAD is output from the second counter circuit 32 which outputs a carry QA in response to a
I t. When a data register corresponding to the dat a 50 master output supplied from the flipflop 3ln. A letter
register k shown in FIG. 1 is being a c Mu 1 by the 'M' denotes a master par& and a letter 'S'denotes a slave
master address MAD and the redundancy switching pan. The groupB counter 306 includes master-slave
signal SOM is being outpul. one of the redundancy cells type flipflops &-33mamounting to the number of bits
providcd in the data repister is selected and the %rial contained in the POUP B. A shin c l wk gaerator M
access to the selected redundancy cell is executed. 55 relates to the group A. and generates a clock si@
the serial accers is smed immediately after the with the same timing as t he serial lccess strobe signal
master address MAD and the %rial a& strobe signal SAS, and a clock signal 51 which is rn h v e d signal
SAS are supplied to the data register. As a result. it is of the signal SAS. A shift clock generator 35 rel am t o
possible to reduce the period of the serial a- strobe the group B. . ad gelrerates a clock signal @I with the
signal SAS 60 t hat the %rial a c w s S p e d ULIl be in- 60 same timing as the serial BEcess strobe si& SAS md a
clock signal 51 which is M invcrtcd signal of the signal creased.
In the CBSC of no. 3A. i t should be appreciated that SAS each time the earry QA is supplied from the cany
the decision result S A for the address 'n' is obtained by circuit 32. A redundancy decision circuit 36 is provided
almost a half of the pcriod than the mst er address with the bits supplied from the slave pan of the flip
MAD corresponding to the address SAAD is incre- 65 flops 31o-31n. and a groupA rtdundancy address sup
mented to the address 'n', and the redundancy switching plied from a ROM (not shown) providd in the memory
signal SOM (the decision result) is obtained at almost device. A redundancy decision circuit 37 is provided
the same time as the master address MAD is changed to with the bits supplied from *e slave pan of the 'nip
strobe signal SAS falls. The master address MAD de-
..
7
5,097,447
8
flops 330 -33m. and a group-B redundancy address
supplied from the ROM. The decision results AG and
BG which are derived from the redundancy decision
circuits 36 and 37, respectively, are supplied to a gate
and latch circuit 38, which outputs the redundancy
switching signal SOM blued on the results AG and BO
when the serial access strobe signal SAS rises.
Refemng IO FIGS. 7(A), 7(B). 7(C), 7@), 7E) . 7 0 ,
7(G), 7 a ) . 7(1). 7(J). and 7(K). the slave address SAD
related to the group A is renewed each time the clock
signal 81ri ses, that is, the serial access strobe signal
SAS falls. T h e master address MAD related to the
group A is renewed each time the clock signal @I rim.
that is, the serial access strobe signal SAS rises. When
the group-A counter 300 makes a round of counting, the
carry circuit 32 outputs the carry QA. In response to the
carry QA. the slave address SAD related to the group B
is renewea when the clock signal G2 rim. that is. when
the serial access strobe signal SAS falls, and the master
address MAD related to the group B is renewed when
the clock signal @I rises. that is, the serial acccss strobe
signal SAS r k s .
FIG. 8 ir a diagram of the entire structure of a semi-
...
signal SAT. a clock signal cO5~shaving the m e timing
as the serial access strobe signal SAS, and a clock signal
CpSAj which is Minverted signal of the signal SAS. An
address counter 50 rcceives the column address signal
J and all the clock signals supplied from the clock genera-
tor 496, and outputs the slave address SAD and the
mst er address MAD. A redundancy decision circuit 51
compares the slave address signal SAD with a redun-
dancy address signal supplied from a read only memory
10 @OM) 49c. and outpuls a redundancy decision signal
Sx. The redundancy address signal indicates the redun-
dancy cells provided in the memory cel l ma y 43. A
gate and latch circuit 52 temporarily stores the redun-
dancy decision circuit SH, and outputs the same s the
The decoder 54 consists of fust and second decoders
5Q and 546 BSshown in FIG. 9. When the redundancy
switching signal SOM is inactive, the f i t d d e r 540
is selected. On the other hand, when the redundancy
20 switching signal SOM is active, the xcond decoder 546
is wlected. Each bit o f the decoder output is supplied
with the gates of two MOS transistors T1 and T2,
which arc coupled to corresponding signal lines of a bus
15 redundancy switching signal SOM to a decoder 54.
conductor memory device according to a preferred 58. A data rcgisler 53 has a storage capacity equal t o
embodiment of the present invention. Referring to FIG. 25 one line of the memory cel l array 43, and includes a
8, the memory device includes a RAM 40 and a SAM group 530 of register cells and a group 536 of redun-
(%rial acccss memory) 41. T h e RAM 40 is configured dancy register cells. each of which is coupled l oa corrc-,
BI follows. The RAM 40 is supplied with an external sponding pair o f MOS transistors such as T1 and T2.
address signal which has been multiplexed. An address T h e redundancy register cells are coupled to the cone.
huller 42 receives the external address signal and sepa- 30 sponding redundancy cells provided in the memory Cell
rarely outputs a row address signal and a column ad- array 43. The decoder 54 selects one of the register cells
dress signal. A row decoder 44 decodes the row address on the basis of the supplied master address MAD. ' Ihe
signal, and selects one word line from among a plurality data register 53 is connected to the bit lines of the mem-
of word liner provided in a memory cell array where a ory cell array 43. Turning to FIG. 8. a serial input/out-
plurality of memory cells MC arc arranged in an array. 35 put buffer 56 is interposed between a serial input/output
Some ofthe memory cells arc redundancy cells located terminal 55 coupled to an ext ernal data line (not shown)
at a prcdctermined area in the memory cell array 43. and the data register 53, and passes serial data in the
The redundancy cells are replaceable with (is.. used in bidirection.
place of) defective cells in the memory cell array 43. A FIG. 10 is a circuit diagram o f the address counter 50.
column decoder 45 decodes the column addrcss signal, 40 T h e addrers counter 50 is made up of mluter.slave type
and relccts one bit line out of a plurality of bit lines in flipflops FFo-FF. which amount to the number of bits
the memory cell array 43. A wnw amplifier and I/O of the column address signal.
gate 46 amplifies the potential of the selected bit line, FIG. 11 is a circuit diagram of the muter-slave type
md performs data reading and writing. An input/out. flip-flop FFo Each of the other flip-flops FFl-FF" is
put buffer 48 is interposed between a random input/out- 45 configured in the snme manner m the flip-flop FFo A
put terminal 47 and the sense amplifier and I/O gale 46 slave part S of the flip-flop FFoincludes a first gate 64.
and paws parallel data in the bidirecrion. a v c o nd gate 71 and a slave-side flipflop ED. The fmt
A clock generator 490 is supplied from an extemsl gate 64 is made up of two Pchannel MOS transistors
device such as a CPU with a row addrtss strobe signal 60, 61, and two N-channel MOS transiston 62. a,
m, a column address strobe Signal m, a write en- H) which are totem pole connactcd. The second gate 71 is
able si nd m, and a transfer signal m. ?he transfer made up of three P-channef MOS lransistors 65,66 and
signal h instructs the RAM 40 and the SAM 41 t o 67, and chree N-channel MOS transiston 68.69 and 70,
operate in synchronism with each other. T h e clock which are totem pole Connected. The slave-side flip
generator 494 genent n the initial counter addreu set - flop 80 is made up of four Pchannel MOS transistors
cing signal SAT. which is supplied to I) clock generator 55 72. 73, 74 and 75, and four Nchannel MOS transiston
49b related to the serial access memory 41. Further, the 76.77,78 and 79. The fmt gate 64 inpuu a bit &ofthe
clock generator 490 generates various control signals, col umn addrers signal when the clock signal aSArb "L
which u e supplied to a RAM pori 57 coupled 10 the @ow).' and the clock Signal - 7 is "H (high)': The
slave-side flipflop 80 latches the input addrers bit terminal 47.
On the other hand, the arida- memory (SAM) 60 when the clock signal a ms wi t c he s from "H" to "L"
41 is configured as follows. Tbe clock generator 496 (in other words, &e clock signal switches from
receives a e initial counter address setting signal SAT %" to "H), that is, when the wrial access strobe signal
from the clock generator 490 and the serial access SAS falls. Then the slaveiidc flipflop 80 OUIPUU the
strobe signal supplied from the CPU Tor example. and
latched bit &as a bit Ao' (SAD) to a ms t er part M of
generates the following clock signals. That is, the clock 65 the flip-flop FFoand the redundancy decision circuit 51
generator 496 generales a clock signal Oarof the m e r b o m in FIG. 8.
t hi ng as the initial counter address setting signal SAT, The muter part M includes a fmt gate 85. and a
a clock signal which is an inverted signal of the
master-side flipflop 92. The first gate 85 is made up of
5,097,447
9 10
two P-channel MOS transistors 81,82. and two N-chan- of the serial access strobe signal SAS can be reduced
ne1 MOS transistors 83. 8.4, which are totem pole con- and thus the access speed c an be increased.
nectcd. T h e master-side flipflop 92 is made up of three The present invention is not limited to the aforemen-
Pchannel MOS transistors 86. 87 and 88, and three tioned embodiments. and variations and modifications
N-channel MOS transistors 89.90 and 91. The master- 5 may be made without departing from the scope of the
side flipflop 92 latches the bit &' from the slave pan S, present invention.
when the clock signal U 3 ~ 5 changes from "L" to " H
(in other words. the clock simal % changes from
" H t o "L"), that is. when the &rial ai& str& signal
SAS ri ser. Then the master-side flip-flop 92 outputs the 10
latched bit Ad as a bit &" (MAD) to the decoder 54
(FIG. 8).
FIG. 12 is a circuit diagram of the redundancy deci-
sion circuit SI and the gate and latch circuit 52. The
redundancy decision circuit 51 n exclusive-NOR gates 15
ENt-EN.. a single n-input NAND gate 93. The redun-
dancy decision circuit 5 1 compares the slave address
SAD(Ao'-A.') with the redundancy address (fuse ad-
dress Fo-F.) supplied from the ROM 49c. When both
the addresses are the same as each other. the redun- 20
dancy decision circuit 51 outputs the redundancy.deci-
sion signal SH. The gate and latch circuit 52 includes a
first gate 98, a flip-flop 105 and an output inverter gate
108. The first gate 98 is made up of two Pchannel tran-
sistors 94, 95 and two Nchannel transistors 96. 97, 25
which are totem pole connected. The flip-flop 105 is
made up of three P-channel MOS transiston 99.100 and
101, and three N-channel MOS transistors 102,103 and
104. The output inverter gate 108 ir made up of a P-
channel MOS transistor 106 and an N-channel MOS 30
transistor 107. The gate and latch circuit 52 latches the
redundancy decision signal SH from the redundancy
decision circuit SI when the clock signal 05~s c hanges
from "L" to "H" (or the clock signal Gs c ha nge s "H"
to "L"). that is, when the serial access strobe signal SAS 35
ri ses. Then the redundancy decision circuit 52 outputs,
as the redundancy switching signal SOM, the latched
signal S ~t o the decoder 54 shown in FIG. 8.
A description is given of an operation or the embodi-
ment. When the serial access to the SAM 41 is re- 40
quested. the initial counter address setting signal SAT is
set t o %'"'Thereby, the clock si a1 @sAris switched
to "L" and the clock signal &is switched t o "H".
Thus, the flip-flops FFc-FFI shown in FIG. 10 input
the column address bits &-AR) as the initial address 45
value. The slave pan of the address counter 50 latches
the address bits AwA. in synchronism with a fall of the
.
..I
serial a- strobe signal SAS, and simultaneously
outputs the rlave address SAD (Ad-An'). The address
counter 50 latches the slave rddrcrs SAD on the master claim 1. wherein said f mt addrers generating m&s
ride thereof when the ser i al access strobe signal SAS includes f i t counter meQN for inputting said initial
ri res. Md simul~ancously outpua the master address acccss address supplied from the excernsl device in
MAD (A$'-An" ). The redundancy decision circuit 51 synchronism with a f i t edge of a pulse signal supplied
determiner whether the slave address SAD supplicd from the extenral device and for incrcmenting said fmt
from the address counter Jo coincides with the redun- 55 serial access address in synchronism with the a u k -
dancy address FwF,,. Th e redundancy decision signal quent f mt edges of said pulse signal, and Mid recond
S&diudve of t he comparison result is supplied to the a d d r a generating means includes recond counter
gate a d latch circuit 52, which latches the result SH means for Outputting said f mt serial access address as
when the serial mxs strobe signal SAS rises. and out- said second serial a- address in synchronism with a
puts the same as the redundancy stitching signal SOM. 60 stcond edge of said pulse signal following said f i t edge
In the aforemmtioncd manner, it is possible l o S W thereof bo that mid fin1 serial access address derived
the internal operation such L( address setting for the from said fust address generating means prcceda said
redundancy decision procedure and the redundancy second serial access address derived from said second
decision proccdure from the fall (rise) of the serial ac- address generating means by a difference in time be-
cess strobe signal SAS and to complete the m e when 65 tween the f i t edge and the subsequent second edge of
the signal SAS ri ses (falls). Thus, the serial access opcra- said pulse signal.
tion mbe suned when the serial access strobe signal 3. A semiconductor memory device ILS claimed in
SAS ri ses (falls). Thii mans that the length of a period claim 2, wherein said fmt serial a- address preftdm
What is claimed is:
1. A semiconductor memory device comprising:
a random access memory including a plurality of
memory cells and parallel read/write means for
writing data and reading data into and from said
memory cells on the basis of address information;
and
a serial access memory coupled to Faid random access
memory,
said serial acccss memory comprising:
data register means for storing data t o be written into
or read from said random access memory and to be
input from or output to an external signal lie in
serial form, said data register means including a
f mt group of register cells and a second &roup of
redundancy cells;
fin1 address generating means for generating a first
serial access address starting from an initial address
supplied from an external devicr.
second address generaling means, coupled to said
f mt address generating means. for inputting said
first serial a~c c s s address and generating a second
serial acccss address to be supplied t o said data
register means, said first serial access address hav-
ing the same contents as said second serial access
address and preceding said second serial access
address by a predetermined lime;
redundancy decision means, coupled to said rust ad-
dress generating means, for determining whether
said first serial access address is the same as a re-
dundancy address; and
selecting means. coupled to said redundancy decision
means. for selecting one o f a ' d first and Mcond
groups of said data register means on the basis of
the comparison result supplied from said redun-
dancy decision mcans. said dam registered in said
data register means being a c M e d in serial form by
said second serial acccss address.
wherein when said second serial a- sddrers is
supplied to said data register means, said dam is
input in or output from said data register m w s in
seri es.
2. A semiconductor memory device as claimed in
5,097,447
11 12
said second serial access addrcsr by a half of one period
of said pulse signal.
4. A semiconductor memory device as claimed i n
claim 1, wherein said selecting means includes gate and
latch means for inputting the comparison result from 5
snid redundancy decision means and outputting the
same as a redundancy switching signal in synchronism
with the second edge of said pulse signal.
5. A semiconductor memory device as claimed in
claim 4, wherein raid gate and latch means is outputting I O
said redundancy switching signal during one peri od of
said pulse signal from said second edge thereof.
6. A semiconductor memory device as claimed in
claim 1, funher comprising clock generating means for
generating fin; and second clock pulses which are 180 I 5 said serial accesz memory cornprishg:
degrees out of phax with each other. and said first and data register means for storing data to be written into
second address generating mcans generate said first and or read from said random access memory and to be
second seiial access addresses in synchronism with said input from or output to an external signal line in
fi rst and wcond clock pulses. respectively. serial form, said data register means including a
first group of register cells and a xcond group of
claim 6. wherein said first address generating mans redundancy cells:
includes a slave flip-flop controlled by said first and first address generating means. provided for each of
second clock signals, and raid second address generat- . said groups o f address bits, for generating a pan o f
ing means includes a master flip-flop controlled by said a first serial access address starting from an initial
first and second clock signals. address for corresponding one of the groups o f
8. A semiconductor memory device as claimed i n address bits supplied from an external device;
claim 7. wherein said slave flip-flop provided in said second address generating means, provided for each
first address generating means is connected to said mas- of said groups of address bits and coupled to said
ter flip-flop provided in said second address generating related fi rst address generating means, for inputting
means. the related pan of said first serial access address
9. A semiconductor memory device as claimed in and generating a part of a F o n d serial access
claim I. wherein said first address generating means address to be supplied to said data register means.
includes a plurality of slave flip-flops amounting to the said first serial access address having the m e
number of bits forming said lint serial access address. wntents as said wo n d serial access address and
and said second address generating means includes a 35 preceding said second serial access address by a
prcdetennined time; plurality of master flip-flops amounting to the number
of bits forming said second serial access address. redundancy decision means, provided for each of said
10. A semiconductor memory device as claimed in groups of address bits and coupled to said first
claim 1. wherein said first serial access address is com- address generating means, for determining whether
posed of n bits (n i5 an integral). and said redundancy do the pan ofsaid first serial access address is the m e
address is composed of n bits, and wherein said redun- as a corresponding part of a redundancy address,
dancy decision means includes logic gate means for and
corresponding bits o f raid first serial access address and selecting means. coupled to said redundancy decision
said redundancy address and for outputting the compar- means, for selecting one of said first and second
ison result. groups o f said data register means on the basis of
11. A semiconductor memory device as claimed in the comparison results supplied from said rtdun-
claim 10, wherein said logic gate means includes exclu- dancy decision means provided for the groups of
sive-NOR gates provided for the respective bits to be address bits, said data registered in said data regis-
compared. and a NAND gate which receives output Ler means being accessed in serial form by said
signals of sai dexclusive-NOR gates and outputting the x) second serial .cccss address.
Comparison result. wherein when ssid recond serial access address is
12. A semiconductor memory dcvice as claimed in supplied to said data register means, said da~a is
cldm 1. funher comprising generating means for gentr- input in or output from said data register means i n
ser i es.
generating means generates stid fint rerial access ad- 55 . 18. A semiconductor memory device I L ~ claiared in
dress starting form slid initial address when said indica- claim 17, wherein said f mt addrss generating means
tion signal b supplied to said fin1 address generating includes first counter mcans for inputting said initid
means.
u~ess address supplied from the external device in
13. A mi conduct or memory de* as claimed in Synchronism with a f i ~ t edge of a pulse signal supplied
'claim 1. wherein said initial address corresponds to a 60 from the exrtmal device and for incrementing the re-
column address to be supplied to said random - hted pan of said f i t s e d a- addrcss in synchre
KIlClTlOry.
nism with the fubKquenl first edges of said pulse signal,
14. A mi conduct or memory device as claimed in md said m n d address generating means includes xc-
claim 1, funher comprising a read only memory which and counter means for outputting the related pan of
stores said redundancy address.
65 said f i r st serial access address as the related pan of said
I S. A mi conduct or memory device as claimed in sccond serial a c e s address in synchronism with a m-
claim 1. wherein said semiconductor memow device i~ ond edge of said pulse signal following said fmr d g e
UI image memory device which handles image data. thereof So that said first serial access address derived
16. A semiconductor memory device as claimed in
claim 2, wherein the first edge of said pulse signal is a
falling edge and the second edge thereof is a rising edge.
17. A semiconductor memory device comprising:
a random access memory including a plurality of
memory cells and parallel rmd/write means for
writing data and rending data into and from said
memory cells on the basis of address information;
and
a serial access memory coupled 10 said random access
memory,
said address information being divided into groups
each composed of a predetermined number of ad-
dress bits,
..._
7. A semiconductor memory device as claimed in 20
25
30
45
ating an indication signal, wherein the said first address
,
. . . . . . . . . . . . . . . . . . . . , . . . . . . . . . ". ..t.y . _ . _ _ ...+.-. :. : < . , ';: 'I ;.:'- . .
. . . . . . . . . . . . . . . . . . .
.....
._..
. . . ~~, ~,
. . . . . . . .
......
. . . . . . . . . . . . . . . . .... . . . . . . . .
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US005 14&43lA
United States Patent [I91 [)I ] Patent Number: 5,146,431
[451 Date of Patent: Sep. 8, 1992
Eby et al.
MFMOD Ah'D APPARATUS FOR PAGE
RECALL OF DATA INAh' KOXVOLATILE
DRAM MEMORY DEVICE
Inventors: Mlchael D. Ebg, Battle Gound,
Wash.; Kstsuml Fukumoto, Nara,
Japan; h5icbael J. Griffw, Ciao N.
Pbam, both of Vancouver, Wash.
Assignee: Sharp KabushM Knirha, Japan
Appl. No.: 585,771
'Filed: Sep. 20, 1990
ht. CI.'.... ............................................ Cl l C 8/00
U.S. c1. .................................. 365/238.5; 365/236
Field of Search ..................... 365/236. 238.5..233.
365/235. 230.03
References Cited
US. PATENT DOCUMENTS
4,471.471 9/1984 DcMsria ......................... 365/185 X
4.61 1.309 9/1986 Chuang CI al. ...................... 365/1BS
OTHER PUBLICATIONS
Terada et a!.. "A New Architecture for the NVRAM
an EEPROM Backed-up Dynamic RAM", IEEE Jour-
nal of Solid-Stare Circuiis, vol. 23, NO. I , Feb. 1988, pp.
86-90.
Yamauchi et al.. "A Versatile Stacked Storage Capaci-
tor On Rotox Cel l For Megabit NVRAM Applica.
tions", IEDM 89, Dec. 1989. pp. 25.5.1-25.5.4.
Primoy Exominer-Joseph A. Popek
Arrorney, Agenr. or Firm-Momson B: Foerster
ABSTRACT
In a non-volatile DRAM (NVDRAM) memory device
comprised of NVDRAM cells, each comprising a
DRAM cell and an EEPROM cell, a method and appa-
ratus for the page recall of data whereby the page recall
stan address may be specified by the user through the
memory device's external control pins. A page ofmcm-
ory cells is defined as all of the memory cells connected
to 8 single word line. During any recall operation. data
are recalled from EEPROM to DRAM in only one
memory cell per bit line. The externally specified page
recall stan address is input onto an external pad It is
then transmitted through an address selector circuit into
the inputs of a counter circuit. The outputs of the
counter circuit serve as the page recall s1an address,
which reenters the address selector circuitry to be trans-
miited to address decoding circuitry.
IS71
9 Claims, 5 Draaing Sbeets
................
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Address
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Sheet 4 of 5
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Decoding 1- 225
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U.S. Patent Sep: 8, 1992 Sheet 5 of 5
5,146,431
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logic I state, or as a pull-down, providing a full rail
logic 0 state. Since each memory cell has the same
pullup or pull-down capability, each can independently
achieve the full rail logic states. Either a capacitive or
METHOD AND APPARATUS FOR PAGE RECALL
OF DATA IS AN NOhTOLATILE DRk\ f
MJ3fORY DEVICE
5 current imbalance is established in each memory cell by
the programmed state of the EEPROM ponion of each BACKGROUND OF THE INVENTION
This invention relates generally to an integrated
memory device and, more specitically, to a method and
apparatus for the page recall of data in an W D U M
memory device. ..
An NVDRAM cell has been described in "A New
Architecture for the NVRAM-An EEPROM Backed-
Up Dynamic RAM". lEEE Journal of Solid State Cir-
cuiu, Vol. 23, No. 1. Feb. 1988; by Chuang et al. in U.S.
Pat. No. 4/51 1,309; and in Yarnauchi et al .. "A Versatile
Stacked Storage Capadtor on Flotox Cel l for Megabit
NVRAM Applications", from 1989 International Elec-
tron Devices Meeting Technical Digest, pages I EDM
89-595 through 598. These references are lncorporatcd
herein by reference.
A design related to that of the present invention is
described in the article,submitted herewith as Appendix
With ECC and Redundancy", by Fukumoto et al..
which .is incorporated herein by reference.
An .NVDRAM memory device. as has been de-
cell.
During the recall operation in such an NVDRAM,
both sides of the latch are initially set to the same pt e n-
10 tial, and they are then allowed to charge from that
point. The imbalance between the two sides of the cell
causes the two sides to charge at different r at a, such
that the latch will be predisposed to one of the two
stable states. Therefore. once the latch is set . these two
states will be full rail logic 0 or logic I voltage levels.
Because of this design of static-RAM-based NVRAM
devices, no external initiation of the restore function is
necessary to place full logic levels in the memory cells.
In addition, such WR A M devices are able 10 usc a
2o block mode recall operation, in which all data in all
memory cells in the device me transferred from EL
. .
, PROM (0 RAM simultaneously.
A, entitled "A 256-bit Non-Volatile Dynamic RAM
In contrast, in a dynamic-RAM-bmd WRAMde-
vice WD R A M) , the memory cells have no built-in
25 restore capability. Unlike in a static-RAM-based
h'VRAM. data in each memory cell of an NVDRAM is
stored as a variable charge on a capacitor. There are no
active pull-up or pull-down circuit elements within
EEPROM cell, which of charge . fore, circuitry external to the memory cell itself must be
on a floating gate i n a floating gate MOS transistor, is
used to provide a full rail logic 0 or logic 1 potential on
non-volatile. The advantage of the NVDRAM is that Ihe memory cell capacitor.
while data may be quickly read from and Lacking an externally initiated restore operation fol-
DRAM during normal operation, it can be stored in the lowing an to DRAM data in an
non-volatile EEPROM during power down.
EE- NVDRAM device. the memory cells Will contain de-
PROM data in an NVDRAM, however, is directly
graded logic State 0 or 1 Voltage levels. When the data
accessible and must be transferred to the DRAM before in the DRAM memory cells are subsequentlY read Out
being read.
40 conventional DRAM fashion, these degraded memory
(1)
cell states may result in incorrect data bei g sensed.
a DRAM read/write mode in which the WD R A M Therefore. it is necessary to perform a conventional
operates like a regular DRAM; (2) a store mode in DRAM restore operation during the recall operation to
which the DRAM data is trmsfeerred 10 the EEPROM ensure full logic state 0 or 1 voltage levels h the
to be stored; and (3) a recall mode in which the EE. 45 DRAM cell. This restore operation can only reliably
PROM data is transferred to the DRAM to be accessed. 0 c CW to one memory cell per bit line at any one time.
In the normal DRAM read/write operating mode, Thus. in 8 DRAM- bmd NVRAM device
the EEPROM transistor is turned off, and data are (NVDRAM), S b u l I a r ~ ~ u ~ recall of all memory cells
written to and read from the DRAM cell in the conven- (i.e. block mode recall) is not feasible; only one memory
tional manner -namely. the DRAM transistor is turned so Cell per bit line should be recalled at any one time.
SUMMARY OF THE INVENTION
on when data is to be stored on or read from the DRAM
storage capacitor and, otherwise, is turped off.
When the DRAM data needs to be stored in the EE- Accordingly, it is an object of the present invention
PROM. a store operation, which transfers the D U M to provide a method and apparatus for the page recall of
data to the EEPROM, is executed. The data is now 55 data in M NVDRAM memory device-a page being
stored as charge on the floating gate of the EEPROM defined as all of the memory cells on one word l i e .
transistor. When the EEPROM data needs to be re- Each memory cel l is connected to a diflereot bit line
called to the DRAM, a recall operation is executed. from dl of the other cells on a given page. Thus, in the
This operation involves sensing the logic sUte of the present invention. only one memory cel l per bit line is
EEPROM and, accordingly, charging a full logic state M) recalled during each page r-11 opration- mini&.
I or logic state 0 voltage level onto the DRAM storage ing DRAM data degradation.
I t is another object of this invention to provide a capacitor.
In static-RAM-based NVRAM devices in current method and apparatus by which the starting addras of
use, each memory cel l is essentially a crosscoupled a page recall operation in an NVDRAM device may be
latch which has two stable operating states. These SIB- 65 specified. The user has the option of either recalling
ble states are established by active circuit elements
only a single page of memory cells at the specified ad-
within each of the memory cells. The active circuit dress, or several consecutive pages of cells beginning at
elements act either as a pull-up. providing a full rail the specified address.
includes a DRAM cclbnd,an EEpRo ~ cell. The
DRAM
in series with a storage capacitor, is volatile, while the
which typically includes a MOS transistor 30 each
ConrequrntlyS~there is no 'Or altering
independently' There- lhe capacitor charge On each
data in the
the 35
WDUM has at least three
3
5,146,43 1
4
Recalling only desired pages of memory cells is often
more efficient than recalling every. cell in the device.
For instance, one might want to divide the memory in
the device into several partitions. In this c s e , since each
partition functions as a separate piece of memory and
can be used separately from all of the others, it may be
more efficient to recall data only from those pages com-
prising a certain partition rather than from every page
in the device.
The present invention comprises a method and appa-
ratus for the page recall of data in an NVDRAM de-
vice. The page recall start address may be specified
through an external input pad. The user has the option
of either recalling only a single page of memory cells at
the specified address or consecutive pages o f cells start-
ing at the specified address. Only one memory cell per
bit line is recalled during each recall operation.
?he externally specified start address is input onto an
external pad. It is then transmitted through an address
selector circuit into the inputs of a counter circuit. The
outputs of the counter circuit serve as the page recall
stan address, which reenters the address selector cir-
cuitry to be transmitted t o address decoding circuitry.
BRI EF DESCRIPTIONS OF T HE DRAWINGS
FIG. 1 is a timing diagram of various signals used in
the present invention.
FI G. 2 is a circuit diagram of a counter circuit of the
invention.
FIG. 3 is a circuit diagram of an address selector
circuit of the invention.
FIG. 4 is a top-level block diagram of apparatus of
the invention.
FIG. 5 is a diagram of an array of memory cells i n
conjunction with which the method of the invention is
used.
DETAI LED DESCRIPTION OF T HE
PREFERRED EMBODI MENTS
An NVDRAM device contains a plurality of mem-
ory cells to be recalled. These are shown as memory
cells 500 in FIG. 5. which are connected along bit lints
Bt through Bmr and in addition along recall lines RI
through R, + and word lines WI through W,+,. The
word lines WL are used to address the cells 500, in a
manner t o be described in detail below, and the bit lines
Bar e used to recall data stored in the cells 500. In short,
one word line WL (e.g., WLj, where l <i <n+n) is
addressed at a time, and then all of the bit lines B are
activated simultaneously. Then, the recall tine associ-
ated with the active word line (in this case, Rj) is acti-
vated to recall the data from the cells 500 on the active
word line. This procedure is described in detail below.
The NVDRAM Design
The memory cells 500 preferably include NVDRAM
cells which are 8s described h applicants copending
patent application. filed on %pi. 20, 1990, entitled
Method for Measuring EEPROM Threshold Voltages
in a Nonvolatile DRAM. which is incorporated herein
by reference. However, other NVDRAM cell designs
may be used, and the present invention will be applica-
ble to such cells i f they are arranged in an array such as
that of FIG. 5, and are addressed by word lines or their
equivalent, and undergo recall operations by means of
recall lines or their equivalents.
-.
The Page Recall Apparatus and Procedure
Referring t o FI G. 4. external address pads 100 send
address inputs 115, corresponding to a predetermined
page recall start address, to address selector circuits 90
(shown in FIGS. 3 and 4). These address inputs are
provided as outputs 110 to counter inputs 50 shown i n
FI G. 2 (discussed below). In addition, they are pro-
vided as outputs 220 to address decoding circuitry 225
(shown in FIGS. 3 and 4). T h e address decoding cir-
cuitry generatessignals RLI through RLn+, and signals
WL, through WLn+n.
In FIG. 4, the number of external address pads 100 is
determined by the number of recall lines R L and word
lines WL which need to be addressed. In the preferred
embodiment, there are n+n word lines and recall lines,
and the external address pad generates a binary repre-
sentation of the signals provided to these lines, SO that
there are logi(n+n) (or 1 +log2n) external address
pads.
In FI G. 2, conventional parallel load wunters
(CNT1 through CNT.) 10 are cascaded together in a
conventional counter circuit 70 to construct an n-bit
counter whose outputs 20 are A1 through An. Each
counter 10 has an output Q and inputs DATA, clock
(CK-bar), load bar (LD-bar) and set bar (SET-bar).
Except for counter CNT,, the Q output ofeach counter
is connected to the clock (CK-bar) input of the succes-
sive counter. Every time count up signal 30 is pulsed,
output 20 of the counter circuit increments by 1. Every
time LD-bar 40 goes low, inputs (AD@/ through
AD& 50 are loaded onto outputs (Ai through A,) 20,
respectively. These outputs 20 are decoded to generate
the signals WL shown in FI GS. 4 and 6. Finally, send-
ing SET-bar low resets outputs (A/through AJO) t o
logic zeros.
Referring now to FIG. 4. the counter circuit 70 has as
inputs 50 ihe outputs 110 from a number of address
selector circuits 90, which in turn have inputs 115
40 which are the outputs from the external address pads
100. Preferably, only one of the recall lines and one of
the word lines will be a logical I , the others being 0, as
discussed below.
Given the inputs from the external address pads, the
45 address selector circuit sends the address represented
thereby either to the counter circuit or to the address
decoding circuit, depending upon the internal state of
the circuits 90. Thus. the address signals may be Sent via
outputs 110 to inputs 50 of the circuit 70, and they are
50 then fed back into the circuits 90 for sending t o the
address decoding circuit 225. This procedure, described
below, allows addresses to be selected at random by a
w r , or automatically generated by the apparatus of the
invention.
FIG. 3 is a circuit diagram of one address selector
cucuit 90. which interfaces between an address pad 100
and counter circuit inputs (ADdtthrough AD& 50 in
FIG. 2. There is one such address selector circuit per
address line; in the case of address lines (Althrough A,,}
60 20, there are n address selector circuits in the memory
device. The address selector circuits FIG. 3 is the one
associated with counter input (AD@;) 110.
A pad address input 115 from external address pad
100, which input corresponds to counter input (AD@,)
65 110, is one input into NAND gate 120; the other input is
(C~AEB) 130. The output from NAND gate 120 feeds
through inverter 150 t o become counter input ADps;
110. The output from NAND gate 120 also connects to
55
5
:. 5.146;431
6
the input of transmission gate 160, which comprises an
is1.w. lJO>q F p n n d M.OS tian-
rter 190. l n transmksion'gatk 160,
+=A 200 goes back high and +I,VA 280 goes back low.
From 17 to,tg (after ts).,another address may be loaded
onto external address pad 100 in preparation for another
connected via inverter 190. The gate of transistor 170 at 19). Thus, instead of inputting a new recall address
also receives address enable input +=A 200. from pad 100. one may choose instead to use the incre-
The output of transmission gate 160 flows through IO mcnted address on counter outputs 20 lo automatically
bvt 1W~210' ahd' appears' output 220,.which hputs recall the next consecutive page.'ln this case, during the
:rintoedd.r& daddi ng &ciitryZZSehc%d to address I: subiquent page recall operation. 4 1 . ~ ~ 280 going high
'' kl ect or circuit 90. . . . . ai tz'sends address signals (Ai) 230, which now specify
Another input to address selector circuit 90 is input the address of the next consecutive page.'through trans-
fAi)Z30,-bvH.hich connectsfo transmission gate.240. The. Il..mission gates e . y d inverters 210 to address decoding
output of transmission..gate '240-then !Tows through " circuitry 225.
invener 210 and ends upon as output 220, which is input In operation, as discussed above, the address decod-
to the address decoding circuit 225, as shown i n FIG. 4. ing circuit 225 shown in FIG. 4 is designed such that
Transmission gate 24-9, similarly I O transmission gate only of the word lines WL, and its associated recall line
A60, . comprises n-channel transistor 250. pchannel tran- 20 RL, will be a logical 1 for a given page recall operation.
: sistor 260 and inverter 270, and is controlled by internal Thus, for instance, word line WL, may be activated,
address enable input (+I,vA) 280 into the gate of transis- and'then all of the bit lines Blthrough B, are also acti-
vated. The recall line RLn is utilized to recall the data
dress stored on the entire page o f cells, i.e. all of the cells
is as 25 along word line WL,. The dita.are retrieved by 'the
Gni e Jmplifiers, which may be'convenIiorial'in'dc'sjgn.
:fa] j&&pz< CFj r. i :c:* ~ :
-In FIG. 1, from time bto 11. a start None of the recall lines R L should be activated ex-
add~e?.is:input onto external ad in FIG. 3. cept ihe single recall line which is asseiiatid with ihe
At-time tz, an NVDRAM enable per signal (NE-bar) word line being activated. This is because a recall oper-
goes low. As a result, an LD-bar pulse is generated, 30 ation on other cells can destroy the data in those cells,
+ L ~ A (external address enable) 200 goes low, and +rn;c there being no restore operation being performed on
(internal address enable) 280 goes high. 4 w 200 is those cells.
active (high) during normal operation of the I t will be appreciated that the present invention re-
NVDRAM device but stays deactivated (low) during calls entire pages of data from an array of NVDRAM
page recall. +r.vA 280 is active (high) during page recall 35 cells such as that shown in FIG. 5, utilizing addresses
and is low during normal operation. +AEB (address en- for such pages independently of the source o f the ad-
able) 130 is high at all times during the page recall pro- dresses; in the present application, those addresses may
cess. be input by a user of the device or may be automatically
In the address selector circuit 90 of FIG. 3, external generated by a computer or other circuitry of the inven-
address input 115 from external address pad 100 is in- 40 tion, such as described above relative to the counters of
vened through NAND gate 120, since +phd AEB 130 FIG. 2.
is high. Now, since 4 A 200 is low, transmission gate Thus, in summary, in the present invention, one page
160 is off. and input 1 X i s routed through inverter 150 of memory cells in an NVDRAM is recalled at any one
and ends up as A D plcounter input 110. time. A page recall start address is loaded onto pad 100
Output (AD& 110 is now an input 50 IO counter 45 and transmitted through address selector circuits 90 t o
circuit 70 in FIG. 2. Since LD-bar is pulsed low at tz outputs 20 of counter circuit 70. Outputs 20 are then
(LD-bar goes back high a1 ti), counter input (AD p3i) 50 transmitted back through address selector circuits 70 to
is loaded onto counter output (Ai) 20. Counter output address decoding circuitry 225. which translates the
(At) M constitutes one l i e of the page recall start ad- page recall stan address into a formusable by memory
dress specified on external address pad 100 and now Marray 700 as the actual page recall start address. By
appears as input (Ai) 230 back into address seleclor incrementing counter output 20 by 1 automatically,
circuit 90 of FIG. 3.
successive pages of cells can be recalled.
Since ~ I N A 280 went high at 12. address signal At 230 By this method, the abovediscussed advantages of
is now routed through transmission gate 240 and in- the invention are achieved. Specifically, since block
verter 210. AT this point, input (Ai) 230 now enten 55 mode recall is not feasible in an NVDRAM memory
address decoding circuitry 225, which then translates device. the present invention describes a method for
all of the inputs (Ai) 230 them into an address usable as page recall in such a device. Moreover, the method of
the present invention allows a predetermined page re- the actual stari address o f the recall operation.
At 4, the output enable bar signal (OE-bar) goes low call StZTt address to be specified and consecutive pages
and signals the start of a recall operation using the page 60 of memory cells io be recalled.
recall starting address which was initially loaded onto What is claimed is:
external address pad !W. The page recall operation 1. In an "DRAM memory device having address
takes place between 4 and t9. During this operation, lines. an apparatus for the page recall of data, compns-
DRAM data will be restored from a degraded state t o ing:
full logic state 0 or 1 voltage levels.
an external pad connected to the address lines for
inputting a predetermined page recall start address NE-bar returns high at some time after 15 (to reset it),
comprising a plurality of first start address signals, and OE-bar returns high at tg (also resetting). Before 19,
wherein said external pad includes a plurality of at some time 16 and as a result o f NE-bar going high,
250.
ignal flow through counter circuit 70 a
ector circuits 90 during a page recall ope
. .
65
7
5,146,431
...
.
external pad outputs, with each said external pad where each bit line is connected to one of a plurality of
output for outputting one said rust start address first subset of cells in the array ef cells which does not
signal; overlap with others o f said first subsets of the cells 10
a plurality of address selector circuits, wherein one which other bit lines are connected; and where one
said address selector circuit is connected to each 5 word line and a corresponding recall line are connected
said external pad output, each said address selector to each of a plurality of second subsets of cells in the
circuit having a first address selector output for array of cells which does not overlap with others of said
outputting a second start a d d r a signal corre- second subsets of the cells to which other word lines
sponding to one said first start address signal; and bit lines are connected; including the steps of:
a counter circuit having a plurality of counter inputs, 10 (I) activating a single one of the plurality of word
each said counter input being connected t o one said lines, for addressing each cell of the second subset
frnt address selector output for receiving one of of cells to which the activated word line is con-
said second stan address signals, said counter cir- nected. thus creating an activated second subset of
cells;
puts, wherein each said address selector circuit I 5 (2) activating all o f the bit lines, for accessing each
includes an address selector input, and wherein cell in any of the first subsets of cells which is also
each said counter output is connected to one said in the activated second subset of cells; and
address selector input, wherein each said address (3) activating a recall line associated with the acti-
selector circuit has a second address selector out- vated word line, for recalling data from each of the
put corresponding t o one of said fust start address 20 cells which is accessed as a result of step 2.
signals; and 6. An NVDRAM memory device having a plurality
address decoding circuitry having as address decod. of NVDRAM cells, each NVDRAM cell including a
ing inputs said second address selector outputs, said DRAM cell and a corresponding EEPROM cell, said
address decoding circuitry for addressing a page of NVDRAM memory device comprising:
said data. means for reading and writing data to said DRAM
2. The apparatus of claim 1, wherein each said ad- cells;
store mode means for transferring data in said
a first NAND gate having as an input one of said DRAM cells t o said corresponding EEPROM
ixternal pad outputs and an address enable signal, cells; and
and having a NAND gate output; recall mode means for transferring data in said corre-
a first transmission gate having as an input said sponding EEPROM cells to said DRAM cells,
NAND gate output, and having a first transmission wherein said recall mode means comprises means
gate output; for simultaneously transferring data in a plurality
a second transmission gate having as an input one of ofsaid Corresponding EEPROM cells t o a plurality
said counter output, and having a second transmis- 35 of said DRAM cells.
sion gate output; and 7. The memory device of claim 6, further comprising
wherein said first transmission gate and said second a plurality of bit lines and a plurality of word lines, one
transmission gate outputs are coupled together for bit line and one word line being connected to each of
providing one of said first transmission gate output said NVDRAM cells and each of said word lines being
and said second transmission gate output at a time 40 connected to a plurality of said NVDRAM cells, and
as said first address selector output. wherein said plurality of said corresponding EEPROM
3. T?IC apparatus of claim 1, including means for in- cells and said plurality of said DRAM cells are asroci-
crementing said counter outputs. ated with a common word line.
4. An apparatus according to claim 3, wherein said 8. The memory device of claim 7, further comprising
apparatus recalls consecutive pages of data as a function 45 address input means for inputting an address of said
of said incrementing of said counter outputs. common word line.
5. A method for page recall of dam in an ma y o f 9. The memory device of claim 8, further comprising
NVDRAM memory cells, wherein the array includes 8 counter means for generating a plurality of addresses
plurality o f bit lines. a plurality of word lines and a utilized consecutively as said address of said common
plurality of recall liner, wherein one bit lice, one word 50 word line.
line and one recall line is connected to each of the cells; e a e o .
,
cuit funher including a plurality of counter out-
25
dress selector circuit comprises:
30
55
60
65
* '
U.S. Patent ' Sep. 19, 1995 Sheet 9 of 16 5,452,261
1
(FILE 'USPAT' ENTERED AT 10: 17:28 ON 02 DEC 94)
L1
L2
L3
L4
L5
L6
L7
8875 S ADDRESS (3W) ( COUNTER# OR SEQUENCER#)
7556 S FIRST (2W) ADDRESS
5020 S SECOND (2W) ADDRESS
716 S SERIAL? (2W) ADDRESS?
2084 S L1 AND L2
1013 S L3 AND L5
30 S L4 AND L6
FILE 'JPOABS' ENTERED AT 10:33:29 ON 02 DEC 94
4257 S L1 L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
721 S L2
409 S L3
70 S L4
300 S L9 AM3 LID
0 S L11 AND L12
15 S LS AND L11
30 S L8 AND L12
62 S L8 AND L9
4 S L16 AND PRESET?
=>d hi s
(FILE 'USPAT' ENTERED AT 13:48:56 ON 01 DEC 94)
L1
L2 179 S SERIAL ADDRESS
353 S BURST (5w) (MEMORY OR RAM OR DRAM)
L3
L4
8508 S ADDRESS ( 3W) ( SEQUENCER OR COUNTER)
100 S L1 AND L3
FILE 'J POABS' ENTERED AT 14:Ol:ZO ON 01 DEC 94
L5 58 S L1
L6 39SL2
L7 4016SL3
L8 8SL8ANDL9
L9 8 S L8 AND LIO
11111111111111Ill 11111111111111111111111111111111111IIIIIIIIIIIIIIIIIIIllll
z - 2 / , : , . , , ,
1 I I . ' I I;
USCQS2&3905A
United States Patent [I91 11 I ] Patent Number: 5,260,905
Mori
[4s] Date of Patent: Nov. 9, 1993
(541 MULTI-PORT MEMORY
(751 Inventor: Tosbikl Mori, Ibaraki. Japan
[ WAsrignee: MatsurhIta Electric ladushid Co.,
OTHER PUBLICATIONS
Nikkei EIecrmnics pp. 195-219 (May 20, 1985).
A'mory ETuminer-Joseph A. popek
Attorney, Agenr. or Finn-Willian Brinks Olds Hofer
Gilson & Lione
Ltd. Osaka, Japan
121) Appl. No.: 753,882
(221 Filcd: Sep. 3, 1991
1301 Foreign Application Priority Data
[511
S p . 3. 1990 [JPI Japan .................................. 2.233543
Int. '3.' ................................................ GllC 8/00
[521 US. (3. .......................... 365/ 230.05: 365/230.09:
365/189.12; 365/246
365/230.W. 189.12. 221, 189.05
IS81 Meld of Search ................... 36V230.05, 239, 240,
[sal References Ci t ed
FOREIGN PATENT DOCUMENTS
2-150996 6/1990 Japan .............................. 3651230.05
ABsrRAcr
The multi-port mcmory of the present invention is pro-
vided with B random port for describing the graphic
data, a fust serial port for reading the data to be dis-
played, and a second serial port for writing the dynamic
picture image data and which has B transfer mask regis-
ter to transfer the dynamic picture image to a window.
The multi-port memory enables multi-window display
of the dynamic picture imager in a simple circuit struc-
ture, with ensuring high-speed erasure and scroll of the
multi-window.
(571
5 Claims, 8 Draaing Sheets
- 365- 230.09 AL; 2511 SX
C C C Z l X R 5 / 2 5 Gi OC5
u . v - - u u U ~ ~ I L I ~ 1 A~UI VT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION
Page 1 of 3
PATENTNO. : 5, 260, 905
DATED : November 9, 1993
INVENTOR(S) : Toshi ki Mor i
cnrrert ed asshown below:
Col umn 1, Li ne 28, "i " shoul d r ead - - i n- - .
Col umn 1, Li ne 68, "pr ocess posi t i on" shoul d r ead - - pr ocess.
The- - .
Col umn 2, Li ne 22, "ar e, " shoul d r ead - - ar e; - - .
col umn 2 , Li ne 2 6 , del et e "a" ( f i r st occur r ence) .
Col umn 2, Li ne 31, "a" ( second occur r ence) shoul d r ead - - at - - .
Col umn 2, Li ne 49, af t er "ar r ay" i nser t - - 1- - .
col umn 2, Li ne 57, "comput e" shoul d r ead - - comput er - - .
Col umn 3, Li ne 61, del et e "t her e".
Col umn 4, Li ne 61, " 59" shoul d r ead - - 69- - .
Col umn 5, Li ne 5, "l i es" shoul d r ead - - l i nes- - .
Col umn 5, Li ne 11, " 56" shoul d r ead - - 57- - .
Col umn 5, Li ne 14, " 56" shoul d r ead - - 57- - .
Col umn 5, Li ne 33, "f or m" shoul d read - - f r om- - .
Col umn 5 , Li ne 5 3 , "count er , " shoul d r ead - - count er 8.--..
Col umn 5, Li ne 55, "i n" shoul d read - - of - - .
Col umn 5, Li ne 56, "of " shoul d r ead - - i n- - .
I t K catifid that mor appears in the aboveidentified patent and that said Letters Patent is hereby
-
- I
....
UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION
Page 2 of 3
PATENTNO. : 5, 260, 9~5
- November 9, 1993
DATED
INVENTOR(S) : Toshi ki Mor i
torretted assfi om, below:
Col umn 5, Li ne 59, del et e "pr esent ".
it u certified that mor appears in the above-identified patent and that said Letters Patent i s hereby
-
Col umn 5 , Li ne 60, af t er "t he" i nser t - - pr esent - - .
Col umn 6, Li ne 26, del et e "a".
Col umn 6, Li ne 32, del et e "cl ocks".
Col umn 6 , Li ne 41, "i nput t i ng t he" shoul d r ead - - i nput i nt o- - .
Col umn 7 , Li ne 3, "f or m" shoul d r ead - - f r om- - .
Col umn 7, Li ne 21, "t hr ough" shoul d r ead - - t o- - .
Col umn 7, Li ne 2 2 , "t o" shoul d r ead - - t hr ough- - .
Col umn 7, Li ne 4 0 , "out put " shoul d r ead - - out put s- - .
Col umn 7, Li ne 41, af t er "12-1, " i nser t - - and- - .
Col umn 7, Li ne 4 2 , "one" shoul d r ead - - cor r espondi ng- - ,
Col umn 8, Li ne 19, af t er "cor r espondi ng" i nser t - - t r ansf er - - ,
and del et e "t r ansf er ".
col umn 8, Li ne 25, "agat e" shoul d r ead - - a gat e- - .
Col umn 8, Li ne 4 3 , "f or m" shoul d r ead - - f rom- - .
Col umn 9, Li ne 1, " 13" shoul d r ead - - 14- - .
. . . . . - - . . ..
- - .... . ... .
UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION
PATENTNO. : 5,260,905
Page 3 of 3
DATED : November 9, 1993
INVENTOR(S) : Tbshi ki . MGri
It k certi fi edthat error appears in the ahowidentified patent and that s a i d Letters Patent is hereby
Wrrected a~ s h m ~ n below:
Column 9, Line 7 , "ad" should r ead --as--.
Column 9 , Line 53, "on" s houl d read --one--.
Column 10, Line 50,- "form" should read --from--.
~.
Signed and Sealed fflis
Twentyfourth Day of May, 1994 I
Attest
BRUCE LEmUN
Commirrionrr of Parrnrr and Tr adr mor b
AttestirigOfficer
U.S. Patent
Nov. 9, 1993
Sheet 1 of 8 5,260,905
se
RAS.CAS
9
( DTI OE DT se,
U.S. Patent Nov. 9,1993 Sheet 2 of 8 5,260,905
U.S. Patent
5,260,905
US. Patent
I X-
! i
Nov. 3, 1993
Sheet 4 of 8
5,260,905
I
1
I
U.S. Patent
b
iz
Nov. 9, 1993
I
I -
-_ _ _ .
Sheet 5 of 8
.#
Y
2
.c c
b
cv
5,260,905
U.S. Patent
....
Nov. 9, 1993
Sheet 6 of 8 5,260,905
U.S. Patent
NOV.8, 1993
Sheet 7 of 8 5,260,905
....
U.S. Patent Nov. 9, 1993
Sheet 8 of 8
5,260,905
1
MULII-PORT MEMORY
5,260,905
L
mined in accordance with the control signals C1 and U
from the controller 9. ..-... ~.~. ~ . ~ . ~ ~ . ~ ~ ~.
In order to read the serial data from the serial port. a
transfer gate 16 is controlled by a control signal G1
I . Field of the Invention
5 generated from controller 9 by control signals to the
The present invention generally relates to a semicon-
control signal input terminal 22, whereby the data of
ductor memory d e n e and, more particularly to a mu]. one line in the memow array 1 selected by the row
ti-port mmory suiable for use ~f an image memory. address is transferred to the serial data register 2 The
2. Description of the Prior Arl serial address input to the address signal in ut terminal
In M image display apparatus in order to display 0 21 is loaded in the serial d d r w wunler 5. The data
image data o f figures, charactefi, etc. comp&tcd by a selector 3 selects and outputs the data at a bit position of
computer onto a raster-scaming rypc CRT screen, a the serial data register 2 designated by the output from
memory called a frame buffer is needed to store the the serial address counter 8 to the serial data output
image data. A dual-port memory is generally used 85 the terminal to. As the serial address counter 8 counts the
memory for the above putpox, having a random access I s serial clock cycles input through the serial clock input
memory and a serial access memory. Furthermore, the terminal 33, the position of the serial data register 2
dual port memory generally conrains a random port for selected by the data selector 3 moves sequentially to
writinginto the random accc2s memory the image data highn order bits, and accordingly the data of the serial
formed by the computer which is to be generated at an dara register 2 is sequentially read out.
optional position on the CRT. Additionally, the dual *O FIG. 7 is a timing chart showing the serial data trans-
PJnmemory Mntainsserial port fortransferfing data Of fer and reading thereof. T h e input-signals to the control
one line in the random access memory to the =rial signal input teminal 22 are, a RAS signal for control-
access memory and reading the consecutive data necks-
ling the timing to input a row address, a signal for
for the display Onto the CRT from the serial access controlling the timing 10 input a column addrfis and a
memory.
2s m/ msignal for controlling the transfer of serial data.
The dual-pon memory referred (0 above is disclosed, ~t a time ti signal falls, a line address AI of
for instance, in Nikkei Electronics, pp195-219, May
20, 1985 edition by Nikkei MacGrow Hill,
the S t ~ c - the memory =ray 1 10 transfer the serial dam from the
83 shown in FIG. 6, In FIG, 6, a random access address signal input terminal 21, and a logic 0 signal
memory 30
signal indicating the transfer Cycle ofthe
coder and a column 7, A rnem- serial data is input. As a result, a time I3 when the
ory 31 consists of a serial data register 2 for storing data mm
rises data Of the line Of the
rransferred from the memory cell array 1, a
ad- memory array 1 is transferred to the serial data regjster
dress counter 8 for counting serial clocks and a data
selector 3 for selecting an arbitrary bit of data stored in 35
position for reading
the serial data register 2 according to respective outputs
from the serial data register 2 is loaded in the serial
from the serial address counter 8.
address counter 8 by an address A2 input at time 12
Reference numerals 2624 denote terminals of input-
when the signal falls. The serial data transferred to
/output signals and control signals to realize input/out. the serial data register 2 is sequentially read out in syn-
put means to the dual-pon memory. More specifica~ly, 40 chronization with the rising edge of the serial clock 23
reference numerals 20-22 are signal terminals of the which is input after time 13.In this case, a serial daIa CO,
random port. i.e., an input/output terminal of random which is read out fist is the data of the serial data rcgis-
data, an input terminal of address signals and an input ter f dl the position selected by the address A2 loaded in
terminal of control si nals, res ectively The control the serial address counter 8. Afterwards, the content in
signals such p1 m, &, rsp/ aE and the like fed 45 the Serial data register 2 is sequentially read out as C1,
through the input terminal22 are input to a controller 9, c2. a, . . . as the serial address counter 8 counts up in
thereby controlling inside (Le. internal) operations of a synchronous manner with the serial clock cycles input
the memory. On the other hand, signal terminals 23.24 through the serial clock input terminal 23.
of the serial port indicate M input terminal 23 of serial Accessing the memory array through the random
c l o c b counted by the seri al address counter 8 and an 50 pOfl is possible while the data is being read out from the
output terminal 24 of serial data through which serial serial dam register 2, and this can be used for writing the
data stored in the serial data register 2 is output. image data into the memory array 1. Therefore, the
Upon writing the image dam into an arbitrary posi- imaging speed of the image data is improved.
tion of the memory array 1 from the random port, a row However, various functions require the image display
address urd a column address for the memory a ~ i y 1 55 apparatus to achieve a multi-window display. ?hat is.
are, through the address signal input terminal 21 in a not only the image data of figures, characters and the
time sharing manner, t a k a into the address buffers 4,s like compositcd by a compute but Jx, dynamic picture
in accordance with control signals Cl and C2 from the imager such BS video images, etc. are desired to be d i s
controller 9 and input t o the row decoder 6 and column played on the same screen. Since the conventional dual-
decoder 7. thereby accessing the arbitrary position of CO poK memory is provided with the serial ponhaving the
the memory array 1. In the above manner. the image =rial data register in addition to the random port =pa-
data input to the random data inpuUoutput terminal 20 ble of accessing any arbitrary position of the memory
array, if the dual - px~ memory is used for the image is written into the position accessed.
Meanwhile. upon reading the image data fromthe display apparatus, it is possible to substantially incrcax
memory array 1 to the random port. an arbitrary posi- 65 the time which an be allotted to write the da b into the
tion of the memory array 1 is accessed to in the Same memory array 1 from the random wrt. while improving
manner as the aforementioned image data writing pro- the describing speed. However, since the serial poit is
cess position of the memory array accessed is deter- used exclusively to output the data onto the CRT and
BACKGROUND OF THE INVENTION
of memory cell array 1, a TOW de- 30 as the m/
through transfer gate
An address showing a
1
. 5,260.905
3
the memory itself docs not provide a function which
enables the continuous writing of data such 85 the dy-
namic image A considerably complicated circuit has to
be installed outside the memory in order to display the
dynamic images by the conventional image display
apparatus.
SUMMARY OF THE INVENTION
An object of the prcsent invention is therefore to
provide a multi-port memory capable of transferring
data to 8 memory m a y so LE to display a dynamic pic-
ture image or the like at an arbitrary position with the
desired size on the screen in a simple circuit structure.
In order to achieve the aforementioned objective, in
a first embodiment of the present invention, a xmicon-
ductor memory is provided having a memory array
with a random access function, a first wrial access mem-
ory with at least one serial output function, a second
serial access memory with at least one xrial input func-
4
take in the data, a serial address counter which counts
the clock cycles after laking an address signal from the
address signal input means and generates a serial ad-
dress moving sequentially from the bit position where
5 the first and second registers start to take in the input
data t o a bit position of more significance, B serial bit
selector which selects the bit position indicated by the
scdal address, a transfer gate to transfer the content of
the f mt register t o a memory m y . and control means
' 0 for controlling per every bit a transfer control signal
input to the transfer gate in accordance with an output
of the sccond register.
The semiconductor memory embodied by the prcsmt
invention in the abovedescribed structure can transfer
the data for displayinga window of the dynamic picture
image or the like at a desired position on the screen t o a
memory array in accordance with the input data from a
access memory t o the memory array per every bit in BRIEF DESCRIFTION OF THE DRAWINGS
accordance with an output of the memory means.
According t o a second embodiment of the present
invention. a semiconductor memory includes a first
register which takes input data serially in synchroniza-
tion with clocks, input means for inputting transfer
mask data to control the transfer of serial data. a selec-
tor which selects either the data from the transfer mask
input means or the transfer mask data generated inside
the memory, a second register which takes output sig-
nals of the selector, and control means for controlling
per every bit a transfer gate to transfer the serial data in
accordance with an output of the sccond register are
aravided.
These and other objects and features of the present
invention will become clear from the following descrip-
tion taken in conjunction with the preferred embodi-
ment thereof with reference to the accompanying draw-
ings throughout which like parts are designated by like
reference numerals, and in which:
FIG. 1 is a structural diagram of a multi-port memory
according lo one preferred embodiment of the present
invention:
FIG. 2 is a circuit diagram of a transfer gate, a data
register, a data selector and a mask tegister in the multi-
port memory o f FI G. 1;
r - ---
According to a third embodiment of the pr wnt in-
vention a semiconductor memory includes a a serial
data input means, a first register which takes input data
from the serial data input means in synchronization with b of the transfer of da w
clocks, transfer mask data input means for inputting
transfer mask data t o control the transfer of serial data,
a second register which takes data from the transfer
mask data input means synchronously when the first
register takes the input data from the serial data input 45
means, address signal input means for indicating a bit at
the starting position where the first and second registers
stan to take in the data. a serial address counter which
counts the clock cycles after taking an address signal
FI G. 3 is a diagram of an example of the transfer of
FIG. 4 is a diagram explanatory of another example
FIG. 5 is a timing chart o f the memory of FI G. 1
when serial data is input and transferred;
FIG. 6 a StNCtUral diagram of a conventional dual-
port memory;
FIG. 7 is a timing chart of the memory o f FI G. 6
when the serial data i5 transferred and output; and
FIG. 8 is 8 block diagram showing an image dirplay-
hg System 10 which a multi-port memory according to
the present invention is applied.
data;
from the address signal input means and generatis a 50
xri al address sequentially moving from t he bit position
where the fmt and second registers start to rake in the
DETAILED OF THE
PREFERRED EMBODIMENT
input data to a bit position of more significance, a serial The pr mnt invention provides a semiconductor
bit selector which selects the bit position indicated by memory device which includes a serial port for storing
the serial address, t transfer gate lo transfer the content 55 the Serial data such as dynamic picture image or the like,
of the first register t o a memory may. and control a dual-port memory which has a random port for writ-
means for controlling per every bit a transfer control ing and reading IO an arbitrary position of a memory
signal input to the transfer gate in accordance with m array and a serial port for outputting display data t o
CRT. output of the second register.
FIG. 8 shows a system having a color monitor 57
invention, a semiconductor memory includes a there connected t o a color map 56 via a line 59 t o which a
serial data input means, a first register which takes input multi-pori memory 51 according t o the pr mnt inven-
data from the serial data input means in synchronization tion is applied.
with clocks, a second register which t aka transfer mask In this system, the color map 56 is connected, via a
data synchronously when the first register takes the 65 video data bus 66, to the multi-port memory 51 and the
input data from the serial data input means, address color map 56 and the multi.pon memory 51 are con.
signal input means for indicating a bit Pt the starting trolled by a serial port control circuit 55 through lines
position where the first and second registers start to 66 and 67. The multi-pori memory 51is connected to an
According to a founh embodiment Of the prcsent 60
5,260,905
6
imaging hard-ware 53 via data bus 62 and an address data register 11 and mask register 13 in accordance with
bus 63. an output of the serial address counter 14.
Both the multi-pon memory 51 and imaging hard- The second serial address counter 14 functions in the
ware 53 are controlled by the random port control same manner as the first serial address counter 8. The
circuit 54 via lies 64 and 65, respectively. The imaging 5 second serial data register 11 takes in the data from a
hard-ward 53 is connected, via a line 61, to an interface serial data input terminal 25 to a bit position indicated
52 which is connected to a standard bus 60. The multi- by an output of the serial bit selector 12, and the mask
pon memory 51 is connected t o a serial data writing register 13 t aka in an output of the selector 1S t o a bit
circuit 70 viaserial data line 71 and serial mask line 72. position indicated by the output of the serial bit selector
The multi-port memory 51 stores images to be dis- lo 12. The serial bit selector 12, similar to the data selector
played on the color monitor 56. The information stored 3. indicates an arbitrary bit position for the second serial
in the multi-port memory 51 is transmitted, via a video data register 11 in accordance with an output of the
data bus 68, t o the color map 56 sequentially and dis- second serial address counter 14 and indicates also the
played by the color monitor 56. The serial port control same bit position for the mask register 13as the second
circuit 55 controls the transfer of the information stored 15 serial data register 11. A selector 15 is a circuit to switch
in the multi-pon memory 51. To alter the information the mask data t o be input t o the mask register 13 be-
stored in the multi-pon memory 51 through the imaging tween the data input through a mask data input terminal
hard-ware 55 in order t o change the image to be dis- 27 and the data fixed to logic 1 in accordance with a
played on the color monitor 57, the standard bus 60 signal from a mask selection signal input terminal 28.
transmits suitable commands to the imaging hard-ware 20 Terminals of input/output signals and a control signal
53 via the interface 52. The random port control circuit to realize input/output means of signals to the multi-
54 controls alteration of the information stored in the ports memory are designated by reference numerals
multi-port memory 51 according to the information 20-28. Reference numerals 20-22 are signal terminals of
received by the imaging hard-ware 53 through the bus the random port. specifically, 20 being an input/output
61. Addresses of the infomation t o be altered and data 25 terminal of random data. 21 being an input terminal of
for the alteration are supplied through the address bus an address signal and 22 being an input te@nal of a
63 and data bus 62, respectively. The standard bus 60 is control signals. Control signals sent to the control sihnal
connected to an external computer and character data input terminal 22 are input t o a controller 9 thereby to
and graphic data composited by the computer are trans- control the operation inside (Le., internal) the memory.
mitted to the imaging hard-ware 53 through the stan- 30 On the other hand, references 23-28 show signal termi-
dard bus 60. To alter the information stored in the multi- nals o f the serial pon, 23 being a first input terminal of
port memory 51 through the serial data writing circuit serial clock cycles clocks which the first serial address
70, serial data is supplied form the serial data bus 73. counter 8, uses for counting upward 24 being an output
Data regarding an area of the multi-pon memory 51 to tcrminal of serial data through which serial data stored
be altered is sent from the standard bus 60 t o the serial 35 in the first serial data register 2 is outputted, 25 being an
data writing circuit 70 via the interface 52. The serial input terminal of serial data for inputting serial data t o
data writing circuit 70 transfers serial data lines to the the second serial data register 11, 26 being a second
area of the multi-pon memory 51 to be altered through input terminal of serial clock cycles which the second
the serial data line 71 and serial mask line 72 according serial address counter 14 uses for counting upward 27
to data received. Thus, the information of the multi-port 40 being an input terminal of transfer mask data which is
memory 51 is corrected and thereby, the image on the inputting the mask register 13 and 28 being an inpuf
color monitor 57 is altered. terminal of mask selection signals to switch the selector
FIG. I is e. structural diagram of a multi-port memory 15.
51 according to one embodiment of the present inven- When the image data is written in and read out from
tion. In FIG. 1, a random access memory 30 comprises 45 an arbitrary position of the memory cell array 1 from
a memory cell array I t a row decoder 6 and a column the random pon and, when the serial data is read out
decoder 7, a first serial access memory 31 comprises a from the serial data output terminal 24, the memory
firs1 serial data register 2 for storing transfer data from device of the present invention operata in the m e
the memory cell array 1, a first serial address counter 8 fashion as the conventional one shown in FIG. 6.
for counting serial clock cycle and a data selector 3 for 50 The following description is related to the transfer-
selecting the data at an optional bit position stored in the ring operation when the serial data is input from the
serial data register 2 in accordance with an Output from serial data input terminal 25 to the second serial data
the first serial address counter, Multi-port memory 51 register I1 and the content of the sccond serial data
further comprises a first transfer gate 16and buffers 4.5 register I1 is controlled and transferred to the memory
which are in the same StNCtUrC and with the same func- 35 cell array I per every bit. In the following description
tion ES shown of the conventional example Of FI G. 6. selector I5 selects and outputs the transfer mask data
As is apparent from comparison of FIG. 1 with FIG. from the transfer mask data input terminal 27, not the
6, a second serial access memory 32 is provided in addi- data fined t o logic I . to the mask repister 13.
tion to the rust one in the present preferred embodiment A serial address input t o the address signal input
of the invenlion. 60 terminal 21 is loaded in the second serial address
The second serial access memory 32 is comprised of counter 14. The serial bit selector I2 selects the bit
II second serial data register I1 for storing transfer data position of the second serial data register 11 designated
t o the memory Cell array I , a mask register 13 for stor- by the serial address from the second serial address
ing transfer mask data t o control the transfer of data to counter 14, so that the input data from the serial data
the memory cell array 1 from the second serial data 65 input terminal 25 is written into the selected bit position
register 11 per every bit, a second serial address counter of the second serial data register 11. At the Same time.
14 for counting serial clock cycles and a serial bit selec- the serial bit selector 12 selects the same position (i,e.,
tor 12 for selecting the bit positions of the second serial the bit position o f the second send data register 11) BS
....
5,260,905
7 8
a bit position of the mask register 13 to write the trans- The counting number of the second serial address
fer mask data fromthe transfer mask data input terminal counter 14 increases by one for each cycle of the second
27. As serial clock cycles form the second serial clock serial clock 26, thereby moving the bit position Of the
input terminal 26 are counted by the second serial ad- output. i t . , logic "1" of the decoder circuit 50 sewen-
d r a counter 14, the bit position of the second serial 5 tially to a higher bit position of more Significance. Ac-
data register 11 selected by the serial bit selector 12 is cordingly, both the bit position of the latch CirCUit
moved one by one to a higher bit position and accord. within the second serial data register 11 where the serial
inglY, the data fed to the =ria] data input temina] is data 25 is written and the bit position Of the latch Circuit
wucntially written into consecutive bi u of the second within the mask register 13 where the Output Of the
=rial data register 11 the transfer mask data given IO selector 15 is written are sequentially moved. whereby
10 the mansfer mask data input t er mi d 27 is sequen-
Outputs from the serial data input terminal 25 and SCleC-
tially written into consecutive biu of the mask register tor 15 are, in synchroniration with the second serial
13. outputs of the second 11 and
clock 26. written KqUentidly in10 the latch CUCUiu Of
mask register 13 me both sent 10 a second transfer gate the second serial data register 11 and mask 13.
10. when the content of the second serial data register Is The gate is Of data
11 is transferred to one line of the memory array I
which is by the row in the 10-L AS shown in FIG. 2. 0UtP"t Of the second
arraxl input through
address signal input terminal serial data register 11 is connected to one side of the
21 and a control signal input through the control signal
input 22. At this the, since the mask data of 20 output of the mask register 13 is connected to one input
the mask register 13 is a control signal through transfer Of the corresponding AND gate 10-n' The Other
or to prohibit the transfer to the second transfer gate 10 input Of AND lo-' is lo a
per every only the
bits corrcspondiLg to transfer control signal 40 from the controller 9. The
output of each AND gate 10-1 to 10-n is connected to
transferred to the memory array 1.
of the transfer gate IO, second serial data register 11, p h " : ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d i n g Io
serial bit selector 12and mask register 13. T h e serial bit
AND gats 1 ~ - 1 to IO-,,
selector 12 is comprised of a decoder circuit 50, AND 30 comprise for controlling the transfer control
gats 12-" lo I 2-ln and AND gates 12-21 to 12-2n. The signal fed to the transfer gates 10G-1 to 10G-n from the
decoder circuit 50 receives a serial address from the outputs of the mark 13, A( the Same time, the
second serial address COUntCr 14 and outputs a Signal (0
mask register 13, AND gates 10-1 to 10-n and transfer
turn only one of the outputs 1 to n 10 logic "1" SO as 10 g a t s ioG-1 10 1W-n constitute means for controlling
select one bit of each of the second serial register 11 and 35 the
mask register 13. The decoder Circuit50 is formed in the memory 32 10 the random a c c s s memory 30 per every
same structure as the column decoder 7. Outputs 1 to n bit.
of the decoder circuit 50 are input IO the AND g a t s A function of the selector 15 is to switch the transkr
12-11 to 12-In and AND gates 12-21 10 12- h 10which
mask data as described hereinbelow. FIG. 3 is adiagram
a serial clock 26 is input. Therefore, in the arrangement 40 explanatory of the operation when the data from the
as above, the serial clock is sent 10the Output of only transfer mask data input terminal 27 is selected and
one Of the AND 21-11 10 12-10 10the Output of loaded into the mask register 13. In the event that data
the one gate among AND g a t s 12-21 to 12-2n. of a transfer line Y is transferred form the serial data
T h e second serial data register 11 is comprised of register 11 to the memory cell array I to display dy-
latch circuits 11-1 to 11-n. The serial data from the Serial 45 namic picture images at the wi ndow A, B, C on the
data input terminal 25 is input to a data input D of each screen, data of one line is written in the Kcond =rial
latch circuit. A clock input terminal CP Of each latch data register 11 and mask register 13 from the serial data
circuit is connected to an Output of respective AND input terminal 25 and transfer mask data input terminal
gates 12-21 to 12-211 Of the corresponding bit. When a 27 respectively in s)mchronization with the clock
serial clock is input 10 the second serial clock input 50 26. Data (a section Win FIG. 3) of the -nd =rial
terminal 26, 0.5 described earlier. the serial clock is Out- data register I1 corresponding to the transfer bit of the
put from only one of the gates among the AND gat- mask register 3 is transferred to the corresponding ps i -
12-21 to 12-211 by the action of the serial bit xl ect or 12. tion to the line Y of the memory array I. In the manner
and supplied only to the latch circuit connected 10 this as above. the transfer mask data CM be set at an arbi-
one gate. Accordingly, the serial data from the serial 55 wary bit position, and therefore, the desired data can be
data input terminal 25 is written in the latch circuit transferred to a desired optional position on the screen
connected to the AND gate to which the serial clock is by feeding the transfer mask data from the transfer mask
output. data input terminal 27 to the mask register 13. Wi s is
Meanwhile, the mask register 13 cornprim latch useful when the data from the serial pon is transferred
circuits 13-1 to 13-n An output of the selector IS is 60 to a plurality of windows as illustrated in the diagram.
connected to a data input D of each latch circuit. A FIG. 4 explains the operation when a logic "1" is
clock input terminal Cp ofthc latch circuit is connected selected and input to the mask register 13. A logic "1"
to an output of the AND gate 12-11 10 124n of the indicates transfer. If data of the line Y is transferred
corresponding bit. Since the AND gates 12-11 to 12-In from the second serial data register 11 to the memory
drive in the same manner as the AND gates 12-21 to 65 cell array 1 to display a dynamic picture image at a
12-2n, the output of the selector I S is written into the window A on the screen, an address of the starting bit
latch circuit of the same bit position where the serial position X where data is initially to be written in the
data is written. second serial data register 11 is loaded in the second
data
gates loG-I Io and AND gats 'O-'
gate 'OG-' lo 'OG-"'
the Inask data into
Inask register l3 can be 2s agate terminal ofthe corresponding transfer gate 10G-1
FIG. illustratn an or the circuit SINaUre
to 1N-n The transfer control signal 40 is sent 10 the
As described
of =rial data from
, 5,260,905
9 10
serial address counter 13. Then the second serial clock image, for example, television image or the like at a
26 is fed for the number of bits of data necessary for the window on the same screen simultaneously with the
transfer. Accordingly, the data of the necnsary number image data o f figures, characters, etc. constructed on
Of bits are written in the second serial data register 11 the computer. Moreover, the dynamic picture images
from the serial data input terminal 25. At the m e time, 5 a n be displayed at a plurality of windows at optional
a logic I lo indicate the transfer is written into the positions on the screen with high speeds.
same bit position of the mask register 13 ad the second Although the present invention has been fully de-
serial data register 11. When the data (a section W in the scribed in connection with the preferred embodiment
diagram) of the second serial data register 11 corre. thereof with reference to the accompanying drawings,
sponding t o the transfer bit of the mask register 13 is 10 it is t o be noted that various changes and modifications
transferred to 8 psition of the memory array 1 come- are apparent to those skilled in the art. Such changes
sponding to the line Y. the data o f the window A is and modifications are t o be understood as included
transferred onto the screen. Accordingly, if the data to within the scope of the present invention as defined by
indicate the transfer is given as data to be written into the appended claims unless they depart therefrom.
the mask register 13, the data of the necessary bit width What is claimed is:
can be transferred to an arbitrary position by writing 1. A multi-port memory which is a semiconductor
the data of only the number of bits desired t o be trans- memory device comprising:
ferred into the second serial data register 11. Therefore, a memory array comprising means for a random ac-
the time to input serial data can be reduced, enabling cess function;
high-speed operation. Moreover, since the data corre- a first serial access memory comprising a first data
spnding to a window is possible to be transferred to a 20 register for retrieving data stored in the memory
desired position on the screen, the present invention is array serially in synchronization with a first clock;
most effective for the case where the data from the 8 second serial access memory comprising a x Mnd
serial port is transferred to one window as indicated in data register for storing input data serially in syn-
FIG. 4. Although logic 1 is defined as the logic level chronization with a second clock, transfer mask
indicating the transfer of data in the foregoing descrip data input means for inputting transfer mask data to
tion, a logic 0 may be the data t o indicate the transfer control the transfer of serial data t o the memory
depending on the circuit structure, with the same func- array and a third data register for storing the trans-
tion achieved. fer mask data from the transfer mask data input
FIG. 5 is a timing chart when the serial data is written means in synchronization with the sccond clock;
and transferred while the selector 15 is controlled by 30 and
the mask selection signal 28 so that a signal from the control means for controlling the transfer of each bit
transfer mask data input terminal 27 is input to the mask of serial data from the second serial access memory
register 13. As shown in FIG. 5, a =si nal t o control to the memory array in accordance with outputs
t he input timing of the row address, a h signal to from the third data register.
control the input timing of the column address, a 35 2. The multi-pon memory of claim 1 wherein the
m/m signal indicative of the transfer cycle of the
serial data and a DTsel signal to control the transfer of a selector means which selects either the transfer
the serial data are input t o the control signal input termi- mask data from the transfer mask data input means
nal22. or the transfer mask datagenerated inside the mem-
.
second kri al access memory further comprises:
Serial data 25 and transfer mask data 27 which are
input in synchronization with the rising edge of the
second serial clock 26 are written in the second serial
data register I 1 and mask register 13, respectively. A
line address AI of the memory array 1 to perform trans-
fer of the serial data from the address input terminal 21.
a signal of logic 0 indicating the transfer cycle of the
serial data as the m/bF signal and a signal of logic T
as the DTsel signal which indicates that the transfer
cycle transfers the signal of the second serial data regis-
ter 11 to the memory array 1 are input at time t1 when
the signal falls. As 8 result. the data of the serial
data register I1 is transferred to the selected on line of
the memory array 1 at time t3 when t h e m/= signal
rises. An address indicating the starting position to
write into the second serial data register 11 and mask
register 13 by a nexl serial clock 26 is loaded in the serial
address counter 14 by an address A2 input at time 12
when the signal falls.
When the logic I is input to the mask register 13 as
the transfer mask data by controlling the selector 15, the
memory operates in the same manner as shown i n FIG.
5. However, since it is enough to write only the neces-
sary number of bits for the transfer into the second serial
data register I1 and mask register 13, the serial data can
be input in a reduced time.
When using the multi-port memory of the present
invention, such an image display apparatus is realized in
a simple structure that can display the dynamic picture
40
45
50
55
60
65
ory.
3. The multi-pon mcmoryof claim 1 wherein the
address signal input means for designating a starting
bit position where said second and third registers
stan to load the said input data and said transfer
mask data, respectively:
a serial address counter which counts the number of
clock cycles after loading an address signal from
said address signal input means so as to generate a
serial 8ddreu moving sequentially upward form
said starting bi t position to a more significant bit
position; and
a serial bit selector which x1eco the bit position
designated by said serial address counter;
whereby only the data of the desired bits stored in the
second register are transferred to the memory ar-
my.
4. The multi-port memory ofclaim 1 wherein the first
serial access memory comprises:
a serial data output porr;
a serial data register for storing data transferred from
the memory array; and
means for transfemng an arbitrary number of data
bits stored in the serial data register to the serial
data output pon in a sequential manner.
5. The muhi-port memory of claim 1 wherein the
memory array Comprises a random port for reading and
writing data in the memory array.
second serial access memory further comprises:
e o . . .
Form TO 948 (Rev. 10.93)
L
r
U S DEPARTMENT OF COMMERCE - Patent md Tradcinwk Oflice Application No. 75135535 A>
NOTICE OF DRAFTSPERSIN'S PAlENT DRAWING WVIEW
FTO DraApersons review all originally filed drawings regardless of whether they are desigtiated as formal or informal. Additionally.
patent Examiners will review the drawings for compliance with the regulations. Direct telephone inquiries concerning this review to
Modifledforms. 37CFR l.&l(h)(S)
- Modified forms of Eonsuuction must be shownin separate views.
Fig(s)-
drawings when n ccc~~a t y . Canxted &awI?gs must be. submitted
pccording toIhc LnsrmCtions 00 tk back of this Notice.
1. DRAWINGS. 37CFR 1.Wa): Acceprable categorlcs of drawlngs:
Blackfnlc Color.
- Not black solid Liots. Fig(s)
- color drawings an DOL aneptable until petitionIs granted.
2. PHOTCGRAPHS. 37 CFR 1 . 8 4 )
- Phoiographs are not aaccprahle until petition is granted.
3. GRAPHIC FORMS. 37 CFR 1.84 (d)
- Chemical M m a k d c a l formula nM l abel edas separate figure.
- Gmup of wavefom not presented as a single figurc, using
W s )
Fim-
cornmoo vdcal axis with time extending along horizontal axis.
- individuals waveformnot identified with a scpamtc lcttcr
dcslgnallon adj ant to thevmical axis. Figfs)
4. "E OF PAPER 37 CFR 1.We)
- papcr m flexible. saay. white, smooch. nonshiny, anddurable.
- Emurcs. altuaticms.ovawritings, interlineations, cracks. creases.
SbCcl(S)
and folds DM allowmi Shcd(S)
S. SIZEOFPAPER. 37CFRl.WO: Aaatptablepapersizes:
2 1 . 6 1 ~ by3 5 . 6 ~1 ~ (8 V2by I4 inches)
21.6cmby33.1 cm.(SV2by 13inches)
21.6 c m by27.9 cm. (8 If2 by 11 inchcs)
21.0 em by29.7 cm. (DIN size A4)
- All drawing sheets not thc same size. Sheet(s)
- Drawing sheet not an acceptable size. Sheet(s)
5. MARGINS. 37 CFR i.E4(g): Acceptable margins:
2.5 -(I*) 2.scrn.(l")
"1 . Wcm. (114") . Wcm. (U4
") . Wnn (U4'7 .M cm. (114
1. VIEWS. 37 CFR 1 . W)
REMINDER: SpedIication mayrequire revision to correspond to
&awing changes.
- Au vkws no( gmupcd togetha. Fig(s)
- vlcwscontalnantcrLincJ. Fig@)
- scpararcshcct s no( (inLed edge I O edge.
- Vkw connoncd by poJect ion lincs. Fig(s)
'anial views. 37 CFR I.WhX2)
+A* n DM l ahel edseparately.
- Long d w relatiwship betweendilfercnt parts not clear and
unambiguous. 37 CFR 1.84(hXZXii)
WJ)
Fig(%)
sufficiently. Fig@)
l i nw. Fig@)
Fig@)
way. FigW
Figw
dodal views. 37 CFR i.84@)(3)
- Hatching not indicated for sectional portions of anobject
- Hatching of regularly spaced ohliquc parallel lincs not spaccd
- Hatching no( at substantial angle to surrounding axes or principal
- OOSS section notd r a m same as viewwithparts incross section
wi thregularly spaced parallel oblique strokes.
- Hatching of juxtaposed different elements notangled in a different
ltcmate pmltlon. 37 CFR l.&l(hX4)
- A scparau; viewrquiral for a movedposition.
8. ARRANGEMENT OF VIEWS. 37 CFR 1.84(1)
- View placed uponanother vlew 01 within outlineof another.
Ws )
- Words do not appear Ina horlmntal. left-&right fashion when
page is either uptight or huncd sa that (hc top becomes theright
side, excepl for grdphs. Fig(s)
9. SCALE. 37 CFR 1.84(k)
- Scale noi large enough to showmechanism without uowdiig
whendrawing io reduccdin slzc to two-lhirds io r e~uc t i on.
Fie(s)
- Indication such as "auual slzc" M "scale li2" notoermittcd.
Fit&)
Fig($)
- Elements of same viewnM in proportion to eaJl other.
R OF LINES, NUMBERS. &LETTERS. 37 CFR 1.84131
&letters not uniformly thlck andwell detlned.
1 I. SI4L)ING. 37 CFR l.&Ym)
- Shading used for otha &an shape of spherical, cylindrical. and
- Solid black shading area8 not permitted. Flg(s)
conical elements of an &]EL or for flat p a .
Ws )
12. NUMBERS. LETIZRS, & REFERENCE CHARACTERS. 37 CFR
I. Rzl nY
x u m b e r s l,84(pXI) and n s c 8 ) ~ j & ~ 8 c ~ [ refe
- Numbersand reference characters used in cunjuction with
By and legible. 37 CFR
brackets, lnvened commas, or enclosed within outlines. 37 CFR
1 .WPXO Fig(s)
- Numkn and referem charactas not oriented in same direction as
the view. 37 CFR 1.84@)(1) Fig@)
h alphabet not used. 37 CFR 1.84@K2)
Numbers, letters, and reference charscctrs do Rd measureat least
eight. 37cFR@)(3) A .32c . Bin
Fig(s@&R
13. LEAD LINES. 37 CFR 1.84(9)
- hadudes cross each &. Fig(s)
- Lead lines missing. Fig(s)
- Lead lines notas short as possible. Flg(s)
14. NUMBERING OF SHEETS OF DRAWINGS. 37 CFR t.M(t)
- Numberappears In top margin. Fig(s)
- Numbernot larger than nfaence charact ers.
Fi gw
- Sheets not numbered consacutively, andin Arabic numerals,
beginning withnumbcr 1. Sheet(s)
15. NUMBEROFVIEWS. 37CFR 1. B. y~)
- Views nM numbered consecutively, andinArabic numerals,
- View numbers not preceded by the abbreviation Fig.
__ Singlc vicw conlaills a viewnunlkr and thc abhrcviation Rg.
- Nurnhersnotlarger thanrefcrenu: characters.
beglnning withnumbu 1. Fig@)
Ws )
FMs)
\
16. CORRECTIONS. 37CFR I.Ww)
- Corrections not durable andpermanent. Fig@)
17. DESIGN DXAWING. 37- 1.152
- Surface shading shownnot appropriate. 'Fig@)
- Solid black shadint notused for wlor wnmt.
'
Fig(s)
3-'
L
"c'
I N THE UNI TED STATES PATENT AND TRADEMARK OFFI CE
Appl i cant ( s) :
Assi gnee: Mosel Vi t el i c Cor por at i on
Ti t l e:
Ser i al No. : 08/265,535 Fi l i ng Dat e: J une 24, 1994
Exami ner : S. Mai Ar t Uni t : 2511
At t or ney Docket No. : M-2595 US
J i nyong Chung et al .
SERI AL ADDRESS GENERATOR FOR BURST MEMORY
COMMI SSI ONER OF PATENTS AND TRADEMARKS
Washi ngt on, D. C. 20231
WEC EIVEB
FEB 2 2 IF95
GREOCJP 2580
AMENDMENT
Si r:
Appl i cant s submi t t he f ol l owi ng amendment s and r emar ks i n
response to t he Of f i ce Act i on i n t hi s case dat ed December 15,
- 994.
t o - - an addr ess- - ;
t o - - Fi gs. l l ( a)
i n each l i ne
nd 11 ( b) show- -
3 - - - cycl es- - . /
l i ne 8 ch nge ' Fi g. 11" t o - - Fi gs. l l ( a) ,
. ( b) --.
At page df 3 3 $ / g e tlANii t o - - An- - .
At page 1 l i ne 31 change "Fi g. 11" t o - - Fi gs. l l ( a) ,
(b) --.
1 / / '
Pl ease amend Cl ai ms d,
1. ( Amended) An addr ess gener at or f or a [ ser i al l y
5, 6, 9 and 10:
i ressedl r andomaccess memor y, compr i si ng:
an addr ess sequencer havi ng a cl ock i nput t er mi nal , a
)#f111/,8 02/17/Y> GKJh!z!~' m' ~ I Y ;'mJ 110 102 228.00CH
I
- 1 -
I
PATENT
pr eset t er mi nal , and an out put t er mi nal ;
an i nt er nal addr ess enabl e swi t ch connect ed bet ween
t he out put t er mi nal of t he addr ess sequencer and an out put
t er mi nal of t he addr ess gener at or ; and
an ext er nal addr ess enabl e swi t ch connect ed bet ween
an addr ess i nput t er mi nal of t he addr ess gener at or and t he
out put tesrni nal of t he addr ess gener at or ;
wher ei n t he addr ess sequencer [ generat es] includes
means f or i ncr ement al l v t i ml nq t he addr ess seuuencer t o
gener at e a second addr ess i n a sequence of addr esses whi l e
a f i r st addr ess i s bei ng suppl i ed t o t he out put t er mi nal
of t he addr ess gensr at or ' by t he ext er nal addr ess enabl e
swi t ch.
2. ( Amended) The addr ess gener at or of Cl ai m1, f ur t her
compr i si ng:
means f or cont r ol l i ng t he i nt er nal addr ess enabl e
swi t ch; and
means f or cont r ol l i ng t he ext er nal addr ess enabl e
swi t ch, wher ei n t he means f or cont r ol l i ng t he ext er nal
addr ess enabl e swi t ch closes [ oper at es t o cl ose] t he
ext er nal addr ess enabl e swi t ch f or a dur at i on of t he f i r st
addr ess of t he sequence of addr esses, and
wher ei n dur i ng t he dur at i on t he ext er nal addr ess
enabl e swi t ch i s cl osed, t he addr ess sequencer gener at es
t he second addr ess i n t he sequence of addr esses.
5. ( Amended) The addr ess gener at or of Cl ai m2, f ur t her
compr i si ng means f or pr ovi di ng a pr eset si gnal of a
pr edet er mi ned dur at i on and l evel t o t he pr eset t er mi nal dur i ng
at l east a por t i on of t he dur at i on of t he f i r st addr ess, t he
pr eset si gnal set t i ng t he addr ess sequencer t o t he second
addr ess i n t he [ seri es] - o f a d d r e s s e s .
L\DMSW6%M-ZS9S-U\Oll7693 .WP - 2 -
PATENT
v L,
6. ( Amended) The addr ess gener at or of Cl ai m2, f ur t her
compr i si ng means f or pr ovi di ng [a ser i es of ] cl ock si gnal s of
pr edet er mi ned l evel t o t he cl ock i nput t er mi nal , a f i r st of t he
[ ser i es of ] cl ock si gnal s occur r i ng onl y af t er t he dur at i on of
t he f i r st addr ess.
9. ( Amended) An addr ess gener at or f or a [ ser i al l y
addressed] r andomaccess memor y, compr i si ng:
means f or pr ovi di ng a f i r st addr ess i n a sequence of
addr esses, t he f i r st addr ess bei ng pr ovi ded f r oman
ext er nal sour ce as an out put addr ess;
an addr ess sequencer f or gener at i ng t he subsequent
addr esses i n t he sequence of addr esses, a second addr ess
i n t he sequence bei ng pr ovi ded as an out put addr ess
i mmedi at el y f ol l owi ng t he gener at i on of t he f i r st addr ess;
[andl
an i nt er nal addr ess enabl e swi t ch connect ed bet ween
;
t er mi nal of t he addr ess sener at or :
an ext er nal addr ess enabl e swi t ch connect ed bet ween
3
;
means f or [ pr eset t i ng] i ncr ement al l y t i mi ns t he
addr ess sequencer d r i n t o gener at e t he
second addr ess at a same t i me t hat t he f i r st addr ess i s
bei ng pr ovi ded f r omt he ext er nal sour ce.
10. ( Amended) A met hod of gener at i ng a sequence of
addr esses f or addr essi ng a r andomaccess memor y, compr i si ng t he
st eps of :
pr ovi di ng f r oman ext er nal sour ce a f i r st addr ess i n
t he sequence as an out put addr ess;
swi t chi ns i n t he f i r st addr ess as an out 0 ut addr ess
dur i nq a Dr eset per i od:
- 3 -
PATENT
t hen, pr ovi di ng f r oman addr ess sequencer a second
addr ess i n t he sequence as an out put addr ess, t he second
addr ess bei ng gener at ed bv i ncr ement al t i mi nq dur i ng at
l east a par t of a dur at i on of t he st ep of pr ovi di ng t he
f i r st address; and
swi t chi ns i n t he second addr ess as an out t)ut addr esq
I
af t er t he wr eset Der i od.
Pl ease add newCl ai ms 11- 14:
11. The addr ess gener at or of Cl ai m2, wher ei n t he means
f or cont r ol l i ng t he i nt er nal addr ess enabl e swi t ch i s a l ogi cal
i nver si on of t he si gnal s pr ovi ded t o t he cl ock i nput t er mi nal .
12. ?in addr ess gener at or f or a r andomaccess memor y,
compr i si ng:
an addr ess sequencer havi ng a cl ock i nput t er mi nal , a
pr eset t er mi nal , and an out put t er mi nal ;
an i nt er nal addr ess enabl e swi t ch connect ed bet ween
t he out put t er mi nal of t he addr ess sequencer and an out put
t er mi nal of t he addr ess gener at or ;
an ext er nal addr ess enabl e swi t ch connect ed bet ween
an addr ess i nput t er mi nal of t he addr ess gener at or and t he
out put t er mi nal of t he addr ess gener at or ; and
means f or pr ovi di ng a pr eset si gnal of a
pr edet er mi ned dur at i on and l evel t o t he pr eset t er mi nal
dur i ng at l east a por t i on of t he dur at i on of t he f i r st
addr ess, t he pr eset si gnal set t i ng t he addr ess sequencer
t o t he second addr ess i n t he ser i es;
wher ei n t he addr ess sequencer gener at es a second
addr ess i n a sequence of addr esses whi l e a f i r st addr ess
i s bei ng suppl i ed t o t he out put t er mi nal of t he addr ess
gener at or by t he ext er nal addr ess enabl e swi t ch.
13. An addr ess gener at or f or a r andomaccess memor y,
- 4 -
.-.,,
PATENT
compr i si ng:
an addr ess sequencer havi ng a cl ock i nput t er mi nal , a
pr eset t er mi nal , and an out put t er mi nal ;
an i nt er nal addr ess enabl e swi t ch connect ed bet ween
t he out put t er mi nal of t he addr ess sequencer and an out put
t er mi nal of t he addr ess gener at or ;
an ext er nal addr ess enabl e swi t ch connect ed bet ween
an addr ess i nput t er mi nal of t he addr ess gener at or and t he
out put t er mi nal of t he addr ess gener at or ; and
meana f or pr ovi di ng cl ock si gnal s of pr edet er mi ned
l evel t o t he cl ock i nput t er mi nal , a f i r st of t he cl ock
si gnal s occur r i ng onl y af t er t he dur at i on of t he f i r st
addr ess;
wher ei n t he addr ess sequencer gener at es a second
addr ess i n a sequence of addr esses whi l e a f i r st addr ess
i a bei ng suppl i ed t o t he out put t er mi nal of t he addr ess
gener at or by t he ext er nal addr ess enabl e swi t ch.
14. An addr ess gener at or f or a r andomaccess memor y,
compr i si ng:
an addr ess sequencer havi ng a cl ock i nput t er mi nal , a
pr eset t er mi nal , and an out put t er mi nal ;
an i nt er nal addr ess enabl e swi t ch connect ed bet ween
t he out put t er mi nal of t he addr ess sequencer and an out put
t er mi nal of t he addr ess gener at or ; and
an ext er nal addr ess enabl e swi t ch connect ed bet ween
an addr ess i nput t er mi nal of t he addr ess gener at or and t he
out put t er mi nal of t he addr ess gener at or ;
wher ei n t he addr ess Sequencer gener at es a second
addr ess i n a sequence of addr esses whi l e a f i r st addr ess
i s bei ng suppl i ed t o t he out put t er mi nal of t he addr ess
gener at or by t he external . addr ess enabl e swi t ch,
and
wher ei n t he addr ess sequencer i ncl udes a count er
havi ng a mast er por t i on and a sl ave por t i on.
- 5 -
PATENT
L-
REMARKS
Cl ai ms 1- 10 wer e pendi ng; Cl ai ms 1-4 and 8-10 wer e
r ej ect ed and Cl ai ms 5- 7 wer e obj ect ed t o.
have been amended and new Cl ai ms 11-14 added. Reconsi der at i on
Cl ai ms 1, 9 and 10
i s r equest ed.
The amendment s t o t he speci f i cat i on ar e per t he
suggest i ons of t he Exami ner , except t he amendment at page 10,
l i ne 33 whi ch i s t o conf or mt he speci f i cat i on t o t he dr awi ngs
as or i gi nal l y f i l ed.
Cl ai ms 9 and 10 st and r ej ect ed under 35 U. S. C. 112, 2nd
par agr aph as bei ng i ndef i ni t e. The Exami ner st at ed t hat "i n
Cl ai ms 9 and 10, t he ser i al addr ess gener at or woul d not
f unct i on as i nt ended wi t hout *an i nt er nal addr ess enabl e swi t ch
and an ext er nal addr ess enabl e swi t ch. I 1 Cl ai ms 9 and 10 have
been amended t o r eci t e l anguage di r ect ed t o t hese el ement s.
Cl ai ms 1- 4 and 8- 10 st and r ej ect ed under 35 U. S. C. 102( a)
as ant i ci pat ed by pr esent Fi gs. 1B and 2B.
The Exami ner i ndi cat ed t hat Cl ai ms 5- 7 r eci t e al l owabl e
subj ect mat t er and woul d be al l owabl e i f r ewr i t t en i n
i ndependent f or mi ncl udi ng al l t he l i mi t at i ons of t he base
cl ai mand any i nt er veni ng cl ai ms.
I n r esponse, Appl i cant s have added new Cl ai ms 12- 14 whi ch'
r eci t e t he l anguage r espect i vel y of or i gi nal Cl ai ms 5- 7 pl us
t he l anguage of base Cl ai m1. However Cl ai ms 12- 14 do not
i ncl ude t he l anguage of i nt er veni ng Cl ai m2, upon whi ch each of
Cl ai ms 5, 6 and 7 ar e dependent . I t i s bel i eved t hat even
wi t hout t he l anguage of i nt er veni ng Cl ai m2, t hat Cl ai ms 12-14
whi ch r eci t e r espect i vel y t he l anguage of Cl ai ms 1 and 5, 1 and
6 , and 1 and 7 ar e al l owabl e, and al l owance t her eof i s
r equest ed.
Cl ai ms 2, 5 and 6 have been amended t o i mpr ove cl ar i t y,
The l anguage of t he and t o pr ovi de pr oper ant ecedent basi s.
pr esent amendment s t o Cl ai ms 5 and 6 has al so been car r i ed over
t o new Cl ai ms 12 and 13.
- -P-
: I ,
-i L PATJZNT
Addi t i onal l y, each of i ndependent Cl ai ms 1, 9 and 10 has
been amended, and as amended each of t hese cl ai ms i s bel i eved
t o di st i ngui sh over pr esent Fi gs. 1B and 2B.
Speci f i cal l y t he pr esent speci f i cat i on st at es, begi nni ng
at page 4, l i ne 11:
Ther eby t he addr ess sequencer gener at es
each addr ess one cl ock cycl e ahead of t he
t i me t hat addr ess woul d have been gener at ed
i n t he pr i or ar t , and t he addr ess out put i s
suppl i ed t o t he out put buf f er % cl ock cycl e
ahead of t he pr i or ar t ( Fi g. 2B) t i mi ng.
... i n accor dance wi t h t he i nvent i on and i n
or der t o set t he addr ess sequencer
i ni t i al l y t o t he second addr ess t he
mast er si de of t he count er i s i ni t i al l y set
t o val ue 91, and t he sl ave si de of t he
count er i s i ni t i al l y set t o val ue PL,
Thi s pr ovi de8 t he desi r ed i ncrementa!?'
t i mi nq advant ase over t he pr i or ar t .
( Emphasi s added. )
Thus as amended Cl ai m1 now r eci t es i n i t s f i nal cl ause
"wher ei n t he addr ess sequencer i ncl udes means f or i ncr ement al l v
t i mi nq t he addr ess sequencer t o uener at e a second addr ess i n a
sequences of addr esses whi l e a f i r st addr ess i s bei ng suppl i ed
t o t he out put t er mi nal of t he addr ess gener at or by t he ext er nal
addr ess enabl e swi t ch. " ( Emphasi s added. ) Thi s l anguage of
Cl ai m1 i s di r ect ed t o t he above quot ed subj ect mat t er and
pr ovi des t he above- descr i bed advant age.
As f ur t her descr i bed i n t he pr esent speci f i cat i on at page
4 begi nni ng at l i ne 30:
Thus t he per f or mance advant age i s gai ned dur i ng t he
pr eset por t i on of t he addr ess bur st . Si nce t he
addr esses ar e out put one- hal f cycl e ahead of t hat
pr ovi ded i n t he pr i or ar t , t hi s i mpr oves t he
oper at i onal per f or mance of t he syst emi n whi ch t he
bur st memor y i s i nst al l ed.
No such st r uct ur e bei ng pr esent i n Fi gur es 1B and 2B, i t
i s submi t t ed t hat Cl ai m1 di st i ngui shes t her eover .
Cl ai ms 2- 8 and new Cl ai m11 ar e dependent upon Cl ai m1,
and t her ef or e al l owabl e f or at l east t he same r easons as i s
base Cl ai m1.
Cl ai m9 has been amended i n i t s f i nal cl ause t o r eci t e
l l means f or i ncr ement al l y t i mi ng t he addr ess sequencer dur i ng a
preset per i od t o gener at e t he second addr ess at a same t i me
ADM.SS85s\M-2595-WI 17693.W - 7 -
PATENT
t hat t he f i r st addr ess i s bei ng pr ovi ded f r omt he ext er nal
sour ce. n Agai n t hi s i s not met by t he r ef er ence and pr ovi des
t he advant age as di scussed above i n conj unct i on wi t h Cl ai m1.
Si mi l ar l y met hod Cl ai m10 has been amended and r eci t es
begi nni ng i n l i ne 9 "t he second addr ess bei ng gener at ed &
i ncr ement al t i mi ng dur i ng at l east a par t of t he dur at i on of
t he st ep of pr ovi di ng t he f i r st addr ess; ". Agai n t hi s i s not
di scl osed by t he r ef er ence and hence di st i ngui shes t her eover .
New Cl ai m11, dependent upon Cl ai m2 and hence base
Cl ai m1, addi t i onal l y f ur t her di st i ngui shes because Cl ai m11
r eci t es "t he means f or cont r ol l i ng t he i nt er nal addr ess enabl e
swi t ch i s a l ogi cal i nver si on of t he si gnal s pr ovi ded t o t he
cl ock i nput t er mi nal , 11 Thi s i s suppor t ed by Fi g. 10 whi ch
shows t he l ogi cal i nver se of t he BAEN ( i nt er nal addr ess enabl e)
si gnal bei ng t he same as t he 4 cl ock si gnal .
i nt er nal addr ess enabl e si gnal i t sel f i s t he l ogi cal i nver se of
t he Cp cl ock si gnal s. Thus t he i nt er nal addr ess enabl e swi t ch
Hence t he
i s i n ef f ect dr i ven by t he Cp cl ock si gnal vi a an i nver t er ,
pr ovi di ng a si mpl e and r el i abl e st r uct ur e. Thi s i s i n cont r ast
to pr i or ar t wher e i nst ead t he i nt er nal addr ess enabl e swi t ch
i s dr i ven, e. g. by t he 4 cl ock si gnal vi a an edge det ect or and
l at ch. I n accor dance wi t h t he pr esent i nvent i on, t he edge
det ect or and l at ch ar e el i mi nat ed, pr ovi di ng si mpl i f i cat i on.
Cl ai m11 hence i s al l owabl e.
Tn l i ght of t hi s amendment , i t i s r espect f ul l y submi t t ed
t hat each of pendi ng Cl ai ms 1- 14 i s al l owabl e, and al l owance i s
r equest ed. I f t he Exami ner cont empl at es ot her act i on, t he
Exami ner i s r equest ed t o cal l t he under si gned at 408/283- 1222.
Respect f ul l y submi t t ed
-, 1 -
Nor man R. Kl i vank
At t or ney f or Appl i cant ( 8 )
Reg. No. 33. ; 003
United Stoh porWSada a Rnt ckr, MII an envelope
addressed to: Comml u~& PIf rat t and Trrd arks.
Washington, 0.G 20231, f l - * P. I 9 Y . L .
9-A
G 1q95 2 n d . ,I &
Date of Signature
Attorney for Applicant
L\oMS\ssss\acu9S~WOll7693.WP - 8 -
FRANKLI N & FRIEL
25 METRO DRI VE SUI TE 700
SAN J OSE CA 95110
251 1
DATE MAILED:
NOTI CE OF ALLOWABI LI TY
- -
PART I.
1. kdThis communlcatlon Is responslvs t o &&t%dWh Ahxd
2 &All the claims being allowable. PROSECUTION ON THE MEklTS IS (OR REMAINS) CLOSED In this appllcatlon If not Included
herewlth (or previously mailed). a Nolice Of AMowance And Issue Fee Due or other appropriate comrnunlcatlon will be sent In due
course.
3. d The allowed clalms are 1 I 4
4. 0 The drawlngs filed on
5 0 Acknowledgment 19 made 01 the clam for prlorlty under 35 U S C. 119. The certified copy has 1-1 been received. 1-1 not been
6 0 Note the attached Examlner's Amendment
7. 0 Note the attached Examlner Interview Summary Record, PTOL-413.
8 0 Note the attached Examiner's Slalemenl of Reasons for Allowance.
2 I 3 4s
are acceptable.
recelved [ ]been filed In parent application Serial No , filed on
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10 0 Note the attached INFORMATION DISCLOSURE CITATION, PTO-1449.
PART II.
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FROM THE DATE MAILED" indicated on this form Failure lo tlmely comply wlll result in the ABANDONMENT of this application
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APPLICANT MUST MAKE THE DRAWING CHANGES INDICATED BELOW IN THE MANNER SET FORTH ON THE REVERSE SIDE
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a dDr awi ng informallties are Indicated on the NOTICE RE PATENT DRAWINGS, PTO-948. attached hereto or to Paper No
CORRECTION IS REOUIRED.
b. 0 The proposed drawing corrfetion bled on
has been approved by the examiner CORRECTION IS
C D Approved drawing correcllons are descrlbed by the examiner in the attached EXAMINER' S AMENDMENT CORRECTION IS
d. dFor mal drawings are now REQUIRED
2 8
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REQUIRED.
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AND ISSUE FEE DUE ISSUE BATCH NUMBER, DATE OF THE NOTICE OF ALLOWANCE, AND SERIAL NUMBER
Allachmenlr:
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- NOIICe of References Ciled. PTO-892
- Informalion Disclosure Ciletlon. PTO-1449
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1
t PTOL-E5 (REV. 12-99) (M51-0033) 4. PATIENTAM) TRADEMAW< O R E cop(
.IN THE UNI TED STATES PATENT AND TRADEMARK OFFI CE
ant ( s ) : J i nyong Chung et al .
Mosel Vi t el i c Cor por at i on
Ti t l e:
Ser i al No. : 08/ 265, 535 Fi l i ng Dat e: J une 24, 1994
Exami ner : S. Mai Ar t Uni t : 2511
At t or ney Docket No. : M- 2595 US
SERI AL ADDRESS GENERATOR FOR BURST MEMORY
San J ose, Cal i f or ni a
May 10, 1995
ATTENTI ON: Of f i ci al Dr af t sman
COMMI SSI ONER OF PATENTS AND TRADEMARKS
Washi ngt on, D. C. 20231
Si r :
SUBMI SSI ON OF FORMAL DRAWI NGS
Appl i cant submi t s 16 ( si xt een) sheet s of f or mal dr awi ngs,
consi st i ng of Fi gur es I A, l B, 2A, 2B, 3 , 4, 5A, 5B, 6A, 6B, 6C,
7 , 8A, 8B, 9A, 9B, 10, 11A, and 11B i n t he above- named
appl i cat i on. I f t her e ar e any quest i ons r egar di ng t hese
dr awi ngs, pl ease cal l t he under si gned at ( 408) 453- 9200.
Respect f ul l y submi t t ed,
At t or ney f or Appl i cant ( s )
Reg. No. 33, 003
I hereby certify that this correspondence Is being deposited with the
United States Postal Service as first class mail in en envelope
addressed to: Commissioner of Patents and Trademarks, Washington,
D.C., 20231, on
.I/
- 1 -
,
SER. NO. 08/ 265, 535
I
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I , Address An(l)
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FIG. 2A
(PRIOR ART)
external address enable
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(PRIOR ART)
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FIG. 4
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FIG. 6
FIG. 6A FIG. 6B FIG. 6C
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PART B-ISSUE FEE TRANSMllTAL
FiLlNG DATE TOTAL CLAIMS EXAMINER AND GROUP ART UNIT
ERIES CODWSERIAL NO.
VGINSTRUCTIONS: This lorm should be usedfor transmitting the ISSUE FEE. Blocks 2 through 6 should be completed where appropriate.
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DATE MAiLED
SKJERVEN
FfiANEL I N
25 METRO
SAN J OSE
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ti FRI EL
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The COMMISSIONER OF PATENTS AND TRADEMARKS 6
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El? 35110
Check il additional changes are on reverse side
DATE DUE
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, Correspondence address change (Complele only if there is a change)
4. Forprlntlngonthepatentfront Skj e r v e n, Morrill, MacPherson
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3 registered patent attorneys or agents
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S u m ym
I4w4n.m
PATENT
May 10. 1995 ( )
',
L. ;
I I N THE UNI TED STATES PATENT AND TRADEMARK OFFI CE
c??
8 bl i cant (s) :
Assi gnee: Mosel Vi t el i c cor por at i on
J i nyong Chung et al .
g
Ti t l e : SERI AL ADDRESS GENERATOR FOR BURST MEMORY
Ser i al No. : 08/ 265, 535 Fi l i ng Dat e: J une 24, 1994
Exami ner : S. Mai Ar t Uni t : 2511
At t or ney Docket No. : M- 2595 US
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
San J ose, Cal i f or ni a
May 10, 1995
COMMI SSI ONER OF PATENTS AND TRTQEMARKS
Washi ngt on, D. C. 20231
CHANGE OF ATTORNEYS'
TELEPHONE AND FACSI MI LE NUMB ERS
Si r :
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( 408) 453-9200
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At t or neys f or Appl i cant ( s) i n t hi s case has been changed t o:
( 408) 453-7979
The addr ess of t he At t or neys f or Appl i cant ( s) has been
changed and r emai ns:
SKJERVEN, MORRILL, MacPHERSON, FRANKLIN & FRIEL
25 Metro Drive, Suite 7 0 0
San Jose, California 95110-1349
Respect f ul l y submi t t ed,
At t or ney f or Appl i cant ( s1
Reg. No. 33,003
I hereby certify that this correspondence is being deposited with the
United States Postal Service as first class mail In en envelope
addressed to: Commissionerof Patents endlrademarks. Washington,
- 1 - SER. N0: 08/ 265, 535
The Commissioner of Patents
and Trademarks
Has meived an opplication for a patent
for a new and usefil inventioa m e title
and descrption of the invention ore en-
closed The reguhmenrs of law have
been complied with, and it has been de-
termined that opatent on the invention
shall be gmnted under the I QW.
Therefore, this
United States Patent
Gmm to the wson or pmns having
title to thk potent the right 10
othemfmm moking using or selfimg the
invenllon thmtghout the Wnlted States
0 . Amerlm f i r the term of seventeen
veorsfmm the date of this patent. sub-
ject to thepoyment of maintenance fies
0s provided by law.
is of minor character because it does not materially affect the scope or meaning
of the patent (37 CFR $1.322; M.P.E.P $ 1481).
I hereby certify that this correspondence is being deposited with
the United States Postal Service as First Class Mail in an
0 Other:
Respectfully submitted,
Please make the following charges or credits to Deposit Account No. 19-2386 :
the required fee for correcting Applicants error
pursuant to 37 CFR 51.323
100.00
[XI
any additional amount required for this request for Certificate of Correction and
for credit of any overpayment.
Please direct all inquiries concerning this request to the undersigned attorney at (408)
453-9200. This form is submitted in duplicate.
envelope addressed to: Commissioner of Patent, and
Trademarks, Washington, D.C. 2023 I ,
on Oaober 30, 1998.
Norman R. Klivans
Attorney for Applicants
Reg. No. 33,003
56833 VI
- 2-
SER. NO. OW265.535
)ONLY 5
Y f
P F
P
E
PRINTERS MAILING ADDRESS OF SENDER:
TRIM LINE
PATENTNO 5,452,
SKJ ERVEN, MORRILL, MacPHERSON, NO ofaddl
FRANKLIN & FRlEL LLP
25 Metro Drive, Suite 700
Sari J ose, California 95110
-
UNITED STATES PATENT AND TRADEMARK OFFICE
CERTIFICATE OF CORRECTION
PATENT NO. : 5,452,261 -
ISSUE DATE : 09/19/95
INVENTOR(S) :
Chung, J inyong; Murray, Michael A.
FORM PTO 1050 (REV, 3-82)
911 6
t
0
t - - - - i - - - -
----------
I - - - -
Q
m
z
NOTICE RE: CERTIFICATES OF C.ALGTION
/, \' :%,.
' 1 , I \
56 2; 26 / t f l
,, ! $_* DATE : 2//bT
SUBJECT
TO : Supervisor, Art Unit 2.rr f \
Certificate of Correction Request in Patent No.
TO: CERTIFICATE OF CORRECTION BRANCH
3
/ *
se to the following question(s) is sequested;wlih respect to the accompanying request for; certificate of correction.
. Would the change(s) requested under 37 CFR 1.323 constitute new matter or require reexamh&n ofthe application?
\
. fl > '!-.
Would the change(s) requested under 37 CFR 1.323 Materially affect the scope or meaning of the c$uns allowed
->.
by the examiner in the patent? < > '
the change request be granted?
*> ,*f <
I , /
3. Applicant disagrees with cha;hg:(s) initialed and dated by Examiner in lieu of an Examiner's Amendment, Sh uld
0 4. With respect to the change(s) requehgd, correcting Office errors, should the patent read as shown in the certificate
3
f correction? I
DATE:
5. I f the amendment filed had been considered by the Examiner, would the
amendment have been entered?
PLEASE RESPOND WITHIN 7 DAYS Ah'D RETUF24THE FI L
-I
A I
. %
Fa/ Imrunnenr Examiner
0 1.YEs
0 2.YEs
0 3.YEs
0 4.YEs 0 NO
Comments below
0 Comments below
0 Commend below
0 Comments below
cI.s.YEs 0 NO 0 Comments below
. Supervisor Art Unit
r0~-306 (REV. 1 ~ 8 7 ) US. DEPARTMENT OF COMMERCE Patent and Trademark Office
UNITED S I'ATES PATENT AND TRADEMARK ui-FICE
CERTIFICATE OF CORRECTION
PATENT NO. : 5,452,261 Page 1 of 2
DATED : 09/19/95
' Chung, Jinyong; Murray, Michael A.
It is certified that error appears in the aboveidentified patent and that said Letters Patent is hereby
corrected as shown below:
Replace FIG. 7 with attached FIG. 7.
Signed and Sealed this
Sixteenth Day of March, 1999
Atresf:
U.S. Patent Sep. 19,1995 Sheet 9 of 16
c
Page 2 of 2
5,452,261
REPORT ON TEE mING OR DETERMhATION OF AN
ACTION REGARDING A PATENT OR TRADEMARK
TO : Commissioner of Patents and Trademarks
Washington, D.C. 20231 .
In compliance with 35290 and/or 15 U.S.C. 11 16 you are hereby advised that a courI action
has been filed on the following patent(s)/trademarks in the U.S. District Court:
DOCKET NO.
CA 98-449
PLAINTIFF
Mosel Vitelic Corp.
DATE FILED
07/31/90
U.S. DISTRICT COURT
District of Delaware
DEFFSDAN!C
Micron Technology
PATENT/TR&DEMARK NO. DATE OF PATENT/TRADEwLRK HOLDER OF PATENT OR TRADEMARK
1 5,245,583 .\, 09/14/93
2j* ' 5,452,261 09/19/95
- y z
Mosel Vitelic Corp.
Mosel Vitelic Corp.
In the above-entitled case, the following patent(s) have been included:
DATE INCLUDED INCLUDED BY
t 1 Ame nba t t I Answer L I Cr oss Bill t 1 Other Pleading
PATENT/TRADEMARII NO. DATE OF PATENT/TIWE~IARK XOLDER OF PATENT OR TRAD-
1
2
3
4
5
In the above-entitled case, the following decision has been rendered or
judgment issued:
DECISION/JUDGMENT
(BY) DEPUTY CLERK DATE
CLERK
PETER T.. DALLEO, CLERK
_--._
. .
. .
%Zp&. ~
.,
Address: Box ISSUE FEE
COMMISSIONER OF PATENTS AND TRADEMARKS
Washtrigton, D.C. 20231
SERIES COOWERIAL NO. I/ FILING DATE I TOTALCLAJM~ I . ' WMI NER AN0 GROUP ART UNIT I DATEMAI~ED
?.C, ,
Ld.l A 2 2 / X d % + s -
. .I /*'
, *i r v ,--.
, . , . I . . _ I
,', I < j _ . l .
ArstNemsd" '" '
-...>.I ...-. ' I .. % . I . . 1_ I , -. I
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All comrnunlcations regarding this application must give serles code (or filing date), serial number and batch number.
Please direct all communication prior to issuance to Box ISSUE FEE unless advised to contrary.
REMI NDER: Patents lssulng on appfications filed on or atter Dec. 12,1980 may requlre payment of
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fees when due. .
PTOL-85 (REV. 12-93) (oeSlO333) 4. PATENTANDTRADEMAW( OmCE Cow
At - Y. Docket No. : M- 2595 Us
L A W OFFI CES OF
SKJERVEN, MORRILL. MAcPHERSON, FRANKLIN a FRIEL
25 METRO DRI VE, 5 UI T E 7 0 0
SAN JOSE, CALI FORNI A 95110
(408) 263-1222
J une 24, 1994
Our Gase Docket No. H- 2595 US
Commi ssi oner o f Pat ent s and Tr ademar ks
Washi ngt on, D. C. 20231
Tr ansmi t t ed her ewi t h f or f i l i ng i s a pat ent appl i cat i on, as f ol l ows:
I nventor(s):
Ti t l e :
J i nyong Chung and Mi chael A. Murray
SERI AL ADDRESS GENERATOR FOR BURST MEMORY
Encl osed al so are:
Sheet s of drawi ngs: - (Formal ) A ( I nf ormal )
- An Assi gnment of the I nvent i on t o
- A cer t i f i ed copy of a Appl i cat i on.
CLAIMS AS FI LED
Number Number
w
Basi c Fee
S 710. 00
< ot c x 2 - 0 00
I ndependent
3 00.00
Cl ai ms - 3 - 0 x 574 -
-
Appl i cat i on cont ai ns one or more mul t i pl e
t al f ee) - 00.00
Tot al f i l i nE f ee: $ 710. OQ
deDendent claims ( $230 t o
Pl ease make t he f ol l owi ng char ges t o Deposi t Account 19- 2386:
2 Fee or f i l i ng the pat ent appl i cat i on i n t he amount of $ 710. 00
2
The Commi ssi oner i s her eby aut hori zed to charge any addi t i onal
f ees whi ch may be r equi r ed, or cr edf t any over payment to Deposi t
Account 19- 2386.
A Ret ur n Post Card and t hi s sheet in t ri pl i cat e are encl osed.
Respect f ul l y submi t t ed,
I hareby cattify t hr t this aorrerpondease is being
deposited with t h United Stat. 6 Po6tal Servies as express
mai l in an OnValopr addre6led t o: Carrmis6ioner 02 Pat ent s
Reg. No. 33, 003
At t or ney f or Appl i cant(s)
I N THE UNI TED STrn?S PATENT AND TRADEMARK OFFI CE
Appl i cant(s): J i nyong Chung et al.
Assi gnee: Mosel Vi t el i c Cor por at i on
Ti t l e: SERI AL ADDRESS GENERATOR FOR BURST MEMORY
Ser i al No. i 08/ 265, 535 Fi l i ng Dat e: J une 24, 1994
Exami ner : unknown Ar t Uni t : unknown
At t or ney Docket No. : M- 2595 US
...............................................................
San J ose, Cal i f or ni a
August 29, 1994
COlJIMISSIONER OF PATENTS & TRADEMARKS
Washi ngt on, D. C. 20231
Attention: Application Processing Division, Special
Processing and Correspondence Branch
SI NG PARTS RESPONSE TONOTI CE TO FI LE MI S
OF APPLI CATI ON - FI LI NG DATE GRANTED
Dear Si r:
I n r esponse t o t he Not i ce t o Fi l e Mi ssi ng Par t s of
Appl i cat i on - Fi l i ng Dat e Gr ant ed mai l ed by t he Uni t ed St at es
Pat ent and Tr ademar k Of f i ce on J ul y 29, 1994, t he f ol l owi ng
document s ar e encl osed t o compl et e t he f i l i ng of t he above-
i dent i f i ed pat ent appl i cat i on:
1. A decl ar at i on si gned by t he i nvent or s i n compl i ance
wi t h 37 CFR 1. 63.
Copy of Not i ce t o Fi l e Mi ssi ng Par t s of Appl i cat i on -
Fi l i ng Dat e Gr ant ed.
2.
The Uni t ed St at es Pat ent and Tr ademar k Of f i ce i s her eby
aut hor i zed t o char ge t he f ol l owi ng f ees t o Deposi t Account No.
19-2386:
1. Sur char ge f or f i l i ng decl ar at i on
on a dat e l at er t han t he f i l i ng dat e
of t he appl i cat i on. $130. 00
The Commi ssi oner i s her eby aut hor i zed t o char ge any
addi t i onal f ees whi ch may be r equi r ed, or cr edi t any
over payment to Deposi t Account No. 19- 2386.
I t i s her eby r espect f ul l y submi t t ed t hat t he encl osed
l ocument s compl et e t he f i l i ng of t he above pat ent appl i cat i on
nnd j ust i f y t he ei l i ng dat e of J une 24, 1994. Pl ease t el ephone
- 1 -
the undersigned at ( 40P; 283-1222, if there are any questions.
This form is being submitted in triplicate.
Respectfully submitted,
Norman % + R I W R. livans
Attorney for Applicants
Reg. No. 33,003
I hereby certify that this correspondence Is being daposited with the
United S.tater Postal Sodoe as first class mail in an envelope
addressed to: Commissioner of Patsnte and Trademarks, Washington,
D.C., 20231, on&&&&& 1 9 3 y
Attorney for Appiicantb)
- 2 -
- 7
r--- --- - - - - - - -
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-' Fig. 1A (prior art)
Fig. 2A (prior art)
Fig. 2B (prior art)

PRINT or nmwrxcs * ' -' * PVI ' ' - - -~- PU W I
AS ORIG\' .4\LLY FILED
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US005452261A
United States Patent [I91 pi] Patent Number: 5,452,261
Bung et al. 1451 Date of Patent: Sep. 19, 1995
SERIAL ADDRESS GENERATOR FOR
BURSTMEMORY
Inventors: Jinyong Chug, Los Altos Hills,
Calif.; Michael A. Murray, Bellevue,
Wash.
Assignee: Mosel Vitelic Carporation, San Jose,
Calif.
Appl. No.: 265,535
Filed: Jun. 24,1!394
Int. Cl .6 ................................................ eiiC 8/m
US. Cl . .................................... 365/W3; 365/221;
365/236; 365'239; 36V230.06; 36V230.08
Field of Search ...................... 365/230.01, 230.06,
365/230.08,230.09, 236,239, 240, 221,233
Reference Cited
U.S. PATENT DOCUMENTS
5,097,447 3/1992 Ogawa ....................... 365/230.09 x
5,146,431 9/1992 Eby ................................. 365/236 X
5,260,905 11/1993 Mori ........................... 365n30.w x
Primary Examiner-David C. Nelms
Assistant Examiner-Son Mai
Artorney, Agent, or Finn-Skjerven, Morrill,
MacPherson, Franklin 8r Friel; Norman R. Klivans
A serial address generator for a squential (burst mode)
random access memory generates a sequence of inter-
nally generated addresses for fast cycling. The start
address is externally provided. Then, as the clock sig-
nals arrive, the subsequent addresses are generated in
sequence by the address sequencer. The address se-
quencer is preset to the second address in the sequence
following the start address. Simultaneously, the SM
address is connected by an external address enable
switch to an output terminal of the address generator,
bypassing the address sequencer. When the f mt clock
signal amves at the address sequencer, the address se-
quencer output is sampled by closing an internal address
enable switch and opening the external address enable
switch. Thus the internally generated addresses are
provided immediately following the start address. The
address sequencer thereby generates each address one
clock cycle ahead of that in the prior art, and the output
address is provided one half clock cycle ahead of that in
the prior art.
[5fI ABsrRAcr
14 Claims, 16 Drawing Sheets
WuinDer lntemt
control Address
Enable
OCLOCK
PRESET /-7 I I
I I 8
I 1 1 . I I
AddrlSS I
Exl ernal I I
I 1
Sequencerout Z%/m An+i ! I x h 2 ' Aw3
Address En__/ ---\ I I I
I
Internal
Address
Enable
U.S. Patent Sep. 19, 1995 Sheet 1 of 16 5,452,261
r- - - - - - - - --------e
I
Address An(/)
Sequencer Address Out
OCLOCK
PRESET
14
CONTROL 7%- - - -
FIG. 1A
(PRIOR ART)
X Start Address (An)
Address In
X
OCLOCK 7 - -
/
L
3rd
v
I PRESET
FIG. 2A
(PRIOR ART)
external address enable
I
Address In
OCLoCK * ] = V&- bAddr e s s Sequencer Out
14
PRESET
..
7 demal address enable
SEQUENCE
CONTROL
.FIG. 1B
(PRIOR ART)
U.S. Patent Sep. 19, 1995 Sheet 2 of 16
2
2
x
T-
-+
*
x
I
5,452,261
U.S. Patent
Sep. 19, 1995 Sheet 3 of 16 5,452,261
External Address Enable
I
i 1 I
I
34) I
Address
Sequencer
38
PRESET ,
i - C
I
xis-
Sequencer Internal
Control Address
Enable
FIG. 3
Address X Start Address (An)
In
X
0CLOCK \ /
h d I 3id
PRESET I I I
1.h 1
Address I I I I I I
Sequencer out Y/ / / %X Ant1 ! X An+2 I X Ant3
External I I
Address E n d \ I I
I I
Internal I I
Address
Enable /1
\
I I
Address y////////-/////~ A n x Ant1 Ant2 XAnt3
Out
FIG. 4
U.S. Patent
AHD
Sep. 19, 1995 Sheet 4 of 16 5,452,261
I
PRESETD
LD
I
I
I
"i
RD I
FIG. 5A
i
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i I
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U.S. Patent
Sep. 19, 1995
Sheet 5 of 16
5,452,261
FIG. 5B
KEY TO
FIG. 5
U.S. Patent
Sep. 19, 1995 Sheet 6 of 16 5,452,261
BAl J - 1
BAl D
BA2D
I
1 , ' 1 (605
I
I I 1 1 I I
PRESET A i 1 1 I
OCLOCK
I
FIG. 6A
U.S. Patent
Sep. 19, 1995
Sheet 7 of 16
5,452,261
I
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ITFR Z 1 I
I ' 1 (60-7
,
I
I
I
W e c n - r I 4
N=4 B
N=12
N=8
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U.S. Patent
I
Sep. 19, 1995
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Sheet 8 of 16 5,452,261
tY- k 2 0
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FIG. 6C
KEY TO
U.S. Patent
Sep. 19, 1995 Sheet 9 of 16
5,452,261
I
U.S. Patent
Sep. 19,1995
Sheet 10 of 16 5,452,261
I
I
I
U.S. Patent
Sep. 19, 1995 Sheet 11 of 16 5,452,261
I
I
I i
I i
I
CASl b
I
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FIG. 8B
KEY TO
FIG. 8
FIG. 8A FIG. 88
m
U.S. Patent
Sep. 19, 1995 Sheet 12 of 16 5,452,261
I
MUX-D
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AS D
I
N=6
C1 D I c1 I r
FIG. 9A + i I
i I
I
U.S. Patent Sep. 19, 1995 Sheet 13 of 16
5,452,261
P i
i I
FIG. 9B
KEY TO
FIG. 9
U.S. Patent
Sep. 19, 1995 Sheet 14 of 16 5,452,261
0
P
U.S. Patent
Sep. 19, 1995 Sheet 15 of 16 5,452,261
19 m K
5
U.S. Patent Sep. 19, 1995 Sheet 16 of 16 5,452,261
. . -,
5,452,261
1
SERIAL ADDRESS GENERATOR FOR BURST
MEMORY
BACKGROUND OF THE INVENTION 5
1. Field of the Invention
This disclosure relates to random access memory and
specifically to a serial address generator for a burst-type
random access memory.
Video RAM (random access memory), synchronous
RAM and burst RAM each require a sequence of inter-
nally generated addresses for faster cycling and preven-
tion of the external address bus lines from fast switching
to suppress switching noise in the system. Typically the '5
Start address of a Darticular address burst is orovided
2. Description of the Prior Art
10
r -
from an external Source (a host computer or a proces-
sor) and as subsequent clock signals arrive at the address
L
and internal address enable switch 26, and the start
address is provided directly to the output buffer via
external address enable switch 24. This (stan) address
An is therefore available almost immediately as the ad-
dress out at buffer 14, without processing by the address
sequencer 12.
However, further performance improvement (i.e.,
higher speed) is desirable in terms of address output.
SUMMARY OF THEINVENTION
In the above described prior art, the second address
An+I is delivered by the address sequencer to the out-
put buffer at the time of the trailing edge of the first
& h k cycle. In accordance with the invention, instead
the second address An+l is delivered to the output
buffer at the leading edge of the &r&signal. Thus one
balf o f a clock cycle is gained for each address burst.
After provision to the output buffer of the first ad-
generator, the foilowing addresses in the burst are gen- dress A.(which is externally supplied asin FIG. 1B) the
erated continuously in sequence for the duration ofthe *O external address line is disconnected from the output
burst. The Pi or an Presets the address sequencer (tYPi- buffer by an external address enable switch, and an
CaIlY a counter) to the aternally Provided start address internal address enable switch which connects the ad-
(Ad in response to a PRESET si@. The address dress sequencer to the output buffer is closed, allowing
sequencer output is updated with each 4cIwk rising
the address sequencer to provide the subsequent inter-
edge, and the Outputs Of the address generator are 25 nally generated address An+l to the output buffer, also
quentially A,, An+t , An+2, etc.
as in FIG. 1B. Then, during the time that the start ad-
1A including address sequencer 12 outputting the se-
input signals to the address sequencer 12 are the input 30
address signal (the start address An), the 4clak signal
and he
trol signal controls whether the address sequencer 12
counts up or down. I n most applications, upcounting is The provided and the address Out
used, and this fmCtion is built in, rather than being a 35 both begin with the Same address An which iS the initial
control function. ne mi at ed timing diagram is address in the burst, while using the preset signal to
shown in FIG. 2A.
advance the counting of the sequence by one count.
a master side and a slave side, each set to t he A.+I (the second address in the burst) following the
SM address An. I t is to be underston.' 'hat the device of 40 externdb' Provided address An. m e n the f i t
device, where : *&address An clock Si@ &Ves at the address sequencer, the ad-
provided by a I' , dity of lines, :.e. dress sequencer Output is SamplCd by enabling the inter-
addrss out si mis also provided nal address enable (second) switch and disabling the
external address enable (fmt) switch. The address se-
A :'.:I I in FIG. 2A, the first address out An is output 45 Sum=: Output i5 Updated with each nsing edge of the
to buffer 14 when the Preset signal is applied, and kept clock Stgnal $dak. Thereby the address sequencer gen-
until leading edge of &I& arrives. The second address erates each address One clock cycle ahead of the time
out An+) is output to buffer 14 at the trailing edge of that address would have been generated in the prior art,
&iak and the, following addresses are updated at every and the address output is supplied to the output buffer 4
trailing edge of the 4,loclrsignal. so clock cycle ahead of the prior art (FI G. ZB) timing. As
The address generator o f FIG. 1A functions ade- in the prior art. the address sequencer includes a mas-
quately; however it is slower than desired. Faster opera- ter/slave Counter. However, in accordance with the
tion is desirable to improve system performance such as invention and in order to set the address sequencer
needed in a typical burst DRAM (dynamic random initially to the second address An+l. the master side of
access memory) chip. The FIG. IA address generator 55 the Counter is initially set to value A,, and the slave side
delivess the first address late. oue to the propagation o f the counter is initially set to value A,+]. This pro-
delay through the counters inside the addrss se- vides the desired incremental timing advantage over the
quencer. This means a shorter start address duration prior art.
time.
The present invention is applicable specifically to
To improve the start address delivery, i n a second 60 burst DRAM (dynamic RAM) operating in page mode,
prior art address generator the start address is provided and is also applicable to other types o f burst memory
from the Address Input directly. instead of going using sequential type addressing.
through the counters. (See FIG. IB, and corresponding In accordance with the invention, operation of the
timing diagram FIG. 2B). address generator is the same as in the prior a~ except
Rather than providing the start address A. to the 65 during the preset cycle. Thus the performance advan-
address sequencer as in FIG. I A, the address sequencer tage is gained during the preset portion of the address
12 of FIG. 1B is bypassed before and during the preset burst. Since the addresses are output one-half cycle
period by means of external address enable switch 24 ahead of th .r provided in the prior art, this improves the
Such a prior aR address generator is shown in
dress An is being provided to the output buffer, the
quence of addresses to an outpu~ buffer 14. n e three
address sequencer Operates t '
the subsequent
An'1. Output addresses Of each burst are
thereby, each provided to the output buifer approxi-
Additionally, a sequence
mately 1 of a clock cycle earlier than in the prior art of
lB'
Typically the address sequencer r)includes
Therefore, the address sequencer is preset to address
.
5,452,261
3 4
operational performance of the system in which the are output to buffer 22, in contrast to the prior a n of
burst memory is installed. FIG. ZB in which onlv 14 addresses are outoutted
BRIEF DESCRIPJJON OF THE DRAWINGS
. -
within the first two occurrences of clock cycles $crock.
This half-clock cycle advantage is the chief benefit of
FIGS. l A, IB show prior art address generators.
FIGS. 2.4, ZR show timing diagrams for the prior art
address generators of respectively FIGS. l A, 19.
FIG. 3 shows an address generator in accordance
with the present invention.
FIG. 4 shows a timing diagram for the address gener- I O
ator of FIG. 3.
NG. 5 shows a schematic of the internal address
enable switch, external address enable switch, and Out-
put buffer in accordance with the present invention.
ent invention.
5 the present invention. Thus the generation of addresses
(Addrw sequencer out in FIG. 4) is one clock cycle
ahead of that in the prior art, and there is also a half
clock timing advantage in the output addresses (Ad-
dress out ) in contrast to the prior art of FIG. ZB.
In one embodiment the serial address generator of
FIG. 3 is for use in a burst RAM operating in page
mode, with the externally provided addms being the
fin1 (stan) addrers for each page. Thnefore for e m -
ple a RAM chip having 512 word$ per page require
se-
quencer is a nine-bit counter. The serial address genera-
tor in accordance with the invention is also be $&able
FIG. 6shows a counter in accordance with the pres- 15 nine bit nddrases, i.e., 29=512 Thus, the
FIG. 7 showsdetail ofonecellof the counter Of FIG..
6.
FIGS. 8, 9, and 10 show circuitry for generation of
the timing signals for the address generator in accor- 20
dance with the present invention.
FIGS. U(u) and ll@) show a timing diagram for an
address generator in accordance with the present inven-
tion.
DETAILED DESCRIPTION OF THE 25
INVENTION
FIG. 3 shows in a block diagram serial address gener-
ator 18 in accordance with the invention. Address gen-
erator 18 includes address sequencer 20, output buffer 30
22, external address enable switch 24 (as in FIG. 1B)
actuated by an external address enable control signal te,
and internal address enable switch 26 (as in FIG. 1B)
actuated by an internal address enable control signal 30.
Thus the serial address generator o f FIG. 3 appears in 35
the block diagram to be similar to the serial address
generator of LlG. 1B; the distinction is in the internal
structure and operation of address sequencer 20, which
difTers significantly from address sequencer U of FIGS.
1Aand 1B. 40
Sequence control signal 32 (as in the prior art) deter-
mines whether address sequencer 20 is an up or davn
counter. Input signals on lines 34,36 and 38 are conven-
tional (as in the prior art). The output address (address
out) is provided on line 40. Thi s circuit, Wte that o f 45
FIGS. 1A and IB, is a parallel device providing a multi-
bit address. Hence address line 34, the output from the
address sequencer on line 42, and the address out line 40
each represent multi-line busses with as many lines as
there are address bits in the particular application.
FIG. 4 illustrates timing for the address generator of
FIG. 3, and specifically the timing for external address
switch 24 and internal address switch 26 as controlled
SO
for other @on-page mode) types of serially generated
addresses, with the addition of conventional stop cir-
cuitry to terminate a burst of predetermined length.
It is to be appreciated that the serial address genera-
tor of FIG. 3 is used in place of conventional serial
address generator of FIGS. IA, 1B as a portion typi-
cally of a RAM chip. The address out signal provided
on line 40 is conventionally connected to an address
decoder which selects the desired memory cell or cells
to be written to or read from. (The remainder of the
RAM chip is not illustrated herein as being Conven-
tional.)
FIGS. 5 rhrough 10 show a detailed schematic of one
embodiment of the present invention, corresponding to
that shown in the blodc diagram of FIG. 3 except that
the sequence control is not shown, due to only upcount-
ing being available. In FIGS. 5 through 10 the small
numbers adjacent each logic gate indicate the width (in
micrometers) of each transistor gate of tbe logic gate.
Thus, F indicates the width of a P channel transistor
gate and N indicates the width of an N channel van-
sistor gate. ThC gate length is qual for all transistors
except where a two number notation is used i.e., 48/2
means the transistor gate width is 48 micrometm and
the transistor gate length is 2 micrometers. The stan-
dard (default) transistor gate length is 1.2 micrometers,
for this embodiment
Table 1 shows the signal designations in the block
diagram FIG. 3 and the corresponding signal designa-
tions in schematic FIOS. 5 to 10, and in the correspnd-
ing timing diagram of FIGS. l l (u), ll(6). In Table 1
there is no schematic equivalent to the sequence control
si gnal in FIG. 3, since as explained above the circuit
shown in the schematic of FIGS. 5 to 10 uses up count-
ing only and does not have a down counting mode

respectively by their control signals 24 30 of FIG. 3.


Initially, external address enable switch 24 is closed (the $5
external address enable control signal 28 is high) thus
providing the externally provided address on line 34
opton
TABLE 1
CHIEF SIGNALS - EQUIVALENCES
IIMING
directly to buffer 22. After the initidaddress A n (which DIAGRAM SCEMA~C . CHART
is externally provided) is provided to buffer 22, the -FIG. 1 FIGS. S-10 -FIG. I 1
signal &/%k goes low, and the external address enable 60 SM addfar same Yn
control signal 28 goes low, then the internal address
same
Address
enable signal 30 goes high, closing switch 26. At this
time the address sequencer 20 has generated the second
address An+ I. Internal EN, (Bunt Addrcr, N) Addrcrr
of the second address A,+ 1 overlaps with provision of twmk & i d dgnd gmerarlon &imk
the SM address A,. Thus within the first two $+rWk
cycles, all of start address An and second address An+,
BL-
(An)
: $= An
Addrss As seen in the timing diagram of FIG. 4, generation 65 Sequencer
sequence: CASPAD -
CASlb - BAEN- -+ &...
%ucnce (up counlin~ L inherent
5,452,261
5 6
With reference to FIG. 5. input signal An corre-
sponds to the external Address An on line 34 in FIG. 3.
Signal AH (address hold) functions as the external ad-
BLOCK
dress latching and disable. This is the external address
. FIG. 3 FIGS. 5-10 . FIG. I t 5 enable signal, controlling switch 50 in FIG. 5 which
corresponds to switch 24in FIG. 3.
Similarly, the internal address supplied on line 42 of
Ezternal AH(addrcu HOLD) AH FIG. 3 is designated signal BN in FIG. 5, and is pro-
Address [fundons as catcmal
vided as an input to switch 52 corresponding to switch
Enable address latchingand
disableat m e timc] 10 26 in FIG. 3. Switch 52 is controlled by the internal
Intrmal BAEN- (Bunt Addm BAEN - address enable signal which in FIG. 5 is designated
Address Ensbl,)
BAEN-. (The inverse of signal BAEN.) It is to be un-
Enable Add,euOut YmL,YmL,YrrrR, YmR Add,cnOut derstood that the signal BN is provided from the
counter portion of the address generator, described
(Not Shown)
Buffer 22 of FIG. 3 corresponds to the buffer cir-
cuitry 56 of FIG. 5. The outputs of the buffer circuitry
of FIG. 5 are designated as a "IeW and "right" Y (col-
Table 2 shows the externally provided input signals/- 20 ;rR ~ ~ ~ : ~ ~ $ , ~ t ~ ~ ~ ~ t $ ~ ~ ~ ~ ~ ~ L ~ ~ ~ ;
the left memory block and the other for the right mem-
TABLE 2 ory block.) The output o f buffer 56 corresponds to one
FXTEffiVALLY PROVIDED INPUTS bit of the address out signal of FIG. 3.
NAME DFSCRIPTION The left and right (L, R) signals of FIG. 5 control the
External addm 25 buffer 56 outputs, to provide address signals t o left or
A"
VCC power right decoders respectively. Also provided is column
left deca(er addrcpi enable address power up signal YS, which disables the input
R
address pass when the chip is in the precharge state.
YS columnaddress pow- up
AS A d k Sew 3o The internal start address output by the circuit of FIG.
CASPAD Cnlumn Address Strobe input 5 (designated BA") is an input to the associated counter
MIX- Row . colvmn addrcu multiplex cell, as desczibed below.
FIG. 6 shows the counter (corresponding to the ad-
BYOE Bunt erubldoutput enableinput
ATCQE Output nsblc wnuol dress sequencer 20 of FIG. 3) providing a nine-bit
WE Wrilc Enable- 35 count. The counter has nine identical cells 60-'1,60-2. .
. . ,60-9 connected ar shown. Jhch cell has es a first
WE1 Write Enable
input the internal start address BAn. The second cell
input is the carry signal designated BC,I from the prior
cell, Each :cG also receives a f mt timing signal PRE-
40 SET, and a second timing signal 4c~mk. The output of
each counter cell is an output address bit EN (which is
the address out) which then goes to buffer 56 of FIG. 5,
and B second output BC, which is the carry value to the
It is to be understood that the counter of FIG. 6
occurs only once in the address sequencer 20 and ser-
vices all nine address buffer circuits, of which only one
is shown in FIG. 5.
shows details of one of the cellJ of FIG. 6.
50 Signal BC..I is the c a w input signal, while signal BA,,
is the external addreas signal. The timing signals are
NAME DESCRIITION 4 d~k a nd PRESET (and their inverses). The cell output
is the "real" address BN and a carry vaiue BC,, to the
BAEN- Inlmul ddms nablc
BN h t d a d d m next cell. The cell of FIG. 7 includes conventionally a
BAn Ialmul Stm Address 55 left-hand side which is the "slave" side 70 and a right
hand side which is the "master" side 72 (indicated by
BM Bunt mode
the broken line). Thus. there are two latches 700. 7 2 ~
BC. COunrer eany output
BCkI Counter Cwry input
PRESET prrsn Timing one for each side of the counter cell, with one latch at
CAS18 Timing
any one time updating its value while the second latch
M) is holding the previously calculated data and transmit-
&lek 6 Clock TimjnS
ting it as output.
FIG. 5 corresponds most closely to the block dia- FIGS. 8,P and 10 show circuitry for generating the
gram of FIG. 3; however FIG. 5 is for a single address timing signals for the serial address generator. The two
bit and hence shows only one of nine such identical externally provided timing signals are RAS and CAS
circuits as would be used in FIG. 3. These nine circuits 65 PAD. These in turn generate as shown the internal
are connected in parallel to provide a nine bit address timing signals. The sequence is that the input clock
output signal in this particular exemplary embodiient signal CAS-PAD generates riming signal CASlb which
of the invention.
in turn generates signal BAEN- which in turn generates
TABLE I-continued
CHIEF SIGNALS. EQUIVALENCES
TIMING
DIAGRAM SCEMnTlC- CHART
control w this control is not
rquircd)
Owo pain p r dngk
BC. pun1 Caurtcr Carry
. Omput) BCN-l (Bum
Counter Carry ~Inpuc)
addrm), 15 below.
lines for the circuit of FIGS. 5 to 10.
rightdaal er addras mabla
AH ElUmnl8ddtS CNbl C
Table 3 shows the output signals for the circuit of
FIGS. 5 to 10. *
TABLE 3
EXIERNAL O WU T SIGNALS
NAME DESCRIITION
Yrnd kft ad& bit invmcd subsequent cell.
YmL leRa d k bir
YmR
YmR right add= bit
45
right ad& bic invmcd
Table 4 shows the internal signals for the circuit of
FIG.
FIGS. 5 to 10.
TABLE 4
8
5,452,261
7
s.iTal &lmk. The +,l,ksignal of FIG. 3 is shown in the
tunmg diagram of FIGS. ll(a), ll(b).
FIG. 8 shows the circuitry which provides the timing
signal CASlb which is a timing signal for the above-
described counter circuitry. Note that signal CASlb is 5
in part determined by the signal BM (burst mode) and
by the signal WE1 which in this m e is the burst write
L-... ":-"I
wherein during the duration the external address
enable switch is closed, the address sequencer gen-
erates the second address in the sequence of ad-
dresses.
3. The address generator of claim 1, .wherein the
second address is output to the output terminal of the
address sequencer only when the internal address en-
able switch is closed.
"'yYL "1618.u.
FIGS. l l a and l l b show the timing for the signals of
FIGS. 5 to 10. The start address (designated A,in FIG.
3) is designated Y ~ i n the timing diagram of FIGS. l l a
and llb. The output signal of the counter is designated
YN+, , Y N+>. . . in the timing diagram. I t can be seen
that when the clock signal AS goes high, and after a
particular period, the PRESET signal goes high. In
turn, the PRESET signal going low is determined by
the signal CAS-PAD going low.
The overall clock speed of the chip in terms of ad-
dress generation is determined by the signal CAS-PAD;
in one embodiment this signal has a 15 nanosecond
period, providing a 66 MHz operating speed.
It is to be understood that in a typical operation of the
serial address generator, the associated memory array is
considered to be an array of memory cells arranged in
rows and columns. Each "page" is one row, with the
fmt address on the page being that of the first memory
cell in the column. Signal BE/ m, (burst enable output
enable) at the rising edge of AS determines whether one
is to be in burst mode or in normal page mode. Signal
BE/= is determined by the host computer. The output
of buffer 56 of the circuit of FIG. 5 is connected typi-
cally to a column predecoder for determining the par-
ticular column o f a memory array to be addressed. A
predecoder buffers the address signals prior to provi-
sion thereof to the decoder itself. The predecoder in this
case saves power and increases operating speed, by
serving as a buffer for the decoder proper.
The above description is illustrative and not limiting;
further modifications will be apparent to one skilled in
the art and are intended to be covered by the appended
10
15
20
25
30
35
40
4. The address generator of claim 1, further compris-
ing a buffer serially connected between the output ter-
minal of the address sequencer and the output terminal
of the address generator.
5. The address generator of claim 2, further compris-
ing means for providing a preset signal of a predeter-
mined duration and level to the preset terminal during
at least a portion of the duration of the first address, the
preset signal setting the address sequencer to the second
address in the sequence of addresses.
6. The address generator of claim 2, further compris-
ing means for providing clock signals of predetermined
level to the clock input terminal, a first of the clock
signals occurring only after the duration of the first
address.
7. The address generator of claim 2, wherein the
address sequencer includes a counter having a master
portion and a slave portion.
8. The address generator of claim 1, further compris-
ing means for providing an externally generated address
to the address input terminal, wherein the externally
generated address is a first address of a page of the
random access memory.
9. An address generator for a random access memory,
comprising: '
means for providing a fmt address in a sequence of
addresses, the first address being provided from an
external source as an output address;
an address sequencer for generating the subsequent
addresses in the sequence of addresses, a second
address in the sequence being provided as an out-
put address immediately following the generation
of the first address:
claims.
an internal address enable switch connected between
We claim:
an output terminal of the address sequencer and an
1. An address generator for a random access memory. output terminal o f the address generator;
comprising: 45 an external address enable switch connected between
an address sequencer having a clock input termin& a an address input terminal of the address generator
preset terminal, and an output terminal, and the output terminal of the address generator;
an internal address enable switch connected between and
the output terminal ofthe address Sequencer and an means for incrementally timing the address sequencer
output terminal of the address generator; and during a preset period to generate the second ad-
an external address enable switch connected between dress at a -e h e that the f i t address is being
an address input terminal of the address generator provided from the external source.
and the output terminal of the address generator; 10. A method of generating a sequence of addresses
wherein the address sequencer includes means for for addressing a random access memory, comprising the
incrementally timing the address sequencer to gea- 55 steps of:
erate a second address in a sequence of addresses providing from external source a fust address in
while a fmt address is being supplied to the output the sequence as an output address;
terminal o f the address generator by the external switching in the k t address as M output address
address enable switch.
during a preset peri od;
2. The address generator of claim 1, further COmPris- 60 then, providing from an address sequencer a second
address in the sequence as an output address, the
means for controlling the internal address enable second address being generated by incremental
switcb; and timingduringatleastapartofadurationofthestep
means for controlling the external address enable of providing the fust address; and
switch, wherein the means for controlling the ex- 65 switching in the second address as an output address
after the preset period. ternal address enable switch closes'the external
address enable switch for a duration Of the first 11. The address generator o f claim 2, wherein the
address of the sequence of addresses, and means for controlling the internal address enable switch
50
ing:
5,452,261
9 10
is a logical inversion of the signals provided t o the clock
input terminal.
12. An address generator for a random access mem-
ory, comprising: and
an address sequencer having a clock input terminal, a 5
preset terminal, and an output terminal;
an internal address enable switch connected between
the output terminal ofthe address sequencer and an
output terminal of the address generator;
an external address enable switch connected between lo
an address input terminal of the address generator
and the output terminal of the address generator;
_ _ > able switch.
an external address enable switch connected between
an address input terminal o f the address generator
and the output terminal of the address generator;
means for providing clock signals of predetermined
level to the clock input terminal, a first of the clock
signals occurring only after the duration of the first
address;
wherein the address sequencer generates a second
address in a sequence of addresses while a first
address being suppfied to the output terminal of
the address generator by the external address en-
anu
means for providing a preset signal of a predeter-
mined duration and level to the preset terminal
during at least a portion of the duration of the rust
address, the preset signal setting the address se-
quencer to the second address in the series;
wherein the address sequencer generates a second 2o
address in a sequence of addresses while a fint
address is being supplied to the output terminal of
the address generator by the external address en-
able switch.
13. An address generator for a random access mem- 25
ory, comprising:
an address sequencer having a clock input terminal, a
an internal address enable switch connected between
preset terminal, and an output terminal;
the output terminal of the address sequencer and an 30
output terminal of the address generator;
14. An address generator for a random access mem-
an address sequencer having a clock input terminal, a
preset terminal, and an output terminal,
an internal address enable switch connected between
the output terminal o f the addrss sequencer and an
output terminal of the address generator; and
an external address enable switch connected between
an address input terminal of the address generator
and the output terminal of the address generator;
wherein the address sequencer generates a second
address in a sequence of addresses while a f i t
address is being supplied to the output terminal of
the address generator by the external address en-
able switch, and
wherein the address sequencer includes a counter
having a master portion and a slave portion.
ory, comprising:
* * * . a
35
40
45
50
55
M)
69
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