Fpga 04 Lab Manual

Advanced
Electronic USER MANUAL ALS/SDA/FPGA-04/LM REV2.0

Systems
1 of 75

ALS-SDA-FPGA-04 TRAINER
(LAB MANUAL)

Manufactured By:
ADVANCED ELECTRONIC SYSTEMS
#143, 9TH MAIN ROAD, LAGGERE CROSS,
NEAR RAJAGOPAL NAGAR OLD POLICE STATION,
PEENYA INDUSTRIAL AREA, BANGALURU-560 058,
PHONE: 91-80-41625285/41539484.
E-mail: sales@alsindia.net URL: www.alsindia.net
Advanced
Systems
2 of 75
INDEX
CONTENTS PAGE NO
1. On board programs 4
1) Seven segment display 4
2) Input dip switches 5
3) 4X4 matrix switches 7
4) 16X2 alphanumeric LCD display 8
5) Traffic light simulator 9
6) Speed and direction control of DC motor 10
7) Speed and direction control of stepper motor 10
8) ADC 11
9) Temperature sensor 13
10) DAC 14
11) Elevator 15
12) Relay 17
2. Logical Experiments 18
1) 32BIT_ALU 18
2) The logic gates 22
3) 2 to 4 decoder 23
4) 8 to 3 encoder without priority 24
5) 8 to 3 encoder with priority 28
6) 8X1 multiplexer 32
7) Binary to gray converter 34
8) Demultiplexer 36
9) Four bit comparator 39
Advanced
Systems
3 of 75
10) Full adder 40
11) Flip-flops 42
a. J-K flip-flop 42
b. T flip-flop 43
c. D flip-flop 44
d. S-R flip-flop 45
12) Counters 46
a. Binary counter 46
i. Binary counter with asynchronous reset 47
ii. Binary counter with synchronous reset 47
b. BCD counter 48
i. BCD counter with asynchronous reset 48
ii. BCD counter with synchronous reset 48
c. Any sequence counter 49
3. Installation procedure of Xilinx ISE 10.1 50
4. Project creation 55
5. Procedure to create .BIT and .MCS files and .JED file 56
6. Implementation basics for FPGA 58
7. Downloading procedure 60
8. Important hardware details 61
APPENDIX A: Downloading procedure for external interfaces 62
APPENDIX B: Procedure for generating text bench waveforms 63
APPENDIX C: Procedure for performing ISE simulation 65
APPENDIX D: LCD module specification 72
APPENDIX E: ALS-USBJTAG-02
Advanced
Systems
4 of 75
1. ON BOARD PROGRAMS

1. SEVEN SEGMENT DISPLAY

There are six seven-segment displays in the trainer. Any of the six digits can be
selected using EN1 to EN6 signals and the LEDs of each segment is operated by Dis_out (0
to 7). These segments are active high ON i.e., they are common-cathode type. The
connection details of the 7 segment LED display are as mentioned below.
Note: In case of CPLD XC9572 only 4 digits can be used (EN1 to EN4).

CONNECTIONS: Connect 10 pin FRC cable from CN16 to CN17.
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN17
10PIN FRC BOXTYPE
NC GND
Dis_out<0> Dis_out<1>

PIN DETAILS
UCF
Connector
pin
FPGA
3S50
FPGA
3S400
XC9572
CPLD
SEL0 CN9/20 P21 P21 P31
SEL1 CN9/22 P27 P27 P33
SEL2 CN9/24 P29 P29 P35
En1 CN9/5 P2 P2 P12
En2 CN9/6 P3 P3 P13
En3 CN9/7 P7 P7 P14
En4 CN9/8 P9 P9 P15
En5 CN12/37 P166 P166 NA
En6 CN12/38 P167 P167 NA
Dis_out<0> CN9/9 P10 P10 P17
Dis_out<1> CN9/10 P11 P11 P18
Dis_out<2> CN9/11 P12 P12 P19
Dis_out<3> CN9/12 P13 P13 P20
Dis_out<4> CN9/13 P15 P15 P21
Dis_out<5> CN9/14 P16 P16 P23
Dis_out<6> CN9/15 P18 P18 P24
Dis_out<7> CN9/16 P19 P19 P25
Count<0> CN9/26 P35 P35 P37
Count<1> CN9/28 P37 P37 P40
Count<2> CN9/30 P40 P40 P43
Count<3> CN9/32 P43 P43 P45
NOTE: 1.Download bcd_sevenseg.bit/jed files for FPGA/CPLD

Advanced
Systems
5 of 75
RESULT: - First 3 switches of the DIP1 are used to select U7 to U12 of the seven segment
displays. Next 4 switches of DIP1 are used to set the O/p from 0 to F on the selected
display.

2. INPUT DIP SWITCHES

There are 4 DIP (DIP1 to DIP4) switches provided on the baseboard which are
connected to 32 input LEDs (LG1 to LG32) and to the connectors connecting the Daughter
Board. DIP switches are represented on baseboard from DIP1 through DIP4. When the
drag button of the dip switch is kept in the ON side, the input is high (1) the corresponding
O/p LED will go ON and when the drag button of the dip switch is kept in the OFF side the
input is low (0) and the corresponding O/p LED will go OFF.

DIP1 (1) to DIP1 (8) are represented as IN1 to IN8, DIP2 (1) to DIP2 (8)
are represented as IN9 to IN16, DIP3 (1) and DIP3 (8) are represented as IN17 to
IN24 & DIP4 (1) and DIP4 (8) are represented as IN25 to IN32 respectively. If IN1 is
ON LED LG1 will be ON otherwise LG1 will be OFF and so on.

PIN DETAILS

UCF Connector pin
3S50
IC Pins
3S400
IC Pins
XC9572
IC Pins
INPUT<0> CN9/20 P21 P21 P31
INPUT<1> CN9/22 P27 P27 P33
INPUT<2> CN9/24 P29 P29 P35
INPUT<3> CN9/26 P35 P35 P37
INPUT<4> CN9/28 P37 P37 P40
INPUT<5> CN9/30 P40 P40 P43
INPUT<6> CN9/32 P43 P43 P45
INPUT<7> CN9/34 P45 P45 P47
INPUT<8> CN9/36 P48 P48 P50
INPUT<9> CN9/38 P52 P52 P52
INPUT<10> CN10/6 P58 P58 P54
INPUT<11> CN10/8 P62 P62 P56
INPUT<12> CN10/10 P64 P64 NA
INPUT<13> CN10/12 P67 P67 NA
INPUT<14> CN10/14 P71 P71 NA
INPUT<15> CN10/16 P74 P74 NA
INPUT<16> CN10/24 P80 P80 NA
INPUT<17> CN11/37 P162 P162 NA
INPUT<18> CN10/28 P86 P86 NA
INPUT<19> CN10/30 P90 P90 NA
INPUT<20> CN10/32 P94 P94 NA
INPUT<21> CN10/34 P100 P100 NA
Advanced
Systems
6 of 75

Output LEDs
There are 32 O/P LEDs (LR1 to LR32) which are connected to FPGA/CPLD output pins.
These LEDs are active high type, i.e., they switch ON to indicate a logical 1 status.

PIN DETAILS

UCF
Connector
PIN
3S50
IC pins
3S400
IC pins
XC9572
IC pins
OUTPUT<0> CN9/19 P20 P20 P26
OUTPUT<1> CN9/21 P26 P26 P32
OUTPUT<2> CN9/23 P28 P28 P34
OUTPUT<3> CN9/25 P34 P34 P36
OUTPUT<4> CN9/27 P36 P36 P39
OUTPUT<5> CN9/29 P39 P39 P41
OUTPUT<6> CN9/31 P42 P42 P44
OUTPUT<7> CN9/33 P44 P44 P46
OUTPUT<8> CN9/35 P46 P46 P48
OUTPUT<9> CN9/37 P51 P51 P51
OUTPUT<10> CN10/5 P57 P57 P53
OUTPUT<11> CN10/7 P61 P61 P55
OUTPUT<12> CN10/9 P63 P63 NA
OUTPUT<22> CN10/35 P101 P101 NA
INPUT<22> CN10/36 P102 P102 NA
INPUT<23> CN11/4 P107 P107 NA
INPUT<24> CN11/6 P113 P113 NA
INPUT<25> CN11/8 P115 P115 NA
INPUT<26> CN11/10 P117 P117 NA
INPUT<27> CN11/12 P120 P120 NA
INPUT<28> CN11/14 P123 P123 NA
INPUT<29> CN11/16 P125 P125 NA
INPUT<30> CN11/18 P131 P131 NA
INPUT<31> CN11/20 P133 P133 NA
Advanced
Systems
7 of 75
OUTPUT<27> CN11/11 P119 P119 NA
OUTPUT<28> CN11/13 P122 P122 NA
OUTPUT<29> CN11/15 P124 P124 NA
OUTPUT<30> CN11/17 P130 P130 NA
OUTPUT<31> CN11/19 P132 P132 NA

NOTE: Download sw_led_test.bit/jed files for FPGA/CPLD
RESULT: DIP1 to DIP4 are input pins & LR1 to LR32 used to see the corresponding output
in LEDs.

3. 4X4 MATRIX SWITCH

4X4 matrix Pushbutton switch are provided on the baseboard. These switches
could be used as inputs to FPGA/CPLD through the Daughter Board connectors (KEY0 -
KEY3 are read signals & ROW0 - ROW3 are o/p signals). Note: Refer section 3.1 for the 7
segment display pin details.

9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN17
10PIN FRC BOXTYPE
NC GND

PIN DETAILS
UCF Connector pin
XC3S50
IC Pin
XC3S400
IC Pin
XC9572
IC Pin
RESET CN9/20 PIN 21 PIN 21 PIN 31
CLK CN10/18 PIN 79 PIN 79 PIN 9
KEY 0 CN11/29 PIN 147 PIN 147 PIN 67
KEY 1 CN11/28 PIN 146 PIN 146 PIN 66
KEY 2 CN11/27 PIN 144 PIN 144 PIN 65
KEY 3 CN11/26 PIN 143 PIN 143 PIN 63
EN 1 CN9/5 PIN 2 PIN 2 PIN 12
EN5 CN12/37 PIN166 PIN166 NA
EN6 CN12/38 PIN167 PIN167 NA
Dis_out<0> CN9/9 PIN 10 PIN 10 PIN 17
Advanced
Systems
8 of 75
ROW0 CN11/25 PIN 141 PIN 141 PIN 62

NOTE: Download key_switch.bit/jed files for FPGA/CPLD
RESULT: Result of key is seen on the segment display (U7) and pin 1 of DIP1 is used to
enable the seven segment display (0 for enable and 1 is for disable)

4. 16X2 ALPHANUMERIC LCD DISPLAY
A 16 X 2 Alphanumeric LCD display with back light is provided on the baseboard.
The connection details are as shown in the table below. It is of 4 bit data type.
CONNECTIONS: Connect 10 pin FRC cable from CN16 to CN15 for LCD display

PIN DETAILS
UCF Connector pin
3S50
IC PINs
3S400
IC PINs
XC9572
ICPINS
CLK CN10/18 P79 P79 P9
CNTRL1<0> CN9/9 P10 P10 P17
CNTRL1<1> CN9/10 P11 P11 P18
CNTRL1<2> CN9/11 P12 P12 P19
DATA<0> CN9/12 P13 P13 P20
DATA<1> CN9/13 P15 P15 P21
DATA<2> CN9/14 P16 P16 P23
DATA<3> CN9/15 P18 P18 P24
NOTE: Download lcd.bit/jed files for FPGA/CPLD
RESULT: The resultALS BANGALORE is displayed on the LCD DISPLAY.

5. TRAFFIC LIGHT SIMULATOR
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN15
10PIN FRC BOXTYPE
EI
DT3
DT1 DT2
DT0
RW RS
NC GND
Advanced
Systems
9 of 75

There are four Bipolar LEDs L16 to L19 in which one side is connected to Green and
another side is to RED. For example if you want Red color you have to make the pin
connected to red side high and the other low and vice versa. When both are high it will
give Amber color. We have taken the Pin representations as according to the direction from
which the vehicle is coming.

9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
CN18
16-PIN CONN BOXTYPE
GND
GREEN_W
RED_N
RED_E
RED_S
GREEN_N_Rt
GREEN_S_Rt
GREEN_N
GREEN_E
GREEN_S
GREEN_W_Rt
GREEN_E_Rt
RED_W

PIN DETAILS
UCF CORRES.
NAMES
Connector pin
3S50
IC PINs
3S400
IC PINs
XC9572
IC PINS
CLK CLK CN10/18 P79 P79 P9
g_rt<0> GREEN_E_RT CN12/16 P172 P172 P71
g_rt<1> GREEN_S_RT CN12/15 P171 P171 P70
g_rt<2> GREEN_W_RT CN12/22 P182 P182 P79
g_rt<3> GREEN_N_RT CN12/21 P181 P181 P77
ryg<0> GREEN_E CN12/26 P187 P187 P83
ryg<2> GREEN_S CN12/24 P184 P184 P81
ryg<4> GREEN_W CN12/30 P194 P194 P3
ryg<6> GREEN_N CN12/28 P190 P190 P1
ryg<1> RED_E CN12/25 P185 P185 P82
ryg<3> RED_S CN12/23 P183 P183 P80
ryg<5> RED_W CN12/29 P191 P191 P2
ryg<7> RED_N CN12/27 P189 P189 P84

NOTE: Download traffic_light.bit/jed files for FPGA/CPLD
RESULT: The output result is seen on LEDs (L16 to L23).

6. SPEED & DIRECTION CONTROL OF DC MOTOR
Advanced
Systems
10 of 75

PWM method is used to run the DC motor. First 3 pins of DIP1are used to control
the speed of the DC motor Switch (SW5) is used to control the direction of DC motor. DC
motor should be connected to the 2-pin Relimate connector RM2.


9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN24
10-PIN CONN BOXTYPE
PDCM

PINDETAILS

NOTE: Download dc_motor.bit/jed files for FPGA/CPLD

RESULT: connect the DC motor to relaymate connector RM2 & by selecting the above
explained switches we can vary the speed of DC motor & to change the direction of
rotation of DC motor use switch SW5.

7. SPEED & DIRECTION CONTROL OF STEPPER MOTOR

Note: We can run a Stepper motor which draws up to 300mA current.
Caution: If it draws the current more than 300mA, the U1 IC will get heated.

Stepper motor can be interfaced directly to the power-mate connector PM1. Direction of
the stepper motor can be changed by changing the DIP1 pin 1.Speed of the stepper motor
can be controlled through the software by changing the counter value.


UCF
Connector pin
3S50
IC PINs
3S400
IC PINs
XC9572
IC PINS
CLK CN10/18 P79 P79 P9
PDCM CN12/35 P203 P203 P10
PSW<0> CN9/20 P21 P21 P31
PSW<1> CN9/22 P27 P27 P33
PSW<2> CN9/24 P29 P29 P35
Advanced
Systems
11 of 75
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN24
10-PIN CONN BOXTYPE
GND
DOUT<3>
DOUT<1> DOUT<2>
DOUT<0>.

PIN DETAILS

Connection details of the power-mate connector PM1 are as follows:
Signal PM1
VCC PIN 1
DOUT<3> PIN 2
DOUT<2> PIN 3
DOUT<1> PIN 4
DOUT<0> PIN 5

NOTE: Download stepper_motor.bit/jed files for FPGA/CPLD

RESULT: connect the stepper motor to powermate connector PM1 & by selecting the
switch DIP1/pin1 we can change the direction of rotation of stepper motor.

8. ADC- INTERFACE

INTRODUCTION
It is a Successive Approximation ADC Interface. Feed the input voltage to
channels varying from 0 to 5V (Max. 5V). The particular channel (i.e. Channel 0 &1) is
selected from the toggle switches of DIP1 2 & 3 on the baseboard. Switch positions are
from 00 to 01. 00 corresponds to channel 0 and 01 corresponds to channel 1 respectively.

UCF Connector
pin
3S50
IC PIN
3S400
IC PIN
XC9572
IC PINS
CLK CN10/18 P79 P79 P9
CNTRL CN9/20 P21 P21 P31
DOUT<0> CN12/14 P169 P169 P69
DOUT<1> CN12/17 P175 P175 P72
DOUT<2> CN12/18 P176 P176 P74
DOUT<3> CN12/19 P178 P178 P75
Advanced
Systems
12 of 75

Channel 0 is connected to on board variable voltage through a pot. Channel 1 is
meant for giving an external variable voltage input. Now set switches on the baseboard,
the switch position corresponding to the particular channel through which the input is fed,
remains stable. The converted value is displayed on the 7-segment display of the
baseboard. The unused channel inputs are shorted to ground.
For feeding the external voltage to channel 1 of ADC users need to have the
variable power supply of 0 to 5V. The RM1 is used to give the external voltage , PIN1 of
RM1 is ADC input and PIN2 is GND

CONNECTIONS: Connect 16-pin FRC cable from CN21 to CN19 and 10 pin FRC cable from
CN16 to CN17.
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
CN19
16-PIN CONN BOXTYPE
NC GND
STRT
ADDR0
DOUT0
DOUT3
DOUT4 DOUT5
DOUT6 DOUT7
EOC
DOUT1
DOUT2
ADDR1

TRUTH TABLE
ANALOG I/P DIGITAL O/P
1V 33H
2V 66H
3V 99H
4V CCH
5V FFH

PIN Details
UCF

CONNECTOR
PIN
XC3S50
IC PIN
XC3S400
IC PIN
XC9572
IC PIN
ADDR0 CN12/15 PIN 171 PIN 171 PIN70
CHIN0 CN12/13 PIN 29 PIN 29 PIN31
CLK1 CN10/18 PIN 79 PIN 79 PIN9
DISP0 CN9/9 PIN 10 PIN 10 PIN17
Advanced
Systems
13 of 75
UCF

CONNECTOR
PIN
XC3S50
IC PIN
XC3S400
IC PIN
XC9572
IC PIN
DOUT0 CN12/31 PIN 196 PIN 196 PIN4
DOUT1 CN12/32 PIN 197 PIN 197 PIN5
DOUT2 CN12/29 PIN191 PIN191 PIN2
DOUT3 CN12/30 PIN194 PIN194 PIN 3
EOC CN12/23 PIN183 PIN183 PIN6
OEN1 CN9/5 PIN2 PIN2 PIN 12
OEN5 CN12/37 PIN166 PIN166 --
OEN6 CN12/38 PIN167 PIN167 --
STRT CN12/24 PIN184 PIN184 PIN7

NOTE: Download adc.bit/jed file for FPGA/CPLD.
RESULT: By varying the pot P2 we can observe the ADC o/p on 7- segment display.

9. TEMPERATURE SENSOR

SOFTWARE IMPLIMENTATION
Temperature measurement interface senses the temperature in terms of milli volts
proportional to the temperature. The analog voltage between 0 & 5V is fed to channel 2 of
ADC. ADC reads this value and converts it into corresponding temperature in deg. using
conversion table. The output of this channel is 8 bit hex value. The output is then displayed
on two 7-segment displays (20C to 50C as per the LM335 sensor).

CONNECTIONS: Connect 10 pin FRC cable from CN16 to CN17 and 16 pin FRC cable
from CN21 to CN19. keep the DIP1 first pin in OFF position and second pin in ON
position.
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
CN19
16-PIN CONN BOXTYPE
NC GND
STRT
ADDR0
DOUT0
DOUT3
DOUT4 DOUT5
DOUT6 DOUT7
EOC
DOUT1
DOUT2
ADDR1

Advanced
Systems
14 of 75

PIN Details
UCF

CONNECTOR
PIN
XC3S50
IC PIN
XC3S400
IC PIN
XC9572
IC PIN
CLK1 CN10/18 PIN 79 PIN 79 PIN9
DOUT0 CN12/31 PIN 196 PIN 196 PIN 4
EOC CN12/23 PIN 183 PIN 183 PIN6
OEN5 CN12/37 PIN166 PIN166 --
OEN6 CN12/38 PIN167 PIN167 --
STRT CN12/24 PIN184 PIN184 PIN7

NOTE: Download temp_sensor.bit/jed file for FPGA/CPLD

Advanced
Systems
15 of 75

10. DAC INTERFACE

INTRODUCTION
The DAC interface consists of Digital to Analog converter (DAC0800), the outputs of
which are converted to voltages using Op-amps. The voltage outputs of the op-amps are
terminated at test points TP4. A 2-pin jumper JP4 is provided for UNI polar or Bi polar
output. Apply +12V and -12V along with +5V.
CONNECTIONS: Connect 16-core flat cable from CN21 to the CN4 of the on board DAC.
Observe the required output wave using CRO at the test point TP2.
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
CN4
16-PIN CONN BOXTYPE
NC GND
DOUTa<5> DOUTa<4>
DOUTa<3> DOUTa<2>
DOUTa<1> DOUTa<0>
DOUTa<7> DOUTa<6>

PIN Details
UCF

CONNECTOR
PINS
XC3S50
IC PIN
XC3S400
IC PIN
XC9572
IC PIN
CLKIN CN10/18 PIN 79 PIN 79 PIN 9
DOUTA0 CN12/26 PIN 187 PIN 187 PIN 83

NOTE:
1. Download dacsqr.bit/jed file for FPGA/CPLD for Square wave

2. Download dacsine.bit/jed file for FPGA/CPLD for Sine wave

3. Download dacramp.bit/jed file for FPGA/CPLD for Ramp wave

4. Download dactri.bit/jed file for FPGA/CPLD for Triangle wave

RESULT: Observe the sine, square, ramp & triangular waves on CRO. Jumper JP4 is
provided for UNI polar or Bi polar output.
Advanced
Systems
16 of 75

11. ELEVATOR INTERFACE

OPERATION:
There are 4 keys on the interface board, which are used to send a request for the elevator.
Each key is associated with one floor. Key request is acknowledged by a Red LED, which is
a part of the hardware of the interface board.

There are 10 LEDs L1 to L10. L1, L4, L7 and L10 are green LEDs corresponding to the
floor. Remaining 6 LEDS are amber in color, which indicate the shift position. The software
generates a 4-bit code to switch on these LEDs. Whenever a key (SW1 to SW4) is pressed,
a corresponding D flip-flop on the interface board sets the output, which lights ON the red
LED. Software resets this D flip-flop after sensing the request. Then the LEDs between the
previous floor and the current requested floor will light up sequentially at regular intervals.

SOFTWARE IMPLIMENTATION
The VHDL program senses the four keys, outputs the reset pattern, counts up or counts
down a four bit binary sequence and outputs this binary sequence at regular interval. The
timing required is generated by dividing the input clock.

CONNECTIONS: Connect 16-pin FRC cable from CN21 to CN14.Short jumper JP2 (PIN 1 &
2 for 100KHz and pin 2 &3 for 500KHz)
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
CN14
16 PIN BOX TYPE FRC
NC GND
pkeyscn<0>
pdespsg<1>
pdespsg<3>
pdespsg<0>
pkeyscn<2>
pkeyret<0>
pkeyret<2>
pkeyscn<1>
pkeyscn<3>
pkeyret<1>
pkeyret<3>
pdespsg<2>

PIN Details
ucf

correspond
names
connector
pins
xc3s50
ic pins
xc3s400
ic pins
PCLK100K CLK CN10/20 PIN 77 PIN 79
PKEYSCN<3> CLEAR3 CN12/26 PIN 187 PIN 187
PKEYRET<3> LED12 CN12/22 PIN 182 PIN 182
PDSPSEG<3> ELEV3 CN12/30 PIN 194 PIN 194
Advanced
Systems
17 of 75

NOTE:
1. Download elevator. Bit file for FPGA
2. Elevator interface is not possible for CPLD because of in sufficient of logic
cells.
RESULT: Observe the elevator o/p through LEDs L1 to L14.

12. RELAY INTERFACE

OPERATION:
On the base board we have provided one relay. The common pin of the relay K1 is
connected to VCC (CN13/1). When the relay is activated the NO pin of the relay will be
shorted to the common pin. Normally one of the pins in connector CN13 is connected to
VCC. When the Relay operates the other pin also gets VCC. We have also provided one LED
(L15) to check the relay operation. When the relay operates LED switches ON.
To operate the relay use DIP1/1 switch.

C ONNECTIONS: Connect 10 pin FRC cable from CN22 to CN24.

9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
10-PIN CONN BOXTYPE
CN24
GND
REL_IN

UCF

Connector
pins
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
REL_IN CN12/13 PIN 168 PIN 168 Pin68
ON/OFF CN9/20 PIN 21 PIN 21 Pin31

NOTE:Download relay.bit/jed file for FPGA/CPLD.

RESULT: Relay will operate using the dip switch DIP1/pin1 & when the Relay operates LED
L15 switches On.

OPLED<3> LED3 CN9/19 PIN 20 PIN 20
Advanced
Systems
18 of 75

2. LOGICAL EXPERIMENTS

1. 32BIT_ALU
An Arithmetic and Logic unit (ALU) is a combinational circuit that performs logic
and arithmetic operations on a pair of n-bit operands. The operations performed by an ALU
are controlled by a set of function-select inputs. The design is a 32-bit ALU with 2
functions. The functions performed by the ALU are specified in table below.

BLOCK DIAGRAM

TRUTH TABLE

OPCODES FUNCTION OPERATION
ARITHMATIC OPERATIONS
0001 Ain+bin Addition
0010 Ain-bin subtraction
0100 Ain * bin multiplication
LOGICAL OPERATIONS
0011 ~Ain NOT
0101 Ain & bin AND
0110 Ain | bin OR
0111 (Ain ~& bin) NAND
1000 (Ain ^bin) XOR

CONNECTIONS: Connect 10 pin FRC cable from CN22 to CN23 and CN16 to CN17.

Advanced
Systems
19 of 75

Steps to perform the functions:

1. Select the opcode for required operation as given in the truth table. To select the opcode
use DIP5/3 to DIP5/6.
Note: DIP5 PIN3 is used to select opcode LSB bit
Ex: For ADDITION opcode is 0001 here, LSB is 1 so keep DIP5 PIN 3 high
and others low.
2. Initially keep the Enable PIN low (DIP5/1)
3. Make Master PIN (DIP5/2) as high to give first input (Ain).
4. After giving first input press any key in the first row of KEYPAD interface (0 to 3).
Now the first input/s are read.
5. Make master PIN (DIP5/2) as LOW to give second input (Bin).
6. After giving second input press any key in the first row of KEYPAD interface
(0 to 3). Now the second input/s are read.
7. To get the result make Enable PIN (DIP5/1) as High, here LR32 to LR1 are
used to see the output

Note:
To give inputs use dip switches DIP4 to DIP1.
Here DIP4/8 is considered as LSB bit and DIP1/1 is considered as MSB bit.
During the ADDITION of all 32bit operation, the generated overflow bit (33
rd

bit) is displayed on Seven Segment (1)
The ve sign (in case of subtraction) is also displayed on the Seven Segment.

Example:

Subtraction: opcode is 0010

1) dip4/5 dip4/6 dip4/7 dip4/8 (i/p)
1 1 1 1 (15)
- 1 1 0 0 (12)
lr29 lr30 lr31 lr32 (o/p)
0 0 1 1 (03)

Advanced
Systems
20 of 75

2) dip4/5 dip4/6 dip4/7 dip4/8 (i/p)
1 1 0 0 (12)
- 1 1 1 1 (15)
- 0 0 1 1 (-03)

Result = 1101 (2s complement of -03)

Note:
The ve result is displayed in 2s complement format.
The ve sign is represented on first display of 7-segment

AND: Opcode is 0101

dip4/5 dip4/6 dip4/7 dip4/8 (i/p)
1 1 1 1
1 1 0 0
1 1 0 0

PINOUTS of Daughter Boards

UCF I/O
CONNECTOR
PINS
XC3s50
(FPGA)
XC3s400
(FPGA)
input<0> DIP4/8 CN11/20 P133 P133
input<1> DIP4/7 CN11/18 P131 P131
input<2> DIP4/6 CN11/16 P125 P125
input<3> DIP4/5 CN11/14 P123 P123
input<4> DIP4/4 CN11/12 P120 P120
input<5> DIP4/3 CN11/10 P117 P117
input<6> DIP4/2 CN11/8 P115 P115
input<7> DIP4/1 CN11/6 P113 P113
input<8> DIP3/8 CN11/4 P107 P107
input<9> DIP3/7 CN10/36 P102 P102
input<10> DIP3/6 CN10/34 P100 P100
input<11> DIP3/5 CN10/32 P94 P94
input<12> DIP3/4 CN10/30 P90 P90
input<13> DIP3/3 CN10/28 P86 P86
input<14> DIP3/2 CN11/37 P162 P162
input<15> DIP3/1 CN10/24 P80 P80
input<16> DIP2/8 CN10/16 P74 P74
input<17> DIP2/7 CN10/14 P71 P71
Advanced
Systems
21 of 75
input<18> DIP2/6 CN10/12 P67 P67
input<19> DIP2/5 CN10/10 P64 P64
input<20> DIP2/4 CN10/8 P62 P62
input<21> DIP2/3 CN10/6 P58 P58
input<22> DIP2/2 CN9/38 P52 P52
input<23> DIP2/1 CN9/36 P48 P48
input<24> DIP1/8 CN9/34 P45 P45
input<25> DIP1/7 CN9/32 P43 P43
input<26> DIP1/6 CN9/30 P40 P40
input<27> DIP1/5 CN9/28 P37 P37
input<28> DIP1/4 CN9/26 P35 P35
input<29> DIP1/3 CN9/24 P29 P29
input<30> DIP1/2 CN9/22 P27 P27
input<31> DIP1/1 CN9/20 P21 P21
output<0> OPLED32 CN11/19 P132 P132
Advanced
Systems
22 of 75
enable DIP5/1 CN12/35 P203 P203
master DIP5/2 CN12/36 P204 P204
opcode<0> DIP5/3 CN12/13 P168 P168
opcode<1> DIP5/4 CN12/14 P169 P169
opcode<2> DIP5/5 CN12/17 P175 P175
opcode<3> DIP5/6 CN12/18 P176 P176
key_row PB1 CN11/22 P138 P138
key_ret PB5 CN11/26 P143 P143
dis_out<0> SEG1 CN9/9 P10 P10
seg_en<0> AN4 CN9/8 P9 P9

NOTE: Download alu_32bit .bit file for FPGA.

2. THE LOGIC GATES

This design explains the behavior of all logic gates. The block diagram below shows
I/p and O/p signals. It has 2 inputs A and B & 7 outputs: Andg, Org, Xorg, Nandg, Norg,
Xnorg, and Notg.
BLOCK DIAGRAM

Advanced
Systems
23 of 75

Verify the block as per the truth table given below. The state of the outputs is indicated
by the LEDs (Hi = LED ON).

TRUTH TABLE
INPUTS OUTPUTS
A B Andg Org Xorg Nandg Norg Xnorg Notg
DIP1/P1 DIP1/P2 (LR1) (LR2) (LR3) (LR4) (LR5) (LR6) (LR7)
0 0 0 0 0 1 1 1 1
0 1 0 1 1 1 0 0 1
1 0 0 1 1 1 0 0 0
1 1 1 1 0 0 0 1 0
PIN Details

NOTE: Download allgates.bit/Jed file for FPGA/CPLD.

3. 2 TO 4 DECODER

The 2 to 4 decoder's block diagram is shown in figure below. This design has active
low outputs and two selection inputs (S0, S1). The output is selected through selection
lines.
BLOCK DIAGRAM

UCF I/O
CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
A DIP1/1 CN9/20 PIN 21 PIN 21 PIN 31
B DIP1/2 CN9/22 PIN 27 PIN 27 PIN 33
Andgate OPLED1 CN9/19 PIN 20 PIN 20 PIN 26
Orgate OPLED2 CN9/21 PIN 26 PIN 26 PIN 32
Xorgate OPLED3 CN9/23 PIN 28 PIN 28 PIN 34
Nandgate OPLED4 CN9/25 PIN 34 PIN 34 PIN 36
Norgate OPLED5 CN9/27 PIN 36 PIN 36 PIN 39
Xnorgate OPLED6 CN9/29 PIN 39 PIN 39 PIN 41
Notgate OPLED7 CN9/31 PIN 42 PIN 42 PIN 44
Advanced
Systems
24 of 75

PIN Details

I/O I/O
CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
SEL1 DIP1/1 CN9/20 PIN 21 PIN 21 PIN 31
SEL0 DIP1/2 CN9/22 PIN 27 PIN 27 PIN 33
DOUT3 OPLED 1 CN9/19 PIN 20 PIN 20 PIN 26

The truths table is given below for the above design.

TRUTH TABLE

INPUT OUTPUT
DIP1/1 DIP1/2 LR1 LR2 LR3 LR4
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1

NOTE: Download the file decoder 2 to 4.bit/Jed for FPGA/CPLD.

4. 8 TO 3 ENCODER WITHOUT PRIORITY

The encoder is a combinational circuit that is designed to generate a different output code
for each input, which becomes ASSERTED. In general, encoder is a circuit with n inputs,
one for each information element to be encoded, which generates an identifying code for
each of these inputs. Thus for n elements of information to be uniquely encoded, the
output code width m must satisfy the following relation.
2
m
> n
The block diagram showing the inputs and outputs of the design is as shown below. It has
9 input lines, which are active low viz., DIN 1 to DIN9 and 4 output lines viz., DOUT0 to
DOUT3.

Advanced
Systems
25 of 75
BLOCK DIAGRAM

PIN Details

Truth table and waveforms for this design are given below.

UCF I/O CONNECTOR
PINS
XC3S50
IC PINS
XC3S400
IC PINS
XC9572
IC PINS
DIN 1 DIP1/1 CN9/36 PIN 48 PIN 48 PIN 50
DOUT 0 OPLED 4 CN9/25 PIN 34 PIN 34 PIN 36
Advanced
Systems
26 of 75

TRUTH TABLE

ACTIVE LOW INPUTS
DIN
BCD OUTPUTS
DOUT
9 8 7 6 5 4 3 2 1 3 2 1 0
DIP1
/1
DIP1
/2
DIP1
/3
DIP1
/4
DIP1
/5
DIP1
/6
DIP1
/7
DIP1
/8
DIP2
/1
LR
1
LR
2
LR
3
LR
4
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 0 1 1 1 1 1 1 1 1 1 0 1
1 1 0 1 1 1 1 1 1 1 1 0 0
1 1 1 0 1 1 1 1 1 1 0 1 1
1 1 1 1 0 1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1 1 1 0 0 1
1 1 1 1 1 1 0 1 1 1 0 0 0
1 1 1 1 1 1 1 0 1 0 1 1 1
1 1 1 1 1 1 1 1 0 0 1 1 0

NOTE: Download encoder.bit/jed file for FPGA/CPLD.
Advanced
Systems
27 of 75

TIMING DIAGRAM
1

DIN1 0

1 1

DIN2 0

1 1

DIN3 0

1 1

DIN4 0

1 1

DIN5 0

1 1

DIN6 0

1 1

DIN7 0

1 1

DIN8 0

1 1

DIN9 0

1 1

DOUT3
0 0
1 1 1

DOUT2 0 0

1 1 1

DOUT1 0 0

1 1 1 1 1 1

DOUT0
0 0 0 0 0

Advanced
Systems
28 of 75

5. 8 TO 3 ENCODER WITH PRIORITY

The encoder is a combinational circuit that is designed to generate a different output
code for each input, which becomes ASSERTED. In general, encoder is a circuit with n
inputs, one for each information element to be encoded, which generates an identifying
code for each of these inputs. Thus for n elements of information to be uniquely encoded,
the output code width m must satisfy the following relation.
2
m
> n
The block diagram showing the inputs and outputs of the design is shown below. It has
9 input lines, which are active low viz., DIN 1 to DIN9 and 4 output lines viz., DOUT0 to
DOUT3.

BLOCK DIAGRAM

PIN Details
I/O SWITCH
CONNECTOR
PINS
XC3S50 XC3S400 XC9572
PRI IN10 CN9/38 PIN 52 PIN52 PIN 52
DIN<1> IN9 CN9/36 PIN 48 PIN 48 PIN 50
Advanced
Systems
29 of 75

Truth table
and waveforms for this design are given below.

TRUTH TABLE

NOTE: Download encoderp.bit/jed file for FPGA/CPLD.

DOUT<0> OPLED 4 CN9/25 PIN 34 PIN 34 PIN 36
PRI ACTIVE LOW INPUTS
DIN
OUTPUTS
DOUT
9 8 7 6 5 4 3 2 1 3 2 1 0
IN10 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 D1 D2 D3 D4
0 X X X X X X X X X 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 0 1 1 1 1 1 1 1 1 1 0 1
1 1 1 0 1 1 1 1 1 1 1 1 0 0
1 1 1 1 0 1 1 1 1 1 1 0 1 1
1 1 1 1 1 0 1 1 1 1 1 0 1 0
1 1 1 1 1 1 0 1 1 1 1 0 0 1
1 1 1 1 1 1 1 0 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0 1 0 1 1 1
1 1 1 1 1 1 1 1 1 0 0 1 1 0
Advanced
Systems
30 of 75

TIMING DIAGRAM

Pri 1

0

1
DIN1 0

1 1

DIN2 0

1 1

DIN3 0

1 1

DIN4 0

1 1

DIN5 0

1 1

DIN6 0

1 1

DIN7 0

1 1

DIN8 0

1 1

DIN9 0

1 1

DOUT3
0 0
1 1 1

DOUT2 0 0

1 1 1

DOUT1 0 0

1 1 1 1 1 1

DOUT0
0 0 0 0 0

Advanced
Systems
31 of 75

6. 8X1 MULTIPLEXER

A digital multiplexer is a logical circuit, whose output is same as one of the many
inputs. This input is selected depending on the address input (in other words, select lines)
to the multiplexer. If there are 8 inputs then it is a 8 to 1 multiplexer. The block diagram
below shows the input signals and output signal of the Multiplexer with 8 inputs DIN0 to
DIN7, 3 select inputs SEL0 to SEL2, a enable input 'en' and an output line DOUT.

BLOCK DIAGRAM

PINOUTS OF DAUGHTER BOARD

UCF I/O
CONNECTOR
PINS
XC3S50
IC Pins
XC3S400
IC Pins
XC9572
IC Pins
EN IN4 CN9/26 PIN 35 PIN 35 PIN 37
Advanced
Systems
32 of 75
SEL<0> IN3 CN9/24 PIN 29 PIN 29 PIN 35
DOUT OPLED 1 CN9/9 PIN 20 PIN 20 PIN 26

When EN input is high, irrespective of select inputs, output is low. When EN input is low
and input DIN (7-0) With some value, vary the selection inputs & view the output through
OPLED 1.The truth table for this design type is given below, observe the waveform as
given in figure below.

TRUTH TABLE:

SELECTED INPUT Enable input INPUTS output
sel2 sel1 sel0
IN1 IN2 IN3
EN(IN4)

OPLED1
0 0 0 0
IN12=0 0
IN12=1 1
0 0 1 0
IN11=0 0
IN11=1 1
0 1 0 0
IN10=0 0
IN10=1 1
0 1 1 0
IN9=0 0
IN9=1 1
1 0 0 0
IN8=0 0
IN8=1 1
1 0 1 0
IN7=0 0
IN7=1 1
1 1 0 0
IN6=0 0
IN6=1 1
1 1 1 0
IN5=0 0
IN5=1 1

Advanced
Systems
33 of 75

TIMING DIAGRAM

EN

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0
SEL2
SEL1 000 111 110 101 100 011 010 001
SEL0

DOUT

NOTE: Download mux8_1.bit file for spartan-3 FPGA.

Advanced
Systems
34 of 75

7. 4 BIT BINARY TO GRAY CONVERTER

The significant aspect of gray code is that only one bit changes while proceeding
from one decimal to another. Gray code is not used in arithmetic circuits but is used for
input and output devices in digital systems

BLOCK DIAGRAM

For converting binary to gray code
The left most bit is the same as binary
Add MSB to bit on its immediate right & record it in gray code line. Neglect any
carry.
Continue the process of addition until LSB
The number of bits in Gray code is same as binary

Example: Binary 1 0 0 0
Gray 1 1 0 0
PINOUTS OF DAUGHTER BOARD

UCF I/O
CONNECTOR
PINS
XC3S50
IC Pins
XC3S400
IC Pins
XC9572
IC Pins
B0 IN4 CN9/26 PIN 35 PIN 35 PIN 37
G0 OPLED4 CN9/25 PIN 34 PIN 34 PIN 36

Advanced
Systems
35 of 75

TRUTH TABLE
BINARY CODE GRAY CODE
IN1 IN2 IN3 IN4 OPLED1 OPLED2 OPLED3 OPLED4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

TIMING DIAGRAM
IN4

IN3

IN2

IN1

OPLED4

OPLED3

OPLED2

OPLED1

NOTE: Download bintogrey.bit/jed file for FPGA/CPLD.

Advanced
Systems
36 of 75

8. DEMULTIPLEXER (1X8)

The function of a Demultiplexer is just the inverse of a multiplexer. The decoder's
enable logic is connected to the data line, and its select inputs determine which of its
output lines is driven with the data bit. The Demultiplexer shown below has a single input
(E) and 8 outputs (Dout0 to Dout7). Out of 8 output lines one is selected depending on the
status of the three select inputs (SEL 0 through SEL 2).

BLOCK DIAGRAM

PIN Details

UCF I/O
CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
SEL 0 IN3 CN9/24 PIN 29 PIN 29 PIN 35
E IN4 CN9/26 PIN 35 PIN 35 PIN 37
Advanced
Systems
37 of 75

The input 'E' is transmitted to one of the 8 output lines according to the select lines.
i.e. When IN4 i.e. E='0' a '0' will appear on the selected output line or when E='1' a '1'
will appear on that output line.
TRUTH TABLE:

INPUT OUTPUT(DOUT)
SEL2 SEL1 SEL0 LR1 LR2 LR3 LR4 LR5 LR6 LR7 LR8
IN1 IN2 IN3 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 1 1 1 1 1 1 E
0 0 1 1 1 1 1 1 1 E 1
0 1 0 1 1 1 1 1 E 1 1
0 1 1 1 1 1 1 E 1 1 1
1 0 0 1 1 1 E 1 1 1 1
1 0 1 1 1 E 1 1 1 1 1
1 1 0 1 E 1 1 1 1 1 1
1 1 1 E 1 1 1 1 1 1 1

NOTE: Download demux.bit/jed file for FPGA/CPLD.

Advanced
Systems
38 of 75

TIMING DIAGRAM

E

SEL2 000 111 110 101 100 011 010 001
SEL1
SEL0

DOUT 0

DOUT 7

DOUT 6

DOUT 5

DOUT 4

DOUT 3

DOUT 2

DOUT 1

Advanced
Systems
39 of 75

9. 4 BIT COMPARATOR

Comparators can be designed for comparing multi bit numbers. Fig shows the block
diagram of 4-bit comparator. It receives two 4-bit numbers 'A' and 'B' as inputs and
the outputs are 'X', 'Y' and 'Z' where X is A less than B and Y, A is equal to B and Z is A
greater than B. Depending upon the relative magnitude of the two numbers, one of
the outputs will be high.

BLOCK DIAGRAM

Vary the inputs to the comparator through toggle switches and observe corresponding
output through LEDs as mentioned in above block diagram. Table below gives the truth
table of a design type, and observe the waveform as given in figure below shows

PIN Details

UCF I/O CONNECTOR
PINS
XC3S50
IC pin
XC3S400
IC pin
XC9572
IC pin
A3 IN1 CN9/20 PIN 21 PIN 21 PIN 31
Advanced
Systems
40 of 75
X OPLED 1 CN9/19 PIN 20 PIN 20 PIN 26
Y OPLED 2 CN9/21 PIN 26 PIN 26 PIN 32
Z OPLED 3 CN9/23 PIN 28 PIN 28 PIN 34

TRUTH TABLE:
COMPARING INPUTS OUTPUTS
LR1 LR2 LR3
A<3:0> , B<3:0> X Y Z
A < B 1 0 0
A = B 0 1 0
A > B 0 0 1

Where 0-low level 1-high level X-don't care A3, A2, A1, A0, B3, B2, B1, B0- are comparing
inputs. X,Y AND Z are outputs.

NOTE: download the file comparator.bit/jed for FPGA/CPLD.

10.FULL ADDER

INTRODUCTION:

Addition is the most commonly performed arithmetic operation in digital systems. To add
operands with more than one bit, we must provide for carries between bit positions and
the building block is called as Full adder. Besides the addend-bit inputs A and B, a full
adder has a carry-bit input Cin. The sum of the three inputs can range from 0 to 3, and it
has two outputs sum, which is indicated by SUM and carry-bit which is indicated by CARRY
in the block diagram. The block diagram of a full adder is shown below.
BLOCK DIAGRAM

Advanced
Systems
41 of 75
PIN Details
I/O SWITCH Connector
Pins
XC3S50
IC pin
XC3S400
IC pin
XC9572
IC pin
A IN1 Cn9/20 PIN 21 PIN 21 PIN 31
B IN2 Cn9/22 PIN 27 PIN 27 PIN 33
C IN3 Cn9/24 PIN 29 PIN 29 PIN 35
S OPLED1 Cn9/19 PIN 20 PIN 20 PIN 26
CO OPLED2 Cn9/21 PIN 26 PIN 26 PIN 32

Here, S is 1 if an odd number of the inputs are 1, and COUT is 1 if two or more numbers
of the inputs are 1.
TRUTH TABLE
A B C SUM CARRY
IN1 IN2 IN3 OPLED 1 OPLED 2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

TIMING DIAGRAM

NOTE:
1. Full adder Combinational : For FPGA/CPLD Dowload the file fa_comb.bit/jed.
2. Full adder Sequential : For FPGA/CPLD Dowload the file fa_seq.bit/jed.
3. Full adder Structural : For FPGA/CPLD Dowload the file fa_str.bit/jed.

Advanced
Systems
42 of 75

11. FLIP FLOPS

a. J-K FF

The J and K inputs are analogous to S R flip-flop. The problem of what to do when S R are
asserted simultaneously is solved using JK flip-flop. In the JK flip-flop, the unpredictable
state of the RS flip-flop is defined. Inputs J & K behave like inputs S and R to set and Reset
the flip-flop respectively. J asserts the masters S input only if the flip-flops Qn output is
currently 1(i.e. Q=0), and K asserts the masters R input only if Q is currently 1. Thus, if J
and K are asserted simultaneously, the flip-flop goes to the opposite of its current state.
The Block diagram and truth table for JK flip-flop is as shown below.

BLOCK DIAGRAM
PIN Details
UCF I/O CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
J IN1 CN9/20 PIN 21 PIN 21 PIN 31
K IN2 CN9/22 PIN 27 PIN 27 PIN 33
PULSE PB5 CN11/26 PIN 143 PIN 143 PIN 63
ROW PB1 CN11/22 PIN 138 PIN 138 PIN 57
Q OPLED 1 CN9/19 PIN 20 PIN 20 PIN 26
QBAR OPLED 2 CN9/21 PIN 26 PIN 26 PIN 32

Change inputs J & K and press and leave KB1 and observe the output on OPLEDs.

TRUTH TABLE
KB1 J(IN1) K(IN2) Q(D1) Q/(D2)
0 1 0 1
1 0 1 0
1 1 Q/ Q
0 0 Q Q/

NOTE: Download jkflipflop.bit/jed file FPGA/CPLD.

Advanced
Systems
43 of 75

b. T - FLIP-FLOP

T flip-flop is also called as TOGGLE flip-flop. The T flip-flop is the modification of
the JK flip-flop. T flip-flop is obtained by connecting both the inputs of J K flip-flop. T flip-
flop can also be obtained by connecting the nDOUT signal to D input in a D flip-flop.
An enable input is used which when high, allows the clock to toggle (change state) the
output. If enable is low the output remains in the previous state, i.e. clock is not allowed to
toggle the output. In this experiment user has to set data input EN through toggle switch
IN1 and observe the output DOUT and n-DOUT through OPLED1 to OPLED2 by pressing
pushbutton switch key KB1 (which is present in 4x4 key matrix). When KB1 push button is
pressed, the OUTPUT changes state if it enabled. If enable is zero then there is no change
in the output, it will assign the previous output.

BLOCK DIAGRAM

PIN Details
I/O SWITCH Connector
pins
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
EN IN1 Cn9/19 PIN 21 PIN 21 PIN 31
PULSE PB5 Cn11/26 PIN 143 PIN 143 PIN 63
ROW PB1 Cn11/22 PIN 138 PIN 138 PIN 57
DOUT OPLED 1 Cn9/19 PIN 20 PIN 20 PIN 26
n-DOUT OPLED 2 Cn9/21 PIN 26 PIN 26 PIN 32

TRUTH TABLE
INPUTS OUTPUTS
KB1 EN(IN1) DOUT(D1) N-DOUT(D2)
0 DOUT n-DOUT
1 n-DOUT DOUT

Advanced
Systems
44 of 75

TIMING DIAGRAM

EN

DOUT

n_DOUT

NOTE: Download tflipflop.bit/jed file for FPGA/CPLD.

c. D- FLIP-FLOP

This design explains the behavior of D-type Flip-flop. The block diagram of this design
is shown in figure below. It has one data input (DIN) and one push button input (PULSE).
And two outputs DOUT and n-DOUT, which are complement of each other. We often need
latches simply to store bits of information. For every rising edge of input pulse, DOUT will
follow the input DIN.

BLOCK DIAGRAM

Advanced
Systems
45 of 75

PINOUTS OF DAUGHTER BOARDS

Change input DIN and press and leave KB1 and observe the output on OPLEDs.

TRUTH TABLE

NOTE: Download dflip_flop.bit/jed file for FPGA/CPLD.

d. S-R FLIP-FLOP

S-R flip-flop is also known as Set Reset flip-flop .A high to low transition on S input may
cause high to low transition on Q output, similarly a low to high transition on R input can
cause high to low transition on Q. In most of the application Qn is always compliment of Q
output. If both S and R are 1,as they are in several places then both outputs are forced to
0, in such cases negate either of input, the output returns to complimentary operation as
usual. S sets or presets the Q output to 1; R resets or clears the Q output to 0.

BLOCK DIAGRAM

I/O

SWITCH Connector
Pins
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
DIN IN1 Cn9/20 PIN 21 PIN 21 PIN 31
DOUT OPLED1 Cn9/19 PIN 20 PIN 20 PIN 26
n-DOUT OPLED2 Cn9/21 PIN 26 PIN 26 PIN 32
INPUTS OUTPUTS
KB1 DIN(IN1) DOUT(D1) N-DOUT(D2)
0 0 1
1 1 0
Advanced
Systems
46 of 75

PIN Details
I/O SWITCH
Connector
Pins
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
S IN1 Cn9/29 PIN 21 PIN 21 PIN 31
R IN2 Cn9/31 PIN 27 PIN 27 PIN 33
Q OPLED 1 Cn9/19 PIN 20 PIN 20 PIN 26
Q/ OPLED 2 Cn9/21 PIN 26 PIN 26 PIN 32
Change inputs S & R and press and leave KB1 and observe the output on
OPLEDs.
TRUTH TABLE
KB1 S(IN1) R(IN2) Q(D1) Q/(D2)
0 1 0 1
1 0 1 0
1 1 X X
0 0 Q Q/
Here 'X' is the don't care condition since this case is not allowed in SR flip-flop.
NOTE: Download srflipflop.bit/jed file for FPGA/CPLD

12. a. BINARY COUNTER

Figure below shows the block diagram of Binary counter. It has 2 inputs 'CLK' and 'RESET
and 4-bit output COUNT 3 to COUNT 0 which are attached to 4 OPLEDs i.e. OPLED1 to
OPLED4 respectively. The program is designed to count up from 0000 to 1111.

BLOCK DIAGRAM
Advanced
Systems
47 of 75

In this program, the on-board clock signal of 10 MHz (oscillator Y1) is used. This clock
signal is internally divided to get 1KHz(1msec).

(i). Binary Counter with Asynchronous Reset:

If RESET='1', then counter's result is 0000.
If RESET='0', then counter starts to count from 0000 and goes up to 1111 & then
goes back to 0000 value and repeats the count.

NOTE: Download bin_arst.bit/jed file for FPGA/CPLD.

(ii). Binary Counter with Synchronous Reset:

If RESET='0' then counter starts to count from 0000 and goes up to 1111
and then goes back to 0000 value and repeats the count.
If RESET='1', then the count will stop counting.
If RESET='0', then counter will starts to count from the number where it was
stopped.

NOTE: Download bin_srst.bit/jed file for FPGA/CPLD.

PIN Details
I/O SWITCH CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
RESET IN1 CN9/20 PIN21 PIN 21 PIN 31
CLK CLK CN10/20 PIN79 PIN 79 PIN 9
COUNT 0 OPLED 4 CN9/25 PIN34 PIN 34 PIN 36

Advanced
Systems
48 of 75

12. b. BCD COUNTER

Figure below shows the block diagram of BCD counter. It has 2 inputs 'CLK' and 'RESET
and 4-bit output COUNT 3 to COUNT 0 which are attached to 4 OPLEDs i.e. OPLED1 to
OPLED4 respectively. The program is designed to count from 0 to 9 (i.e., 0000 to 1001).

BLOCK DIAGRAM

In this program, the on-board clock signal of 10 MHz (oscillator Y1) is used. This clock
signal is internally divided to get 1KHz (1msec).

(i). BCD Counter with Asynchronous Reset:
If RESET='1', then counter's result is 0000.
If RESET='0', then counter starts to count from 0000 & goes up to 1001 & then
goes back to 0000 value and repeats the count.

NOTE: Download bcd_arst.bit/jed file for FPGA/CPLD.

(ii). BCD Counter with Synchronous Reset:
If RESET='0' then counter starts to count from 0000 and goes up to 1001
and then goes back to 0000 value and repeats the count.
If RESET='1', then the count will stop counting.
If RESET='0', then counter will starts to count from the number where it was stopped.

NOTE: Download bcd_srst.bit/jed file for FPGA/CPLD.

Advanced
Systems
49 of 75

PINOUTS OF DAUGHTER BOARDS

12.c. ANY SEQUENCE COUNTER

INTRODUCTION
Any Sequence counter is the one which counts repeadly the the numbers in which way
they have given in the program. It has 2 inputs 'CLK' & 'RESET & 4-bit output COUNT3 to
COUNT0 which are attached to 4 OPLEDs i.e. OPLED1 to OPLED4 respectively. When the
reset='0' this program repeadly counts the numbers 3,6,9,12,15,0.
BLOCK DIAGRAM
PIN Details
I/O CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
RESET IN1 CN9/20 PIN21 PIN21 PIN31
CLK CLK CN10/20 PIN79 PIN79 PIN9
COUNT 0 OPLED 4 CN9/25 PIN34 PIN34 PIN36

NOTE: Download anyseq_cnt.bit file for spartan-3 FPGA.

I/O CONNECTOR
PINS
XC3S50
IC pins
XC3S400
IC pins
XC9572
IC pins
RESET IN1 CN9/20 PIN21 PIN21 PIN31
CLK CLK CN10/20 PIN79 PIN79 PIN9
Advanced
Systems
50 of 75

3. INSTALLATION PROCEDURE OF XILINX 10.1

After inserting the CD/DVD which contains Xilinx ISE 10.1 software to CPU CD/DVD
Driver follow the below steps to install it properly.

STEP 1: Double click on the setup file. User will see the following window on the screen.
Click Next.

STEP 2: Enter the Registration ID present in CD, and then click Next.

Advanced
Systems
51 of 75

STEP 3: In this window select what all the features have to be installed along with ISE.
Click Next.

STEP 4: Click on I accept.. and then click Next.

STEP 5: Again Click on I accept.. and then click Next.

Advanced
Systems
52 of 75

STEP 6 : Mention the destination directory where ISE should be installed.

STEP 7: Select the what are the options to be installed. Click Next.

STEP 8: Select the options and click Next.

Advanced
Systems
53 of 75

STEP 9: Click on features required and click Next.

STEP 10: Afterwards click on install to begin installation.

STEP 11: Installation begins and installs the features selected.
Wait for some time for Installation

Advanced
Systems
54 of 75

STEP 12: When the installation completes this window appears. Click ok.

Advanced
Systems
55 of 75

4. PROJECT CREATION

After completing the installation of Xilinx ISE 10.1, user can now create the
projects for FPGA/CPLD in that software. To create the project follow the below steps.
Click the Xilinx ISE 10.1 icon present on the desktop Main window will be open
Go to FILE -> New project , Now Enter project location and project name and then click
NEXT
Here you need to enter your devise property such as its family ,speed ,simulator etc as
shown bellow. After that click on next
2. Device family : Ex: Spartan-3/XC9500
3. Device : Ex: XC3S50 OR XC3S400 OR XC9572
4. Package : Ex: PQ208/PC84
5. Speed grade : Ex: 5
6. Top level Module type : HDL
7. Simulator : Modelsim-XE vhdl
8. Generated simulation language: VHDL

Now you have to create New Source .Select VHDL MODULE if u wants to write the
program in VHDL or select verilog module to write verilog programs etc. example is
given bellow .Once this is over click on next.
1. In the first text box : Select the VHDL module
2. In the second text box : Enter the file name
3. In the third text box : It will show the same PATH, Whatever
user has entered in the
FIRST WINDOW.
FOURTH WINDOW: Define VHDL source
Entity name : Default
Architecture name : Default
This window shows a table to enter inputs and outputs
Port name Direction MSB LSB

1. Port name: Enter the Input and Output names
2. Direction :Select In or out or In/out (Depending upon the application)
3. MSB: Select the number of bit
4. LSB: Select the number of bit
Click on NEXT to proceed
FIFTH WINDOW: New source information
Source type : VHDL module
Source name :<name>.vhd
Entity name :<Default>
Architecture name:<Default>
Click FINISH to go into Main window. In main window the default library files is
already given and the entity according to your process done while creating project will
be displayed. Now you can write the program.
Advanced
Systems
56 of 75

5. PROCEDURE TO CREATE .BIT AND .MCS FILE (FPGA)

After writing the program for FPGA user need to follow the bellow steps carefully. In main
window there are mainly two sub windows (Sources and Processes) that are very
important for project.
In sources window keep the .vhd file selected and in process window you have
synthesize, implement design, generate programming file and configure target device.

1. Synthesis: In the Source Window highlight the .vhd Or .v file which is to be
Synthesized. Then in the process window right click on the Synthesis and Select
RUN.
2. Implementation: In the Source Window highlight the .vhd Or .v file for which
the I/O pins has to be assigned. In the Process window select +User Constraints in
that select Assign package pins. It gives message that User Constraint File will be
created. Click Yes. Xilinx PACE Software window appears with I/O names. Select Loc
and Give Pin numbers for signals and then save. A bus delimiter will appear click ok.
Then the .UCF file will be appeared the source window these pins can also be given
using Edit Constraints. In the process window right click on the Implement design
and select RUN to implement the design file.
3. Generate a bit file: In the Source Window highlight the .vhd Or .v file for which
the .bit file has to be created. In the process window right click on the Generate
programming file and select RUN to create the .bit file.
4. Generate .mcs File:
a) In process window right click on generate PROM, ACE or JTAG file (iMPACT).
b) Click PROM file.
c) Click NEXT.
d) Click Xilinx serial PROM.
e) Click mcs as a PROM file format.
f) Enter PROM file name.
g) Specify the location in which mcs file to be stored.
h) Click NEXT.
i) Select a PROM as XCF and beside of this text box as xcf01s.
j) Click on ADD.
k) Click on NEXT.
Advanced
Systems
57 of 75
l) File generation summery will open and then click on NEXT.
m) Click on Add File.
n) Select bit file to convert as mcs file.
o) Click open.
p) MESSAGE: Would you like to add another design file to data stream click NO.
q) Click FINISH to start generating file.

Now the .bit and .mcs files are created. To download these file to FPGA and EEPROM,
read the chapter 4.
NOTE: Same procedure has to be followed to create the .JED file which is
downloadable file for CPLD.

Advanced
Systems
58 of 75

6. IMPLEMENTATION BASICS FOR FPGAS

For physical verification of the code, user has to follow VLSI design flow, which is as
follows.
1. Design entry
2. Synthesis
3. Gate level simulation
4. Implementation
5. Programming

1) Design entry: In this, the user can write HDL code either in VHDL or verilog. There are
mainly two types which user has to specify.
Entity
Architecture

Entity: Entity is the specification of input and output signals / ports.
Architecture: Architecture is the functional description of the design in HDL format.
2) Synthesis: Synthesis is a process of conversion of HDL code to Gate level net list of
the design. Net list is the connectivity description of gate level circuit. Synthesis is a target
technology dependent issue; hence user has to specify the target / device correctly
including its package type and speed grade. After synthesis EDA tool will generate
EDIF/XNF file.
3) Simulation: In simulation the user can verify the functionality of design after
synthesis.This simulation is also called gate level simulation. In this user can select
required input and output signals, and simulate various input conditions and observe the
output results. Any wrong results obtained from the program have to be rectified by
modifying HDL code, re-synthesis and simulate till user gets desired results.

4) Implementation: This is also called place and route. Before implementation of design,
user must write the UCF (user constraint file) that describes the pin locking of input and
output signals.

Advanced
Systems
59 of 75

At the time of implementation set the UCF file to place and route tool to implement
the design and fix the Input / Output signals as per design requirement. User can get the
gate consumption and pin diagram details by referring the implementation reports.

5) Programming: Programming is the process of downloading the final .bit file/.mcs file
generated by the tool into the target device. Interface the target device to parallel port of
computer through JTAG . Tool will offer two options JTAG/ OPTIONAL PROM formatter.

Select the cable type viz. parallel. Once the cable is sensed then, download the
design by using download option. If the device is configured properly the green LED
(Done) given on the FPGA board will glow indicating proper configuration of the device.

Advanced
Systems
60 of 75

7. DOWNLOADING PROCEDURE

1. Connect one end of a 10-pin FRC cable to the Daughter Board CN1 and other end to
the 10 PIN FRC connector or JTAG parallel adapter, the other end of which connects
to the PC parallel port.
2. Short the 1&2 pins of jumper JP1 on Daughter board of FPGA to download the .bit
file and 2&3 to download .mcs file. For CPLD no jumper selection is needed, directly
you can download the .JED file to CPLD.
3. In the process view click on Configure Device (iMPACT).
4. Select the boundary scan mode and click on NEXT.
5. Select automatically connect cable and identifies Boundary scan chain.
Click on FINISH.
6. MESSAGE: For FPGA There are two devices detected in the boundary scan
chain and for CPLD one device will be detected. iMPACT will now direct you
to associate ,start with the first. Click on OK.
7. To program in PROM, double click on XCF01s select the .mcs file and click OK.
If you want to program directly to FPGA, select XC3S50 device and select the .bit
file.
9. NOTE: You may select both PROM and FPGA associate each with .mcs and .bit file
respectively. You can program any one of the devices.
9. Right click on xcf01s. Then click program and click OK.
10. After downloading, short pin 2 and 3 of jumper JP1 on Daughter board.
11. Press PROG switch to configure the IC. Only if PROM is programmed
NOTE: If only FPGA is programmed dont press PROG switch.
12. Done LED will lights up when FPGA is configured successfully.
NOTE: while generating bit file ensure that the Startup clock is connected to
the CCLK clock.

Advanced
Systems
61 of 75

8. IMPORTANT HARDWARE DETAILS

1) FOR FPGA (3S400 or 3S50)
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
10-PIN CONN BOXTYPE
CN22
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
16 PIN CONN BOXTYPE
CN21
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN16
10PIN FRC BOXTYPE
P197 P196
P194
P189
P185
P183
P178
P181
P171
P190
P187
P184
P108
P182
P172
P191
P175
P203
P176
P168
P204
P169
NC
NC
NC
GND
GND GND
P15
P19
P12
P10
P16
P13
P18
P11

2) FOR CPLD (xc9572)

9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
10-PIN CONN BOXTYPE
CN22
9
7
5
3
1
10
8
6
4
2
12 11
13 14
16 15
9
7
5
3
1
10
8
6
4
2
12
14
16
11
13
15
16 PIN CONN BOXTYPE
CN21
9
7
5
3
1
10
8
6
4
2
9
7
5
3
1
10
8
6
4
2
CN16
10PIN FRC BOXTYPE
NC
NC
NC
GND
GND
GND
P5 P4
P3
P84
P82
P80
P75
P77
P70
P1
P83
P81
P74
P76
P79
P71
P2
P72
P68 P69
P25 P24
P21
P19
P10 P17
P23
P20
P18 P11

As the above two connectors are very important on the board, because through
these connectors only we will operate the on board peripherals (such as DAC,
ADC, ELEVATOR etc).

In these connectors the P indicated PIN of FPGA that means consider P171
which is directly brought to CN21 pin 1 from FPGA. The corresponding peripheral
connector details is given next chapter with its the explanation.

By these all connections you can operate the required peripherals but
some, connections to the peripherals are directly connected (such as AN1,
AN2.. in seven segment display and Keypad row, column etc), you cant change
its pin outs.

Advanced
Systems
62 of 75

APPENDIX-A: DOWNLOADING PROCEDURE FOR EXTERNAL INTERFACES.

1. Connect +5V and GND to the interface using the 4-way power-mate. Colour code of the
4-way power-mate connector (power-mate) on the interface is as shown bellow.
+5V Blue
GND Black
+12V RED
-12V GREEN
2. Switch on power supply.
3. Connect 26 core FRC connector from the ALS FPGA trainer (CN21) present on the
baseboard to 26-pin connector on the ALS NIFCS.
4. Connect 10 pin FRC JTAG connector (master serial cable) to the Daughter board at one
end and 10 pin JTAG FRC connector of the Downloading tool CPLD/FPGA at the other
end.
5. Run Xilinx JTAG programmer (IMPACT) utility to load the design *.bit file into the
SPARTAN-3 FPGA .

NOTE: Care should be taken such that, PIN1 on the trainer coincides with the
PIN1 of the of FRC cable (Observe the notch on the connector).

Advanced
Systems
63 of 75

APPENDIX B: PROCEDURE FOR GENERATING TEST BENCH WAVEFORMS

Synthesize the program for which the TEST BENCH WAVE FORM has to be created.
Right click on particular source file and select new source.
Right click on device (ex: xc3s50-5pq208) in source window and select Properties.
Select simulator as ISE Simulator
It is advisable to use clocks in the process sensitivity list or any process which is either
same as or divided by 2 of the input clock specified in the Entity ports list. Otherwise it
takes a lot of simulation clocks before generating output waveform. If any divided by
clock software is used, either by-pass that procedure or change the main program under
simulation to use a direct clock which is specified in the Entity port list.
In new source window select TEST BENCH waveform option. Give test bench file name
and path.
Click NEXT.
Select source file name and click NEXT.
Click FINISH.
Select the rising edge or falling edge
- Select SINGLE clock.
- Clock HIGH time and clock LOW time.
- Dont select ASYNCRONOUS signal support unless the source file is irrespective of clock.
- Click OK.
Set the input values as required (shown in blue colour) waveform and set end of test
bench.
Save the waveform save icon given in that window only.
In the sources window instead of implementation select behavioral model
In process window Double click on simulate behavioral model.
Now the required waveforms can be observed in the wave default window.
Click on zoom full option given on top of the default window.
Now study the output waveform and verify with the source file.

Advanced
Systems
64 of 75

EXAMPLES

TRAFFIC LIGHT SIMULATOR

Select the input clock as 10Mhz in the program written in order to test/verify the
output waveforms with practical values. The waveform is shown bellow. For all the
programs the procedure is same as given in chapter-IV.

- SCHEMATICS

To create schematic for written VHD code double click on the view RTL schematic in
Synthesize-XST . The schematic symbol will automatically create. The schematic symbol
shown bellow is example of bcd_7seg program.

Advanced
Systems
65 of 75

APPENDIX-C: PROCEDURE FOR PERFORMING ISE SIMULATION
STEP 1:

Open the project for which user wants to perform the simulation. In the source window
select .vhd program for which the simulation need to be done. In the Process window
click on synthesis. Check for errors. If no errors proceed.

STEP 2:

Advanced
Systems
66 of 75

In the sources window, right click on the component (XC3S50) and select the
properties.
STEP 3:

In the properties window select ISE Simulator(VHDl/verilog) and click OK

STEP 4:

In the sources window select the Behavioral Simulation.

Advanced
Systems
67 of 75

STEP 5:

In the sources window right click on component and select the New Source

STEP 6:

Select the Test Bench Waveform and write file name (eg: tst_bcdctr) in the File name
tab. And click Next.

Advanced
Systems
68 of 75

STEP 7:

Select the source file for which simulation has to be done and click Next.

STEP 8:

Then click finish.

Advanced
Systems
69 of 75

STEP 9:

This window will appear as soon as you finish the previous step.This setting will be
more or less same for all the projects. Select Combinatorial if there is no clock in the
vhd file under simulation.

STEP 10:

Advanced
Systems
70 of 75

After Step 9 this window appears.
STEP 11:

Right click anywhere on the waveform area shown in step 10 above and select Set End
of Test Bench
STEP 12:

End of Test Bench time is the time duration of simulation. Enter appropriate time as
required.
STEP 13:

Advanced
Systems
71 of 75

In this widow set the inputs according to your program requirement by right clicking on
the waveform. Then save this test bench waveform. Using File/Save or CTRL+S
STEP 14:

This simulated waveform window appears after clicking on the Simulator Behavioral
Model present in Processes window.

Advanced
Systems
72 of 75

APPENDIX-D: LCD MODULE SPECIFICATION

LCD MODULE: LM16201
Size (L X W X T): 80 X 36 X 10 mm Minimum Viewing Area
(L X W) 64.7 X 14 mm Character construction
5 X 7 dots Character size (H X W) 6.56 X 3.07 mm
Character pitch 3.77 mm
Dot size (H X W) 0.75 X 0.55 mm

ABSOLUTE MAXIMUM RATINGS

Min. Typical Max.
Power supply voltage 4.0 V 5.0 V 7.0 V
LCD bias voltage 4.5 V 5.5 V 11.0 V
Operating Temperature 0 25 Deg C 50 Deg C
Storage Temperature 20 Deg C 25 Deg C 50 Deg C

ELECTRICAL CHARACTERISTICS (VDD = 5V @ 25 Deg C)

Min. Typical Max.
Input High Voltage 2.2 V - -
Input Low Voltage - - 0.6 v
Output High Voltage 2.4 V - -
Output Low Voltage - - 0.4 V

Power Supply Current IDD - 0.8 mA 1.8 mA
ILED - 130 mA 195 mA

Drive Method : 1/16 Duty

DESCRIPTION OF INSTRUCTION CODES:

1) Clear Display
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0 0 0 0 0 0 0 0 0 1

When this instruction is executed, the LCD display is cleared & returned to its original
status if it was shifted. The cursor goes to the left edge of the display (the left end of the
first line if 2-line mode).
2) Return Home

Advanced
Systems
73 of 75
Code 0 0 0 0 0 0 0 0 1 *
* No Effect
The cursor or blinks go to the left edge of the display (to the left end of the first line in the
2-line display mode). The display returns to its original status if it was shifted, DDRAM
contents do not change. Sets the DDRAM address 0 in address counters.

3) Entry mode set
Code 0 0 0 0 0 0 0 1 I/D S
I/D: When the I/D is set, the 8-bit character code is written or read to and from the
DDRAM, the cursor shifts to the right by 1 character position (I/D = '1';increment) or to
the left by 1 character position (I/D = '0'; decrement). The address counter is incremented
(I/D = 1) or decrement (I/D = 0) by 1 at this time. Even after the character pattern code
is written or read to and from the CGRAM, the address counter (AC) is incremented (I/D =
'1') or decrement (I/D = '0') by 1.
S: Shifts the entire display either to the left when S=1 & I/D=1 or to the right when I/D =
0.Thus it looks as if the cursor stands still and the display moves. The display does not
shift when reading from the DDRAM or when writing into or reading out from the CGRAM
when S=0.

4) Display ON/OFF control
Code 0 0 0 0 0 0 1 D C B
D: The display is ON when D='1' and OFF when D='0'.When off due to D = '0'display data
remains in the DDRAM. It can be displayed immediately by setting D = '1'.
C: The cursor is displayed when C = '1' and goes off when C ='0'.Even if the cursor
disappears, the function of I/D, etc does not change during display data write.

The cursor is displayed using 5 dots in the 8th line when the 5 x 7-character font are
selected.
B: The character indicated by the cursor blinks when B = '1'.The blink is displayed by
switching between all black dots and display characters at 409.6 msecs interval when fCP
or fOSC =250 kHz. The cursor and the blink can be set to display simultaneously. (The
blink interval changes according to the reciprocal of fCP or fOSC.409.6 x 250/270 = 379.2
ms when fCP = 270KHZ.)

5) Cursor or display shift
Code 0 0 0 0 0 1 S/C R/L * *
Shifts cursor positions or display to the right or left without writing or reading display data.
This function is used to correct or search for the display. In a 2-line display, the cursor
moves to the 2nd line when it passes the 40th digit of the 1st line. Notice that the 1st and
2nd line will shift at the same time. When the displayed data is shifted repeatedly each line
Moves horizontally. The 2nd line display does not shift into the 1st line position.

Advanced
Systems
74 of 75

6) Function set
Code 0 0 0 0 1 DL N F * *
DL: Sets interface data length, When DL = 1,the data input/output to and from the MPU is
carried out by means of 8 bits DB7-DB0.When DL=0,the data input/output to and from the
MPU is carried out in two steps through the 4 bits DB7-DB4.
N: Sets number of display lines.
The 2-line display mode of the LCD is selected when N=1,while the 1-line
Display mode is selected when N=0.
F: Sets character font
The 5x7 dots character font is selected when F=0,While the 5x10 dots
Character font is selected when F=1 and N=0.

NOTE: This instruction is to be executed at the start of the program

7) Set CGRAM address
Code 0 0 0 1 A5 A4 A3 A2 A1 A0
Sets CGRAM address into the address counter in binary A5 to A0.In the 5x7 font mode the
CGRAM block is defined by A5-A3 while A2-A0 defines the row.

8) Set DDRAM address
Code 0 0 1 B6 B5 B4 B3 B2 B1 B0
Sets the DDRAM address into the address counters in binary B6 to B0. Data then written or
read from the ODM pertains to the DDRAM. However when N=0 (1-line display), B6-B0 is
00-4f(hex). When N=1 (2 line display), B6-B0 is 00-27 (hex) for the first line and 40-67
(hex) for the second line.

9) Read busy flag and address
Code 0 1 BF C6 C5 C4 C3 C2 C1 C0
Reads the busy flag (BF) that indicates the system is now internally executing a previously
received instruction. BF=1 indicates that internal operation is in progress. The next
instruction will not be accepted until BF goes 0.Check the BF status before the next write
operation.

At the same time, the value of the address counter expressed in binary C6 to C0 is read.
The address counter is used by both CG and DDRAM addresses, & its value is determined
by the previous instruction.

10) Write data to CG or DDRAM
Code 1 0 D D D D D D D D
Advanced
Systems
75 of 75
Writes binary 8 data DDDDDDDD to the CG or DDRAM. Whether the CG or DDRAM is to be
written into is determined by the previous specification of CG or DDRAM address setting.
After write, the address is automatically incremented or decremented by 1 according to
entry mode. The entry mode also determines display shift.
11) Read data from CG or DDRAM
Code 1 1 D D D D D D D D
Reads binary 8 bit data DDDDDDDD from the CG or DDRAM. The previous designation
determines whether the CG or DDRAM is to be read. Before entering the read instruction,
you must execute either the CGRAM or DDRAM address set instruction. If you don't, the
first read data would be invalid.
After a read, the entry mode automatically increases or decreases the address by 1.
However display shift is not executed no matter what the entry mode is. The cursor shift
instruction operation is the same as that of the DDRAM addresses set instruction.
NOTE: By making use of above commands the user can output alphabets,
numeric, special characters onto the display.
CGROM: The display has built-in ASCII character codes in CGROM.
CGRAM: The user can generate special character pattern & store it in CGRAM. In other
words, CGRAM is a CHARACTER GENERATOR RAM having a storage function of character
pattern, which enable to change freely by user program
DDRAM: The display data RAM (DDRAM) stores display data represented in 8-bit
(hexadecimal) character codes. Its capacity is 80X8 bits or 80 characters.
Depending on 8-bit character code that is written into the DDRAM, LCD will
Select the character pattern either from CGRAM or from CGROM.
FOR 5X7 Dot matrix:
Character codes from 00h to 07h selects CGRAM blocks 0 to 7.
Character codes from 08h to 0Fh selects CGRAM blocks 0 to 7.
Character codes from 20h to 7Fh select CGROM displayable ASCII character
Character codes from 80h to 9Fh are invalid.
Character codes from A0h to FFh select CGROM kana (Japanese) and Greek
character

Advanced
Systems
76 of 75

APPENDIX D

ALS-USBJTAG-02

ALS-USBJTAG-02 is a downloading tool for Xilinx and Altera. It works on USB
port.

1) For Xilinx initially keep the toggle switch downwards located at the side of
connector.

1. INSTALLATION
1.1
Connect the USB terminal of the tool to your PC USB port, then you will see
Found New hardware wizard window ,in that click NEXT

1.2 Wait till the following wizard completes.

Advanced
Systems
77 of 75
1.3
After completion of wizard that click on FINISH

1.4
Check for detection of programming cable in Computer Device Manager

2. Now user can download the program through IMPACT software.

Advanced
Systems
78 of 75

2) For ALTERA initially keep the toggle switch upwards located at the side of
connector.

1. INSTALLATION
1.1
After connecting the USB terminal of the DSJTAG to the PC USB terminal you
will see the following window.

Click second option (Install from a list or specific location (Advanced)).Then click
NEXT

1.2
Brows for the driver folder which is found in the Altera installed folder.
Advanced
Systems
79 of 75

a. Wait until the search wizard completes, after search complete click
NEXT
Advanced
Systems
80 of 75

1.4
Click FINISH

1.4
Check for detection of programming cable in Computer Device Manager
Advanced
Systems
81 of 75

1.5 Now user can download the software using altera programmer and selecting
proper hardware (USB-Blaster) in hardware setup.

Fpga 04 Lab Manual

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Fpga 04 Lab Manual

Загружено:

Авторское право:

Доступные форматы

Advanced

Electronic USER MANUAL ALS/SDA/FPGA-04/LM REV2.0

Вам также может понравиться