Test Chap 1

VLSI TESTING 2012 Chapter 1-1
VLSI TESTING
1
CHAPTER 1
INTRODUCTION
TO VLSI TESTING
PING-LIANG LAI
VLSI TESTING 2012 Chapter 1-2 PING-LIANG LAI

What is this Chapter About?
Introduce fundamental concepts and various aspects of VLSI
testing
Focus on
Importance of testing in the design and manufacturing processes
Levels of abstraction in VLSI testing
Challenges in test generation and fault modeling
Provide overview of VLSI test technology
Outline
Introduction
Design and Testing
Cost of an Integrated Circuit (IC)
Testing During VLSI Life Cycle
Test Generation, Fault Model, Fault Coverage and Defect Level
Levels of Abstraction
Overview of VLSI Test Technology
Concluding Remarks
LAB1
Introduction
Integrated Circuits (ICs) have grown in size and complexity since the late 1950s
SSI, MSI, LSI, and Very Large Scale Integration (VLSI)
Moores Law: scale of ICs doubles every 18 months
Growing size and complexity poses many and new testing challenges
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1960s 1970s 1980s 1990s 2000s
N
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m
b
e
r

o
f

T
r
a
n
s
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s
t
o
r
s
VLSI
LSI
M
S
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S
S
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Importance of Testing (1/2)
Moores Law results from decreasing feature size (dimensions)
From 10s of m to 10s of nm for transistors and interconnecting wires
Operating frequencies have increased from 100 KHz to several
GHz
Decreasing feature size increases probability of defects during
manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products
Importance of Testing (2/2)
Rule of Ten: cost to detect faulty IC increases by an order of
magnitude as we move from
Device PCB System Field operation
Testing performed at all of these levels
Testing also used during
Manufacturing to improve yield
Failure Mode Analysis (FMA)
Field operation to ensure fault-free system operation
Initiate repairs when faults are detected
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
ASICs Design
Type of Application-Specific Integrated circuits (ASICs)
Full-custom ASICs
Semi-custom ASICs
Cell-based ASICs
Gate Array-based ASICs
Programmable ASICs
Programmable Logic Devices
Field Programmable Gate Array
Building block Interconnection
Full-custom Yes Yes
Semi-custom No Yes
Programmable No No
VLSI TESTING 2012 Chapter 1-9
ASICs Design Flow
Full Custom Design Flow
Composer
SBTSPICE
Virtuoso
Circuit-Level Design
Pre-Layout Circuit-Sim
Physical Layout
Physical Verification
& RC Extraction
Dracula
Post-Layout Sim
SBTSPICE
Tape Out
Spice Model
Spice Model
& RC
BONeS
Matlab
Specification
System-Level
Design & Sim
Verilog-XL Synopsys VCS
Design-Compiler
Ambit
RTL-Level Sim
RTL Synthesis
MathWork RTW
Behavior
Synthesis
Cell Library
Verilog-XL
Synopsys VCS
Cell Library
Model
Gate-Level Sim
Silicon Ensemble Ultra / Dracula
Apollo/Hercules
Physical
Verification
RC Extraction
Dracula Star-RC
Post-Layout Sim
Star-time TimeMill Star-sim
Tape Out
Cell-Based Full-Custom FPGA
ASIC
Advanced VLSI Research Center
Hspice
Hspice
Cell Based Design Flow
SPW
Visual Architect
The VLSI Testing Process
Verification Testing (also called Design Verification)
Verifies correctness of design and test procedure
More common to correct design than test procedure
Functional test, AC and DC parameter test
Manufacturing Testing
Factory testing of all manufactured chips for parametric faults and for random
defects
Reliability Testing
Reliability testing guarantees the reliability of product
Various higher power supply, increasing test time and high temperature
Acceptance Testing (incoming inspection)
Customer performs tests on purchased parts to ensure quality
Verification vs. Testing
Design Verification vs. Manufacturing Test
Design Verification ensure design matches intent
Manufacturing Test ensures parts are manufactured correctly
How is Manufacturing Test performed?
Automatic Test Equipment (ATE) applies input stimulus to the Device Under
Test (DUT) and measure the output response.
If the ATE observes a response different from the expected response, the DUT
fails that test
HW Design Manufacturing
Netlist Silicon Specification
Verification Testing
Testing Principle
Testing Principle: three components, input patterns, DUT, and stored golden
response
When the chip is digital, the stimuli are called test patterns or test vectors.
ATE carries out this process
A powerful computer operating under the control of a test program, a program written
in a high level language
Digital Signal Processor (DSP) used for analog testing
Input patterns
Stored golden response
Output response
PIs or
POs or
Scan in Scan out
ATE for Manufacturing Test
Major ATE Companies: Agilent Technologies, Advantest, Credence
Systems Corporation, HCL Technologies, LTX, National Instruments,
Rohde & Schwarz, SPEA, Teradyne, Verigy..
Flow of Manufacturing Test
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
Silicon Wafer and Dies
Exponential cost decrease technology basically the same
A wafer is tested and chopped into dies that are packaged
Die ()
Wafer ()
AMD K8, source: http://www.amd.com
dies along the edge
Die Chip ()
Packaging process
yield Die wafer per Dies #
wafer of Cost
die of Cost
=
yield test Final
test final and packaging of Cost die testing of Cost die of Cost
IC of Cost
+ +
=
( )
area Die 2
diameter Wafer
area Die
radius Wafer
wafer per Dies #
2
area Die desity Defect

1 yield Wafer yield Die

|
.
|
\
|

+ =
Todays technology: o ~ 4.0, defect density 0.4 ~ 0.8 per cm
2
(A greater portion of the cost that varies between machines)
(sensitive to die size) (# of dies along the edge)
Examples of Cost of an IC
Example 1: Find the number of dies per 30-cm wafer for a die that is 0.7 cm on a side.
The total die area is 0.49 cm
2
. Thus
Example 2: Find the die yield for dies that are 1 cm on a side and 0.7 cm on a side, assuming a defect
density of 0.6 per cm
2
.
The total die areas are 1 cm
2
and 0.49 cm
2
. For the large die the yield is
( )
( )
347 , 1
99 . 0
2 . 94
49 . 0
5 . 706
49 . 0 2
30
49 . 0
2 / 30
area Die 2
diameter Wafer
area Die
radius Wafer
wafer per Dies #
2
2
= =
=
t t
35 . 0
0 . 4
1 6 . 0
1
area Die desity Detect

1 yield Wafer yield Die
4
=
|
.
|
\
|

+ =
|
.
|
\
|

+ =
58 . 0
0 . 4
49 . 0 6 . 0
1 yield Die
4
=
|
.
|
\
|

+ =

For the small die, it is
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
Testing typically consists of (three parts)
Applying set of test stimuli to
Inputs of Circuit Under Test (CUT), and
Analyzing output responses
If incorrect (fail), CUT assumed to be faulty
If correct (pass), CUT assumed to be fault-free
Pass/Fail
Circuit
Under Test
(CUT)
Input
Test
Stimuli
Output
Response
Analysis
Output
1
Output
m
Input
1
Input
n
Testing During VLSI Development
Design Verification targets
design errors
Corrections made prior to
fabrication
Remaining tests target
manufacturing defects
A defect is a flaw or physical
imperfection that can lead to
a fault
Design Verification
Wafer Test
Final Testing
Package Test
Design Specification
Design
Fabrication
Quality Assurance
Packaging
Design Verification
Different levels of abstraction during
design
CAD tools used to synthesize design
from RTL to physical level
Simulation used at various level to
test for
Design errors in behavioral or RTL
Design meeting system timing
requirements
Design Specification
Behavioral (Architecture) Level
Register-Transfer Level
Logical (Gate) Level
Physical (Transistor) Level
Yield and Reject Rate
We expect faulty chips due to manufacturing defects
Called yield
2 types of yield loss
Catastrophic due to random defects
Parametric due to process variations
Undesirable results during testing
Faulty chip appears to be good (passes test)
Called reject rate
Good chip appears to be faulty (fails test)
Due to poorly designed tests or lack of Design for Testability (DFT)
fabricated parts of number total
parts acceptable of number
yield =
test final passing parts of number total
test final passing parts faulty of number
rate reject =
Electronic System Manufacturing
A system consists of PCBs that
consist of
VLSI devices
PCB fabrication similar to VLSI
fabrication
Susceptible to defects
Assembly steps also susceptible
to defects
Testing performed at all stages of
manufacturing
Bare Board Test
Board Test
System Test
Unit Test
PCB Fabrication
PCB Assembly
System Assembly
Unit Assembly
System-Level Operation (1/2)
Faults occur during system operation
Exponential failure law
Interval of normal system operation is random number exponentially
distributed
Reliability
Probability that system will operate normally until time t
Failure rate , is sum of individual component failure rates,
i
t
n
e t T P

= > ) (
=
=
k
i
i
0

t
0
t
1
t
2
t
3
t
4
t
S
1
0
failures
Normal system operation
System-Level Operation (2/2)
Mean Time Between Failures (MTBF)
Repair time (R) also assumed to obey
exponential distribution
is repair rate
Mean Time To Repair (MTTR)
Fraction of time that system is operating
normally called system availability
High reliability systems have system
availabilities greater than 0.9999
Referred to as four 9s
t
e t R P

= > ) (
1
0
= =
}
dt e MTBF
t
1
= MTTR
MTTR MTBF
MTBF
ilability system ava
+
=
System-Level Testing
Testing required to ensure system availability
Types of system-level testing
On-line testing concurrent with system operation
Off-line testing while system (or portion of) is taken out of service
Performed periodically during low-demand periods
Used for diagnosis (identification and location) of faulty replaceable
components to improve repair time
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
Test Generation (1/4)
A test is a sequence of test patterns, called test vectors, applied to
the CUT whose outputs are monitored and analyzed for the correct
response
Exhaustive testing applying all possible test patterns to CUT
Functional testing testing every truth table entry for a combinational logic
CUT
Neither of these are practical for large CUTs
Fault coverage is a quantitative measure of quality of a set of test
vectors
29
Test usually is including (test vector file, instructions of test program)
Test Vector, Test pattern or true table (0, 1, L, H, Z, X)
Test time of each test vector is called test period (test cycle)
Type of Test method
Exhaustive Vector: list all possible input as test vector to reach 100% fault coverage
N-inputs, 2
N
test vectors
14-inputs of 74181ALU, 2
14
=16,384 test vectors
10 MHz and 38-inputs of 16-bit ALU need 7.64 hours. (WOW!!)
Functional Vector
Major using in verification test
71181 ALU only need 448 test vectors
However, few algorithm to verify all function on a chip
Structural Vector
A vector based on a specific fault model, but fault model must extract (is it possible?);
Using EDA tools to automatic generate test vectors
74181ALU only 47 test vectors
Fault coverage for a given set of test vectors
100% fault coverage may be impossible due to undetectable faults
Reject rate = 1 yield
(1 fault coverage)
A PCB with 40 chips, each with 90% fault coverage and 90% yield, has a
reject rate of 34.4%
Or 344,000 defective parts per million (PPM)
faults of number total
faults detected of number
coverage fault =
faults le undetectab of number faults of number total
faults detected of number
efficiency detection fault
=
Goal: find efficient set of test vectors with maximum fault
coverage
Fault simulation used to determine fault coverage
Requires fault models to emulate behavior of defects
A good fault model
Is computationally efficient for simulation
Accurately reflects behavior of defects
No single fault model works for all possible defects
An Example A Test Pattern
A test pattern
A test pattern with don't cares
Test generation: generates a test for a target fault
stuck-at 1
0
0
1
1
1
0/1
0/1
stuck-at 0
1
x
x
x
x
x
1/0
1/0
(Good value and faulty value are
different at a PO)
An Example Fault Modeling
The effects of physical defects
Most commonly used fault model: single stuck-at-fault
Other fault models
Break faults, Bridging faults, Transistor stuck-open faults, Transistor stuck-on
faults, Delay faults
A
B
C
D
E
F
G
A: s-a-1 B: s-a-1 C: s-a-1 D: s-a-1
A: s-a-0 B: s-a-0 C: s-a-0 D: s-a-0
E: s-a-1 F: s-a-1 G: s-a-1
E: s-a-0 F: s-a-0 G: s-a-0
2 7 = 14 faults
An Example Fault Coverage (FC)
Fault Coverage
Example:
list fault in faults #
detected faults #
FC =
a
b
c
6 stuck-at faults
{a/0, a/1, b/0, b/1, c/0, c/1}
Test Faults detected FC
{(0,0)} c/1 16.67%
{(0,1)} a/1, c/1 33.33%
{(1,1)} a/0, b/0, c/0 50.00%
{(0,0), (1,1)} a/0, b/0, c/0, c/1 66.67%
{(1,0), (0,1), (1,1)} All 100.00%
An Example Testing and Quality
Quality of shipped parts is a function of yield Y and the test (fault)
coverage T
Defect level (DL): fraction of shipped parts that are defective
Yield (Y):
Fraction of good
parts
Rejects
Quality:
Defective parts
per million
(DPM)
Shipped Parts
An Example Defect Level, Yield and Fault Coverage
DL: defect level
Y: yield
T: fault coverage
DL = 1- Y
(1-T)
Yield (Y) Fault Coverage (T) DPM(DL)
50% 90% 67,000
75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000
90% 90% 10,000
90% 95% 5,000
90% 99% 1,000
90% 99.9% 100
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
High levels have few implementation details needed for effective
test generation
Fault models based on gate & physical levels
Example: two circuits for same specification
Ckt B test vectors do not detect 4 faults in Ckt A
f(a, b, c)=E
m
(2, 7) + d(6) = abc + abc + Xabc
0 0 0 1 1 1 1 0
0
1
1
X
1
ab
c
0 0 0 1 1 1 1 0
0
1
1
X
1
ab
c
f = abc + abc
f = ab + bc
Test Vectors
{111, 110, 101, 011, 010, 000}
Test Vectors
{111, 101, 010, 000}
f
SA1
b
c
a
SA1
SA1
SA1
a
b
f
c
Circuit A
Circuit B
Circuit A
Circuit B
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
ATE consists of
Computer for central control and flexible test & measurement for different
products
Pin electronics & fixtures to apply test patterns to pins & sample responses
Test program controls timing of test patterns & compares response to
known good responses
Automatic Test Pattern Generation (ATPG)
Algorithms generating sequence of test vectors for a given circuit based on
specific fault models
Fault simulation
Emulates fault models in CUT and applies test vectors to determine fault
coverage
Simulation time (significant due to large number of faults to emulate) can be
reduced by
Parallel, deductive, and concurrent fault simulation
Design for Testability (DFT)
Generally incorporated in design
Goal: improve controllability and/or observability of internal nodes of a chip
or PCB
Three basic approaches
Ad-hoc techniques
Scan design
Boundary Scan
Built-In Self-Test (BIST)
Design of Testability Ad-hoc
Ad-hoc DFT techniques
Add internal test points (usually multiplexers) for
Controllability
Observability
Added on a case-by-case basis
Primarily targets hard to test portions of chip
Internal node
to be
controlled
Normal system data
0
1
controllability test point observability test point
Primary
output
Test mode select
0
1
Test data input
Test mode select
Internal node to be
observed
Normal system data
Design for Testability Scan
Scan design
Transforms flip-flops of chip
into a shift register
Scan mode facilitates
Shifting in test vectors
Shifting out responses
Good CAD tool support
Transforming flip-flops to shift
register
ATPG
44
FFs
Combinational
Logic
Primary
Inputs
Primary
Outputs
FF
D
i
Clk
Q
i
FFs
Combinational
Logic
Primary
Inputs
Primary
Outputs
Scan Data In
Scan
Data
Out
FF
Clk
Q
i
D
i
Q
i-1
Scan
Mode
0
1
1
2
3
Design for Testability Scan
Boundary Scan (BS) scan design applied to I/O buffers of chip
Used for testing interconnect on PCB
Provides access to internal DFT capabilities
IEEE standard 4-wire Test Access Port (TAP)
TAP pin I/O Function
TCK input Test clock
TMS input Test Mode Select
TDI input Test Data In
TDO output Test Data Out
input data
to IC
capture
FF
Capture
update
FF
Update
Input
Scan In
Shift
Scan Out
Output
Input
BS Cell
Control
BS Cell
Pad
tri-state control
from IC
Output BS Cell
0
1
0
1
A Board Containing 4 ICs with BS
Internal
Logic
Internal
Logic
Internal
Logic
Internal
Logic
Boundary-scan cell Boundary-scan chain
System interconnect
Serial
Data in
Serial
Data out
Design for Testability BIST
Built-In Self-Test (BIST): major for at-speed requirement
Incorporates test pattern generator (TPG) and output response analyzer
(ORA) internal to design
Chip can test itself
Can be used at all levels of testing
Device PCB System Field operation
TPG
Circuit
Under
Test
Primary Inputs
Primary Outputs
BIST Mode
ORA
Pass
Fail
0
1
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
Concluding Remarks
Many new testing challenges presented by
Increasing size and complexity of VLSI devices
Decreasing feature size
This chapter presented introduction to VLSI testing
Remaining chapters present more details as well as solutions to
these challenges
Outline
Introduction
Design and Testing
Concluding Remarks
LAB1
LAB1
LAB1 An Verilog Example for Design Verification using
Functional Test
Hardware: Personal-Computer (PC) only
Software tools: ModelSim Simulator (Mentor), Xilinx ISE Synthesizer
Language: Verilog HDL
LAB1 download: http://soc.cs.nchu.edu.tw/pllai
LAB goals:
Verilog
Testbench

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area Die desity Defect

area Die desity Detect

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