Faster and More Efficient Computers Based On Carbon Nanotube Field Effect Transistors

Khalid Anwar 260367591

December 10, 2012

McGill University








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Abstract
The limits of silicon based transistors are being reached as memory and processor speeds reach
their theoretical maximum. This paper supports the argument for replacing the current silicon
field effect transistors, found in todays computers, by Carbon Nanotube Field Effect Transistors
(CNTFETs) in the near future, with the expectation of faster and more efficient computer
systems. The size of a carbon nanotube field effect transistor is expected to be in the single digit
nanometer domain, which implies that a single wafer of computer chip would accommodate
many times more transistors than a wafer containing Silicon (Si) based field effect transistors.
This will increase the efficiency of computers as well as their speed in performing logical
operations. However, the main problems so far have been the synthetic growth mechanisms for
Carbon Nanotubes (CNTs) that have hindered progress in the application of these CNTs in
integrated circuits. However, researchers have recently developed alternative growth
mechanisms that resolve the issues arising in the previous mechanisms. Experiments conducted
to compare the progress between CNTFETs produced via alternative growth mechanisms, and
current state-of-the art Silicon Metal Oxide Semiconductor Field Effect Transistors (Si
MOSFETs) show that these CNTFETs have great potential, and with some minor modifications
would be excellent replacements for Si MOSFETs in the near future.








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1 Introduction
Until now, the performance of computers has been pushed up by lowering the size of
chips while incrementing the number of transistors they contain. In accordance with Moores
law, which states, the number of transistors on integrated circuits doubles every two years,
chip speeds have risen and prices have dropped (Geer, 2005). However, silicon based transistors
cannot shrink indefinitely. The minimum size that these Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs) can be made to reach is 65 nanometers, beyond which they cannot
function properly. The time required for a computer to execute an instruction is proportional to
the number of transistors on an integrated chip in the computer. The limits of MOSFETs are
being reached, as memory and processor speeds hit their present theoretical maximum.
Computer based industries are set to take a giant step beyond MOSFETs with the
application of nanotechnology, which provides new ideas and methods of running faster
processors (Joerg Appenzeller, 2003). It has been proposed that the integrated circuits on these
processors should be made from Carbon Nano Tube Field Effect Transistors (CNTFETs). This
paper explores the option of replacing Silicon MOSFETs found in todays computers with
CNTFETs in the near future, which would bring the expectation of faster and more efficient
computer systems. This is done by first discussing the different types of carbon nanotubes
available, their advantages and limitations, and their traditional production methods using
solution based techniques. The shortcomings in these methods are explained, which have
prevented the implementation of CNTFETs thus far, before moving on to an analysis of recent
experiments improving on these shortcomings using inert gas based techniques. In light of these
promising approaches to CNT production, the many advantages of transistors based on CNT
technologies as opposed to Si based technologies are enumerated.



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2 Background

In a computer chip, transistors are not considered as a separate entity by itself, but parts
of what is known as an integrated circuit (also known as a microchip). Many transistors work in
concert to help the computer execute instructions or to perform calculations. An integrated
circuit is one piece of semiconductor material, most commonly silicon, loaded with transistors
and other electronic components (Chandler, 2001).
The switch operation of a transistor, where it switches between two binary states 0 or 1, is
what enables computers to perform very complex tasks. The time required for a computer to
perform tasks is proportional to the number of transistors it has (Chandler, 2001). In other words,
the greater the number of transistors there are, the quicker a computer can execute instructions.
As such, the need to decrease the size of transistors has risen, to allow more transistors to be
packed onto a single wafer.
Current transistor technology, however, restricts the ability to make a single processor
core more powerful; the minimum length a silicon based transistor can be reduced to is
constrained by the size of the transistors gate which switches between the on (1) and off (0)
state. For smaller and smaller transistors, the gate becomes narrower and the ability to block the
flow of electrons become less, which results in continuous consumption and hence wastage of
electrical energy. Also, increasing the frequency causes transistors to switch more frequently
and, as such, generate more heat and consume more power (Geer, 2005). The minimum length
for a Si MOSFET is currently 65 nanometers, beyond which the transistor will not function
properly.



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In response to these limitations, manufacturers are making chips with multiple processing
cores instead of just a super powerful one. The speed of multiple core chips are not necessarily as
fast as the highest performing single-core models, but they improve overall performance by
handling more work in parallel (Geer, 2005). However, there are two critical problems with
multiple core processors: power consumption and heat generation. Although thermal designs
advances have mitigated some problems, they are not sufficient to compensate for increasing
power and heat buildup (Geer, 2006).
CNTFETs can help solve the issue related to the size reduction of silicon based
transistors beyond 65 nanometer (nm). According to a computer news report, Intel Inc. plans to
produce chips in the single digit nanometer domain within the next decade, based on CNTFETs
(Anonymous, 2012). This will not only allow packing more transistors onto a single wafer, but it
will also solve the problems related to heat generation and power consumption. The approximate
6.5 times reduction in size relates to greater efficiency and faster clock power. This improvement
in performance will be much greater than the elevated performance of multiple processor cores
working in parallel (Merkle, 2001).
3 Discussion
Carbon nanotube field effect transistors are made from carbon nanotubes, which can be
thought of as a stripe cut from a single graphite plane (so-called graphene) and rolled up to a
hollow seamless cylinder (Joerg Appenzeller, 2003). There are two types of carbon nanotubes:
Single-Wall Nano Tubes (SWNTs) and Multiple-Wall Nano Tubes (MWNTs). The paper by R.
Seidel et al. (2004) shows that SWNTs are best suited for CNTFETs due to their excellent
electrical and mechanical properties.



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3.1 Limitations of SWNTs
Several synthetic growth mechanisms of SWNTs have been proposed, although none of
them has yet received definitive experimental or theoretical support (Joerg Appenzeller, 2003),
as they lack sufficient control over SWNT structure, leading to inhomogeneity in the resulting
properties. Moreover, synthetic methods yield carbon nanotubes that are a mixture of metallic
and semiconducting SWNTs and are decorated with impurities such as MWNTs, other forms of
graphitic carbon and metallic catalyst particles (Liu & Hersam, 2010). These poly-dispersity
issues have hindered efforts to use SWNTs in the application of integrated electronic circuits
where reliable and reproducible performance is a requirement.
In the past decade, significant progress has been made in the post synthesis sorting of
SWNTs. Many post synthetic separation methods have been developed such as electrophoresis,
physicochemical modification, electrical breakdown, ultracentrifugation and chromatography to
separate the impurities and most importantly the mixture of metallic and semiconducting SWNTs
(Li & Zhang, 2011). All these approaches are able to effectively separate the impurities and also
separate the semiconducting SWNTs with a very high percentage. However, these methods are
tedious and costly (He et al., 2012). Also, these methods are all solution based and as such start
with chemical reactions leaving the SWNTs chemically decorated. This alters the electronic
structures and properties of the tubes (Liu & Hersam, 2010). Consequently, device performances
are altered and hence these methods are not practical.

3.2 Proposed Solution



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Recently, selective growth post synthetic methods are being implemented for sorting the mixture
of semiconducting and metallic SWNTs without chemical decoration (Li & Zhang, 2011). These
methods are inert gas based as opposed to the solution based which enables the sorting to be
chemical free (Joerg Appenzeller, 2003). Experiments conducted by Liu et al (2007) provide
evidence where chemical vapor deposition (CVD) methods have been used for preferential
production of SWNTs with a high percentage of semiconducting nanotubes. Also, according to
Maoshuai et al. (2007), the chemical vapor deposition method is considered to be the most
economic process to obtain SWNTs with a selected metallic and semiconductor composition.
The selective growth sorting method can maintain the perfect alignment of carbon
nanotubes with good control of the electronic type uniformity; thus it can be considered to
contribute a reliable solution to the major issue existing in the application and integration of
carbon nanotubes in integrated circuits. Further research is under way for the practical
implementation of this method (Qian, Huang, Gao, Wang, & Ren, 2010).

3.3 CNTFETs versus Si MOSFETs
To gauge the progress of prototype CNTFETs made from high percentile semiconducting
SWNTs, it is crucial that they are compared against the best silicon MOSFETs in existence. The
four key device metrics used to compare these two technologies are: intrinsic speed (CV/I)
versus physical gate length (L
g
), energy delay product versus L
g
, transistor sub threshold slope
versus L
g
, and CV/I versus I
ON
/I
OFF
ratio (on-to-off current) (Chau et al., 2005). These metrics
help us understand the gain or loss in the prototype transistors in terms of speed, switching
energy, scalability and off-state leakage.



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The data based on the experiment by Chau et al. (2005) can be found in Appendix A. The
results of the experiment are as follows:
The intrinsic device speed of the very best CNTFET, reported to date, exhibits significant
improvement over the current state-of-the art Si MOSFETs owing primarily to the superior
device mobility of CNTs which is at least 20 times higher than that of Si. The CNTFETs also
improved significantly compared to the Si MOSFETs with respect to the energy-delay product.
This is also due to the higher effective mobility of CNTs. However, the sub threshold slopes of
the CNT devices are degraded when compared to the silicon devices. The reasons for the
degraded sub threshold slope are the use of relatively thick gate-oxide and metal source-drain
contacts.
According to the data (see Appendix A), the intrinsic speed improves with decreasing
I
ON
/I
OFF
ratio due to the increase in the on-state current from high overdrive, but at the expense of
considerable increase in the off-state current. This is valid for both CNTFETs and MOSFETs.
However, the result shows that the increase in CNTFETs intrinsic speed is more than that of
MOSFETs provided that the I
ON
/I
OFF
ratio is the same.
It can be seen that the CNTFETs are superior to the MOSFETs in three of the four
metrics used to gauge progress. One area where it is not superior to the MOSFETs indicates the
need for a P-N junction technology so that the metal source-drain contacts can be replaced with
doped semiconducting contacts. It is expected that the sub threshold slope and hence the
scalability of CNTs, will greatly improve once the P-N junction technology is introduced (Chau
et al., 2005).



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The issue of power consumption with the Si MOSFETs can be deduced to be resolved by
the CNTFETs based on the energy-delay product metric in the above experiment. Also, the
intrinsic device speed of CNTFETs are much greater than that of MOSFETs which implies that
if the size of a CNTFET and a MOSFET is the same, then the chip comprising of CNTFETs will
be faster, and hence the computer will be more efficient. Moreover, the successful introduction
of P-N junction technology will help resolve the issue with scalability and thus the production of
CNTFETs in the one-digit nanometer domain will be possible. This means more chips can be
packed onto a single wafer, allowing for much faster computer systems.

4 Conclusion
Prospective computers should be based on carbon nanotube technology as opposed to
silicon based ones as transistors based on this technology would make computer systems faster
and more efficient. This paper has investigated the option of replacing MOSFETs with
CNTFETs in future computers by exploring the most viable solution available to date, both
economically and logically, to resolve the issues associated with the current CNT technology.
The discussed chemical vapor decomposition methods resolve many of these issues, and are the
most economic methods available. However, it is still not clear whether it will meet one aspect of
Moores law, which is the cost of computers going down every two years. More research is being
conducted to find alternatives to CVD methods to produce pristine semiconducting SWNTs.
Finally, the paper has provided strong evidence based on experiments that transistors based on
CNT technology are superior to that of Si based technology.




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Appendix A
Data from the experiments carried out by Robert Chau, Suman Datta, Mark Doczy, Brian
Doyle, Ben Jin, Jack Kavalieros, Amlan Majumdar, Matthew Metz and Marko Radosavljevic in
Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor
Applications:

Figure : Gate delay (intrinsic device speed CV=I) versus transistor physical gate length








Figure 1Figure 2: Energy-delay product per device width versus transistor physical gate



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Figure 3: Subthreshold slope versus transistor physical gate
length. The planarand nonplanar Si FETs as well as the IIIV
planar devices are n-channeltransistors, while the CNT FETs are
p-channel transistors.
Figure 4: I V characteristics of a CNT PMOS transistor with Pd
metal sourcedrain at different drain biases V , illustrating am
bipolar conduction. Pd has a p-type work function with respect to
nanotubes. The energy band diagrams exhibit: (A) dominant hole
injection in the on state, (B) equal hole and electron injection at
the minimum current point, and (C) dominant electron injection
in the am bipolar branch