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1C 1LO
+
1_
Fig. 1 Zeta Converter Topology.
A. Stages o{Operation and Waveforms
In DCM this converter presents three stages of operation,
represented schematically in Fig. 2. The main ZETA
converter waveforms within a high fequency period are
shown in Fig. 3.
1O
T
T
(e)
Fig. 2 Stages of operation of the ZETA converter working in DCM.
(a) First, (b) Second and (c) Third stages of operation.
-i(t)
"'iD(t)
vr(t)
vLit)
Il
~
e m
~
"
Vg
tc
-
l t
-VO
' t '
L
t
t
vs(t)
.. . ...
t
t
vD(t) Vg+V
t
tc tD
t
T
Fig. 3 ZETA converter waveforms within a high frequency period.
The stages of operation of the steady state ZETA
converter will be analyzed fom the assumption that all
semiconductors are ideal. In the frst stage (0 ` t ` te), the
voltage 1_ is applied to inductors Lm and Lo and the inductors
are charged. In the second stage (te ` t ` te + td) the switch S
is turned off and the diode enters into conduction. Lm
transfers the energy stored in the previous step for the
coupling capacitor C, in a similar way Lo enables the
connection to the load, acting as a current source. This stage
is characterized by the decreasing of the current into the
diode (which is the smn of the currents hm and ir(J fom its
maximum value until zero. At this moment, the third stage (te
+ td ` t ` 7 starts. At this stage the switch S as well as the
diode remains tured off. The coupling capacitor current ic is
constant and equal to the output inductor curent iLa, which
has the opposite direction of the magnetizing inductor current
i
m, causing the voltage at the inductors to be equal zero.
B. Static Transfer Characteristic
The conduction time of the diode (tn) is constant when
there is no variation of the load R in DCM [5, 6]. So, the
instantaneous static gain g(t) of the ZETA converter in DCM
can be expressed by (1). This characteristic implies in a
1`... .-1.+.....1 *. 1.-+..-..1. + ... ... +... +
300
(1)
where
D-
1
(2)
d(t is the instantaneous duty cycle of the converter, f is
the switching fequency and R is the load resistance.
It is possible to conclude that the control-to-output
relationship of the converter is also linear, in the steady-state
analysis.
III. DYNAMIC COMPUTER SIMULATION MODEL
The dynamic model [7] is based on the techniques
described in [8]. Without more details, Fig. 4 presents the
model.
B
VD
UVd1
Fig. 4 Dynamic computational model used. This is a control-to
output AC model that contains the dynamic behavior of the ZETA
converter in DCM.
The gains and matrices of the model can now be
presented.
A = Al fo + A2 ( 1 -fo )
B B1 fo + B2 (1 -fo )
C
=
C1 fo + C 2 ( 1 -fo )
X
=
-A
-
1
B
U
U
=
V
g
(3)
X is the steady-state solution of the converter. The indexed
matrices are obtained bv analvzim the circuit of Fi. 2 in the
rLm 0
L
m
0 rLo +
rc
A =
L
o
1
1
0
C
0
1
C
o
rm
+
rc
0
L
m
0 ro
A =
L
a
2
1
.
0
C
0
C
o
1
L
m
0
0
B= B =
L
o
2
0
0 0
0
o
0
L
o
L
o
0 0
0
RC
a
0
L
m
0
L
o
0 0
0
RC
o
c c []
'
1 2
0
1
(4)
The resistances rrm and rro are the equivalent series
resistances (ESR) of the inductors, while rc is the ESR of the
coupling capacitor C.
The conversion ratio (fo) for the ZETA converter is
shown in (5).
D
(5)
where D is the duty cycle at the chosen quiescent operation
point.
The gains kc and k
s
are given by
k
2DJ
c (D+DJ)
2
k
1
s
V
D3
J
D(D+DJ)
2
L D
2
(
J
(D+DJ)
2
CD3 J
D(D+DJ)
2
D
2
J
(D+DJ)
2
(6)
1
(7)
301
IV. CONTROL OPTIMIZATION
Equipped with a dynamic simulation model, it is possible
to use sofware such as MATLAB
TM
as an aid in the control
design for this converter. The use of the model associated
with the MATLAB
TM
, allows adjustment of the PID
controller in a quick and simple way. This section presents
the optimization of a PID controller using the model
provided in Fig. 5.
K1
Signal ConsI|ainI
KJ
ZL1A
L.1/20 1D
K
Scope
Fig. 5 Simulink
optimization model.
The gains K I and K2 in Fig. 5 represent the voltage
divider at the output of the ZETA converter, which is
necessary to adjust the signal level to the limits of operation
of the control circuit. The gain K3 symbolize the effect of the
pulse width modulator (PWM) used in the converter.
The block Signal Constraint of the design optimization
library is responsible for carying out the optimization of the
PID parameters. In this block, restrictions are imposed on the
output signal of the system, as shown in Fig. 6. One can
select any system variable, specif its limits, and through an
algorithm, the program search for a set of variables values
that allow a response within the constraints imposed on the
output signal. In this case, the chosen parameters to be
optimized are the proportional, integral and derivative gains.
Kp, Ki and Kd respectively.
Importantly, any controller can be optimized through this
technique, not only PID controllers. A lead-lag compensator,
e.g., can be optimized with almost equal ease.
Table I show the restrictions imposed on the output signal
of the system.
Fig. 6 Signal Constraint block. The waveforms in the fgure are the
steps to optimize the system response. When the wave lies between
TABLE I
Desired Response
Parameter Value
Step Value 100
Step Time Os
Rise Time O.4ms
Settling Time O.Sms
% Overshoot 10%
% Rise 90%
% Settling 1%
% Undershoot 2%
V. RESULTS
The results of the optimization of the controller will now
be presented. MA TLAB
simulations were performed with
the component values shown in Table II.
TABLE II
Component Values
Component Defnition Valne
R Load Resistance 125n
/m
ESR of Magnetizing
on
Inductance
rLo ESR of Output Inductace on
rc
ESR of Coupling
0.14n
Capacitance
LI Magnetizing Inductance S5JlH
L" Output Inductance 22mH
C Coupling Capacitace 6S0nF
Co Output Capacitance S20nF
Vs
Input Voltage 34V
f
Switching Frequency 20kHz
D
Quiescent operation point
0.5
duty cycle
Me
Optimization Kp limits 0< Kp < 1
1 Optimization Ki limits O<Ki <0
1 Optimization Kd limits -1 < Kd < 1
The optimization process resulted in the parameters for
the PID controller shown in Table III.
Parameter
TABLE III
Optimized Parameters
Value
0.4905
3.9193.10
1
4.1351.10-
5
To validate the model and also the parameters of the PID
controller, a circuit was built in PSIM
sofware. The circuit
is presented in Fig. 7.
Fig. 8 presents the closed-loop step response of the
system, obtained using the designed PID controller. The
results were obtained using PSIM
and MA TLAB
sofware.
The comparison between the step response of the system
with the controller and the step response of the open-loop
system (with an equivalent DC gain) is presented in Fig. 9.
To verif the controller performance under another
reference signs, a square wave was used as reference. The
system response is displayed on Fig. 10.
302
Ld1 ..K
1. .1111d
Fig. 7 PSIM
simulation circuit.
!zd
!dd
dd
od
4d
zd
Fig. 8 Step response of the closed-loop system with PID controller.
Vrej 5u(t).
!2O
!OO
GO
cO
4O
2O
Fig. 9 Step response of the open-loop and closed-loop systems.
Vrf 5u(t), d(t) 0.49.
Fig. 10 Square Wave (200Hz) response of the PSIM
circuit.
A prototype was designed and tested. A picture of the
prototype is shown in Fig. I I. The converter open-loop step
response for a duty cycle d(t) 0.5 are presented in Fig. 12.
==
~
Fig. 1 1. The Zeta Prototype.
Fig. 12 Prototype step response for d(t)=O.S.
VI. CONCLUSIONS
This paper has presented a new computational model of
303
of the feedback control of the ZETA converter was
presented. Despite of the slight differences between the
obtained response of the system simulated in MA TLAB
and in PSIM