Crosstalk Scenario in Multiline

VLSI Interconnects
Divya Mishra1, Shailendra Mishra2, Praggya Agnihotry3 and B.K. Kaushik4
1
Vidya Engineering College/Applied Science Dept., Meerut, India
Email:mdivya03@rediffmail.com
2
Meerut Institute of Engineering and Technology/Electronics & Communication Dept., Meerut, India
3
Subharti Institute of Engineering and Technology/ Electronics & Communication Dept., Meerut, India
4
G.B.Pant Engineering College/ Department of Electronics & Communication Engineering, Pauri-Garhwal-246001
Uttarakhand India
Email :{ mishra22feb@rediffmail.com, praggyagnihotry@gmail.com, brajesh_k_k@yahoo.com}
Abstract- Within the confines of the topic we aim to interconnects amongst which few are mentioned
acquaint the need, present trend and viability of which help us to encounter the same with their
the research. This paper describes various solution.
strategies followed by researchers to predict the
crosstalk effect, magnitude and extent of
II. MODELS AND THEORIES FORMULATED
amendments required to minimize the same with
respect to multilne VLSI Interconnects.
Ashok Vittal et al.[3] found that application of GaAs
on silicon (Si) substrate is a promising option for its
Index Terms- Interconnects, Multi line
potential application in new hybrid technologies
interconnects, Single line interconnects, VLSI,
specifically with respect to multiline
Crosstalk, RLC interconnect, Simulation,
interconnects.GaAs-on-Si provides immense potential
multilayer interconnects
for high-speed and optoelectronic capability of GaAs
circuits with low material cost and superior
I. INTRODUCTION mechanical properties of the Si substrate. These
devices also enable better heat sinking as the thermal
The present scenario of modern high speed, high
conductivity of Si is three times more than that of
density CMOS VLSI circuits aim at decreasing
GaAs. The technology is expanding rapidly from
feature size along with increasing chip dimensions.
research to device and circuit development as it is
These results in increased complexity and the problem
highly suitable for multiline circuit modeling.
cannot be ignored as we aim at faster, dynamic and
The VLSI chips needs millions of closely spaced
minimal circuits which consume least of power
interconnection lines to integrate the components on a
without compromising on their functionality. Kevin T.
chip. Hence, it becomes necessary to use multilayer
Tang et al. [1] found that the continuous decrement in
interconnections in two or more levels to achieve
the feature size has brought to the arrival of certain
higher packing densities, shorter transit delays, and
problems like signal integrity, delay, crosstalk, rise
smaller chips. When a number of conductor are
time at a much significant level in comparison with
compared on the basis of resistivity and silicon
the past.
compatibility it is found that aluminum(Al) with
Single Line Model includes lumped elements resistivity 2.65µΩ.cm thermal expansion coefficient
representing series resistance, "effective" inductance, 25.0×10-6 °C-1 and melting point 660°C is preferred for
total capacitance for one line, impedance and metal interconnections. This still possesses some
propagation delay for the transmission line equivalent. limits as reduction of device dimensions leads to
The model is suitable for simulating reflections, time increment in current density, resulting in decreased
delays and skew, attenuation and signal transmission reliability due to electro migration and hillock
quality. On the other hand, Multi Line Model has formation causing electrical shorts between successive
several lines for connections forming a detailed model levels. Besides Al other viable options are Tungsten,
that can be used for simulating crosstalk and ground Al/Cu Al/Ti/Cu, Al/Ta/Al, Al/Ni, Al/Cr, Al/Mg and
bounce. [2] Al/Ti/Si, Al–Cu–Ti, Al–Cu–Ti, Al–Cu–Co, and Al–
Co. [3]
In recent years, based on the gravity of the issue a
The concept of multiline is an option available which
number of material selection strategies, modeling and
greatly solves the interconnect problem arising due to
simulation techniques have been proposed to reduce
unprecedented high density of interconnections
the problem of crosstalk in multiline VLSI
operating at extremely high speeds and carrying high
current densities. It aims at using the concept of
parallel processing by providing two or more paths
between the driving gate and the loading gate. These
paths piled vertically are isolated from one another by
insulating layers between any two consecutive paths
thereby taking the same area on the chip as a single-
path interconnects. Based on the number of paths, an
array of such multipath interconnects could carry
much higher currents on the chip. Furthermore, this
interconnect structure could be built by an extension
of the available microelectronics fabrication
techniques. [3]
Brajesh Kumar Kaushik et al. [4] obtained valuable
conclusions on the estimation of crosstalk effect with
an equivalent linear resistor used to model the
nonlinear CMOS transistors. It is widely known that
transistor in a CMOS gate operates partially in the
linear region and partially in the saturation region
during switching. It is only in the linear region that a
transistor can be accurately approximated by a
resistor, whereas in the saturation region, the
transistor is more accurately modeled as a current
source with a parallel high resistance. They obtained
analytical expressions for the output waveform on
victim line while using CMOS driver model instead of
linear resistance. They concluded that the models
proposed are useful for accurate noise estimation in
the presence of inductive effects and would be
extremely effective in guiding noise-aware physical-
design optimizations both in case of multiline and
single line interconnects.
VLSI Interconnect modeling was previously realized
using a single lumped capacitance. However the
continuous scaling, multiline arrangements led to the
decreasing wire cross-sectional area and increment in
the wire length. This made the resistance more
significant and led to the development of RC delay
model, first as a lumped RC circuit and then as a
distributed RC model to improve accuracy. In due
course, with faster on-chip rise time, higher clock
frequencies and use of Cu wire as interconnect
necessitated the use of RLC models as a distributed
network quoted by Narain D. Arora et al. [5]
Another scientific approach has been proposed by
Thomas W.Chen et al. [6] who analyzed the coupling
between interconnects by use of model fitted
equations to determine a delay change curve for
coupled interconnect. A specific flowchart approach is
followed where first coupled interconnects are
simulated by setting all aggressors to steady state
value and causing a transition on the victim line to
generate a simulated victim delay waveform. The
parameters are then estimated for the without noise
signal by measuring the simulated victim delay
waveforms generated previously to determine the
delay and rise time. However, during this all
aggressors except one are positioned in steady state.
Once the process is followed for all the aggressors
independently a quadratic dcc function is developed to
generate a waveform at the output of the victim line
by superposition. On the basis of results found, the
mean and standard deviation of victim delay through
coupled interconnect is estimated which results from
switching transients on multiple aggressor lines.
Qi-jun Zhang et al. [7] realized a unique approach to
address the Multiline VLSI Interconnect scenario. He
modeled a four-bit bus structure in which the
excitation signals propagate through the bus lines to
various circuit blocks where all 13 four conductor
transmission lines have the same cross-sectional
geometry with excitation of 5-V pulses, 1-ns rise/fall
time and 5-ns duration A frequency-domain approach
based on the group delay and transfer functions was
used to optimize this circuit. The group delay after
optimization was lower and flatter, the peaks of cross-
talk voltages were reduced and the reflection in the
output response was significantly smaller than that
before optimization along with significant
improvement in rise/fall time of signal.
Junmou Zhang et al. [8] proposed placing of shield
around a victim line to minimize delay uncertainty
and improvise signal integrity which is of high value
in multiline circuits where interconnect abnormalities
alter the curtail signal values .He proposed an analytic
model of the peak noise for shielded interconnects
based on a pseudo-2π RC model in order to model
interconnect. The research concluded that greater is
the number of connections tying the shield line to the
power/ground grid, smaller is the coupling noise on
the victim signal. An analytic model of the peak noise
for coupled interconnects with a shield between the
lines is proposed in this paper which predicts the peak
noise model with an average error of 4.4% as
compared to SPICE.
Jan M. Rabaey [9] found that one of the basic
approaches to avoid crosstalk in multiline circuits is to
prewire the minimum-width wires on a minimum
pitch distance. Wires on adjacent layers are routed
orthogonally and signals on the same layer are
separated by VDD or GND shields. The above
mentioned approach minimizes the cross talk and
delay variation is reduced to maximally 2%. However,
this comes at a cost in area, and a 5% capacitance
which results in the increment in performance and
power.

Kevin T. Tang et al. [10] obtained the results for
interconnect between CMOS driver and receiver
modeled as lossy transmission line. Lap lace
transformation equations were used to solve time
domain differential equations characterizing the
structure. For different load and waveform conditions,
expressions for the peak coupling noise voltage
between two interconnect lines in CMOS VLSI
circuits were presented. It concluded that, in case of
high speed CMOS VLSI circuits the driver’s
impedance should be comparable to the line
impedance for reducing the propagation delay of the
CMOS driver stage, minimize the reflection at the
driver’s end and decrease the relaxation time of the
coupling noise voltage on the quite line.
Yu Cao et al. [11] devised a new approach to handle
the inductance effect on multiple signal lines.
Primarily, the worst case switching pattern was first
identified over which a numerical approach was used
to model the effective loop inductance for multiple
lines. On the basis of look-up table for effective loop
inductance, an equivalent single line model was
generated to decouple a specific signal line from the
others present in multiline circuits to perform static
timing analysis. They developed an efficient way to
handle delay and noise estimation for multiple on-chip
global wires. They concluded that effective loop
inductance; instead of partial inductance aims to
directly determine the electrical characteristics of the
coupling interconnect and greatly reduce the number
elements for further modeling and estimation. In case
of multiple lines, effective inductance is smaller than
inductance, and primarily affected by the mutual
inductance, which depends on the number of coupling
lines and their coupling length. Compared to the use
of full RLC net list for multiple lines, the approach
greatly improves the computation efficiency and
maintains accuracy for timing and signal integrity
analysis.
Emer Tuncer et al. [12] realized a process for
reducing crosstalk noise in VLSI circuits and
proposed an algorithm for the same which is equally
valid for multiline circuits. In this process they
proposed to primarily identify the victim net in the
integrated circuit and calculate the change in ground
capacitance for the victim net to identify the noise
amplitude less than equal to maximum allowed noise
level. The process then selects from a library one cell
or a grouping of cells having an input capacitance for
the victim net nearest to the change in ground
capacitance. In the next step selected cell or cell group
is coupled to the victim net which results in change in
ground capacitance .This results in noise of amplitude
less than or equal to an allowable maximum noise
height already predicted. Hence it helps to estimate
the level of distortion due to coupling effect in
multiline VLSI Interconnects.
It is found by A.Deutsch et al. [13]hat as the devices
are scaled, voltage swings reduce along with
reduction of noise amplitude. But rise times are
shorter and so are cycle times hence faster devices
generate more noise. This noise is caused by
simultaneous switching devices, crosstalk, and
common mode effects etc. Total noise of the circuit
has direct impact on the wiring density, chip size,
clock frequency and system cost. It is proposed that
RLC circuit is better for crosstalk prediction than RC
circuit.
J.A. Kong et al. [14] emphasized on the basic fact that
in high-speed digital circuits, high frequency
phenomena affects the characteristics of the
interconnections. Physical irregularities or non
uniformities in the connections may cause severe
reflections and they can no longer be considered as
conducting wires, but behave as transmission lines
and/or waveguides Hence, a detailed analysis of
electromagnetic coupling between two adjacent vias
in a multilayered integrated circuit was done by means
of equivalent magnetic frill array models incorporated
with the even and odd-mode approach. The coupling
responses in the frequency domain and crosstalk
waveforms in the time domain for some multilayered
via structures were calculated. Based on these
formulas a 4-layer experimental model was
constructed and measurements were taken for the
transmission, reflection, and coupling responses. The
measurements show good agreement with the
calculated results over a frequency range of up to 18
GHz. A new method is devised which is flexible
enough handling a variety of non uniform multiline
structures, as in most cases it is possible to
approximately deal with a non uniform multiline as
small segments of uniform multiline connected in
cascade, and the total wave transmission matrix will
be the multiplication of all the sub matrices
representing each small uniform segment.
H. Ymeri et al. [15] proposed a new analytical model
based on the induced current density distribution
inside silicon substrate to calculate the frequency-
dependent distributed inductance and the associated
distributed series resistance of silicon semi conducting
VLSI interconnects. It is found that the silicon semi
conducting substrate skin effect must be considered
for the accurate prediction of the high-frequency
characteristics of VLSI interconnects. In order to
obtain the results they used Helmholtz equation for
the magnetic vector potential inside the silicon
 substrate and the Lap lace equation outside silicon
while the expressions for the magnetic potentials and
the electric field in the structure were obtained in
integral form. The results so obtained are valid for the
self- and mutual inductance and resistance per unit
length of silicon semi conducting VLSI interconnects
of multiline level usage, provided that no important
skin effect occurs in the strip conductors with finite
thickness.
III. CONCLUSION
On basis of various models predicted, simulated and
verified by various scientists it can be concluded that
Multiline VLSI Interconnects is one of the great
possibilities to meet the ever demanding challenges of
modern high speed, high density CMOS VLSI circuits
which aim at decreasing feature size along with
increasing chip dimensions. However the limitations
of crosstalk, glitches, signal integrity , spikes, logic
levels, rise-time etc which become more significant in
multiline VLSI circuits with ever reducing feature size
can be brought to limitations if the above mentioned
models are properly analyzed and strategies followed.
[11]. Yu Cao, Xuejue Huang, Norman Chang', Shen Lin',
0.Sam Nakagawa', Weize Xie',and Chenming Hu, “Effective
On-chip Inductance Modeling for Multiple Signal Lines
andApplication on Repeater Insertion”, EECS Department,
University of California, at Berkeley
[12]. Emre Tuncer,Hamid Savoj and Premal Buch,
“Reduction of Crosstalk Noise in VLSI Circuits”
[13]. Deutsch, H.H. Smith,G.V. Kopcsay, B.L.
Krauter,C.W.Surovie and P.W. Coteus, “ Multiline Crosstalk
and Common Mode Analysis” IBM Research Division,NY
[14]. J.A. Kong, “Three Dimensional Transient Analysis
of Microstrip Circuits in Multilayered Anisotropic Media”
Research Laboratory of Electronics Massachusetts Institute of
Technology
[15]. H. Ymeri,1 B. Nauwelaers and Karen Maex1,
“Distributed Inductance and Resistance Per Unit Length
Formulas for VLSI Interconnections on Silicon
Substrate” Department of Electrical Engineering (ESAT)

IV. REFERENCES

[1]. Kevin T. Tang and Eby G. Friedman “Peak Crosstalk

Noise Estimation in CMOS VLSI Circuits” University of
Rochester.
[2]. SPICE / Electrical Models Tyco Electronics
[3]. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-
Sadowska,Kai-Ping Wang, and Sherry Yang, “Crosstalk
inVLSI Interconnections” IEEE Transaction CAD of IC and
Systems ,VOL.18,NO 12 DEC 1999
[4]. Brajesh Kumar Kaushik and Sankar Sarkar
“Crosstalk Analysis for a CMOS-Gate-Driven Coupled
Interconnects” IEEE Transactions On Computer-Aided Design
Of Integrated Circuits And Systems, Vol. 27, No. 6, June 2008
[5]. Narain D. Arora, “Challenges of Modeling VLSI
Interconnects in the DSM Era” Simplex Solutions, Inc.,
Sunnyvale, CA, USA.
[6]. Thomas W. Chen, Ft. Collins “Method for Analysis
of Interconnect Coupling in VLSI Circuits” CO(US)
[7]. Qi-jun Zhang, Fang Wang, Michel Nakhla,
“Optimization of High-Speed VLSI Interconnects:A
Review(Invited Article)” Department of Electronics, Carleton
University,Ottawa
[8]. Junmou Zhang and Eby G. Friedman, “Crosstalk
Noise Model for Shielded Interconnects in VLSI-based
Circuits” Department of Electrical and Computer Engineering
University of Rochester
[9]. Jan M. Rabaey, “Ultra Deep Sub-micron
Design Challenges-An Overview ”BWRC University of
California @ Berkeley
[10]. Kevin T. Tang and Eby G. Friedman, “ Interconnect
Coupling noise in CMOS VLSI Circuits” Dept. of Electrical
and Computer Engineering University of Rochester