A High Yield 12-bit 250-MS/s CMOS D/A Converter

J ose Bastos, Michiel Steyaert, and Willy Sansen

Katholieke Universiteit Leuven, ESAT-MICAS
Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
Abstract
A 12-bit linearity binary-weighted all MOS transistor
D/A converter is presented. Experimental results demonstrate
the feasibility of fabricating with high yield such a converter
in a standard CMOS 0.7pm technology. The output drives a
doubly terminated 50Q coaxial cable. The full scale 10-90%
rise/fall time is 4 ns. The active chip area is lmm2.
Introduction
Recent interest in using digital signal processing in such
fields as wireless personal communications and video signal
processing has created a demand for fast D/A converters with
accuracy higher than 10 bits. The accuracy of D/A converters
that rely on static mirrors is limited by the achievable
transistor matching in a given technology. In CMOS VLSI
technologies the maximum accuracy is typically 10 bits [ 11-
121. In this paper we present a 12 bit linearity 250MS/s all
MOS transistor D/A converter, which demonstrates the
feasibility of fabricating with high yield such a converter in a
CMOS 0.7pm digital standard technology.
Chip Architecture
In order to achieve high speed current steering is the
preferred architecture. Current steering D/A converters are
based on current cells which are binary weighted, or
monotonic decoded unit cells. The two architectures trade a
reduction in layout area and complexity for increased
differential non linearity (DNL) and glitch energy.
Independent of the architecture, the most important static
specification, the integral non linearity (I NL) has the same
difficulty requirement. As our most important goal is to
achieve 12 bit integral linearity, we have chosen a binary
weighted architecture because it has minimum layout area
and it offers considerable advantages in eliminating
systematic errors introduced by process gradients. A block
diagram of the DAC architecture is shown in Fig. 1.
Design for Linearity
A. Random Errors
Due to the matching fluctuation of the current sources,
the INL specification varies randomly in a set of several
DACs realized in the same process technology. Hence it is of
primary importance to establish the circuit yield as a
function of the matching accuracy in the current sources.
Theoretical yield estimations are found in the literature
[3]-[4]. However, a correct yield estimation can only be
obtained by Monte-Carlo simulations. The result of such a
simulation is shown in graphical form in Fig. 2. We can see
that, with a unit current source relative standard deviation
(oyl) of 0.3%, we can guarantee a 99% yield.
This result allows to estimate the minimum channel area
of the unit current source. The relative standard deviation of
matching between two unit current sources as function of the
bias point and the channel dimensions is approximately
given by [5]
CT 2 ( AV, ) =- AVT
WL
The parameters AVT and AD are technology constants
previously extracted for the 0.7pm CMOS technology, and
are shown in Table I [6]. Defining a bias point of
V,,=Z.OV, a minimum channel area of the unit current
source is obtained. This value is (WL),,,=50pm2. This is the
first and most important constraint of the design.
A second constraint arrives from the total drain current
specification Ztotal of ZOmA, for a 0.5V voltage output over
a 25Q load. This constraint imposes a maximum W/L ratio
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of U12.5. The unit current source transistor has thus channel
dimensions W/L=2/25 p d p m.
B. Systematic Errors
The unit current source finite output impedance and the
voltage drop along the ground line can introduce significant
linearity errors [7]. Due to the large L of the unit current
source, the output resistance of the cascode configuration of
the unit current source and the current switch transistor is
sufficiently high. Maximum resistance for the column
ground lines and the backbone ground line is not exceeded.
Parameter gradients over the die can represent the limiting
accuracy obtainable for large dies. For this reason, the
distance influence on matching has been studied for the
applied technology. Table I shows the process parameters
SVT and Sp which model the matching degradation with
distance for the threshold voltage and the current factor.
Although the wafer gradients introduce a deterministic
matching error, we do not know the position of the die in the
wafer, which means that the parameter gradient can have any
direction in the die. This problem has been tackled in the
linear architecture by introducing a special wiring method or
switching sequence [ 11-[2], which increases the wiring
complexity and silicon area. We have defined an algorithm,
which builds the binary weighted current sources by
connecting the outputs of centroid distributed unit current
sources over the array area. In this way all the two
dimensional systematic error sources whose period is a
rational fraction of the array length, do not contribute to the
degradation of the integral linearity. Fig. 3 shows this
distribution for the four most significant bits.
Layout
A straightforward approach to the layout of a matrix with
4096 unit current sources spends a considerable amount of
layout area. For this technology, if we route 12 bit lines in a
64x64 square matrix, the total area occupied by the routing is
2.4mm2, roughly 10 times more area than the gate area of
the transistors! A straightforward layout is thus not
acceptable.
The solution is to reduce the array size and to route less
bit lines. We define a 16x16 matrix of new unit current
sources, each having a value of 16 old unit current sources,
for the 8 most significant bits. The channel dimensions of
the current source are now 32/25 ,um/pm, and the routing of
the 8 bit lines is done over the transistor. In this approach
no silicon area is used in the routing, and a most compact
layout for the array is obtained. The four least significant
bits are constructed by connecting in series the necessary
number of new unit current sources. These current sources
are layed out around the array, and also serve to provide
identical surroundings to all the array elements, thus
avoiding micro loading effects. The layout of the unit current
source is shown in Fig. 4. The sources are connected by the
vertical running metal 1, over the gate, and thus occupies no
extra area. The drains are connected to the corresponding bit
line (running parallel in metal 2), also over the gate. The
complete layout of the unit current source array occupies
only650x650pm2.
Design for Speed
The conventional D/A has three main dynamic error
sources: imperfect synchronization of the inputs,
digital
signal feedthrough, and current variation due to drain voltage
variation of the current sources.
The transistors used in the differential switches have the
same (minimum) length but a width proportional to the
current they are switching. For the most significant bits, the
width is very large, and thus their gate and drain capacitance
are also large, and significant delays are introduced. To
synchronize the inputs a 4-stage tapered driver stage with a
size factor of 2 has been used to buffer the bit lines.
Charge feedthrough of digital input signals to the output
can, due to the large gate-drain capacitance of the MSBs, also
affects negatively the settling time. This source of error is
significantly reduced by using cascode switches.
The cross point of rising/falling waveforms in the input
drivers is also very important. In a symmetrical switching
circuit the cross point is too low and there is a significant
voltage swing at the drain of the current sources. We use an
input driver scheme which combines the advantages of
decreased gate voltage swing and delayed switching. The
scheme is shown in Fig. 5 In this circuit, the cross coupled
NMOS transistors work as delay elements, so that the on-off
transition is slightly delayed. The delay can be fine tuned by
changing the voltage V, at the source of the transistors.
Changing the voltage V, has the extra advantage that, by
decreasing the voltage swing at the gates of the switching
transistors, there is less digital signal feedthrough.
Measurement Results
Figure 6 shows a microphotograph of the DAC. The
active area occupied by the circuit is lmm2.
The INL error measured in 30 out of 30 functionally
working samples is less than 112LSB. It can be stated that
the design yield is greater than 90%, at a 95% confidence
level. Figure 7 shows a typical integral linearity plot. The
average INL is 0.39 LSB. In most of the cases, the
maximum INL occurs at half the scale, and coincides with
the DNL at the MSB transition, as expected. This fact
demonstrates that the centroid layout has successfully
minimized the effect of the die gradients.
Figure 8 shows a full scale positive and negative output
step (50Q doubly terminated coaxial cable, 20pF load). The
rise/fall time is less than 4ns. The dies have been bonded to a
28pin DIP. The bond wire inductance is the remaining source
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of error, causing the extra ringing at the output for a full
scale voltage swing.
Conclusion
A 12 bit linearity current steering CMOS DIA converter
capable of video speed has been presented. Taking advantage
of the matching properties of a modem CMOS 0.7pm
technology and using a very compact layout, a design yield
greater than 90% is obtained.
Acknowledgment
J. Bastos is supported by a grant from the Portuguese
National Research Board (J NICT).
References
[I ] Y . Nakamura et al., "A IO-bit 70MS/s CMOS D/A Converter", IEEE J .
Solid-State Circuits, vol. 26, pp. 637-642, April 1991.
[2] T. Wu, C. J ih, J . Chen, C. Wu, "A Low Glitch 10-hit 75-MHz CMOS
Video D/A Converter", IEEE J . Solid-State Circuits, vol. 30, pp. 68-72,
16-
14-
12-
10
8 -
6 -
4 -
2-
0
~~
J anuary 1995.
[3] K. Lakshmikumar, R. Hadaway, and M. Copeland, "Characterization
and Modeling of Mismatch in MOS Transistors for Precision Analog
Design", IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1057-1066,
0 X + X 0 X X % X ?$C 0 X + Y 0 X
* O Y + X O Y x X O X + * O
+ X 0 X 0 X + f + K 0 Y 0 X + X
X + * O * * o x o x * o x +
0 x x o x + * + * o x t o *
x o x o x o * x * x x o x o * o
- x o x x x o x o Y x x o * x
X x x + * + x o x o * + * + x x
x o x x x o * o x x x o * x
x x x + * + x o x o x + x + x x
0 Y x 0 * + * + * 0 x * o x
* o x o x o x x * x x o * o * o
+ Y 0 x 0 x + x + x 0 x 0 Y + x
Y O * + % + * o x
0 x + x 0 x x Y x x 0 x + x 0 x
x o * + * o * Y * o x + x o
* O * O Y
2 4 6 8 10 12 14 16
December 1986.
[4] K. Lakshmikumar, M. Copeland, and R. Hadaway, "Reply to 'A
Comment on 'Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design'", IEEE J . Solid-state
Circuits, vol. 23, pp. 296, February 1988.
[5] M. Pelgrom, A. Duinmaijer, and A. WelbersMatching Properties of
MOS Transistors", IEEE J . Solid-state Circuits, vol. SC-24, pp. 294-
.~
296, February 1988.
[6] J . Bastos et al., "Matching of MOS Transistors with Different Layout
Stvles", IEEE International Conference on Microelectronic Test
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State Circuits, vol. SC-21, pp. 983-988, December 1986.
[7] T. Miki et al., "An 80 MHz 8-bit CMOS D/A Converter", IEEE J . Solid-
Table I
Mismatch Parameters
-channel unit
0.4 m V/ m m
0.2 0.3 %/mm
Table I1
Characteristics of the DAC
Resolution 12 bit
Differential Nonlinearity <OS LSB
Integral Nonlinearity <O.SLSB
Conversion Rate 250MSIs
RiseFall Time (1 0-90%) <4ns
F.S. Output Current 20mA
Supply Voltage 3.3v
Process 0.7pm CMOS
Chip Size (without pads) 1 mm2
100
40
20
Bits, (
Fig. 4. Unit current source layout.
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0.3 t b
lout
ldump
I I
I I
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-0.5'
Fig. 5. Basic current cell. m r i m - 1-_1
Fig. 7. DAC integral linearity plot (typical)
Fig 8 Full scale output transitions
Fig 6 Die microphotograph
lx
l x
Fig. 1. DAC architecture.
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