Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II

LAB: 1
TITLE: INTRODUCTION TO ALTERA MAX PLUS II


Learning Outcomes:

At the end of the practical, student able to:
i. Explain schematic design using CPLD
ii. Explain function clocks (wave form) in digital computer.
iii. Use schematic CPLD to simulate digital output for SR, D, master slave and
JK flip-flop.
iv. Design shift register using flip-flop JK.


Laboratory Equipment:
i. Computer
ii. Software Altera Max Plus II



Theory:

A digital system can be represented at different levels of abstraction. This
keeps the description and design of complex systems manageable. Figure 1 shows
different levels of abstraction.


Figure 1 : Levels of abstraction: Behavioral, Structural and Physical

The highest level of abstraction is the behavioral level that describes a
system in terms of what it does (or how it behaves) rather than in terms of its
components and interconnection between them. A behavioral description specifies
the relationship between the input and output signals. This could be a Boolean
expression or a more abstract description such as the Register Transfer or
Algorithmic level.

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


The structural level, on the other hand, describes a system as a collection of
gates and components that are interconnected to perform a desired function. A
structural description could be compared to a schematic of interconnected logic
gates. It is a representation that is usually closer to the physical realization of a
system.

Schematic Logic Design

A schematic design defines the functionality of a logic circuit using one or
more schematic files, each of which contains components from a Altera-supplied
library, such as gates, flip-flops and building-block functions similar to 74xx TTL
devices. Schematics can also contain "custom" symbols for which you define the
functionality using behavioral modules (similar to PAL devices).

The following figure 2 summarizes the design flow using CPLD.

Figure 2 : Flow Design

Waveform
In schematic design, waveform viewers or editor are typically used in
conjunction with a simulation. A waveform view allows the designer to see the signal
transitions over time and the relation of those signals with other signals in a
schematic design, which is typically written in a hardware description language.
Simulators can be used to interactively capture wave data for immediate
viewing on a waveform viewer; however, for larger schematic design the usage
model is typically to save the output of simulation runs by running batch jobs and to
view the waveforms off-line as a static database.
Waveform editor allow you to zoom in and out over a time sequence, and
take measurements between two cursor points. In addition, the waveform view has
many ways of displaying signal information, such as in hexadecimal, binary, or a
symbolic value.


Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


Flip-flops
The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit
has two outputs, one for the normal value and one for the complement value of the
stored bit. Binary information can enter a flip-flop in a variety of ways and gives rise
to different types of flip-flops.

SR Flip-flop

Figure 3: Symbol for active high and active low SR Flip-flop

Flip-flop is a sequential logic circuit which is capable of storing one bit
of data. It can store either a binary number 0 or 1 and the circuit has two
states known as SET and RESET. When a flip-flop is flip to the set (where it
stores a binary 1) or flop to the reset (where it stores the binary 0), the output
of the circuit will remain (Latched / locked) as long as it is been power
supplied.

SR flip-flop can be construct using both NAND or NOR gates. A flip-
flop using NOR gate is an active high logic circuit which the output will be set
to 1 when the given input S is logic 1. Otherwise, the flip-flop using NAND
gate is an active low logic circuit. The input S must be logic 0 when the
needed output want to be set as logic 1.

Operation table for active high and active low SR Flip-flop:

Table 1
S R
Operation for
active high
Operation for
active low
0 0 hold invalid
0 1 reset set
1 0 set reset
1 1 invalid hold


JK Flip-flop

Figure 4: Logic symbol for JK flip-flop - positive and negative edge triggered
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II



JK flip-flop operation is similar to the SR flip-flop operation. The only
difference is the flip-flop does not have the forbidden or invalid state. The
truth table for both flip-flop are mostly the same, except when the given input
of J = K = 1, the flip-flop will be in the toggle state. Toggle is a condition
where the output of a flip-flop will invert from 0 to 1 and vice versa at positive
or negative clock edge triggered.

JK flip-flop is a universal flip-flop as it can be converts into D flip-flop
and T flip-flop. It is widely use in digital electronic circuit especially as a
counter and a basic register when a few numbers of flip-flop are combined
altogether.

Operation table for JK Flip-flop:

Table 2
J K Operation
0 0 hold
0 1 reset
1 0 set
1 1 toggle

D Flip-flop

Figure 5: Logic symbol for D Flip-flop

D flip-flop is known as Delay or Data flip-flop because of its ability to
store data and transfer the information after receiving the pulse. This flip-flop
usually can be found in a design of a register.

D Flip-flop can be constructed using either SR or JK flip-flop by
connected with the inverter between the input S and R, or J and K input.
Below figure shows the reconstructed D flip-flop using SR or JK.


Figure 6: Internal D Flip-flop

Here is the truth table for D flip-flop:

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


Table 3
Clk D Q
t+1
0 0
1 1


Master-Slave Flip-flop

A master-slave flip-flop is constructed from two separate flip-flops.
One circuit serves as a master and the other as a slave. The logic diagram of
an SR flip-flop is shown in Figure 7.

Figure 7: Logic diagram of a master-slave flip-flop

The master flip-flop is enabled on the positive edge of the clock pulse
CP and the slave flip-flop is disabled by the inverter. The information at the
external R and S inputs is transmitted to the master flip-flop. When the pulse
returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled.
The slave flip-flop then goes to the same state as the master flip-flop.
The timing relationship is shown in Figure 8 and is assumed that the
flip-flop is in the clear state prior to the occurrence of the clock pulse. The
output state of the master-slave flip-flop occurs on the negative transition of
the clock pulse. Some master-slave flip-flops change output state on the
positive transition of the clock pulse by having an additional inverter between
the CP terminal and the input of the master.

Figure 8: Timing relationship in a master slave flip-flop


Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


Shift Register

A shift register is a cascade of flip-flops, sharing the same clock, which has
the output of any one but the last flip-flop connected to the data input of the next one
in the chain, resulting in a circuit that shifts by one position the one-dimensional bit
array stored in it, shifting in the data present at its input and shifting out the last bit in
the array, when enabled to do so by a transition of the clock input.

One of the most common uses of a shift register is to convert between serial
and parallel interfaces. It is also been used to handle data processing in arithmetic
and logic unit (ALU).

Below figure 9 shows process the data being shifted in timing diagram.


Figure 9


Procedure:

Part A: Schematic Logic Design

1. Run MAX+plus II software by click StartProgramsMAX+plus II
MAX+plus II 10.2 Baseline.

2. Click MAX+plus IIGraphic Editor to open the schematic editor.

3. Double click on the editor to get the component from the library. Then, double
click c:\maxplus2\max2lib\prim on the Symbol Libraries box.

4. Double click and2 in the Symbol Files box to get the 2-input AND gate.

5. Repeat the above steps to get the component below:




Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


Table 4
Symbol Component Quantity

OR 1

Input 2

Output 2


6. To move the component, left click on the component and drag it to the
suitable place.

7. Arrange the logic circuit as Figure 10:


Figure 10

8. To draw the line, point the mouse to the input/output component until the
pointer becomes + symbol. Then, click and drag the line to other component.

9. To rename the input and output pin, click the text and rename.

10. The component can be flip vertical / horizontal and rotate 90,180, 270 by
right click on the mouse and choose flip or rotate.

Saving File

11. Go to File Save aschoose folder on the directories and save the
schematic file as Component1a.gdf

Set project, compile schematic, check for errors

12. The schematic circuit should be free from any errors. To check the error, the
file need to be set the current project. Click File Project Set Project to
Current File.

13. Compile the schematic and make sure there is no error. Click File Project
Save & Compile. The result will be shown as Figure 11.
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II




Figure 11

Creating symbol for the drawn schematic

14. MAX + plus II can provide a symbol for the drawn schematic. Click File
Create Default Symbol. This symbol can be called into the other schematic
later.

15. To call this symbol, please refer to step 3. Double click in the new graphic
editor. Find the file in the directory where it has been saved before (Figure 3).




Figure 12





Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II


16. The recall symbol will appear as Figure 13.

Figure 13

17. Based on the logic schematic in the Figure 10, complete the truth table below:

Table 5
Input Output
a b y z
0 0
0 1
1 0
1 1

18. Based on the truth table, complete the Karnaugh Map (K-Map)

Table 6: y-output

0 1
0
1


Table 7: z-output

0 1
0
1



19. From the table 6 and 7, generate the Boolean equations.






Part B :Execute Schematic using Waveform Editor

1. Run the Waveform Editor. Click MAX+plus II Waveform Editor.

2. To draw a waveform, double click in the Name column. Click on the List
button in the Insert Node popup window.
Y =
Z =
a
a
b
b
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II



3. Select a(I) and click OK to insert the a input node. Repeat the step to insert all
nodes into the waveform editor as figure 14.




Figure 14

Changing transition period

4. Transition period (0 to 1 or 1 to 0) can be set through Options Grid Size. An example, set
the transition period to 50ns.

5. Select node a and click icon - Overwrites a node with Clock waveform. Overwrites Clock
popup window will appear then click OK.


Figure 15


6. Click icon - Changes the display scale to view the whole waveform.

7. For b waveform, repeat step 5 and change the Multiplied By: 2.

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II

Figure 16

Setting the simulation end time

8. Since all combinations of a and b have been attempted after 200 ns, we can stop the
waveform at 240 ns. Click File End Time and type 240ns in Time: box.


Figure 17


Saving waveform editor and executing schematic

9. Save waveform diagram by clicking File Save As component1a.scf

10. Execute the logic schematic by clicking File Project Save & Simulate. Popup window
as Figure 9 will appear.


Figure 18

11. Check the result of the simulation and compare with your truth table (Table 5).


Figure 19

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II
Part C: Simulate Digital Output for Various Flip-flop

SR Flip-flop
1. Create the active high SR flip-flop schematic as below using graphic editor.



Figure 20: Active high SR Flip-flop

2. Save the schematic as SRNorff.gdf

3. Generate the waveform for SR flip-flop using waveform editor.

4. Complete the SR flip-flop truth table below using the generated waveform.

Table 8
Input Output
Operation
S R Q
Q
1 0
0 0
0 1
0 0
1 0
1 1
0 0

5. Create and show the symbol for SRNor flip-flop.

6. Create the active low SR flip-flop schematic as below using graphic editor.


Figure 21: Active Low SR Flip-flop

7. Save the schematic as SRNandff.gdf

8. Generate the waveform for SR flip-flop using waveform editor.

9. Complete the SR flip-flop truth table below using the generated waveform.

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II
Table 9
Input Output
Operation
S R Q
Q
1 0
0 0
0 1
1 1
1 0
1 1
0 0

10. Create and show the symbol for SRNand flip-flop.

JK Flip-flop

1. Create a JK flip-flop schematic as below using graphic editor.

Figure 22: JK Flip-flop

2. Save the schematic as JKff.gdf

3. Generate the waveform for JK flip-flop using waveform editor.

4. Complete the JK flip-flop truth table below using the generated waveform.

Table 10
CLK
Input Output
Operation
J K Q
Q
1 0
0 0
0 1
1 1
0 0
0 1
0 0

5. Create and show the symbol for Dff flip-flop.
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II
D Flop-flop

1. Create a D flip-flop schematic as below using graphic editor.



Figure 23: D Flip-flop

2. Save the schematic as Dff.gdf

3. Generate the waveform for D flip-flop using waveform editor.

4. Complete the D flip-flop truth table below using the generated waveform.

Table 11
CLK
Input Output
D Q
Q
1
0
0
0
1
1
0

5. Create and show the symbol for Dff flip-flop.


Master-Slave Flip-flop


1. Using two SR flip-flops, design the Master-Slave Flip-flop as logic diagram below:

Figure 24: Master-Slave Flip-flop
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II

2. Save the schematic as MSff.gdf

3. Generate the waveform for MS flip-flop using waveform editor.

4. Complete the MS flip-flop truth table below using the generated waveform.

Table 12
CLK
Input Output
Operation
S R Q
Q








5. Create and show the symbol for MSff flip-flop.


Part D : Shift Register using JK flip-flop

1. Create the shift register using the previous JK flip-flop. Refer to Figure 25.

Figure 25


2. Save the schematic as Shiftreg.gdf
3. Generate the waveform and prove that the data been shifted.


Question:

1. Basic Flip-flop
i. Draw the logic circuit for an unclocked NOR gate flip-flop.
ii. Enter the expected timing diagram for signals Q and Q' in Figure 26.
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II

iii.
Figure 26: NOR gate flip-flop timing diagram
iv. Draw the logic circuit for an unclocked NAND gate flip-flop.
v. Enter the expected timing diagram for signals Q and Q' in Figure 27.

Figure 27: NAND gate flip-flop timing diagram
2. Master Slave Flip-flop
i. Draw the logic circuit implemented with gates for the SR master-slave flip-flop in
Figure 24. Use NOR gate flip-flops.
ii. Enter the expected timing diagram for the signals Y, Y', Q, and Q' in Figure 28.

Figure 28: SR master-slave flip-flop timing diagram
3. Edge triggered flip-flop
i. Draw the logic circuit for the D-type positive-edge triggered flip-flop in Figure 5.
Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 1: Introduction to Altera Max Plus II
ii. Enter the expected timing diagram for the signals S, R, Q, and Q' in Figure 29.

Figure 29: D-type edge triggered flip-flop timing diagram


Conclusion :
Your conclusion should be related to your practical and theoretical understanding on the related topic.
(not less than one page of explanation)