Академический Документы
Профессиональный Документы
Культура Документы
Full
Full
-
-
Custom Design
Custom Design
Standard Cell
Standard Cell
Gate Array
Gate Array
FPGA
FPGA
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Full
Full
-
-
Custom Design Style
Custom Design Style
Designers can control the shape of all mask patterns Designers can control the shape of all mask patterns
Designers can specify the design up to the level of Designers can specify the design up to the level of
individual transistors individual transistors
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Standard Cell Design Style
Standard Cell Design Style
Selects pre Selects pre- -designed cells (of same height) to designed cells (of same height) to
implement logic. implement logic.
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Gate Array Design Style
Gate Array Design Style
Prefabricates a transistor array. Prefabricates a transistor array.
Needs wiring customization to implement logic. Needs wiring customization to implement logic.
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FPGA Design Style
FPGA Design Style
Logic and interconnects are both prefabricated. Logic and interconnects are both prefabricated.
Illustrated by a symmetric array Illustrated by a symmetric array- -based FPGA based FPGA
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Comparison of Design Styles
Comparison of Design Styles
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Comparison of Design Styles
Comparison of Design Styles
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Layout Representation
Layout Representation
Layout Editor Layout Editor
A CAD tool that allows a human designer to create A CAD tool that allows a human designer to create
and edit a VLSI layout. and edit a VLSI layout.
A layout is a collection of tiles A layout is a collection of tiles
A tile is a rectangular section within a single layer. A tile is a rectangular section within a single layer.
Tiles are not allowed to overlap within a layer. Tiles are not allowed to overlap within a layer.
The elements of a layout are referred to as block The elements of a layout are referred to as block
tiles. tiles.
The area of a block that does not contain a block is The area of a block that does not contain a block is
referred to as vacant space. referred to as vacant space.
Vacant space can be partitioned into a series of Vacant space can be partitioned into a series of
vacant tiles. vacant tiles.
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Layout Representation Examples
Layout Representation Examples
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Data Structures for Layout Representation
Data Structures for Layout Representation
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Atomic Operations for layout Editors
Atomic Operations for layout Editors
Atomic Operations: Atomic Operations:
Basic set of operations that give a designer the Basic set of operations that give a designer the
freedom to fully manipulate a layout. freedom to fully manipulate a layout.
Basic Atomic Operations Basic Atomic Operations
Point Finding Point Finding: Given the coordinates of a point : Given the coordinates of a point p = p =
(x, y) (x, y), determine whether , determine whether p p lies within a block, and lies within a block, and
if if so, identify that block. so, identify that block.
Neighbor Finding Neighbor Finding: Determine all blocks touching a : Determine all blocks touching a
given block given block B B. .
Block Visibility Block Visibility: Determine all blocks visible in the : Determine all blocks visible in the
x x and and y y directions from a given block directions from a given block B B. .
Area Search Area Search: Given a fixed area : Given a fixed area A A defined by its defined by its
upper left corner upper left corner (x, y) (x, y), its length , its length l l and width and width w w, ,
determine the blocks with which determine the blocks with which A A intersect. intersect.
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Atomic Operations for layout Editors
Atomic Operations for layout Editors
Basic Atomic Operations (Contd.) Basic Atomic Operations (Contd.)
Directed Area Enumeration Directed Area Enumeration: Given a fixed area : Given a fixed area A A, ,
visit each block intersecting visit each block intersecting A A exactly once in a exactly once in a
sorted order. sorted order.
Block Insertion Block Insertion: Insert a new block B such that it : Insert a new block B such that it
does not intersect with any existing block. does not intersect with any existing block.
Block Deletion Block Deletion: : Remove block Remove block B B from layout. from layout.
Plowing Plowing: Given an area : Given an area A A and direction and direction d d, remove , remove
all blocks all blocks B B
i i
from from A A by shifting them in direction by shifting them in direction d d
while preserving their order. while preserving their order.
Compaction Compaction: Plowing or compressing the entire : Plowing or compressing the entire
layout. layout.
Channel Generation Channel Generation: Determining vacant space in : Determining vacant space in
layout and partitioning it into tiles. layout and partitioning it into tiles.
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Corner Stitching Data Structure
A floor with some solid tiles (blocks) are given.
Partition the floor with maximal horizontal strips to define blank or
vacant tiles.
For each tile, store its position, size description, and other
attributes.
Insert corner stitches (pointers), 4 per tile (for both solid and
vacant) pointing to the appropriate neighboring tiles.
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Point Finding using Corner Stitches
Point Finding using Corner Stitches
Given a point p Given a point p
2 2
, find a path through the corner , find a path through the corner
stitches from the current point p stitches from the current point p
1 1
to p to p
2 2
traversing the traversing the
minimum number of tiles. minimum number of tiles.
Steps Steps
1. 1. Move up or down using the Move up or down using the rt rt or lb pointers until a or lb pointers until a
tile is found whose vertical range contains the tile is found whose vertical range contains the
destination point. destination point.
2. 2. Move left or right using Move left or right using tr tr or or bl bl pointers until a tile pointers until a tile
is found whose horizontal range contains the is found whose horizontal range contains the
destination point. destination point.
3. 3. Whenever there is a misalignment (search goes Whenever there is a misalignment (search goes
out of the horizontal range of the tile that contains out of the horizontal range of the tile that contains
the destination point) due to the above the destination point) due to the above
operations, repeat steps 1 and 2. operations, repeat steps 1 and 2.
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Point Finding using Corner Stitches
Point Finding using Corner Stitches
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Partitioning
Partitioning
The process of decomposition of a large system into independent
manageable subsystems which can be designed independently and
concurrently
Input
a set of components or modules
a netlist
in the form of a weighted graph or hypergraph: nodes
representing modules; edge or hyperedge representing a net
Output
a set of subcircuits that when connected, function as the original
circuit
terminals required for each subcircuit to be connected to other
subcircuits
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Levels of Partitioning
Levels of Partitioning
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Partitioning Example
Partitioning Example
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Partitioning
Partitioning
Problem Formulation
Problem Formulation
Given a Given a hypergraph hypergraph G G = ( = (V V, , E E) )
Vertex = a component. Vertex = a component.
Hyperedge Hyperedge = a = a net net - - a connection between two components. a connection between two components.
Net Net - - a set of electrically equivalent terminals a set of electrically equivalent terminals
a(v a(v
i i
) ) = area of a component = area of a component
A(V A(V
i i
) ) = = a(v a(v) ), , v v V V
i i
(Area of partition (Area of partition V V
i i
) )
P = {p P = {p
1 1
, , , p , p
m m
} } (set of (set of hyperpaths hyperpaths). ).
H(p H(p
i i
) = ) = number of times number of times p p
i i
is cut; affects delay due to partitioning. is cut; affects delay due to partitioning.
Objective Objective
Partition Partition V V into disjoint clusters V into disjoint clusters V
1 1
, , , , V V
k k
, such that cut , such that cut- -size and size and
max( max(H(p H(p
i i
) ) ) are minimized. ) are minimized.
Constraints Constraints
Number of terminals in a partition has an upper bound Number of terminals in a partition has an upper bound
Area of each partition Area of each partition
Number of partitions must be within a range Number of partitions must be within a range
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Kernighan
Kernighan
-
-
Lin (KL) Partitioning Algorithm
Lin (KL) Partitioning Algorithm
A group A group- -migration based algorithm migration based algorithm
starts with an initial partition, generated randomly
moves components between partitions to improve
Problem Formulation Problem Formulation
Input
An undirected graph G(V,E), |V| = 2n and |E| = m
Cost or weight d(a,b) for each edge (a,b) in E
Output
Two partitions X and Y such that the total cost of the
cut is minimized, and each partition has n vertices
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Bipartition
Bipartition
-
-
Without Heuristics
Without Heuristics
Try all possible bisections. Find the best one.
For 2n vertices, # of possibilities = (
2n
C
n
) = n
O(n)
For 100 vertices, there are 5 10
28
possibilities.
Take 1.59 x 10
13
years if one can try 100M possibilities
per second.
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KL Algorithm
KL Algorithm
Start with an initial bisection P = {X, Y};
Repeat
repeat
Choose a pair of free cells a X, b Y s.t.
exchanging a and b gives the highest gain,
gain(a,b);
Tentatively exchange a and b, and lock a and b;
Let g
i
= gain(a,b);
until all pairs are locked;
Unlock all vertices;
Find k s.t. G = g
1
+ g
2
+ .. + g
k
is maximized and
actually exchange cell pairs up to this k
th
step;
Until G = 0;
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KL Algorithm
KL Algorithm
-
-
Gain
Gain
gain(a,b) = D(a) + D(b) - 2d(a,b), where
d(a,b) = weight between a and b
D(a) = Out(a) - In(a)
Out(a) = total weight of all edges of a that cross the bisection
In(a) = total weight of all edges of a that do not cross the
bisection
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KL Algorithm
KL Algorithm
-
-
Example
Example
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KL Algorithm
KL Algorithm