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VLSI Physical Design Automation

Introduction, Partitioning, Floor-planning


VLSI Physical Design Automation
VLSI Physical Design Automation
Introduction, Partitioning, Floor Introduction, Partitioning, Floor- -planning planning
Arnab Arnab Sarkar Sarkar
Dept. of Computer Sc. & Dept. of Computer Sc. & Engg Engg., .,
Indian Institute of Technology Kharagpur Indian Institute of Technology Kharagpur
Advanced VLSI Design Lab., IIT Kgp
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VLSI Design Cycle
VLSI Design Cycle
System Specification System Specification
Architectural Design Architectural Design
Functional Design Functional Design
Logic Design Logic Design
Circuit Design Circuit Design
Physical Design Physical Design
Fabrication Fabrication
Packaging, Testing and Packaging, Testing and
Debugging Debugging
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
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Physical Design
Physical Design
Physical design process Physical design process
The process of converting the specification of an electrical The process of converting the specification of an electrical
circuit called circuit called netlist netlist into a geometric representation called layout. into a geometric representation called layout.
Physical Design Automation Physical Design Automation
Deals with the research and development of algorithms and data Deals with the research and development of algorithms and data
structures related to physical design process. structures related to physical design process.
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Physical Design Cycle
Physical Design Cycle

Stages:
Stages:
Partitioning Partitioning
Floor Floor- -Planning Planning
Placement Placement
Routing Routing
Compaction Compaction
Physical Design
Circuit
Design
(a)
(b)
(c)
(d)
Partitioning
Floorplanning
&
Placement
Routing
Compaction
Fabrication
cutline2
cutline1
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Design Styles
Design Styles

Full
Full
-
-
Custom Design
Custom Design

Standard Cell
Standard Cell

Gate Array
Gate Array

FPGA
FPGA
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Full
Full
-
-
Custom Design Style
Custom Design Style
Designers can control the shape of all mask patterns Designers can control the shape of all mask patterns
Designers can specify the design up to the level of Designers can specify the design up to the level of
individual transistors individual transistors
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Standard Cell Design Style
Standard Cell Design Style
Selects pre Selects pre- -designed cells (of same height) to designed cells (of same height) to
implement logic. implement logic.
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Gate Array Design Style
Gate Array Design Style
Prefabricates a transistor array. Prefabricates a transistor array.
Needs wiring customization to implement logic. Needs wiring customization to implement logic.
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FPGA Design Style
FPGA Design Style
Logic and interconnects are both prefabricated. Logic and interconnects are both prefabricated.
Illustrated by a symmetric array Illustrated by a symmetric array- -based FPGA based FPGA
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Comparison of Design Styles
Comparison of Design Styles
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Comparison of Design Styles
Comparison of Design Styles
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Layout Representation
Layout Representation
Layout Editor Layout Editor
A CAD tool that allows a human designer to create A CAD tool that allows a human designer to create
and edit a VLSI layout. and edit a VLSI layout.
A layout is a collection of tiles A layout is a collection of tiles
A tile is a rectangular section within a single layer. A tile is a rectangular section within a single layer.
Tiles are not allowed to overlap within a layer. Tiles are not allowed to overlap within a layer.
The elements of a layout are referred to as block The elements of a layout are referred to as block
tiles. tiles.
The area of a block that does not contain a block is The area of a block that does not contain a block is
referred to as vacant space. referred to as vacant space.
Vacant space can be partitioned into a series of Vacant space can be partitioned into a series of
vacant tiles. vacant tiles.
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Layout Representation Examples
Layout Representation Examples
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Data Structures for Layout Representation
Data Structures for Layout Representation
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Atomic Operations for layout Editors
Atomic Operations for layout Editors
Atomic Operations: Atomic Operations:
Basic set of operations that give a designer the Basic set of operations that give a designer the
freedom to fully manipulate a layout. freedom to fully manipulate a layout.
Basic Atomic Operations Basic Atomic Operations
Point Finding Point Finding: Given the coordinates of a point : Given the coordinates of a point p = p =
(x, y) (x, y), determine whether , determine whether p p lies within a block, and lies within a block, and
if if so, identify that block. so, identify that block.
Neighbor Finding Neighbor Finding: Determine all blocks touching a : Determine all blocks touching a
given block given block B B. .
Block Visibility Block Visibility: Determine all blocks visible in the : Determine all blocks visible in the
x x and and y y directions from a given block directions from a given block B B. .
Area Search Area Search: Given a fixed area : Given a fixed area A A defined by its defined by its
upper left corner upper left corner (x, y) (x, y), its length , its length l l and width and width w w, ,
determine the blocks with which determine the blocks with which A A intersect. intersect.
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Atomic Operations for layout Editors
Atomic Operations for layout Editors
Basic Atomic Operations (Contd.) Basic Atomic Operations (Contd.)
Directed Area Enumeration Directed Area Enumeration: Given a fixed area : Given a fixed area A A, ,
visit each block intersecting visit each block intersecting A A exactly once in a exactly once in a
sorted order. sorted order.
Block Insertion Block Insertion: Insert a new block B such that it : Insert a new block B such that it
does not intersect with any existing block. does not intersect with any existing block.
Block Deletion Block Deletion: : Remove block Remove block B B from layout. from layout.
Plowing Plowing: Given an area : Given an area A A and direction and direction d d, remove , remove
all blocks all blocks B B
i i
from from A A by shifting them in direction by shifting them in direction d d
while preserving their order. while preserving their order.
Compaction Compaction: Plowing or compressing the entire : Plowing or compressing the entire
layout. layout.
Channel Generation Channel Generation: Determining vacant space in : Determining vacant space in
layout and partitioning it into tiles. layout and partitioning it into tiles.
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Corner Stitching Data Structure
A floor with some solid tiles (blocks) are given.
Partition the floor with maximal horizontal strips to define blank or
vacant tiles.
For each tile, store its position, size description, and other
attributes.
Insert corner stitches (pointers), 4 per tile (for both solid and
vacant) pointing to the appropriate neighboring tiles.
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Point Finding using Corner Stitches
Point Finding using Corner Stitches
Given a point p Given a point p
2 2
, find a path through the corner , find a path through the corner
stitches from the current point p stitches from the current point p
1 1
to p to p
2 2
traversing the traversing the
minimum number of tiles. minimum number of tiles.
Steps Steps
1. 1. Move up or down using the Move up or down using the rt rt or lb pointers until a or lb pointers until a
tile is found whose vertical range contains the tile is found whose vertical range contains the
destination point. destination point.
2. 2. Move left or right using Move left or right using tr tr or or bl bl pointers until a tile pointers until a tile
is found whose horizontal range contains the is found whose horizontal range contains the
destination point. destination point.
3. 3. Whenever there is a misalignment (search goes Whenever there is a misalignment (search goes
out of the horizontal range of the tile that contains out of the horizontal range of the tile that contains
the destination point) due to the above the destination point) due to the above
operations, repeat steps 1 and 2. operations, repeat steps 1 and 2.
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Point Finding using Corner Stitches
Point Finding using Corner Stitches
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Partitioning
Partitioning
The process of decomposition of a large system into independent
manageable subsystems which can be designed independently and
concurrently
Input
a set of components or modules
a netlist
in the form of a weighted graph or hypergraph: nodes
representing modules; edge or hyperedge representing a net
Output
a set of subcircuits that when connected, function as the original
circuit
terminals required for each subcircuit to be connected to other
subcircuits
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Levels of Partitioning
Levels of Partitioning
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Partitioning Example
Partitioning Example
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Partitioning
Partitioning

Problem Formulation
Problem Formulation
Given a Given a hypergraph hypergraph G G = ( = (V V, , E E) )
Vertex = a component. Vertex = a component.
Hyperedge Hyperedge = a = a net net - - a connection between two components. a connection between two components.
Net Net - - a set of electrically equivalent terminals a set of electrically equivalent terminals
a(v a(v
i i
) ) = area of a component = area of a component
A(V A(V
i i
) ) = = a(v a(v) ), , v v V V
i i
(Area of partition (Area of partition V V
i i
) )
P = {p P = {p
1 1
, , , p , p
m m
} } (set of (set of hyperpaths hyperpaths). ).
H(p H(p
i i
) = ) = number of times number of times p p
i i
is cut; affects delay due to partitioning. is cut; affects delay due to partitioning.
Objective Objective
Partition Partition V V into disjoint clusters V into disjoint clusters V
1 1
, , , , V V
k k
, such that cut , such that cut- -size and size and
max( max(H(p H(p
i i
) ) ) are minimized. ) are minimized.
Constraints Constraints
Number of terminals in a partition has an upper bound Number of terminals in a partition has an upper bound
Area of each partition Area of each partition
Number of partitions must be within a range Number of partitions must be within a range
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Kernighan
Kernighan
-
-
Lin (KL) Partitioning Algorithm
Lin (KL) Partitioning Algorithm
A group A group- -migration based algorithm migration based algorithm
starts with an initial partition, generated randomly
moves components between partitions to improve
Problem Formulation Problem Formulation
Input
An undirected graph G(V,E), |V| = 2n and |E| = m
Cost or weight d(a,b) for each edge (a,b) in E
Output
Two partitions X and Y such that the total cost of the
cut is minimized, and each partition has n vertices
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Bipartition
Bipartition
-
-
Without Heuristics
Without Heuristics
Try all possible bisections. Find the best one.
For 2n vertices, # of possibilities = (
2n
C
n
) = n
O(n)
For 100 vertices, there are 5 10
28
possibilities.
Take 1.59 x 10
13
years if one can try 100M possibilities
per second.
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KL Algorithm
KL Algorithm
Start with an initial bisection P = {X, Y};
Repeat
repeat
Choose a pair of free cells a X, b Y s.t.
exchanging a and b gives the highest gain,
gain(a,b);
Tentatively exchange a and b, and lock a and b;
Let g
i
= gain(a,b);
until all pairs are locked;
Unlock all vertices;
Find k s.t. G = g
1
+ g
2
+ .. + g
k
is maximized and
actually exchange cell pairs up to this k
th
step;
Until G = 0;
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KL Algorithm
KL Algorithm
-
-
Gain
Gain
gain(a,b) = D(a) + D(b) - 2d(a,b), where
d(a,b) = weight between a and b
D(a) = Out(a) - In(a)
Out(a) = total weight of all edges of a that cross the bisection
In(a) = total weight of all edges of a that do not cross the
bisection
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KL Algorithm
KL Algorithm
-
-
Example
Example
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KL Algorithm
KL Algorithm

Complexity & Drawbacks


Complexity & Drawbacks
Complexity Complexity
O(cn O(cn
3 3
), n ), n is the no. of vertices is the no. of vertices, , and and c c is no. of is no. of
passes passes
Initial computation of Initial computation of D D s s O(n O(n). ).
Within a pass, computation of gain for all free Within a pass, computation of gain for all free
pairs pairs O(n O(n
2 2
). ).
No. of passes is usually small. No. of passes is usually small.
Drawbacks Drawbacks
considers unit vertex weights only considers unit vertex weights only
not applicable to not applicable to hypergraphs hypergraphs
partition sizes have to be pre partition sizes have to be pre- -specified specified
high time complexity high time complexity
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Partitioning Outcome
Partitioning Outcome
Output of Partitioning Phase Output of Partitioning Phase
A set of blocks A set of blocks
Area of each block Area of each block
Possible shapes of each block Possible shapes of each block
No. of terminals in each block No. of terminals in each block
Netlist Netlist specifying the connections between blocks specifying the connections between blocks
Fixed Block Fixed Block
Layout of circuit within block is known Layout of circuit within block is known hence hence
fixed dimension (shape). fixed dimension (shape).
Flexible Block Flexible Block
Exact dimensions not yet determined Exact dimensions not yet determined
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Floorplanning
Floorplanning
Input to the floorplanning problem: Input to the floorplanning problem:
A set of blocks, both fixed and flexible. A set of blocks, both fixed and flexible.
Pin locations of fixed blocks. Pin locations of fixed blocks.
A A netlist netlist. .
Requirements: Requirements:
Find locations for each block so that no two Find locations for each block so that no two
blocks overlap. blocks overlap.
Determine shapes of flexible blocks. Determine shapes of flexible blocks.
Objectives: Objectives:
Minimize area. Minimize area.
Reduce net Reduce net- -length for critical nets. length for critical nets.
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Pin Assignment
Pin Assignment
Input to the pin assignment problem: Input to the pin assignment problem:
1. 1. A placement of blocks. A placement of blocks.
2. 2. Number of pins on each block, possibly an Number of pins on each block, possibly an
ordering. ordering.
3. 3. A A netlist netlist. .
Requirements: Requirements:
1. 1. To determine the pin locations on the blocks. To determine the pin locations on the blocks.
Objectives: Objectives:
1. 1. To minimize net To minimize net- -length. length.
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A Slicing Floorplan
A Slicing Floorplan
I H
G F
E D
C
B
A
V
H
V V V
V
H H
C B
E D I H G F A
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A Non
A Non
-
-
Slicing Floorplan
Slicing Floorplan
E
D
C
B
A
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A Hierarchical Floorplan
A Hierarchical Floorplan
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Floorplanning Algorithms
Floorplanning Algorithms
Floorplanning Algorithms
Rectangular Dual-Graph
Approach
Hierarchical
Approach
Simulated
Annealing
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Rectangular Dual
Rectangular Dual
-
-
Graph Approach
Graph Approach
Output of partitioning algorithms represented by Output of partitioning algorithms represented by
a graph. a graph.
Floorplans can be obtained by converting the Floorplans can be obtained by converting the
graph into its rectangular dual. graph into its rectangular dual.
The rectangular dual of a graph satisfies the The rectangular dual of a graph satisfies the
following properties: following properties:
Each vertex corresponds to a distinct Each vertex corresponds to a distinct
rectangle. rectangle.
For every edge, the corresponding rectangles For every edge, the corresponding rectangles
are adjacent. are adjacent.
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Rectangular Floorplan & its Dual Graph
Rectangular Floorplan & its Dual Graph
Without loss of generality, we Without loss of generality, we
assume that a rectangular assume that a rectangular
floorplan contains no cross floorplan contains no cross
junctions. junctions.
Under this assumption, the Under this assumption, the
dual graph of a rectangular dual graph of a rectangular
floorplan is a floorplan is a planar planar
triangulated graph (PTG). triangulated graph (PTG).
5
4 3
2
1
5 4 3
2 1
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Rectangular
Rectangular
Floorplan
Floorplan
& its Dual Graph
& its Dual Graph
Every dual graph of a rectangular floorplan (without Every dual graph of a rectangular floorplan (without
cross junction) is a PTG. cross junction) is a PTG.
However, not every PTG corresponds to a rectangular However, not every PTG corresponds to a rectangular
floorplan. floorplan.
4 3
2 1
3 2
Complex
triangle
3 4
2 1
4 1
Replace by
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Drawbacks
Drawbacks
A new approach to floorplanning, in which many A new approach to floorplanning, in which many
sub sub- -problems are still unsolved. problems are still unsolved.
The main problem concerns the existence of the The main problem concerns the existence of the
rectangular dual, i.e. the elimination of complex rectangular dual, i.e. the elimination of complex
triangles. triangles.
Select a minimum set E of edges such that each Select a minimum set E of edges such that each
complex triangle has at least one edge in E. complex triangle has at least one edge in E.
A vertex can be added to each edge of E to A vertex can be added to each edge of E to
eliminate all complex triangles. eliminate all complex triangles.
The weighted complex triangle elimination The weighted complex triangle elimination
problem has been shown to be NP problem has been shown to be NP- -complete. complete.
Some heuristics are available. Some heuristics are available.
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Hierarchical Approach
Hierarchical Approach
Widely used approach to floorplanning. Widely used approach to floorplanning.
Based on a divide Based on a divide- -and and- -conquer paradigm. conquer paradigm.
At each level of the hierarchy, only a small number of At each level of the hierarchy, only a small number of
rectangles are considered. rectangles are considered.
A small circuit C, ant all possible floorplans. A small circuit C, ant all possible floorplans.
After an optimal configuration for the three modules has After an optimal configuration for the three modules has
been determined, they are merged into a larger module. been determined, they are merged into a larger module.
The vertices The vertices a a , , b b , , c c are merged into a super vertex at are merged into a super vertex at
the next level the next level
c
c b
a
b a a
a
c b
b
c
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Contd.
Contd.
The number of floorplans increases exponentially The number of floorplans increases exponentially
with the number of modules with the number of modules d d considered at each considered at each
level. level.
d d is thus limited to a small number (typically d < is thus limited to a small number (typically d <
6). 6).
All possible floorplans for: All possible floorplans for:
d = 2
d = 3
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Hierarchical Approach :: Bottom
Hierarchical Approach :: Bottom
-
-
Up
Up
Hierarchical approach works best in bottom Hierarchical approach works best in bottom- -up up
fashion. fashion.
Modules are represented as vertices of a graph, Modules are represented as vertices of a graph,
while edges represent connectivity. while edges represent connectivity.
Modules with high connectivity are clustered Modules with high connectivity are clustered
together. together.
Number of modules in each cluster Number of modules in each cluster d. d.
An optimal floorplan for each cluster is An optimal floorplan for each cluster is
determined by exhaustive enumeration. determined by exhaustive enumeration.
The cluster is merged into a larger module for The cluster is merged into a larger module for
high high- -level processing. level processing.
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Hierarchical Approach :: Bottom
Hierarchical Approach :: Bottom
-
-
Up
Up
A Greedy Procedure A Greedy Procedure
Sort the edges in decreasing weights. Sort the edges in decreasing weights.
The heaviest edge is chosen, and the two modules of The heaviest edge is chosen, and the two modules of
the edge are clustered in a greedy fashion. the edge are clustered in a greedy fashion.
Restriction: number of modules in each cluster Restriction: number of modules in each cluster d. d.
In the next higher level, vertices in a cluster are In the next higher level, vertices in a cluster are
merged, and edge weights are summed up merged, and edge weights are summed up
accordingly. accordingly.
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Hierarchical Approach :: Bottom
Hierarchical Approach :: Bottom
-
-
Up
Up
Problem Problem
Some lightweight edges may be chosen at higher Some lightweight edges may be chosen at higher
levels in the hierarchy, resulting in adjacency of levels in the hierarchy, resulting in adjacency of
two clusters of highly incompatible areas. two clusters of highly incompatible areas.
Possible solution Possible solution
Arbitrarily assign a small cluster to a neighboring Arbitrarily assign a small cluster to a neighboring
cluster when their sizes will be too small for cluster when their sizes will be too small for
processing at a higher level of the hierarchy. processing at a higher level of the hierarchy.
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Hierarchical Approach :: Bottom
Hierarchical Approach :: Bottom
-
-
Up
Up
b b
b
a a
a
d d
d
c c
c
e
e
e
1
10
10 3
3
3
2
Greedy clustering Merging small clusters
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Estimating Cost of a Floorplan
Estimating Cost of a Floorplan
The cost of a floorplan is usually estimated from the The cost of a floorplan is usually estimated from the
connections and the area of the connections and the area of the floorplan floorplan. .
The area can be easily estimated because the The area can be easily estimated because the
dimensions of each cluster can be passed up from dimensions of each cluster can be passed up from
the bottom the bottom- -up clustering. up clustering.
The area of a particular choice can thus be The area of a particular choice can thus be
computed for each candidate computed for each candidate floorplan floorplan. .
The cost can be estimated by summing up the edge The cost can be estimated by summing up the edge
weights multiplied by the distance between the centers weights multiplied by the distance between the centers
of the clusters. of the clusters.
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Hierarchical Approach :: Top
Hierarchical Approach :: Top
-
-
Down
Down
The fundamental step is the partitioning of modules. The fundamental step is the partitioning of modules.
Each partition is assigned to a child floorplan. Each partition is assigned to a child floorplan.
Partitioning is recursively applied to the child Partitioning is recursively applied to the child
floorplans. floorplans.
Major issue here is to obtain balanced graph Major issue here is to obtain balanced graph
partitioning. partitioning.
k k- -way partitioning, in general. way partitioning, in general.
Not very widely used due to the difficulty of obtaining Not very widely used due to the difficulty of obtaining
balanced partitions. balanced partitions.
One can combine top One can combine top- -down and bottom down and bottom- -up approaches. up approaches.
Apply bottom Apply bottom- -up technique to obtain a set of clusters. up technique to obtain a set of clusters.
Apply top Apply top- -down approach to these clusters. down approach to these clusters.
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