Technology Natarajan

Microelectronics: Analysis and Design April 13, 2004 Sundaram Natarajan
730
1 A( s) F( s) 0. (10.1.1)
CHAPTER 10: STABILITY ANALYSIS OF FEEDBACK AMPLIFIERS,
FREQUENCY COMPENSATION, AND OSCILLATORS
10.0: INTRODUCTION
We discussed feedback amplifiers in Chapter 8 and the frequency responses of amplifiers in the
previous chapter. It should be clear to the reader that the forward-path gain usually depends on the operating
frequency. Even if forward-path amplifier is absolutely stable having its poles strictly in the left half of the s-
plane, an improper feedback may render the feedback amplifier unstable. Therefore, an important problem
associated with feedback amplifiers is their stability. In an amplifier, the feedback signal generally opposes the
external input. However, if the phase of the feedback signal is such that it adds to the original signal, the output
signal may become uncontrollable by the input. This results in an unstable amplifier. An unstable amplifier is
useless except as an oscillator. In this chapter, we discuss the stability of feedback amplifiers and the methods
of frequency compensation to provide adequate stability. Since an unstable amplifier can serve as an oscillator,
the closely related topic of sinusoidal oscillators is also discussed in this chapter.
10.1: STABILITY OF FEEDBACK AMPLIFIERS
The stability of a feedback amplifier depends on the location of the poles of the closed-loop gain in
the s-plane. The closed-loop gain of an ac-coupled amplifier has poles both in the low and high frequency
ranges. However, the closed-loop gain of a dc amplifier will only have high-frequency poles. The low-
frequency poles of the closed-loop gain A
c
(s) of an ac-coupled amplifier are usually in the left half s-plane.
Therefore, in most amplifier circuits, the stability problem does not usually arise due to the low frequency
poles. The stability problem is mainly due to the possibility of high frequency poles of the closed-loop gain
being in the right half s-plane. Therefore, we will concentrate only on the high frequency stability. For high
frequency stability analysis, we have to use the high frequency transfer functions of the amplifiers, and
therefore, the stability analysis is applicable to both dc and ac coupled amplifiers.
We can find the absolute stability of an amplifier in several ways. One criterion requires that the
impulse response of the closed-loop-amplifier should asymptotically go to zero as t . For impulse response
to become zero as t , the natural frequencies or the poles of the closed-loop gain must be in the left-half of
the s-plane. Therefore, a simple method is to find the poles and verify their locations in the s-plane. The poles
of A
c
(s) can be found by finding the roots of the following characteristic equation (see (8.1.6)):
731
Re[ p
i
] < 0, i
(10.1.2)
A( s)
A
m
( 1 s/
p
)
.
(10.1.3)
A
c
( s)
A( s)
1 A( s) F
A
m
( 1 A
m
F)
1
( 1 s/
pc
)
,
(10.1.4)
pc
( 1 A
m
F )
p
.
(10.1.5)
Fig. 10.1.1: Root-locus of a pole in a feedback amplifier with one pole and a constant feedback.
-
p
(F = 0) -
pc
j
For an amplifier to be stable, all the poles must have strictly negative real parts; i.e., for stability, the poles
of the closed-loop gain must satisfy that
where s = p
i
is the pole.
We consider some specific cases of feedback amplifiers that are practically important using this
approach. F is usually a real constant in amplifiers. Furthermore, the poles of A(s) are typically negative and
real. The zeros of A(s) are usually at very high frequencies, and therefore, we will assume that all of them are
at for simplicity. These assumptions are usually true in practical amplifiers and allow us to simplify the
analysis and focus on the fundamental concepts related to stability of feedback amplifiers.
An amplifier with a single Pole
Let the forward-path gain A(s) have one high frequency pole at s = -
p
and the form
If F is a constant,
where
The pole of the closed-loop gain is at s = -
pc
, which is also real and negative. The movement of the root in the
s-plane (called the root locus), as F increases from a value of 0 (F = 0 implies no feedback), is illustrated in
Fig. 10.1.1. From Fig. 10.1.1, we note that the pole remains on the negative real axis of the s-plane irrespective
732
A( s)
A
m
( 1 s/
p1
) ( 1 s/
p2
)
.
(10.1.6)
s
2
(
p1

p2
) s ( 1 A
m
F)
p1
p2
0.
(10.1.7)
s
(
p1

p2
)
2
(
p1

p2
)
2
4
( 1 A
m
F)
p1
p2
.
(10.1.8)
s
(
p1

p2
)
2
, (10.1.9)
( s j ) ( s j ) s
2
2s
2

2
s
2
2s
2
n
,
Fig. 10.1.2: Root-locus of a pole in a feedback amplifier with two poles and a constant feedback.
-
p1
-
p2
j Excessive ringing in
transient response or
peaks in frequency
response.
45
45
-(
p1
+
p2
)
2
(F = 0) (F = 0)
of the value of F. Therefore, the closed-loop amplifier is unconditionally stable.
An amplifier with two poles
An amplifiers transfer function with two high frequency poles has the form of
This characteristic equation is
Solving the above, the pole positions of the closed-loop gain are
The root-loci in this case are shown in Fig. 10.1.2. As F increases from the value of zero, the two poles move
closer to each other and then merge at the point,
where both the poles are negative real and equal. If the value of F increases any further, the poles become
complex-conjugate with negative real part. Here also, the closed-loop amplifier will be stable irrespective of
the value of F. However, the complex-conjugate nature of poles is an indication of the magnitude characteristic
becoming resonant. With complex-conjugate poles of - j the denominator becomes
where is called the undamped natural frequency. A related quantity, known as the pole-Q factor
n

2

2
733
Q
p

n
2
. (10.1.10)
A( s)
A
m
( 1 s/
p1
) ( 1 s/
p2
) ( 1 s/
p3
)
.
(10.1.11)
s
3
(
p1

p2

p3
) s
2
(
p1
p2

p2
p3

p3
p1
) s ( 1 A
m
F)
p1
p2
p3
0 .
(10.1.12)
A( s)
1000
( 1 0.1s) ( 1 0.01s) ( 1 0.001s)
.
(10.1.13)
Q
p
is defined as
To avoid the excessive ringing in the amplifier's transient response, a value of Q
p
< 0.707 is preferable. If A(s)
is a second order approximation of a higher order transfer function, there is a potential for the amplifier to
become unstable with higher values of F.
An amplifier with Three Poles
Let the forward-path gain A(s), having three high frequency poles, be described by
We can find the closed-loop poles using the characteristic equation of
No simple formulas exist to find the roots of (10.1.12). However, the loci of the poles, as F increases from the
zero value, are shown in Fig. 10.1.3. For sufficiently large values of F, two of the three poles of the closed-loop
amplifier can move into the right half s-plane, and the amplifier can become unstable. This is also the case if
A(s) has more than three poles. Therefore, we conclude that, if the number of poles exceeds two in the open-
loop gain, the closed-loop amplifier can become unstable unless the value of F is properly controlled. We know
that the midband gain of the closed-loop amplifier is A
fm
(1/F) (see (8.1.11)). Therefore, a lower limit exists
for the value of A
fm
for the circuit to be absolutely stable, when A(s) has more than two poles. Consider an
example below.
Example 10.1
The gain of an amplifier is
A( s)
90010
3
( 1 69210
9
s) ( 1 20010
12
s)
.
Exercise
E10.1. An amplifier has a gain of
What maximum constant value of F (<1) can one achieve so that the pole-Q factor of the closed-
loop poles is less than or equal to 0.5? Answers: F = 960.6 10
-6
.
734
A( j
o
) ( 1/ F) ,
(10.1.14)
A( j
o
)
1000
( 1 1.1110
3

2
o
) j
o
( 0.111 10
6

2
o
)
.
(10.1.15)
o
333.17 r / s , and A( j
o
) 8.183 .
Fig. 10.1.3: Root-locus of a pole in a feedback amplifier with three poles and a constant feedback.
-
p1
j
Excessive ringing in
transient response
or peaks in
frequency response.
45
unstable
-
p2
45
-
p3
(F = 0)
(F = 0)
(F = 0)
If this amplifier is used in a feedback amplifier with a constant feedback factor, find the frequency
o
and the
critical value of F at which two of the closed-loop poles are located on the j-axis. Ignore the loading effects.
SOLUTION
Since A(s) has three poles, the root-loci should be similar to the ones shown in Fig. 10.1.3. For some
critical value of F, a pair of poles of the closed-loop gain will be on the j-axis, say at s = j
o
. Then, (1+AF)
= 0 at these characteristic roots s = j
o
. Therefore,
and the phase of A(j
o
) should be equal to r/s. Consequently, the imaginary part of A(j
o
) should be zero.
Substituting s = j
o
,
Setting Im[A(j
o
)] to zero, There are two possible positive solutions for
o
. One of
o
( 0.111 10
6
2
o
) 0.
them,
o
= 0, corresponds to the frequency at which the phase of [A(j
o
)] = 0. The correct positive solution for
o
and the corresponding value for A(j
o
) are:
Therefore, the critical value of F is For a stable amplifier, F should be less than 1/ A( j
o
) 0.1222.
0.1222. If F 0.1222, the circuit becomes an oscillator.
735
Nyquist Criterion
Although the method of finding the characteristic roots can be used to check for stability of a feedback
amplifier, it has some practical problems. First, the poles and zeros of the forward-path gain A(s) or the loop-
gain L(s) may not be available. Sometimes, only the frequency response A(j) may be available either from
the data books (Examples: op-amps and CFAs) or measured data from the laboratory. In these cases, using the
frequency response directly is best suited to determine the stability. Even if the amplifier is stable, what is more
important is for the designer to know if the amplifier is close to break into oscillation. This is because the actual
circuit may be unstable even if the design is theoretically found to be stable. The contributing causes may be
the changes in the magnitude of the actual gain, an improper feedback factor F, or factors that are not accounted
in determining the loop-gain, L(s) = A(s)F(s), such as the stray effects and approximations used in modeling
the circuit. Therefore, the designer is not only interested in the absolute stability but also what is called the
relative stability. To assess the relative stability, we use the frequency response of the loop-gain.
We first concentrate on the determination of absolute stability using the frequency response
characteristics of the loop gain. This is carried out using the Nyquist criterion. Although this technique is
general enough, a simple form of this criterion is used here. In amplifier circuits, because of the open-loop
stability requirement, the forward-path gain A(s) has all its poles in the left half s-plane. Since the feedback
network (F-network) is usually a passive network, its poles should also be in the left half s-plane. Therefore,
L(s) has all its poles in the left half s-plane. If so, [1 + L(s)] also has its poles in the left half s-plane. The zeros
of [1 + L(s)] are the poles of the closed-loop gain. Therefore, the stability test should be concerned about the
locations of the zeros of [1 + L(s)].
To apply the Nyquist criterion, Nyquist plot is obtained by plotting Re[L(j)] v.s. Im[L(j)] as varies
from - to + . This is a polar plot and is usually obtained only for the portion as varies from 0 to . The
A( s)
90010
3
( 1 69210
9
s) ( 1 20010
12
s) ( 1 39.810
12
s)
.
Exercise
E10.2. An amplifier has a gain of
For what constant value of F will two of the closed-loop poles have (a) the same value and (b)
the magnitudes of the imaginary and real parts are equal?
Answers: (a) F = 867.6 10
-6
, (b) F = 1.593 10
-3
E10.3. In Problem E10.2, for what constant value of F will two of the closed-loop complex poles have
zero real parts? Answer: F = 23.17 10
-3
736
20 log L( j ) 20 log A( j ) 20 log F( j ) dB, (10.1.16a)
Arg L( j ) Arg A( j ) Arg F( j ) . (10.1.16b)
Arg L( j
p
) 180 ( equivalently radians) .
(10.1.17a)
Im L( j
p
) 0, Re L( j
p
) < 0
(10.1.17b)
Fig. 10.1.4: A typical polar plot of a loop-gain, L(s).
(-1,0)
p
Re[L(j)]
Im[L(j)]
=
= 0
conjugate curve
other portion, called the conjugate curve, can be obtained as the mirror image of this portion about the real axis.
A typical polar plot is shown in Fig. 10.1.4. The Nyquist criterion states that
For [1 + L(s)] not to have any zero in the right half s-plane (i.e., for the closed-loop amplifier to be
stable) if all its poles are in the left-half s-plane, the Nyquist plot of L(j) should not encircle the
critical point (-1,0).
The polar plot, shown in Fig. 10.1.4, does not encircle the critical point (-1,0). Therefore, the feedback
amplifier for which this polar plot has been obtained is a stable circuit. The polar-plot method is not convenient
in amplifier applications. Typically, the frequency responses of both A(s) and F(s) are available in terms of the
magnitude and phase plots. Then, the magnitude and phase of L(j) can quickly be obtained using
and
The above equations imply that we just need to add the magnitude in dB and phase responses of F(j) to the
magnitude and phase responses of A(j). If F is a constant, the phase of the loop-gain is the same as that of the
amplifier. If the magnitude and phase plots of L(j) are available, the Nyquist criterion can be applied by using
a simple inspection test on these plots. The inspection test depends on two important critical frequencies. We
will define these two critical frequencies first.
1. The phase-crossover frequency
p
is the frequency at which Arg[L(j)] passes through -180 ; i.e., the
phase crossover frequency must satisfy
An equivalent condition is
737
L( j
g
) 1 ( equivalently 0 dB ) .
(10.1.18)
g
<
p
.
(10.1.19)
M Arg L( j
g
) 180 .
(10.1.20)
GM 20 log L( j
p
) dB .
(10.1.21)
2. The gain-crossover frequency
g
is the frequency at which L(j) passes through unity gain (0 dB).
Thus, the gain-crossover frequency should satisfy
We can find the values of the above two critical frequencies either graphically or analytically using
the above definitions. The Nyquist criterion is easy to apply now. If L(j
p
) 1, the feedback signal aids the
original input signal, and the feedback amplifier becomes unstable. Therefore, the condition for stability is
L(j
p
) < 1 (or 20log L(j
p
) < 0). For monotonically decreasing magnitude and phase plots, as in most
amplifiers, this is equivalent to the following:
Under conditions discussed earlier, the closed-loop amplifier is stable, if the gain-crossover frequency
is less than the phase-crossover frequency.
That is, the following condition should be satisfied:
The magnitude and phase plots of the loop-gain of a stable feedback amplifier are shown in Fig. 10.1.5
in which we find that 20log L(j
p
) is less than 0, and
g
<
p
. It can be noted that this inspection test is easy,
if both magnitude and phase plots have the same scale for the -axis.
Relative Stability - Phase and Gain Margins
Granted that the designer can determine the absolute stability of an amplifier using the inspection test,
it is also of interest to find whether an amplifier has "good" relative stability. The relative stability is measured
in terms of two quantities, the phase and gain margins. For a stable amplifier, the phase of L(j
g
) should be
greater than -180 . If for some reason should this negative phase decrease to -180 at this frequency, the circuit
will break into oscillations. Therefore, the phase margin is the amount of additional phase decrease at
g
that
will make the amplifier unstable, and therefore, the phase margin is
The amplifier can also become unstable if the value of L(j) becomes unity (0 dB) at =
p
. For a
stable amplifier, 20log L(j
p
) should be less than 0 dB at =
p
. The gain margin is usually defined in dB.
It is the negative of 20log L(j
p
) in dB, and thus,
If for some reason, should 20log L(j) increase more than GM dB at =
p
, then the amplifier breaks into
oscillations.
The definitions of the phase and gain margins are illustrated in Fig. 10.1.5. For a stable amplifier, the
738
Fig. 10.1.5: Magnitude and phase responses of a loop-gain and the illustration of the definitions
of
g
,
p
, M, and GM.
-60
-40
-20
0
20
40
60
80
(log scale)
g
GM
0-dB line
20log[L(j)]
-225
-180
-135
-90
-45
(log scale)
0
-180 line
M
p
Arg[L(j)]
phase and gain margins must clearly be positive. The phase and gain margins clearly suggest how much
tolerance the designer has in terms of the phase and magnitude deterioration that can be allowed before the
amplifier becomes unstable. A phase margin of 30 to 60 combined with a gain margin of at least 10 dB is
acceptable as a measure of "good" relative stability.
If the magnitude and phase plots of the amplifiers gain A(j) are available (from the laboratory
measurements or data books), the inverse of F(j) can be plotted on the same plot to find the frequency of
intersection in the magnitude plot to identify the value of
g
. This procedure is especially useful for design
purposes, if F is a constant as in amplifiers. With a constant F, the phase of L(j) will be the same as that of
the amplifier. Therefore, the value of
p
can be found quickly. The frequency of the intersection of A(j) and
(1/F) gives the value of
g
. If F is a constant, the value of
p
should occur in the frequency range where A(j)
decreases at the rate of -40 dB/decade and, for stability, we must satisfy that
g
<
p
. Therefore, at the
frequency of intersection, the difference in the slopes of A(j) and (1/F) should not exceed 20 dB/decade.
Example 10.2
739
L( s) A F
59.52( 1 769.810
12
s) ( 1 120.2510
12
s)
( 1 793.910
9
s) ( 1 9.09210
9
s) ( 1 1.10810
9
s)
.
f
p
36.6 MHz, and f
g
10.3 MHz .
Ar g L( j
g
) 126.6 , and L( j
p
)
dB
17.2 dB.
M Arg L( j
g
) 180 53.4 and GM 17.2 dB.
Fig. 10.1.6: Magnitude and phase responses of the loop-gain in Example 10.2.
G
a
i
n

i
n

d
B
P
h
a
s
e

i
n

d
e
g
r
e
e
s
Frequency in MHz
1.0 3.0 10 30 100
20
-225
10
0
-10
-20
-180
-135
-90
-45
f
g
= 10.3 MHz
Phase response
Magnitude response
M = 53.4
f
p
= 36.6 MHz
GM =17.2 dB
0-dB line
180 line
Find the stability margins of the amplifier of Fig. 9.8.2 in Example 9.13.
SOLUTION
The amplifiers loop-gain has been reproduced below for convenience.
Expanded magnitude and phase plots of this function, near the frequency range of interest, are shown
in Fig. 10.1.6. The phase function tends toward -450 . From these plots,
Clearly, since f
p
> f
g
, the amplifier is stable. Also,
Therefore, the phase and gain margins are:
Example 10.3
In the inverting amplifier circuit of Fig. 10.1.7, R
1
= 1 k, and R
2
= 9 k. The difference mode and
common mode input impedances of the op-amp are very high and can be ignored. Also assume that output
impedance is small, and its effect can also be neglected. However, the op-amp's difference mode gain A
d
is
finite and frequency dependent and has the form
740
A
d
( s)
A
o
( 1
1
s) ( 1
2
s) ( 1
3
s)
.
L( s)
R
1
R
1
R
2
A
d
( s)
0.1A
o
( 1
1
s) ( 1
2
s) ( 1
3
s)
.
(10.1.22)
L( s)
10
5
1 a
1
s a
2
s
2
a
3
s
3
,
(10.1.23)
a
1

1

2

3
, a
2

1

2

2

3

3

1
, and a
3

1

2

3
.
Fig. 10.1.7: An op amp circuit with feedback
analyzed in Example 10.3.
+
-
+
-
+
-
V
o
A
d
R
2 R
1
V
s
Fig. 10.1.8: A modified form of the network of
Fig. 10.1.7 analyzed in Example 10.3.
+
-
+
-
V
o
A
d
R
2
R
1
V
s
R
1
I
s
=
Determine the phase and gain margins for this feedback amplifier, if
(a) A
o
= 10
6
,
1
= 10
-6
s,
2
= 10
-8
s, and
3
= 10
-9
s,
and
(b) A
o
= 10
6
,
1
= 10
-1
s,
2
= 10
-6
s, and
3
= 10
-8
s.
Find the minimum values of (R
2
/R
1
) in the circuit, which provides at least 45 phase margin in both cases.
SOLUTION
The equivalent circuit of the amplifier circuit is shown in Fig. 10.1.8, which has the shunt-shunt
structure. If we assume that R
o
= 0 and R
id
, the loop-gain can easily found to be
We used the graphical method in the previous example. Analytical methods will be used in this example. We
can express the loop-gain as
where
The values of a
1
, a
2
, and a
3
for the two cases are:
(a) a
1
= 1.011 10
-6
, a
2
= 11.01 10
-15
, and a
3
= 10 10
-24
and
(b) a
1
0.1, a
2
101 10
-9
, and a
3
= 10
-15
.
Since all the critical frequencies are poles, both magnitude and phase functions are monotonically
741
L( j )
10
5
( 1 a
2
2
) j ( a
1
a
3
2
)
.
(10.1.24)
p
a
1
/ a
3
. (10.1.25)
p
1.01110
6
1010
24
317.96 Mr / s .
10
10
( 1 a
2
x)
2
x( a
1
a
3
x)
2
1,
(10.1.26)
a
2
3
x
3
( a
2
2
2a
1
a
3
) x
2
( a
2
1
2a
2
) x 10
10
0, (10.1.27)
x
3
1.0110
18
x
2
10.00110
33
x 10010
54
0.
M 61.5 , and GM 39.1 dB.
p
0.1
10
15
10 Mr / s .
decreasing functions. For sinusoidal frequencies,
Using the definition of (10.1.17b), the value of the phase crossover frequency is
The value of
p
in case (a) is
Since L(j
g
) = 1, we have the following equation for
g
using (10.1.24):
where Rewriting the above equation in the polynomial form for x, we get x
2
g
.
neglecting 1 in comparison to 10
10
. Substituting the values for a
3
, a
2
, and a
1
for case (a), the above equation can
be simplified to
Solving the above equation, we find that the positive real value of Therefore, x
2
g
4.327510
18
.
Obviously, the inverting amplifier is unstable if the op-amp has the gain described in
g
2.08 Gr / s >
p
.
(a). Using the values of
g
and
p
, the phase and gain margins can be calculated to be
Next, if the op-amp has the gain described in (b), the value of
p
is
Substituting the appropriate values of a
3
, a
2
, and a
1
in (10.1.27) and solving for the value of
g
,
All the calculations can be carried out in a hand-held calculator, and it is less time-
g
786.3 kr / s <
p
.
consuming than the graphical method. Using the new values of
g
and
p
, the values of the phase and gain
742
M 51.3 , and GM 40.1 dB.
L( s)
k 10
6
1 a
1
s a
2
s
2
a
3
s
3
,
Arg L( j
g
) tan
1

g
( a
1
a
3

2
g
)
( 1 a
2

2
g
)
135 .
3
g
1.10110
9

2
g
101.110
15
g
10010
21
0.
10
12
k
2
( 1 a
2
2
g
)
2

2
g
( a
1
a
3
2
g
)
2
1.
( R
2
/ R
1
) ( 1 / k) 1 8764.
( R
2
/ R
1
) 6.281.
margins can be found to be
If we use the op-amp described in (b), the inverting amplifier is stable with sufficient phase and gain margins.
We can also find the value of k = [R
1
/(R
1
+ R
2
)] to provide a phase margin of 45 using the analytical
methods. For any general value of k = [R
1
/(R
1
+ R
2
)], (10.1.23) becomes
For a phase margin of 45 ,
g
must satisfy
Substituting the values of a
1
, a
2
, and a
3
for case (a) in the above equation, the above equation can be converted
to
Solving the above equation, we find that
g
= 86.14 Mr/s. At this frequency, the loop gain must be equal to
unity. Therefore,
Using
g
= 86.14 Mr/s in the above equation, the value of k can be computed to be 1.14110
-6
. Therefore,
Going through the same process in case (b), the required value of k is found to be 0.1373 for a 45 phase
margin. Therefore,
Often, the analytical methods are faster and accurate.
In the previous example, the reader should note that the op-amp's gain has many poles with magnitudes
less than the value of frequency at which its gain drops to 0 dB in case (a). Therefore, the phase function
decreases more rapidly than magnitude function. This requires the value of (R
2
/R
1
) to be very large. To put it
in another way, the minimum closed-loop dc gain is restricted to an approximate value of 8,764 (Note that
in this circuit). To get a closed-loop voltage gain lower than this value, the stability would V
o
/ V
s
( R
2
/ R
1
)
743
be a problem. This type of op-amp cannot be used to realize a closed-loop gain of say, 10 or even 1000 for
example. Then, since (R
2
/R
1
) is decided by the desired value of the closed-loop gain, the natural method of
achieving stability for lower gain values is to shape the frequency response of the amplifier. This process,
called the frequency compensation, is our next topic.
10.2: FREQUENCY COMPENSATION
The frequency compensation techniques are used to shape the frequency response of amplifiers so that
the feedback amplifier is not only stable but also has sufficient phase and gain margins. This topic is important
particularly in applications that use IC amplifiers. Many general purpose op-amps, such as A741, are
internally frequency compensated. These types of op-amps can be used in a variety of applications. Some op-
amps are uncompensated and are to be externally compensated. The compensation can be tailored to a given
application in these types. In uncompensated op-amps, the manufacturer's data books suggest the pins to which
these external elements should be connected. They also suggest the values of these components for a given
application. Therefore, only general concepts of frequency compensation will be discussed in this section. In
amplifiers, the feedback factor F is a constant, and this is assumed throughout this section. We also assume that
A(s) represents a dc amplifier, such as an op-amp, during this discussion.
Dominant-Pole Compensation
If the forward path gain has more than two pole frequencies whose magnitudes are less than
g
for a
given F, it is likely that the closed-loop amplifier may become unstable. If an additional pole is introduced in
the amplifier transfer function so that the modified magnitude characteristic intersects 20log(1/F) line with a
slope difference of -20 dB/decade, the instability will not occur. This method of compensation is called the
R
x
50 , Z
t
( s)
90010
3
( 1 69210
9
s) ( 1 20010
12
s)
,
R
F
530 , R
Q
10 k, and C 10 pF.
Fig. E10.4.
+
-
+V
i
+V
o
R
Q
R
F
CFA
C
Exercise
E10.4. A practical differentiator using a CFA is shown in Fig.
E10.4. The CFA has
and R
o
= 15 . The circuit parameters are
Determine the stability margins. What is the unity-gain crossover frequency of the closed-loop
gain? Answers:
g
1.6809 Gr / s,
p
3.3172 Gr / s, M 34.07 , and GM 10.18 dB.
744
A( s)
A
o
( 1 s/
p1
) ( 1 s/
p2
) ( 1 s/
p3
)
.
(10.2.1)
A
com
( s)
A
o
( 1 s/
dp
) ( 1 s/
p1
) ( 1 s/
p2
) ( 1 s/
p3
)
.
(10.2.2)
L( s) F A
com
( s)
FA
o
( 1 s/
dp
) ( 1 s/
p1
) ( 1 s/
p2
) ( 1 s/
p3
)
.
(10.2.3)
dp

p1
,
p2
,
p3
.
Arg L(j ) 90 tan
1
( /
p1
) .
(10.2.4a)
L(j )
2
( A
o
F)
2
( /
dp
)
2
1 ( /
p1
)
2
,
(10.2.4b)
dp

p1
cos( M)
A
o
F sin
2
( M)
.
(10.2.5)
dp
2
p1
3A
o
F
.
(10.2.6)
dominant-pole compensation. Assume, for the purpose of discussion, that
where
p1
<
p2
<
p3
. Let us first analytically examine how the dominant-pole compensation improves the
phase and gain margins. By adding another pole frequency to the above transfer function at s = -
dp
, the
compensated amplifier gain can be described as follows:
If F is constant, the loop gain is
In dominant-pole compensation, it will shortly be shown that
Typically (A
o
F) 1, and therefore, the unity-gain crossover frequency
g

dp
. Furthermore, the values of
p2
and
p3
are typically much higher than the value of
p1
. Therefore, for
dp

p1
, the phase and magnitude
functions of L(j) can be approximated as follows:
and
If a phase margin of M is required,
g
must be equal to [
p1
cot(M)]. Using the fact that L(j
g
) = 1, we find
that
For example, to have a phase margin of M = 60 , the newly created pole should then be located at
Since (A
o
F) 1 typically,
dp

p1
, which confirms the earlier assumption.
With general purpose op-amps, F may be as high as unity in feedback amplifiers. With a constant
feedback, F = 1 is the worst possible value. Such feedback arises in the op-amp circuit with a closed-loop gain
of unity. This amplifier is widely used as a buffer (see Fig. P1.43). Therefore, it is an important case. If a
745
Fig. 10.2.1: Typical magnitude responses of uncompensated and compensated op amps.
Frequency in Hz (log scale)
G
a
i
n

i
n

d
B
-40
-20
0
20
40
60
80
100
120
10
0
10
1
10
2
10
3
10
4
Uncompensated
Compensated
slope = -20 dB/decade
slope = -20 dB/decade
slope =
-40 dB/decade
10
5
10
6
10
7
10
8
unity-gain amplifier is realized employing an op-amp that has A
o
= 10
5
and
p1
= 6 Mr/s, the dominant pole
must be at s = -
dp
= -84.85 r/s for a 45 phase margin. The typical magnitude characteristics of both
uncompensated and compensated amplifiers are shown in Fig. 10.2.1. A general purpose op-amp with internal
frequency compensation will have its magnitude characteristic similar to that of the compensated op-amp
because a general purpose op-amp should be useful in almost all applications including the buffer.
Since the frequency response of a compensated op-amp is dominated by the newly introduced pole
frequency, s = -
dp
, in the useful frequency range (up to
g
with F = 1), this type of compensation is called the
dominant-pole compensation. This compensation is also known as lag-compensation. There is narrow-banding
(intentional narrow-banding) because the bandwidth of the amplifier is reduced considerably by introducing
the dominant pole, and it is a major disadvantage of the dominant-pole compensation.
dp
is generally very low,
and the typical frequency range of applications is such that >
dp
. In the frequency range >
dp
, the
amplifier gain decreases, and therefore, the narrow-banding reduces the available amount of feedback at high
frequencies. Since all the benefits of feedback depend on the large amount of the loop-gain, the performance
of the closed-loop amplifier with dominant-pole compensation will not be as good as we expect it to be at high
frequencies.
Implementation of the Dominant pole Compensation
IC amplifiers use a CE- (CS-) amplifier as an intermediate stage to achieve the high gain. To add a
746
A( s)
A
o
( 1 s/
p1
) ( 1 s/
p2
)
,
(10.2.7)
Fig. 10.2.2: The possible methods of implementing a dominant-pole compensation.
(b)
I
s
R
i
Q
C
c
R
c
(a)
I
s
R
i
Q
C
c
R
c
dominant pole to the amplifier transfer function, a suitable capacitor may be added either at its input or between
its base-collector junction as shown in Fig. 10.2.2. In Fig. 10.2.2(a), the additional pole will be caused by the
(R
i
C) time-constant, where R
i
is the input resistance. In Fig. 10.2.2(b), the "Miller effect" is used to generate
large input capacitance, and this capacitance associated with the input resistance R
i
produces the additional
pole. Generally, for a given value of
dp
, the second method requires a far lower capacitance value for C
c
than
what is required in Fig. 10.2.2(a). Thus, the "real estate" for integrating the compensating capacitor will be
much lower in the second case than in the first.
The methods shown in Fig. 10.2.2 are the general techniques. If we add these compensating capacitors,
we are changing the circuit configuration, and the poles also move from their positions. Therefore, the
determination of these capacitance values for a given phase margin requires some analysis. Consider an
example below.
Example 10.4 (Design)
In the small-signal equivalent circuit of an uncompensated op-amp of Fig. 10.2.3, R
id
= 3 M, R
1
=
500 k, R
2
= 10 k, R
o
= 100 , g
m1
= 0.5 mS, g
m2
= 4 mS, C
1
= 10 pF, and C
2
= 130 pF. A dominant-pole
compensation is to be provided by connecting an additional compensating capacitor (a) across the resistor R
1
,
and (b) between the nodes "a" and "b." The phase margin should be 60 after compensation with F = 1. Find
the required value of the capacitance in each case.
SOLUTION
Let us first find the dc gain and the pole positions for the uncompensated circuit. The transfer function
of the amplifier can be found to be
747
A
o
g
m1
g
m2
R
1
R
2
10
4
,
p1
1/ ( R
1
C
1
) 200 kr / s , and
p2
1/ ( R
2
C
2
) 769.2 kr / s .
(10.2.8)
dp
2
p2
3 A
o
F
51.28 r / s .
1
R
1
( C
1
C
c
)
51.28 r / s .
A
com
( s)
A
o
( 1 C
c
s/ g
m2
)
1 a
1
s a
2
s
2
,
(10.2.9)
Fig. 10.2.3: A macro-model equivalent circuit of an op amp described in Example 10.4.
R
id
V
d
+
-
R
1
C
1
g
m1
V
d
V
1
+
-
R
2
C
2
g
m2
V
1
+
-
V
2
R
o
V
2
+
-
V
o
+
-
a b
Fig. 10.2.4: The equivalent circuit of the op amp with frequency compensation.
R
id
V
d
+
-
R
1
C
1
g
m1
V
d
V
1
+
-
R
2
C
2
g
m2
V
1
+
-
V
2
R
o
V
2
+
-
V
o
+
-
a
b
C
c
where
All zeros are at . By connecting a capacitor across the resistor R
1
, no new pole is created; however the value
of
p1
will decrease to, say
dp
. The value of
p2
will not be affected. To achieve the compensation with a phase
margin of 60 and F = 1, the critical frequencies
dp
and
p2
should satisfy (10.2.5). Thus, in terms of the new
notations,
Since
dp
1/ [ R
1
( C
1
C
c
) ],
From the above equation, we find that To realize this capacitance value in integrated circuits, C
c
38.99 nF.
a large "real estate" is required, and this method is not suitable in ICs.
Consider the next case where the compensating capacitor is connected between the nodes "a" and "b"
as shown in Fig. 10.2.4. Here also, no new pole is created. However, the pole positions of both poles will be
different from
p1
and
p2
. The new transfer function including the effect of C
c
is (see (9.4.6) and (9.4.7))
748
A
o
g
m1
g
m2
R
1
R
2
, a
1
R
1
C
1
C
c
( 1 g
m2
R
2
) R
2
( C
2
C
c
) ,
(10.2.10)
a
2
R
1
R
2
C
c
( C
1
C
2
) C
1
C
2
.
(10.2.11)
p1n
( 1 / a
1
) , and
p2n
( a
1
/ a
2
) .
(10.2.12)
p1n
( 2
p2n
/ 3A
o
) .
(10.2.13)
3A
o
a
2
2a
2
1
0 . (10.2.14)
C
2
c
24.35C
c
231.7 0, (10.2.15)
A
com
( s)
10
4
( 1 7.91510
9
s)
1 655.6410
6
s 28.66210
12
s
2
.
s
p1n
1.57 kr / s, s
p2n
22.87 Mr / s, and s
z
126.34 Mr / s.
where
and
Typically, the value of C
c
is very small. Therefore, the zero at s = (g
m2
/C
c
) is at a very high frequency, and its
effect may be ignored. Furthermore, to have a dominant pole, (a
1
/2)
2
should be much greater than a
2
. Let the
new critical frequencies be
p1n
and
p2n
. Then, the approximate values of the new critical frequencies are:
For a phase margin of 60 with F = 1,
p1n
(
p1n
becomes the dominant pole) and
p2n
must satisfy
Using (10.2.12) in (10.2.13),
Using (10.2.10) and (10.2.11) in (10.2.14), and substituting all the known values of the parameters, the
following quadratic equation can be obtained for C
c
:
where C
c
is in pF. Solving for the positive value of C
c
, Clearly, the small-valued C
c
is C
c
31.66 pF.
amenable for integration.
Let us calculate the values of the new critical frequencies after adding the capacitance C
c
to verify the
design. Using the calculated value of C
c
and other parameters in (10.2.9)-(10.2.11), we find that
The poles and zeros of the compensated amplifier are
Clearly, with this type of compensation,
p1n
<
p1
and
p2n
>
p2
. This is the pole-splitting (Section 9.8).
Because the second pole moves up, for a given dc gain, the first pole position is also high in comparison to
what was in case (a) of this example. The compensation scheme in (b) provides more bandwidth than the
compensation scheme of (a).
Since F = 1, the loop gain is the same as the amplifier gain. Setting the magnitude function to unity,
we find that At this frequency, the phase of the above transfer function is -126.1 .
g
13.27 Mr / s .
Therefore, This phase margin, although not the required value, is adequate. The error is caused M 53.9 .
749
Fig. 10.2.5: The phase margin and the bandwidth as a function of the compensating capacitance
value in Example 10.4.
P
h
a
s
e

M
a
r
g
i
n

i
n

d
e
g
r
e
e
s
C
c
in pF
U
n
i
t
y
-
G
a
i
n

C
r
o
s
s
o
v
e
r
F
r
e
q
u
e
n
c
y

i
n

M
H
z
30
52
32 34 36 38 40 42 44 46 48 50
56
60
64
(31.66p,53.889)
(42.16p,60.00)
1.0
1.5
2.0
2.5
(31.66p,2.112M)
(42.16p,1.685M)
Phase Margin
Unity-Gain
Crossover
Frequency
by the additional lagging phase introduced by the RHP zero.
One needs to increase the capacitance value of the compensating capacitor to increase the phase margin
to 60 . Since we have the approximate capacitance value, we can use the parametric-variation and
performance-evaluation features of PSPICE to estimate both the phase margin and the unity-gain cross-over
frequency as a function of C
c
. The plot of both these quantities is shown in Fig. 10.2.5. From this plot, we find
that it is required to have to achieve the required phase margin. Observe that when the value of C
c
42 pF
C
c
is changed to the new value from the earlier one of 31.66 pF, f
g
falls from 2.112 MHz to 1.685 MHz, a
reduction of 20.2%.
In typical linear applications, the feedback is negative. The frequency response properties of these
circuits depend on the GB-product of the op-amp (see (8.1.18)), and therefore, the GB-product of an op-amp
is an important quantity in most applications. The GB-product of the compensated op-amp is (A
o
dp
), which
is about the same as the unity-gain crossover frequency
g
. Of the two types of compensation techniques, the
second one is preferred because it provides a dominant-pole compensation with a wider bandwidth, a larger
GB-product, and smaller value for C
c
. It is instructive to note that there is a drop of 20% in the value of unity-
gain crossover frequency while the improvement in the phase margin is only about 6 .
Frequency Compensation of IC op-amps
In a general purpose IC op-amp, the dominant-pole compensation is used. We have already seen how
this is accomplished. Now, we specifically concentrate on the compensation of the most popular 741-type op-
750
R
i d
3.14 M, g
m1
145 S, R
1
3.277 M, g
m2
6.74 mS, R
2
80.34 k, and R
o
87.2 .
C
1
1
2f
p1
R
1
1
218.910
3
3.27710
6
2.57 pF,
C
2
1
2f
p2
R
2
1
232810
3
80.3410
3
6.04 pF.
dp

g
A
o
210
6
228.810
3
27.46 r / s.
a
1
R
1
[ C
1
C
c
( 1 g
m2
R
2
) ] R
2
( C
2
C
c
)
1
27.46
.
amp. If the small reverse transmissions are ignored, the small-signal equivalent circuit of this op-amp has the
same small-signal equivalent circuit shown in Fig. 10.2.4. With a supply voltage of to the op-amp, the 15 V
dc parameters were calculated in Section 7.3 and are given in Fig. 7.3.8. These dc parameters are:
The first two dominant poles are caused by C
1
and C
2
in combination with R
1
and R
2
respectively. PSPICE
analysis shows that, before compensation (i.e., without the compensation capacitor C
c
), the corresponding
critical frequencies are and 328 kHz respectively. Therefore, the capacitance values are: 18.9 kHz
and
After connecting C
c
, the poles move because of the pole-splitting creating a dominant pole. The resulting
transfer function will have the same form of (10.2.9). In a 741-type op-amp, a phase margin close to 90 is
achieved with F = 1. If so, using (10.2.5), we find that the new second pole must be at a very high frequency.
Assuming that the second pole is at and using (10.2.4b),
g
A
o
dp
, where s = -
dp
is the new dominant pole
after compensation. Also note that
dp
is the bandwidth of the compensated amplifier. Therefore, the unity-gain
crossover frequency must be equal to the GB-product of the amplifier. We calculated the dc gain to be A
o
=
228.8 kV/V ((see (7.3.18)). In the 741-type op-amp, the nominal value of f
g
is 1 MHz. Using the calculated
value of A
o
, the bandwidth
Since s = -
dp
is the dominant pole, using (10.2.12) and (10.2.10),
C
c
is the only unknown value in the above equation. Calculating this value, we find that C
c
20.5 pF. However,
a nominal value of is used in the circuit. Although the phase margin should be approximately C
c
30 pF
90 with F = 1, the positive real zero reduces the phase margin to about 80 . Even such a reduced phase margin
is substantially high.
The reduced phase margin in Example 10.4 (as well as in the op-amp 741) is due to the additional
751
A
com
( s)
A
o
1 a
1
s a
2
s
2
,
(10.2.16)
A
o
g
m1
g
m2
R
1
R
2
, a
1
R
1
C
1
C
c
( 1 g
m2
R
2
) R
2
C
2
, and a
2
R
1
R
2
C
2
( C
1
C
c
) .
(10.2.17)
Fig. 10.2.6: The dominant-pole frequency compensation with the elimination of the RHP zero.
R
id
V
d
+
-
R
1
C
1
g
m1
V
d
V
1
+
-
R
2
C
2
g
m2
V
1
+
-
V
2
R
o
V
2
+
-
V
o
+
-
a
b
C
c
1
lagging phase caused by the positive real zero in the transfer function. The phase margin can be increased by
increasing the value of C
c
. This, in turn, reduces the unity-gain crossover frequency of the amplifier, the
bandwidth, and the GB-product (see Fig. 10.2.5). If this positive real zero was not present, the amplifier would
have higher bandwidth and hence higher value of GB-product without sacrificing the phase margin. One
method of achieving this is to place a unity-gain buffer in the feedback path of the compensation capacitor as
shown in Fig. 10.2.6.
If the output resistance of the buffer is zero, transfer function of the circuit of Fig. 10.2.6 is
where
Although the positive real zero has been eliminated, since (10.2.5) and (10.2.12) are applicable in this case also,
the unity-gain crossover frequency
g
will increase slightly. Besides, the above analysis neglects the output
resistance of the buffer. A nonzero output resistance R
o
of the buffer causes another pole and a zero, which are
both negative and real. This left-half plane high frequency pole tends to decrease the phase margin.
Compensation using a nulling resistor (Lead-Lag Compensation)
Another method of increasing the phase margin and the unity-gain crossover frequency is to use a
nulling resistor in series with C
c
as shown in Fig. 10.2.7. In this arrangement, one can move the zero from
positive real axis to the negative real axis thus enhancing the phase margin and increasing the unity-gain
crossover frequency.
752
A
com
( s)
A
o
[ 1 C
c
s( R
z
1/ g
m2
) ]
1 a
1
s a
2
s
2
a
3
s
3
,
(10.2.18)
A
o
g
m1
g
m2
R
1
R
2
, a
1
[ R
1
( 1 g
m2
R
2
) R
2
] C
c
( R
2
C
2
R
1
C
1
) R
z
C
c
,
a
2
R
1
R
2
C
c
( C
1
C
2
) C
1
C
2
R
z
C
c
( R
1
C
1
R
2
C
2
) , and a
3
R
1
R
2
R
z
C
1
C
2
C
c
.
(10.2.19)
A
com
( s)
A
o
( 1 s/
z1
)
( 1 s/
p1
) ( 1 s/
p2
) ( 1 s/
p3
)
.
(10.2.20)
p1
1
[ R
1
( 1 g
m2
R
2
) R
2
] C
c
,
p2
g
m2
C
c
C
1
C
2
( C
1
C
2
) C
c
,
p3
C
1
C
2
( C
1
C
2
) C
c
R
z
C
1
C
2
C
c
.
(10.2.21)
s
z1
1
C
c
( R
z
1/ g
m2
)
(10.2.22)
Fig. 10.2.7: The frequency compensation with a nulling resistor to control the RHP zero.
R
id
V
d
+
-
R
1
C
1
g
m1
V
d
V
1
+
-
R
2
C
2
g
m2
V
1
+
-
V
2
R
o
V
2
+
-
V
o
+
-
a
b
C
c R
z
The transfer function of the compensated amplifier of Fig. 10.2.7 is
where
Since the transfer function has three poles and a zero, it can be expressed as
Since there is a dominant pole, without loss of generality, let
p1

p2

p3
. These assumptions mean that the
poles are widely separated. Then, the approximate values of
p1
,
p2
, and
p3
are
The zero is at
Choosing a value for R
z
> (1/g
m2
), the zero can be made negative and real. Furthermore, R
z
can be
chosen so that this negative real zero cancels one of the poles, specifically, the pole located at s = -
p2
. Doing
so, the unity-gain crossover frequency can be made much higher than that can be achieved in the previous two
cases for a given phase margin. Equivalently, if the compensating capacitor C
c
is chosen to provide a specific
GB-product, the phase margin can be increased with such an appropriate choice for R
z
. Thus, equating the
approximating value of
p2
to
z1
and solving for R
z
,
753
R
z
1
g
m2
1
C
1
C
c
C
2
C
c
C
1
C
2
C
2
c
.
(10.2.23)
p1

p3
cos( M)
A
o
F sin
2
( M)
,
(10.2.24)
p3
g
m2
[ C
1
C
2
( C
1
C
2
) C
c
] C
c
C
1
C
2
( C
1
C
c
) ( C
2
C
c
)
.
(10.2.25)
1
[ R
1
( 1 g
m2
R
2
) R
2
] C
c
2
3
[ C
1
C
2
( C
1
C
2
) C
c
] C
c
g
m1
R
1
R
2
C
1
C
2
( C
1
C
c
) ( C
2
C
c
)
C
3
c
0.7592 C
2
c
1.649 C
c
1.5 0,
If the pole located at s = -
p2
cancels out, then to meet a specific phase margin,
p1
and
p3
must satisfy the
following equation for a specific phase margin:
where
p1
is the dominant pole. Consider a numerical example.
The small-signal equivalent circuit of an uncompensated MOSFET op-amp has the form shown in Fig.
10.2.6 in which R
id
, R
1
= 740 k, R
2
= 117 k, g
m1
= 0.1 mS, g
m2
= 0.9 mS, C
1
= 1 pF, and C
2
= 10 pF.
A dominant-pole compensation is to be provided by connecting a series combination of a resistor R
z
and a
capacitor C
c
. It is required to have a phase margin of 60 after compensation with F = 1. Find the required
values of C
c
and R
z
. Find the GB-product, unity-gain crossover frequency, and the expected phase margin of
the amplifier.
SOLUTION
Using (10.2.23) in (10.2.21),
Substituting the above
p3
and
p1
from (10.2.21) and using A
o
= (g
m1
g
m2
R
1
R
2
), F = 1, and M = 60 in
(10.2.24),
All the values except that of C
c
are known. Therefore, substituting all the known values and rearranging the
equation, we get the following equation for C
c
:
where C
c
is in pF. Solving the above equation, the positive real value of C
c
is 1.32 pF. Therefore, we select C
c
1.5 pF.
Using this value of C
c
and other known element values in (10.2.23), R
z
14.2 k.
The gain-bandwidth product is
754
GB A
o

p1
g
m1
g
m2
R
1
R
2
[ R
1
( 1 g
m2
R
2
) R
2
] C
c
65.94 Mr / s ( 10.5 MHz) .
A
com
( s)
7792.2 ( 1 19.6310
9
s)
1 120.110
6
s 2.33510
12
s
2
18.4410
21
s
3
.
z1
50.93 Mr / s,
p1
8.323 kr / s, and
p2
,
p3
63.31 j 50.04 Mr / s.
GB A
o

p1
64.85 Mr / s ( 10.32 MHz) .
A
com
( s)
64.8810
6
( 1 19.6310
9
s)
s ( 1 19.4410
9
s 153.5410
18
s
2
)
.
Fig. 10.2.8: The frequency responses of the compensated MOSFET op amp in Example 10.5.
G
a
i
n

i
n

d
B
P
h
a
s
e

i
n

d
e
g
r
e
e
s
Frequency in Hz
100 1.0K 10K 100K 1.0M 10M 100M
-20
0
20
40
60
80
-225
-180
-135
-90
-45
0
12.437 M, -120.74
0 dB, -180 lines
Magnitude
Phase
f
g
= 12.437 M
Straightforward substitution of the element values in (10.2.18) and (10.2.19) provides
Factoring the denominator and numerator polynomials, we can find the locations of the poles and zero. We
identify that
The zero does not cancel out with the high frequency pole. Two of the high frequency poles are complex-
conjugate. However, the LHP zero provides a phase lead to the gain in the high frequency range. Although the
values of
z1
and
p2
are not exactly equal, this difference does not make any discernable difference in both
magnitude and phase responses. The gain-bandwidth product is
The gain and phase crossover frequencies are high and can be found using the following approximate transfer
function, which is obtained by neglecting the constant term of 1 in the denominator:
The maximum lagging phase is -180 , and therefore, the phase crossover frequency is . Substituting s = j
g
and setting the magnitude function equal to unity, we get the following equation for
g
:
755
6
g
3.00810
15

4
g
2.63910
31

2
g
1.78610
47
0.
Arg [ A
com
( j
g
) ] 120.7 , and M 59.3 .
Fig. 10.2.9: A CMOS operational amplifier using a nulling resistor compensation.
+
-
v
GS1
+
-
v
GS2
+V
DD
M
1
M
2
+v
2
M
3
M
4
+v
1
M
5
M
6
R
BIAS
I
BIAS
2
I
BIAS
-V
SS
-V
SS
+V
S
i
L
i
D12
R
L
+v
O
M
11
M
12
M
10
M
9
i
D11
+
-
V
GG
M
8
M
7
I
REF
M
13
C
c
I
BIAS
2
The positive real solution for is 6.105 10
15
. Therefore,
g
= 78.13 Mr/s ( = 12.43 MHz). Evaluating
2
g
f
g
the phase at this frequency,
Clearly, the phase margin is very close to the desired value. Both magnitude and phase functions are shown
in Fig. 10.2.8.
A
com
10
4
( 1 44.8810
9
s)
( 1 683.18310
6
s 29.934710
12
s
2
345.34510
21
s
3
)
.
Poles: s 1463.83, s 43.339510
6
j 9.9909310
6
, and Zero s 22.281610
6
.
Exercise
E10.5. In Example 10.4, we considered the design of frequency compensation of an op-amp using the
circuit of Fig. 10.2.4. We needed C
c
= 31.66 pF. Instead, assume that a series connection of a
capacitance C
c
= 33 pF and a resistance of R
z
= 1.61 k replaces C
c
. Find the new overall gain of
the op-amp with compensation. How many poles and zeros are there in the new transfer function?
Is there any pole-zero cancellation? If the op-amp is used with F = 1, what is the phase margin?
Answers:
There is no pole-zero cancellation. M = 86.76
756
v
o
( t ) V
S
1 e
t /
,
(10.2.26)
i
C
C
c
dv
O
( t )
dt
i
O
. (10.2.27)
The practical method of implementing the compensation scheme using the nulling resistor in a
MOSFET operational amplifier is shown in Fig. 10.2.9. The MOSFET M
13
realizes the resistor R
z
. Observe that
the dc bias current is zero, and its transconductance under pinch-off mode realizes this resistance.
Large-signal Response of Compensated IC Op-amps and Slew-rate
The small-signal response of a frequency compensated op-amp can be obtained using the models of
Figs. 10.2.3 and 10.2.7. However, the behavior of the op-amp circuits with large input signals, such as a step
input, is significantly different from those based on the small-signal models. This behavior is also of
considerable interest to a designer. We postponed the study of this behavior until this point because it depends
on the frequency compensation discussed earlier. Therefore, before concluding this section, the large-signal
behavior of IC op-amps is addressed.
A simple method of studying the large-signal behavior of an op-amp is to apply a step input to a unity-
gain buffer shown in Fig. 10.2.10. Using the linear model of Fig. 10.2.4 for a compensated op-amp, using a
dominant-pole approximation, it can be shown that
where V
S
is the amplitude of the step input and = (1/B) is the op-amp's time constant. The expected response
with a 5-V step input is shown in Fig. 10.2.11 for the 741-type op-amp, (dotted line) marked with "linear
model." However, the actual response, also shown in Fig. 10.2.11, is completely different. The actual response
increases linearly and slowly with a slope of 0.5 V/s before reaching the steady-state. This phenomenon is
known as the slew for large signals. The rate of change of the output voltage, [dv
o
(t)/dt] in the region of the
constant slope, is called the slew-rate (SR), which is usually expressed in V/s.
The discrepancy between the actual and observed responses for large signals is due to the compensation
capacitor in the op-amps. To understand this phenomenon, consider the simplified schematic of a frequency
compensated IC op-amp shown in Fig. 10.2.12. A
2
is the second stage, which is typically a cascade connection
of an emitter-follower and a high-gain CE- amplifier. Therefore, the input impedance is high, and A
2
is also
high. For an approximate analysis, assume that the inverting input terminal of this amplifier is at virtual ground,
and the input current is zero. If so,
Consider the situation of the unity-gain buffer of Fig. 10.2.10. The output of the buffer should be at
zero for t < 0. Therefore, the inverting input terminal must also be at zero for t < 0. If a sudden large signal
757
SR
dv
O
( t )
dt
I
BIAS
C
c
.
(10.2.28)
Fig. 10.2.10: A unity-gain Amplifier
using an op-amp.
+
-
+V
s
-V
s
+
-
v
I
+
-
v
O
Fig. 10.2.11: The step responses of the unity-gain amplifier of
Fig. 10.2.10 with 741-type op-amp.
Time
O
u
t
p
u
t

v
o
l
t
a
g
e
0 4 s
0
2.0V
4.0V
6.0V
Actual response
Linear model
8 s 12 s 16 s 20 s
Fig. 10.2.12: A simplified schematic of an IC op-amp with frequency compensation.
Q
3
Q
4
-
+
v
D
I
BIAS
-V
s
Q
1
Q
2
i
C1
i
C2
i
C1
i
O
+
-
i
C
C
c
1 A
2
+v
O
+v
O
+V
CC
input is applied at the noninverting input, this appears directly between the input terminals. Recall from Chapter
5, if the differential mode input exceeds about 100 mV, the input stage enters the saturation mode. Specifically,
Q
1
will be cutoff, and Q
2
carries the entire bias current I
B
. The output current i
O
becomes a constant equal to
bias current (-I
BIAS
). A strict analysis requires nonlinear circuit analysis. However, assume that i
O
remains a
constant for t > 0 to simplify the analysis. Using this value of i
O
in (10.2.27),
758
SR (I
BIAS
/ C
c
) 0.503 V/ s .
dv
O
( t )
dt
max
V
m
. (10.2.29)
max
SR
V
m
.
(10.2.30)
Since both I
BIAS
and C
c
are constants, the output voltage cannot change at a rate more than the right side of the
equation, and hence the slew-rate is limited by the compensation capacitance. Clearly, a larger compensating
capacitance value implies lower slew-rate. In the 741-type op-amp shown in Fig. 7.2.1, the value of I
BIAS
is the
sum of the collector currents of Q
4
and Q
6
, which is 15.1 A (Section 7.3). Using this current and C
c
= 30 pF,
and the the slew-rate is
The manufacturers' suggested minimum value for the slew-rate of the 741-type op-amp is 0.5 V/s. This
general purpose op-amp has slow speed. However, high speed op-amps with slew-rates ranging from a few tens
of V/s to a few thousands of V/s are currently available in the market. Generally, CFAs have high slew rates.
However, voltage-mode operational amplifiers are also available with high slew rates. AD9631, from Analog
Devices Inc. for example, has a slew-rate of 1300 V/s along with a unity-gain crossover frequency of 320
MHz.
So far, we considered the effect of slew-rate using the step input. Another important signal is a
sinusoid. We now examine the behavior of the op-amp for large sinusoidal input signals. Let v
O
(t) = V
m
sin(t),
where V
m
is the amplitude of a sinusoid. Then, the maximum rate of change of the output should be
For an undistorted output, this maximum rate of change should be less than the value of the slew-rate. Thus,
for a given amplitude of the sinusoidal output, the maximum frequency of operation is limited by
This maximum frequency is called the full-power bandwidth. For example, if the output sinusoid has an
amplitude of 10 V in a 741-type op-amp, the full-power bandwidth is only 7.96 kHz. However, up to 10 kHz,
no distortion occurs even if the output signal swing is 14 V with a 15 V power supply. This is a nonlinear
phenomenon. Only beyond 10 kHz, the above relationship holds. A typical plot of amplitude v.s. frequency
is shown in Fig. 10.2.13 for the 741-type op-amp from Texas Instruments Inc.
In linear as well as nonlinear applications of op-amps, the designer should be aware of the slew-rate
limitations. For improper output amplitudes, the slew-induced phase lag may cause the stability problem also.
Since the slew-rate is an inherent problem of the op-amp, nothing can solve this problem except that it should
be avoided. Therefore, we usually assume that the rate of change of the output voltage is within the slew rate
and ignore this limitation during the design phase. However, the limitation imposed by the slew rate can be
759
X
o
X
i
A( s)
1 A( s) F( s)
.
(10.3.1)
L( j
o
) A( j
o
) F( j
o
) 1.
(10.3.2)
10 k
1 k 100 k 1 M
2
4
6
8
10
12
14
16
18
20
0
V
O
M

-

M
a
x
i
m
u
m

P
e
a
k

o
u
t
p
u
t
v
o
l
t
a
g
e

-

V
V
CC
= 15 V, V
CC
= -15 V
R
L
= 10 K, = 25C
+ -
f - Frequency Hz
Fig. 10.2.13: Frequency v. s. maximum output voltage in a 741-type op-amp. (Source: Texas
Intruments - Linear Data book.)
verified in the PSPICE simulation of the designed circuit. If this causes a problem, the designer should select
an op-amp with a higher slew-rate or limit the input amplitudes.
10.3: Principle of Sinusoidal Oscillators and Barkhausen criterion
If the closed-loop gain of an amplifier has a pair of poles on the j-axis for some feedback factor the
circuit becomes a sinusoidal oscillator (see the equation (10.1.4)) even with negative feedback, and the input
has no control on the output. Therefore, a study of sinusoidal oscillators is very much appropriate at this stage
because their properties also depend on the loop-gain.
A sinusoidal oscillator delivers a sinusoidal output of a specific frequency
o
without any input signal.
It is also a feedback amplifier; however, it has no input signal. In an oscillator, the feedback is usually positive,
and thus, the block-diagram representation of a circuit with positive feedback is shown in Fig. 10.3.1. If no
loading effect exists in this block diagram, the closed-loop gain is
If the circuit is a sinusoidal oscillator with a frequency of oscillation of
o
, the characteristic equation must
have a zero at s = j
o
. Only then, can there be a nonzero output with zero input. Therefore, at s = j
o
, the
characteristic equation should satisfy or equivalently, 1 A( j
o
) F( j
o
) 0
Evidently, the properties of an oscillator depend on the loop-gain L(s) = A(s)F(s).
If X
i
= 0, the block diagram reduces to the one shown in Fig. 10.3.2. The method of finding the loop-
760
L( s) A( s) F( s)
X
r
X
t
.
(10.3.3)
L( j
o
) 1, and Arg L( j
o
) 2n, n 0, 1, 2, .
(10.3.4)
Fig. 10.3.1: The block-diagram representation of an amplifier with a positive feedback.
+
F
X
i +
+
A
X
f
X
e
X
o
Fig. 10.3.2: The block-diagram representation
of an oscillator.
F
A
X
e
= X
f
X
o
Fig. 10.3.3: The method of finding the loop-
gain of an oscillator.
F
A
X
t
= 1
L = X
r
gain in an oscillator circuit is illustrated in Fig. 10.3.3. The feedback is now positive, and the loop-gain is
For an oscillator to operate at a specific frequency of
o
with a pure sinusoidal waveform, the loop-gain
should have only one pair of zeros at s = j
o
. If the loop-gain has too many zeros on the j-axis, the circuit
will oscillate at every one of these frequencies, and the waveform will not be a pure sinusoid. Therefore, the
condition (10.3.2) should be satisfied only at the desired frequency. The condition (10.3.2) at the frequency
of oscillation is known as the Barkhausen criterion. Since L(j
o
) is a complex quantity, we can obtain two
different conditions from (10.3.2). There are again two methods in which these two conditions can be
expressed. Using the polar form, (10.3.2) is equivalent to
The above equation suggests that, if the test signal X
t
in Fig. 10.3.3 goes through the amplifier and the
feedback network, the total phase shift should be 0 (or 2n radians), and the magnitude of the loop-gain should
be unity at this frequency. If the magnitude of the loop-gain is more than unity at this frequency, the signal
amplitude tends to grow indefinitely although the amplifier saturation will limit the amplitude of the oscillation.
761
0
.
(10.3.5)
Re L( j
o
) 1 ,
(10.3.6)
Im L( j
o
) 0.
(10.3.7)
The amplitude of the output can also be limited using additional nonlinear elements, a topic which will be
addressed later in this chapter (see Example 10.7). If the magnitude of the loop-gain is less than unity, the
oscillation will die down; the circuit ceases to be an oscillator. This clearly illustrates that the amplitude of
oscillation is an indeterminate quantity. Nonlinear circuit analysis is required for a strict analysis of an
oscillator circuit. However, if the amplitude of the oscillation is not of interest, linear circuit analysis can be
used to find the frequency of oscillation and the approximate condition for oscillation for a preliminary design.
When an oscillator circuit is designed and built, the frequency of oscillation should remain constant.
However, due to the change in the operating temperature or parametric drifts over a long period, the
characteristics of an oscillator may change. This may cause a change in the oscillator's frequency. The
frequency stability of an oscillator depends on the phase characteristic of the loop-gain. Should the phase
characteristic change for some reason, the frequency of oscillation also changes. If () is the change in the
phase of the loop-gain and (
o
) is the corresponding change in the value of
o
, for small changes,
It is clear form the above equation that the phase characteristic should be steep around = 0 to keep the change
in
o
small.
Although the conditions of (10.3.4) give an excellent insight into the operation of an oscillator circuit,
an alternative method of interest is to express (10.3.2) using the imaginary and real parts of L(j
o
) as
and
where "Re" and "Im" mean the real and imaginary parts. The above two equations are often employed to
develop the design equations for the frequency and the condition of oscillation respectively. In practical
circuits, the value of Re[L(j
o
)] is set higher than unity to insure sustained oscillations.
10.4: Loop-Gain Determination
We first address the methods of finding the loop-gain in a practical oscillator circuit. The loop-gain
of a practical oscillator circuit uses conceptually the same method shown in Fig. 10.3.3. Consider the oscillator
configuration using the two-port representations for both A- and F-networks shown in Fig. 10.4.1. Following
the suggestion of the block diagram of Fig. 10.3.3, we can cut open the loop at a "convenient" point as shown
762
L( s) ( V
r
/ V
t
) ,
L( s) ( I
r
/ I
t
) .
Fig. 10.4.1: Feedback amplifiers with zero input signal.
A-network
F-network
Z
o
Z
i
a b
Fig. 10.4.2: Ilustration of finding the loop-gain using (a) a test voltage source and (b) a test
current source source.
(b)
I
r
A-network
F-network
Z
t
a
b
I
t
Z
t
a
b
(a)
+
-
+
-
V
r
A-network
F-network
Z
t
a
b
V
t
Z
t
a
b
in Fig. 10.4.1 across "ab," inject an independent test source, and find the return signal. If the test source is a
voltage source V
t
as shown in Fig. 10.4.2(a), the loop-gain is
where V
r
is the return voltage. However, if a test current is used as shown in Fig. 10.4.2(b),
Observe that, in both circuits, there is a termination impedance Z
t
. In practical circuits, there is a loading effect,
and Z
t
represents this loading effect. Z
t
is the impedance seen by the sources in Fig. 10.4.1 before the cut is
made. If the circuits are not properly terminated by the impedances, the corresponding loop-gain will be
incorrect. Obviously, to avoid this problem, it is convenient to look for a pair of terminals at which Z
t
= if
we use a voltage source as the test source. Similarly, if a test current source is used, it convenient to look for
a short-circuit, where Z
t
= 0. Even if Z
t
, if the output impedance Z
o
across the cut "ab" is zero, we can
ignore the loading effect in Fig. 10.4.2(a) and use a voltage source because an ideal voltage source has a zero
output impedance. Similarly, even if Z
t
0, we could use a current source as shown in Fig. 10.4.2(b) and ignore
the loading effect if the output impedance Z
o
is . These different possible techniques will be used to find the
763
loop-gain in several examples later.
10.5: ACTIVE-RC SINUSOIDAL OSCILLATORS
Oscillator circuits can be classified in different categories. In one classification, the oscillators are
classified into sinusoidal and non-sinusoidal. The non-sinusoidal oscillators are also known as the relaxation
oscillators and are discussed in a later chapter. In this section, however, we concentrate on the sinusoidal
oscillators. The sinusoidal oscillators can further be classified in two categories, namely, active-RC and active-
LC circuits. Active-RC oscillator circuits use only resistors and capacitors along with amplifiers since inductors
are bulky in the low frequency range. Active-LC circuits, which are typically realized in the high frequency
range, use the inductors and capacitors in the form of tuned circuits. Traditionally, such oscillators are realized
in the form of discrete transistors, However, in such discrete circuits, the bias and operating points interfere
with the gain and tunning. Furthermore, the effects of the junction capacitances of the transistors should be
included in the analysis of high frequency circuits. These problems are eliminated with the use of VOAs and
CFAs. In this section, we consider several active-RC oscillator configurations.
Phase-shift Oscillators
It is convenient to use voltage-mode op-amps (VOAs) and current-feedback amplifiers (CFAs) in these
Fig. E10.6
(a)
+
-
A
d
R
1
+V
o
R
2
R
4
R
3
C
2
C
1
(b)
+
- +V
o
A
d
C C C
R R
R
F
( a) L( s)
( 1 R
3
/ R
4
) R
2
C
2
s
R
1
R
2
C
1
C
2
s
2
( R
1
C
1
R
1
C
2
R
2
C
2
) s 1
, and ( b) L( s)
R
F
R
2
C
3
s
3
3R
2
C
2
s
2
4RCs 1
.
Exercise
E10.6. In the circuits shown in Fig. E10.6, assume that the VOAs are ideal. Open the loop at ,@ and
find the loop-gain in each circuit. Answers:
764
1
s
1 s
s V
x
sV
y
0, and ( 1 2s) V
y
sV
x
sV
t
.
V
x
( 1 s) (s)
2
1 5s 6( s)
2
( s)
3
V
t
.
V
r
( R
F
/ R) (s)
3
1 5s 6( s)
2
( s)
3
V
t
.
Fig. 10.5.1: (a) A phase-shift oscillator and (b) the circuit to find its loop-gain.
(a)
+
-
C
2
C
1
C
3
+V
o
R
1
R
2
R
3
R
F
(b)
+
-
C C
C
+V
r
R
R
R
R
F
+
-
V
t
V
r
R
F
I
x
=
+V
x
+V
y
circuits because they require fewer external circuit elements. One possible configuration is shown in Fig.
10.5.1(a) in which either a VOA or a CFA can be used. However, this circuit suffers from high frequency
oscillations if a CFA is used. The current flowing in R
3
is converted back to a voltage by the resistor R
F
. In this
process, a 180 phase shift is produced. The ladder network, formed by R
1
, R
2
, R
3
, and the capacitors C
1
, C
2
,
and C
3
, is the feedback network. This feedback network introduces another 180 phase shift in the loop-gain,
and the total phase shift around the loop will be 360 . There is no real advantage in selecting unequal values
for the resistances and capacitances, and therefore assume that R
1
= R
2
= R
3
= R, and C
1
= C
2
= C
3
= C. If the
op-amp is ideal, the output impedance of the op-amp is zero. Therefore, the loop may be cut open at the output
of the op-amp, and a test voltage source may be used to find its loop-gain as shown in Fig. 10.5.1(b). Because
of the negative feedback in this circuit, the output impedance will be relatively low. Using KCL at the nodes
where V
x
and V
y
have been marked, we get
where = (RC). A straightforward solution of the above two equations is
Using the op-amp property, observe that I
x
= (V
r
/R
F
). Also, I
x
= -(s)(V
x
/R)/(1+s). Equating these expressions,
we get
Therefore,
765
L( s)
V
r
V
t
( R
F
/ R) (s)
3
1 5s 6( s)
2
( s)
3
.
(10.5.1)
L( j
o
)
j ( R
F
/ R) (
o
)
3
1 6(
o
)
2
j (
o
) 5 (
o
)
2
.
(10.5.2)
o
1
6
1
6 RC
.
(10.5.3)
Re[ L( j
o
) ]
R
F
R
(
o
)
2
5 (
o
)
2
1.
R
F
( 29R) ,
(10.5.4)
Substituting s = j
o
in (10.5.1),
Applying (10.3.7) and setting the imaginary part to zero,
At this frequency, it is required that
Substituting (10.5.3) in the above equation, the condition for oscillation becomes
which is the condition of oscillation. Usually, the value of R
F
is set higher than (29R) to keep the magnitude
of the loop-gain higher than unity at this frequency to guarantee the sustained oscillations. However, if the
value of R
F
is set much higher than (29R), the amplitude of the oscillations will increase. Although the
amplitude grows, the saturation of the op-amp limits the amplitude of the oscillation to the supply voltages.
However, the waveform of the signal will be highly distorted. The amplitude can be lowered by connecting
external diodes or Zener diodes. Consider a design example next.
Design a phase-shift oscillator using the circuit of Fig. 10.5.1(a) with a frequency of oscillation of
Verify your design with PSPICE simulation. 1 MHz 5 %.
SOLUTION
We choose the VOA AD8057, which has the bandwidth product of 325 MHz. Choosing
to meet the condition of oscillation, the value of R should be 309 . we select C 210 pF, R 300 .
The value of R
F
should be higher than (29R) to have a sustained oscillation, and we choose
The output waveform obtained from PSPICE simulation using the model for AD8057 R
F
9.3 k>29R.
is shown in Fig. 10.5.2. The actual frequency of oscillation is 975.6 kHz, which meets the specifications
closely.
766
V
o
V
x
1
R
3
R
4
K.
(10.5.5)
Fig. 10.5.2: The output voltage obtained from the phase-shift oscillator designed in
Example 10.6.
Time in s
O
u
t
p
u
t

S
i
g
n
a
l
17.0 17.5 18.0 18.5 19.0 19.5 20.0
-1.5V
-1.0V
-0.5V
0V
0.5V
1.0V
1.5V
(17.818u,895.346m) (18.843u,899.263m)
Wien-bridge Oscillator
The main problem with the phase-shift oscillator is that the feedback network is a high-pass network,
and the gain of this network increases with frequency. This is main reason for the high frequency oscillations
with the use of a CFA. Furthermore, it uses a third-order network. A Wien-bridge oscillator, shown in Fig.
10.5.3, is a very popular circuit because of the ease with which it can be built for fixed frequency applications.
To realize a pair of poles, the circuit requires a minimum of two energy-storing elements. Such circuits using
the minimum number of energy storing elements are called canonical. Clearly, the Wien-bridge oscillator is
canonical unlike the phase-shift oscillator. This is another reason for its popularity. Either a VOA or a CFA
can be used in this circuit because the feedback network is a lowpass network.
The part of the circuit, formed by the amplifier and the two resistors R
3
and R
4
, is essentially a
noninverting finite gain amplifier. If the IC amplifier (VOA or CFA) is ideal, the gain of this amplifier is
The positive feedback is provided by the RC-network. If the op-amp is ideal, we can open the loop at the node
o
1
RC 3
, and R
F
( 12R) .
Exercise
E10.7. In the circuit of Fig. E10.6(b), the VOA is ideal and R
3
= R
4
. Show that the frequency of
oscillation and the condition for oscillation are
(b) Assume that C = 100 pF. Select the values of the resistors so that the frequency of oscillation
is 1 MHz 5%. Answers: R = 910 , and R
F
= 11 k.
767
L( s)
V
r
V
t
K R
2
C
1
s
1 [ ( R
1
R
2
) C
1
R
2
C
2
]s R
1
R
2
C
1
C
2
s
2
.
(10.5.6)
L( j
o
)
j KR
2
C
1
o
( 1 R
1
R
2
C
1
C
2
2
o
) j [ ( R
1
R
2
) C
1
R
2
C
2
]
o
.
(10.5.7)
o
1 / ( R
1
R
2
C
1
C
2
) . (10.5.8)
K 1 R
3
/ R
4
1 R
1
/ R
2
C
2
/ C
1
, or equivalently, R
3
/ R
4
R
1
/ R
2
C
2
/ C
1
.
(10.5.9)
R
1
R
2
R, C
1
C
2
C.
o
1/ ( RC) , and K 3 or equivalently R
3
2R
4
.
Fig. 10.5.3: The Wien-bridge oscillator, and the circuit to find its loop gain.
+
-
+V
o
C
1
C
2
R
4
R
3
R
1
R
2
+V
x
+
-
+V
r
C
1
C
2
R
4
R
3
R
1
R
2
+V
t
+V
x
"X." Then, the loop-gain can be found to be
Observe that the loop gain becomes zero as s . Therefore, high frequency oscillations are not likely even
with a CFA in this circuit. This is an added advantage over the phase-shift oscillator. Substituting s = j
o
in
(10.5.6), the loop-gain is
Equating the imaginary part of L(j
o
) to zero and solving this equation,
By setting the real part of L(j
o
) equal to 1, the condition for oscillation is
Usually, in fixed frequency applications, the element values are chosen as follows:
The gain is set slightly higher than 3 to have sustained oscillations. Note that the design of this circuit, based
on the above equations, is very simple (See Example 10.7). This is another reason for the popularity of this
circuit.
The circuit can be made a variable frequency oscillator in several possible ways. One possible solution
is given in Fig. P10.26 (Problem 10.32). Another possible method is to vary both resistors R
1
and R
2
simultaneously keeping their ratio constant. Indeed, digitally programmable resistors (without having to adjust
768
v
1
R
4
v
O
/ ( R
3
R
4
) Fv
O
.
(10.5.10)
manually) can be used for this purpose.
Amplitude Stabilization
In both the circuits discussed so far, we ignored the amplitude control of the output signal. However,
from a practical point of view, controlling the amplitude of the output signal is preferable. To make sure that
the circuit starts oscillating when the circuit is powered up, the initial design is such that the magnitude of the
loop-gain is set to be slightly greater than unity. The amplitude of the oscillation then builds up until the
average loop-gain over a cycle of oscillation reduces to unity due to the inherent nonlinearity in the circuit.
If the design magnitude of the loop-gain is too high, the output will be highly distorted. Adjustment of the loop-
gain manually is very much inconvenient. Even if one adjusts it once, the parameters can change due to aging
or due to environmental changes. If the parameters change, so will the condition for oscillation. If the loop-gain
becomes less than unity, the oscillator will cease to operate. Therefore, the magnitude of the loop-gain is
normally set to a value higher than unity, and an external circuitry is added to control the amplitude.
The popular Wien-bridge oscillator with the amplitude control circuitry is shown in Fig. 10.5.4. There
are two potential divider circuits between the output and the positive and negative dc supplies. These power
supplies will normally be the same that are used to power the op-amp. Let be these power supplies. The V
CC
diodes conduct during alternate half of the oscillations. The currents through the diodes remain almost zero
except when the output voltage reaches the positive and negative peaks. Furthermore, choosing the value of
R
A
high enough, the diode currents can be kept to small values. Besides, the average values of the diode
currents are even smaller because the conduction angle is small. Therefore, we ignore the currents through the
diodes in the following analysis. At any instant,
If v
O
= 0, the diodes do not conduct, which will be proven shortly. The node potentials are
o
1
R
1
R
2
C
1
C
2
, and R
3
R
4
( R
1
/ R
2
) ( 1 C
1
/ C
2
) .
Exercise
E10.8. (a) In the circuit of Fig. E10.6(a), the VOA is ideal. Show that the frequency of oscillation and the
condition for oscillation are
(b) Assume that C
1
= C
2
= 100 pF and R
2
= 2R
1
. Select the values of the resistors so that the
frequency of oscillation is 1 MHz 5%.
Answers: R
1
= 1.1 k, R
2
= 2.2 k, and R
3
= R
4
= 10 k.
769
v
a
( 1 ) V
CC
v
O
,
(10.5.11)
v
b
( 1 ) V
CC
v
O
,
(10.5.12)
R
B
/ ( R
A
R
B
) .
(10.5.13)
v
D1
v
1
v
a
( F ) v
O
( 1 ) V
CC
,
(10.5.14)
v
D2
v
b
v
1
( F) v
O
( 1 ) V
CC
.
(10.5.15)
Fig. 10.5.4: A Wien-bridge oscillator with amplitude control.
+
-
-V
CC
R
B
R
A
R
4
R
3
+v
b
+v
O
C
R
B
R
A
R
+v
a
+v
1
R
C
D
1
D
2
+V
CC
and
where
If v
O
= 0, v
1
is zero, v
a
is positive, and v
b
is negative. Therefore, both diodes do not conduct as assumed earlier.
The diode voltages, v
D1
and v
D2
, are:
and
and F must be less than unity. However, the value of can be chosen to be greater than the value of
F. First assume v
O
increases positively. Therefore, only D
2
can conduct for some positive value of v
O
, and D
1
will remain under cutoff for all possible positive values of v
O
. If D
2
starts conducting, the voltage across the
diode will remain relatively constant. It should be clear from (10.5.15) that v
O
clearly reaches a maximum value
and should remain constant if D
2
conducts. For simplicity, let the conducting diode voltage be 0.7 V. If so,
equating v
D2
in (10.5.15) to 0.7 V, the positive maximum of the value of v
O
is
770
v
Omax
( 1 ) V
CC
0.7
( F)
. (10.5.16)
1 R
A
/ R
B
1 / 1.318.
Fig. 10.5.5: The transient response of the output voltage of the oscillator circuit of
Fig. 10.5.4 designed in Example 10.7.
Time
O
u
t
p
u
t

v
o
l
t
a
g
e
1.6 ms 1.7 ms 1.8 ms 1.9 ms 2.0 ms
-15 V
-10 V
-5 V
0 V
5 V
10 V
15 V
(1.7065m,9.3874)
(1.7605m,-9.4063) (1.9804m,-9.3913)
(1.9245m,9.3874)
Note that must satisfy 1 > > F in accordance with the assumption made earlier so that v
Omax
is positive.
Using the symmetry in the circuit, it can be shown that the negative peak of the output occurs at -v
Omax
. We
illustrate the amplitude stabilization in this circuit through a design example.
In the Wien-bridge oscillator circuit of Fig. 10.5.4, R
3
= 6.2 k, and R
4
= 3 k. The supply voltage to
the op-amp is 15 V. It is desired to obtain a sinusoidal output with an amplitude of 10 V with a frequency
of oscillation of 10 kHz. Design the circuit.
SOLUTION
Using the given specifications in (10.5.27), it is required that = 0.7584. F R
4
/ ( R
3
R
4
) 0.3261.
Thus, the ratio (R
A
/R
B
) is given by
Choosing the value of R
B
should be 31.4 k. However, we select a standard value of R
A
10 k,
R
B
33 k.
To operate at a frequency of 10 kHz, we choose The circuit was C 10 nF, and R 1.59 k.
simulated in PSPICE. To initiate the oscillation, an initial value of 3 V was assigned to the capacitor from the
non-inverting input of the op-amp to the circuit ground. The selected op- amp was LM324, and the diodes were
771
L( s)
( 1 R
2
C
2
s)
( 1 R
1
C
1
s) R
2
C
2
R
3
C
3
s
2
.
(10.5.17)
L( j
o
)
( 1 j R
2
C
2
o
)
( 1 j R
1
C
1
o
) R
2
C
2
R
3
C
3
2
o
1 R
1
R
2
C
1
C
2
2
o
j ( R
2
C
2
R
1
C
1
)
[ 1 ( R
1
C
1
o
)
2
]R
2
R
3
C
2
C
3
2
o
.
R
2
C
2
R
1
C
1
,
(10.5.18)
Fig. 10.5.6: The quadrature oscillator.
+
-
+
-
+V
o2
+V
o1
+V
r
+V
t
R
2
C
2
C
1
R
1
C
3
R
3
L( j
o
)
1
R
2
C
2
R
3
C
3
2
o
(10.5.19)
1N4148. The models of these devices are available in PSPICE library. They were used in the simulation. The
transient response of the output of the op-amp is shown in Fig. 10.5.5. Observe from the response that the
amplitude stabilizes to the required value of 10 V amplitude. The frequency of oscillation is about 9.208 kHz
instead of the designed value of 10 kHz. The amplitude of oscillation is also smaller than the design value.
Quadrature Oscillator
A quadrature oscillator, shown in Fig. 10.5.6, uses the principle of phase-shift oscillator. However, it
provides two outputs that are orthogonal. If the output V
O1
is considered as a sine waveform, then the output
V
O2
will be a cosine wave. That is why the name quadrature oscillator. In some applications, two such outputs
are required, and this circuit is useful. Opening the loop at the node, "X" shown in Fig. 10.5.6, the loop-gain
can be found to be
Substituting s = j
o
in (10.5.17), the loop-gain is
Since the imaginary part of the loop-gain must be zero, the condition for oscillation in this case is
With the above condition, the loop-gain becomes
Since the loop-gain must be unity at the frequency of oscillation,
772
o
1
R
2
R
3
C
2
C
3
,
(10.5.20)
A
1
d
( s) , (10.5.21)
L( s)
V
r
V
t
K RCs
[ 1 3RCs ( RCs)
2
]( 1 Ks)
,
(10.5.22)
R
1
R
2
R, C
1
C
2
C, and K ( 1 R
3
/ R
4
) .
(10.5.23)
L( j
o
)
j K
o
RC
[ 1
2
o
RC( RC 3K) ] j
o
[ 3RC K K(
o
RC)
2
]
.
(10.5.24)
o
1
RC ( RC 3K)
.
(10.5.25)
K
RC ( RC)
2
18RC 45
2
( RC 9)
6( RC )
. (10.5.26)
Device Limitations
We discussed so far oscillator circuits that use conventional voltage-mode op-amps (VOAs) assuming
the op-amps to be ideal. In the frequency range in which the VOAs are useful in active-RC circuits, any VOA
can be assumed to have infinite input and zero output impedances in most practical situations. However, as the
VOA is frequency-compensated with a dominant pole, its gain starts decreasing from a very low frequency at
the rate of 20 dB/decade. Typically, the VOAs gain can be described using the integrator model in the low
frequency range, and thus the gain can be described as
where is the op-amps time-constant, equal to the inverse of its gain-bandwidth product, B. Clearly, this
frequency dependent characteristic of the op-amp does influence the loop-gain both in terms of the phase and
magnitude. Therefore, this finite frequency dependent gain of the VOA influences both the frequency of
oscillation and the condition for oscillation in practical situations.
To understand the influence of the finite gain of the VOA, consider the Wien-bridge oscillator as an
example. If the amplifier is finite and described by (10.5.21), the new loop-gain can be obtained from the circuit
of Fig. 10.5.3(b) as follows:
where
Substituting s = j
o
in (10.5.22), the loop-gain is
Equating the imaginary part of L(j
o
) to zero and solving this equation,
By setting the real part of L(j
o
) equal to 1, the condition for oscillation becomes as follows:
Specifically, consider the design example 10.7. The VOA LM324 has a gain-bandwidth product B =
773
K ( 1 R
3
/ R
4
) 3.003.
f
max
0.5
21010
6
7.958 kHz.
2 Mr/s, and therefore, = 159.2 ns. Using the element values of R = 1.59 k, C = 10 nF, and this value of ,
we find that
o
= 60.18 kr/s, and f
o
= 9.578 kHz. The condition for oscillation under these conditions becomes
that
Since the actual value of K was higher than the above required value, the circuit did oscillate. However, the
actual frequency of oscillation was even lower than the above predicted value.
The second limitation is due to the finite slew-rate of the VOAs. Recall from (10.2.30) that the
maximum frequency of operation is limited by the slew-rate and the amplitude of the output signal in a VOA.
The slew-rate for LM324 is 0.5 V/s. With an expected amplitude of 10 V for the sinusoidal signal, the
maximum frequency of oscillation should be limited to
The expected frequency of oscillation exceeds the above limit. This limitation causes two problems.
The first effect is to cause further phase lag in the op-amp, which reduces the frequency of oscillation. Clearly,
this explains the reason for actual frequency of oscillation of 9.208 kHz to be lower than the above predicted
value of 9.578 kHz.
The second effect of the slew-rate limitation is the distortion. If the maximum frequency of operation
exceeds the limit set by the equation of (10.2.30), one should expect distortion in the output. The total harmonic
distortion (THD) defined in Chapter 6 is applicable here also. During the PSPICE of the circuit designed in
Example, harmonic analysis was performed, and THD was found to be 2.23%. This amount of THD may not
be acceptable in most practical applications.
The device limitations discussed in the previous paragraphs can be overcome using modern VOAs that
have GB-products in the order of a few hundreds of MHz having slew-rates in the order of many tens of V/s
o
1
R
1
R
2
C
1
C
2
K ( R
1
C
1
R
2
( C
1
C
2
)
.
Exercise
E10.9. (a) In the circuit of Fig. E10.6(a), the VOA is ideal except for its frequency dependent gain of 1/(s).
Show that the actual frequency of oscillation is
where K = (1+R
3
/R
4
). If = 490 ps, what is the expected percentage change in the frequency of
oscillation from the ideal value of in the design of Problem E10.8?
o
( R
1
R
2
C
1
C
2
)
1/ 2
Answers: -0.879%.
774
V
y
V
t
R
2
/ [ 1 R
2
( C
2
C
i
) s]
R
2
/ [ 1 R
2
( C
2
C
i
) s] R
1
1/ ( C
1
s) ]
R
2
C
1
s
1 [ ( R
1
R
2
) C
1
R
2
( C
2
C
i
) ]s R
1
R
2
C
1
( C
2
C
i
) s
2
.
(10.5.27)
V
r
V
y
( R
F
R
G
) Z
t
R
o
R
G
R
G
Z
t
[ R
o
( R
G
R
X
) R
X
( R
F
R
G
) R
F
R
G
]
,
(10.5.28)
V
r
V
y
1
R
F
R
G
.
(10.5.29)
Fig. 10.5.7: The Wien-bridge oscillator using a CFB and the circuit to find its loop-gain.
CFA
+
-
+V
o
R
1
C
1
R
2
C
2
R
G
R
F
C
c
CFA
+
-
+V
r
+V
t
R
1
C
1
R
2
R
G
R
F
+V
y
C
2
C
i
C
c
to low hundreds of V/s. Such op-amps can be used to design oscillators for up to a few tens of MHz. Also,
current-mode amplifiers, such as OTAs, CFAs, and CCII
+
, have not only much higher bandwidth than VOAs
but also have much higher slew-rates. The Wien-bridge oscillator using a CFA is shown in Fig. 10.5.7. We can
use the model of Fig. 8.5.3 for the CFA to find the loop-gain of the oscillator. The value of R
2
is typically a few
hundreds of ohms but the value of R
i
is typically a few Ms in most CFAs. However, the value of input
capacitance C
i
could be comparable to the value of C
2
. Therefore, the circuit to find the loop-gain includes the
capacitance C
i
. However, we ignore the influence of C
c
for now.
Using the simple voltage division, we find that
The gain of the non-inverting amplifier can be shown to be
where Z
t
is the transfer impedance, and R
o
is the output resistance, R
X
is the input resistance at the inverting
input of the CFA. Since Z
t
in a CFA,
Using (10.5.27) and (10.5.29), the loop-gain is
775
L( s)
V
r
V
t
( 1 R
F
/ R
G
) R
2
C
1
s
1 [ ( R
1
R
2
) C
1
R
2
( C
2
C
i
) ]s R
1
R
2
C
1
( C
2
C
i
) s
2
.
o
1
R
1
R
2
C
1
( C
2
C
i
)
, and
R
F
R
G
R
1
R
2
( C
2
C
i
)
C
1
.
(10.5.30)
V
r
V
y
( K ) R
F
( C
c
C
t
) s
( D
o
D
1
s D
2
s
2
)
,
D
o
1 ( 1 ) ( 1 K) , D
1
R
F
( 1 ) [ ( 1 K) C
t
C
c
], D
2
( 1 ) R
2
F
C
c
C
t
,
K ( 1 R
F
/R
G
) , ( R
X
/ R
F
) , ( R
o
/ R
F
) , and ( R
F
G
t
) .
C
c
K( 1 ) ( 1 K) C
t
.
(10.5.31)
The above loop-gain has the same form as that of (10.5.17). The frequency of oscillation and the condition for
oscillation can be shown to be
The Wien-bridge oscillator circuit of Fig. 10.5.7 was designed with AD8001A, a CFA from Analog
Devices. The rated supply voltage to the CFA is 5 V. With a closed-loop voltage gain of about 3, using the
manufacturers suggested value of R
F
= 750 , the bandwidth of the amplifier is expected to be in excess of
400 MHz. The circuit was designed to operate with a frequency of oscillation of around 50 MHz. The
manufacturers suggested values of R
i
, C
i
, R
o
, and R
X
are 10 M, 1.5 pF, 15 , and 50 respectively. With
chosen values of C
1
= 21 pF and C
2
= 20 pF, R
1
= R
2
=150 . Also, with R
F
= 750 , we chose R
G
= 360 .
When the circuit was simulated in PSPICE, the frequency of the output was only 40.98 MHz against the
expected value of 49.93 MHz, and the total harmonic distortion was 1.39%. Again, because of the phase-shift
introduced by the amplifier, the frequency of oscillation is 17.9% lower than the expected value. The frequency
error can be almost be eliminated by connecting the third capacitor C
c
shown in Fig. 10.5.7. To find the
required value of C
c
, assume that Z
t
= 1/(G
t
+ C
t
s). Then, using this parameter in (10.5.28), we find that
where
The terms associated with G
t
are very small, and therefore, the terms associated with can be neglected. Also,
there is a dominant pole at s (-D
o
/D
1
) (-1/D
1
). The influence of the dominant pole can be removed using
the zero, and the phase-lag can be almost eliminated until a very high frequency. To achieve this, we can
choose C
c
using
Using the parameters of AD8001 and the resistance values of R
F
and R
G
in the above equation, we find that
C
c
should be about 2.11 pF. We added a 2.2-pF capacitor for C
c
and simulated the circuit in PSPICE. The
output waveform is shown in Fig. 10.5.8. From this figure, we find that f
o
= 49.5 MHz, and total harmonic
distortion increased to 4.79%. The increased distortion is due to the slew-rate limitation as well as saturation
776
I
x
I
z
, V
x
V
y
I
x
R
iX
, and I
y
0, R
oZ
,
I
z1
I
x1
V
x
V
t
R
i X1
, I
z1
V
z1
Cs
Cs
1 R
1
Cs
0, and
V
x
R
2
I
x1
V
x
V
z1
R
i X2
0.
V
z1
( 1 R
i X2
/ R
2
) ( 1 R
1
Cs) V
t
1 Cs[ R
1
2( R
i X1
R
i X2
) 2R
i X1
R
i X2
/ R
2
] R
1
C
2
s
2
[ R
i X1
R
i X2
R
i X1
R
i X2
/ R
2
]
.
L( s)
V
r
V
t
( 1 R
i X2
/ R
2
) R
1
Cs
1 Cs[ R
1
2( R
i X1
R
i X2
) 2R
i X1
R
i X2
/ R
2
] R
1
C
2
s
2
[ R
i X1
R
i X2
R
i X1
R
i X2
/ R
2
]
.
Fig. 10.5.8: The transient response of the output voltage of the oscillator circuit of
Fig. 10.5.7 with compensation designed for 49.93 MHz.
Time
O
u
t
p
u
t

v
o
l
t
a
g
e

i
n

V
150ns 160ns 170ns 180ns 190ns 200ns
-4.0
-2.0
0
2.0
4.0
(156.70n,3.2184) (176.90n,3.2185)
of the output but the frequency of oscillation has an error less than 0.5%.
An Oscillator Circuit using Current Conveyors
The Wien-bridge oscillator can be implemented using both non-inverting (CCII
+
) and inverting (CCII
-
)
current conveyors. One circuit, for implementing the Wien-bridge oscillator, is shown in Fig. 10.5.9. Except
for the finite input resistance R
iX
at the X-port, we assume that both CCII
+
s are ideal and described by the
following equations:
To find the loop-gain, assume that we open at the Y-port of the CCII
+
-1 and apply a test voltage V
t
and
find the return voltage V
r
. By inspection, we find that
Solving the above equations,
Observe that V
r
= [R
1
Cs/(1 + R
1
Cs)]V
z1
. Therefore,
Substituting s = j
o
in the above equation and setting the imaginary part to zero, the frequency of oscillation
777
o
1
C R
1
[ R
i X1
R
i X2
R
i X1
R
i X2
/ R
2
]
.
(10.5.32)
( 1 R
i X2
/ R
2
) R
1
[ R
1
2( R
i X1
R
i X2
) 2R
i X1
R
i X2
/ R
2
]
1, or equivalently R
2
( R
1
/ 2 R
i X1
)
( 1 R
i X1
/ R
i X2
)
.
(10.5.33)
L( s)
g
m1
g
m2
C
1
C
2
s
2
( g
m4
g
m3
) C
1
s
.
(10.5.35)
Fig. 10.5.9: A Wien-bridge ocillator using CCII
+
as active devices.
Y
I
y1
= 0
+V
z1
I
z1
= I
x1
1
+V
o
X
Z
I
x1
C
R
1
+V
r
+V
t
CCII
+
Y
X
I
y2
= 0
C
Z
R
2
+V
x
(2)
CCII
+
Y
X
Z
(1)
is
Using the real part, the condition for oscillation is
There are many other possible oscillator circuits using the active devices of CCII
+
and CCII
-
, where one can
independently control the frequency using a single resistor, independent on the condition of oscillation. Such
circuits require one more active device. Furthermore, to obtain the voltage-mode output, one requires an
additional buffer as shown in Fig. 10.5.9.
Oscillator Circuits using OTAs
Since the transconductance values of the OTAs can be varied or programmed using an external power
supply (Section 7.5), the OTA-oscillator circuits can also be used as voltage-controlled oscillators (VCOs) to
implement the Wien-bridge oscillator. The entire circuit can be fully integrated with adjustable frequency over
several decades. In this section, one oscillator circuit, among several possible ones, is shown in Fig. 10.5.10(a).
For simplicity of analysis, assume that the OTAs in the circuit are ideal. If so, the input and output
impedances of the OTAs are infinity. Each OTA acts as an ideal voltage-controlled current source (see Fig.
7.5.3(c)). Opening the loop at "X," the circuit to find the loop-gain is shown in Fig. 10.5.10(b). The loop-gain
is
Substituting s = j
o
and equating the imaginary part to zero, the condition for oscillation is
778
g
m4
g
m3
.
(10.5.36)
o
g
m1
g
m2
C
1
C
2
. (10.5.37)
Fig. 10.5.10: (a) An OTA oscillator and (b) the small-signal equivalent circuit to find its
loop-gain.
(a)
+
-
+
-
+
-
+
-
+V
r
+V
o
+V
t
C
1
g
m1
g
m2
g
m4
g
m3
C
2
(b)
+
-
+
-
V
t
C
1
g
m1
V
t
+
-
V
2
C
2
g
m2
V
2
+
-
V
r
g
m3
V
r
g
m4
V
r
We can satisfy this condition externally by controlling the g
m
-values of these two OTAs. In practice, the value
of g
m3
should be slightly greater than g
m4
. In any case, equating the real part of L(j
o
) to unity, the following
equation for the frequency of oscillation results:
Since the frequency of oscillation depends on the g
m
-values of the OTAs, it can be controlled externally.
10.6: ACTIVE-LC AND CRYSTAL OSCILLATORS
With the recent advances in technology and with the availability of high speed monolithic high gain
amplifiers, the operating frequency of active-RC oscillators can be as high as a few tens of MHz. Only over
a decade ago, this frequency range was realizable using only using LC-tuned circuits. However, the realizable
frequency range of LC-oscillator circuits has gone much beyond this range recently extending to many
hundreds of MHz and even GHz. The high frequency oscillators, such as those used in modern receivers and
digital computers, can be realized using inductors and capacitors because they require relatively small-size
inductors at high frequencies. An advantage of LC-oscillators is that the tuned-circuits have very high values
779
L( s)
AZ
1
Z
2
R
o
( Z
1
Z
2
Z
3
) Z
2
( Z
1
Z
3
)
.
(10.6.1)
L( j )
AX
1
X
2
j R
o
( X
1
X
2
X
3
) X
2
( X
1
X
3
)
.
(10.6.2)
X
3
( X
1
X
2
) , and L AX
1
/ X
2
1.
(10.6.3)
Fig. 10.6.1: A general form of the LC-oscillator circuits.
+
-
Z
i

Z
3
Z
1
Z
2
R
o
A
+V
o
of Q-factor. Thus, if there is any distortion due to harmonics, the tuned circuits filter out these harmonics better
than RC-circuits, and LC-oscillators provide almost a pure form of a sinusoid. There are two popular types of
LC-oscillators: (a) Colpitts oscillator and (b) Hartley oscillator. The general configuration of both these
circuits is shown in Fig. 10.6.1.
The feedback network, formed by Z
1
, Z
2
, and Z
3
, provides 180 phase-shift in the loop-gain. Assume
that the input impedance of the amplifier is infinity and the amplifier has a nonzero output resistance of R
o
.
Then, the loop-gain can be found to be
The impedances Z
1
, Z
2
, and Z
3
are either inductive or capacitive in these two circuits. If Z
i
= jX
i
for sinusoidal
frequencies, the loop-gain becomes
Since L must be equal to 1 to meet the Barkausen criterion, (X
1
+ X
2
+ X
3
) = 0, or equivalently,
Since A is positive, X
1
and X
2
must have the same sign, and X
3
must have the sign opposite to those of X
1
and
X
2
. That is, if X
1
is capacitive, X
2
must also be capacitive and X
3
must be inductive. This is the case in a Colpitts
oscillator. If both X
1
and X
2
are inductive as in a Hartley Oscillator, X
3
should be capacitive.
Colpitts Oscillator
The Colpitts oscillator is popular because it requires only one coil. Consider a transistor circuit for high
frequency applications shown in Fig. 10.6.2. Typically, the collector-load is an inductance L
C
that has a very
high impedance at the frequency of interest. Therefore, it can be considered as an open-circuit in the small-
780
L( s)
g
m
R ( 1 LC
s
2
)
1 a
1
s a
2
s
2
a
3
s
3
.
(10.6.4)
a
1
R( C
x
C
1
) , a
2
L( C
1
C
) , and a
3
( RL) [ C
1
C
x
C
( C
1
C
x
) ],
(10.6.5a)
C
x
C
2
C
, and R ( R
B
r
) .
(10.6.5b)
o
a
1
a
3
( C
1
C
x
) )
L [ C
1
C
x
C
( C
1
C
x
) ]
. (10.6.6)
C
x
C
1
1
g
m
R
1
g
m
1
R
B
1
r
.
(10.6.7)
Fig. 10.6.2: (a) The Colpitts oscillator, and (b) its small-signal equivalent circuit.
(a)
R
B1
L
C
R
B2
R
E
C
1
C
2
+V
CC
+V
o
L
L
C
+
-
R
B
C
2
g
m
V
C
1
(b)
signal equivalent circuit. Since this circuit is used for high frequency applications, the small-signal equivalent
circuit, including the junction capacitances, is shown in Fig. 10.6.2(b). The loop-gain is in the form of
The coefficients of the denominator polynomial are
where
Substituting s = j
o
in (10.6.4) and equating the imaginary part of L(j
o
) to zero, we find that
Using Re[L(j
o
)] 1, the condition for oscillation is
Typically, Therefore, [1/(g
m
R
B
)] is much smaller than (1/g
m
r
) = (1/
dc
), and the condition for oscillation R
B
r
.
simply requires that the values of C
1
and C
2
should be selected so their ratio is in the order of
dc
or slightly
lower. Consider a design example next.
781
g
m
45.8 mS, r
4.839 k, C
10 pF, and C
1 pF.
( C
1
C
x
) / ( C
1
C
x
) 1/ ( L
2
o
) C
24.33 pF.
C
x
/ ( 1 C
x
/ C
1
) 24.33 pF.
( C
x
/ C
1
) 5.29110
3
.
L( s)
189.02( 1 10010
21
s
2
)
1 19.50910
6
s 470.110
18
s
2
54.82710
24
s
3
.
L( j
o
)
189.03( 1 10010
21
2
o
)
( 1 390.110
18
2
o
) j
o
( 16.19710
6
41.02310
24
2
o
)
.
In the Colpitts oscillator circuit of Fig. 10.6.2, V
CC
= 12 V. Based on the desired dc biasing conditions,
the resistance values have been found as R
B1
= 100 k, R
B2
= 39 k, R
E
= 2.1 k, and R
C
= 4.7 k. The value
of ranges from 100 to 400. The typical value of = 200. The coil has an inductance value of 100 nH. Based
on the dc bias conditions, the small signal parameters for the transistor have been calculated to be
Design the oscillator to provide an output with a frequency of oscillation of f
o
= 100 MHz.
SOLUTION
Using the equation of (10.6.6), we find that
Therefore,
The ratio (C
x
/C
1
) should be greater than the maximum value on the right side of (10.6.7). The maximum value
of the right side of (10.6.7) occurs if is minimum. Using the minimum value of = 100 and R
B
= (R
B1
R
B2
)
= 28.06 k,
Using the previous two equations, we find that C
1
should be less than 4.62 nF. Therefore, a standard value of
is selected. Using this value for C
1
, the value of C
x
can be found to be Therefore, C
1
3.9 nF C
x
24.48 pF.
Note that C
forms a substantial portion of C

x
. Therefore, it is indeed justified to C
2
C
x
C
14.48 pF.
include the effects of the junction capacitances in the analysis.
To verify this design, we can find the loop-gain using (10.6.4) and (10.6.5). With the minimum value
of = 100, the loop-gain is
Using s = j
o
in the above equation,
Since the numerator is purely real, for the imaginary part of L( j
o
) to zero, the imaginary part of its
denominator should be zero. Using this fact, we find that
782
o
16.19710
6
41.02310
24
628.35 Mr / s f
o
100 MHz.
L( j
o
) 1.1865 > 1.
Substituting the value of the above frequency in the loop-gain,
This is greater than unity, and the circuit will have sustained oscillations. However, the output may be distorted.
To reduce the distortion, one has to adjust the value of C
1
.
Crystal Oscillators
In some fixed frequency applications, such as in digital and computer systems, the stability and the
accuracy of the clock frequency are important. In these applications, crystal oscillators are used. The frequency
stability of crystal oscillators is excellent with respect to both time and temperature. If a voltage is applied
across a piezoelectric crystal, which is usually a quartz crystal, the crystal oscillates with a stable frequency.
The crystal frequency depends on the dimension of the crystal. Crystals are available in the market for
frequencies ranging a few tens of kHz to many hundreds of MHz. The electrical equivalent circuit of a crystal
is shown in Fig. 10.6.3. The value of L is such that where
o
is the frequency of oscillation. (
o
L/ r) 1,
Therefore, the effect of r can usually be neglected to find the frequency of oscillation. The value of C
p
is much
higher than the value of C
s
. After neglecting the effect of r, the impedance of the crystal is
o
1
L ( C
p
C
2
R
eff
/ R
id
)
, and
RR
eff
(
o
C
2
)
2
R/ R
eff
g
md
R
id
1
g
md
R
< 1,
Fig. E10.10
+V
o
+V
CC
R
C
R
L
C
I
BIAS
Q
1
Q
2
Exercise
E10.10. (a) In the circuit of Fig. E10.10, neglect the Early effect and
show that the frequency of oscillation and the condition for
oscillation are
where R
eff
= (R
C
R), R
id
= (2r
), and C
p
= C + C
1
+ (C
1
+
C
2
)/(C
1
C
2
).
(b) Assume that V
CC
= 12 V, R
C
= 100 k, and I
BIAS
= 0.1 mA. L = 10 H. The fundamental
parameters of the BJTs are: = 200, C
jeo
= 10 pF, C
jco
= and
F
= 500 ps. Ignore the dc bias 3 pF,
current through R. Obtain a design to have the frequency of oscillation of f
o
= 10 MHz by selecting
the resistance value of R and the capacitance value for C. Answers: R = 330 k, C = 7.41 pF.
783
Z( j )
1
j C
p
1/ ( LC
s
2
) 1
1/ ( LC
x
2
) 1
,
(10.6.8)
C
x
( C
p
C
s
) / ( C
p
C
s
) .
(10.6.9)
s
1/ LC
s
. (10.6.10)
p
1/ LC
x
. (10.6.11)
Fig. 10.6.3: A quartz crystal and its
electrical equivalent circuit.
a
b
L
r
C
s
C
p
C
p
>> C
s
a
b
Fig. 10.6.4: The reactance function of a quartz
crystal.
X
(log scale)
p
0
where
There is a parallel resonance as well as a series resonance. Since C
p
C
s
in a crystal, both these resonant
frequencies are close to each other. The Q-factor at the resonant frequency is more than a few tens of thousands
because of the low value of r. The series resonance occurs at the frequency
The parallel resonance occurs at
The plot of the reactance function of the crystal as a function of frequency is shown in Fig. 10.6.4.
Because C
p
C
s
, the value of C
x
will be very close to C
s
. Therefore,
p
will be very close to the value of
s
,
and the reactance characteristic has a very steep slope between these two frequencies. This is the reason for
such a high frequency stability in crystal oscillators.
Crystal oscillator circuits can be realized by replacing the inductor in LC-oscillators. Consider a crystal
oscillator using a CMOS inverter circuit shown in Fig. 10.6.5(a). The resistor R
f
is used to establish the dc bias
conditions for the two MOSFETs. Its value is usually very high. Therefore, it is almost an open circuit for the
small-signal operation. Also, ignoring the junction capacitances that are also very small, the small-signal
equivalent circuit is shown in Fig. 10.6.5(b). In getting this equivalent circuit, we have also assumed that both
784
A ( g
m1
g
m2
) ( r
o1
r
o2
) , R
o
( r
o1
r
o2
) , Z
1
1
j C
1
, and Z
2
1
j C
2
.
(10.6.12)
1
o
C
p
1
1
LC
s
2
o
1
o
C
1
1
o
C
2
1
1
LC
x
2
o
0.
1
o
1
C
1
1
C
2
1
C
p
1
1
LC
s
2
o
0
(10.6.13)
o
1 / LC
s

s
. (10.6.14)
( C
1
/ C
2
) ( g
m
1
g
m2
) ( r
o1
r
o2
) .
(10.6.15)
Fig. 10.6.5: (a) A crystal oscillator using a CMOS and (b) its small-signal equivalent circuit.
(b)
(g
m1
+g
m2
)V
gs
+
-
V
gs
Z
C
1
C
2
(r
o1
r
o2
)
(a)
+V
DD
R
f
C
1
C
2
+V
o
M
2
M
1
transistors have the same geometry, and therefore, they have identical parameters.
The circuit of Fig. 10.6.5(b) is exactly similar to the conceptual circuit of Fig. 10.6.1, in which
We also identify that Z
3
= Z, where Z is given by (10.6.8). Using the reactances of these three impedances in
first equation of (10.6.3), at the frequency of oscillation of
o
Since C
x
C
s
, the above equation can be reduced to
Obviously, the approximate solution for
o
is
The actual oscillator frequency lies somewhere between
s
and
p
, whose values are given by (10.6.10) and
(10.6.11). Since these values are quite close, the approximation is valid. The condition for oscillation can also
be found using the second equation of (10.6.3), which is
The external capacitances values, usually in the order of a few pFs, are selected to meet the above condition.
Once the crystal oscillator starts oscillating, it locks into the crystal frequency.
785
A
d
( s)
10
4
( 1 53.0510
6
s) ( 1 2.65310
9
s)
.
10.7: CONCLUSIONS
An important problem faced by the designer of feedback amplifiers is its stability, which is determined
by the loop-gain of the feedback amplifiers. Therefore, the stability analysis using the Nyquist criterion was
also discussed in this chapter. Normally, the designer is not only interested in determining the absolute stability
but also the stability margins. We illustrated the process of designing amplifiers for a given phase margin with
specific examples. The frequency compensation, which helps to stabilize the amplifiers with sufficient phase
margins, was also examined, and the frequency compensation of the most popular op-amp 741-type was
addressed. The frequency compensation of a MOSFET configuration using a RHP zero was also discussed.
Another closely related subject matter is the topic of sinusoidal oscillators, and their performance
characteristics depend on the loop-gain of a feedback circuit. Thus, in Sections 10.5 and 10.6, some important
sinusoidal oscillator circuits were discussed.
Many versatile electronic circuits can be designed for both linear and nonlinear applications using op-
amps and other modern monolithic IC devices. Several functional building blocks are considered in the next
chapter.
PROBLEMS
SECTION 10.1
10.1. An op-amp has a gain of
What maximum constant value of F (<1) can one achieve so that the pole-Q factor of the closed-loop
poles is less than or equal to 0.5?
10.2. A feedback amplifier, after suppressing the biasing details, is shown in Fig. P10.2. The BJTs have
= 200. The dc bias currents are: I
C1
= 1 mA, I
C2
= 2 mA, and I
C3
= 5 mA. R
C1
= R
C2
= 0.62 1.8 k,
k, R
F
= 12 k, and R
E
= 0.5 k. Find the loop-gain by finding A and F.
10.3. In Problem 10.2, assume that we add the junction capacitances of the transistors and find the loop-gain
to find the stability margins. Assume that C
1
= C
2
= C
3
= 2 pF, C
1
= C
2
= 72 pF, and C
3
52 pF,
= 130 pF. Find the loop-gain as a function of frequency. (Hint: Use the unilateral models.)
10.4. In the circuit of Fig. P10.4, assume that R
s
= R
L
= 10 k, R
f
= 1 k, and r = The op-amp has 0.1 k.
R
id
= 100 k, R
o
= 1 k, and it has a finite gain of
786
A
d
( s)
10
5
( 1 0.01s) ( 1 10
6
s) ( 1 10
7
s)
.
A( s)
100
( 1 10
4
s) ( 1 10
6
s)
,
Fig. P10.2.
+
-
R
C1
R
C2
1 k
V
s
R
F
+V
o
Q
1
Q
2
R
E
Q
3
Fig. P10.4.
+
-
I
s
R
s
I
o
r
A
d
R
f
R
L
Fig. P10.6.
K
1 nF
10.45 k
12.1 k
+V
i
+V
o
1 nF
Fig. P10.5.
+
-
V
s
10 k
R
if
0.5 mA
R
of
+12 V
+V
o
Q
1
10 k
1 k
Q
2
330
Find the loop-gain.
10.5. In the circuit of Fig. P10.5, the BJTs have = 100, C
jeo
= 20 pF, C
jco
= 4 pF, and
F
= Find the 500 ps.
loop-gain in the high frequency range.
10.6. Assume that the amplifier in the circuit of Fig. P10.6 is an ideal VCVS of gain K. Find the loop-gain.
Plot the movement of the characteristic roots as K varies from 0 to 3. Can you suggest the form of the
impulse response of the circuit, if (a) K = 1, (b) K = 2, and (c) K = 3.
10.7. If
787
A( s)
10
5
( 1 10
2
s) ( 1 10
4
s)
2
.
A( s)
10
5
( 1 10
4
s)
3
.
A
d
( s)
10
5
( 1 10
3
s) ( 1 10
6
s) ( 1 10
8
s)
.
A
d
( s)
30010
3
( 1 410
3
s) ( 1 72.310
9
s)
.
for what constant value of F will the closed-loop poles have (a) the same value and (b) the magnitudes
of the imaginary and real parts are equal?
10.8. An op-amp has a gain of
If the feedback is constant, at what frequency will the phase of the loop-gain be -180 ? For what value
of F will the magnitude of the loop-gain be unity at this frequency? This is the critical F at which the
oscillations will commence.
10.9. Repeat Problem 10.8, if A is
10.10. For the loop-gain obtained in Problem 10.3, find the values of the gain-crossover frequency, phase-
crossover frequency, and the phase and gain margins.
10.11. Repeat the Problem 10.10 for the circuit described in Problem 10.3.
10.12. Recall the noninverting amplifier designed in Example 8.4 using circuit of Fig. 8.3.6 in which R
1
= 2
k and R
2
= 18 k. The op-amp has R
id
= 100 k and R
o
= 100 . The op-amp has a frequency
dependent gain of
Find the stability margins of the closed-loop amplifier.
10.13. Repeat Problem 10.12 with R
1
= , and R
2
= 0 (unity-gain buffer).
10.14. The circuit shown in Fig. P10.14 is an equivalent circuit of an inverting amplifier. C
S1
is the lumped
effect of the stray and input capacitances, which is 20 pF. Assume that R
1
= 10 k and R
2
= 100 k.
The op-amp has R
id
= 2 M, R
o
= 100 , and
C
L
is a load capacitor having a value of 500 pF. Note that C
L
and C
S1
introduce two additional poles
to the loop-gain. Find the loop-gain and determine the stability margins.
10.15. In the circuit of Fig. P10.14, if we connect a 3-pF capacitor across the resistor R
2
, find the new loop-
gain and the stability margins.
D10.16.In the design referred to in Problem 10.12, assume that the op-amp has R
id
and R
o
0. However,
788
A
d
( s)
10
5
( 1 10
2
s) ( 1 10
6
s) ( 1 10
8
s)
.
A
d
( s)
10
4
( 1 510
3
s) ( 1 10
6
s) ( 1 10
8
s)
.
Fig. P10.14.
+
-
R
id
+
-
V
d
A
d
V
d
C
S1
R
o
R
1
R
2
C
L
+V
s
+V
o
Fig. P10.17.
+
-
+V
i
+V
o
R
C
A
d
Fig. P10.19.
+
-
+V
i
+V
o
R
G
CFA
R
F
Fig. P10.18.
+
-
+V
i
+V
o
R
1
R
2
A
d
C
Fig. P10.20.
+
-
+V
i
+V
o
R
c
R
F
CFA
C
it has a finite frequency dependent gain given in Problem 10.12. Find the minimum value of the
closed-loop dc gain for a phase margin of at least 45 . What is the corresponding gain margin?
D10.17.The circuit shown in Fig. P10.17 is an inverting integrator circuit.
(a) Assuming the op-amp to be ideal, design the circuit such that the unity-gain crossover
frequency of the gain (V
o
/V
i
) is 100 kr/s. For an integrator, this frequency is important.
(b) If the op-amp is ideal except for its frequency dependent gain of
find the stability margins.
10.18. A practical differentiator circuit is shown in Fig. P10.18. The VOA has infinite input impedance and
a zero output impedance. However, it has a finite frequency dependent gain of
The circuit components are: C = 2 nF, R
2
= 0.47 k, and R
1
= 0.18 k. Determine the stability
margins.
10.19. A noninverting amplifier using a CFA is shown in Fig. P10.19. The macro-model of the CFA is shown
in Fig. 8.5.3. The model parameters of the CFA are
789
R
x
50 , R
i
, C
i
0, Z
t
( s)
310
6
( 1 16.510
6
s) ( 1 2.27410
9
s) ( 1 530.510
12
s)
,
R
F
R
G
750 .
R
x
50 , R
i
, C
i
0, Z
t
( s)
1.2410
6
( 1 69210
9
s) ( 1 198.910
12
s) ( 1 39.7910
12
s)
,
R
F
910 , R
c
10 , and C 180 pF.
R
G
( R
F
/ 2) .
and R
o
= 15 . The circuit parameters have been chosen to realize a closed-loop nominal gain of (V
o
/V
i
)
= and they are 2 V/ V,
Determine the stability margins.
10.20. A practical differentiator using a CFA is shown in Fig. P10.20. The CFA has
and R
o
= 15 . The circuit parameters are
Determine the stability margins. What is the unity-gain crossover frequency of the closed-loop gain?
D10.21.In problem 10.19, the loop-gain depends on the actual value of R
F
(the feedback resistor). Assume
Determine the value of R
F
that provides phase margin of at least 60 . What is the ideal value of the
closed-loop gain?
SECTION 10.2
10.22. An uncompensated op-amp has its first pole at s = -4 Mr/s and a dc gain of 100 dB. If a dominant pole
compensation is used to obtain a 45 phase margin with F = 1, where should the dominant pole
frequency be located?
D10.23.An op-amp has a dc gain of 80 dB and poles at s = -0.1 Mr/s (-
p1
) and s = -1 Mr/s (-
p2
). It can be
modeled using the circuit of Fig. 10.2.3, and
p1
and
p2
can be realized by 1/(R
1
C
1
) and 1/(R
2
C
2
)
respectively. Also, assume that g
m2
= 40 mS, C
1
= 100 pF, and C
2
= 100 pF. A dominant-pole
compensation is to be achieved by connecting a compensating capacitance C
c
as shown in Fig. 10.2.4.
There is also a third parasitic pole at s = -5 Mr/s (-
p3
). Assume that this pole is fixed and does not
move. Find the value of C
c
to get a phase margin of 45 with F = 1.
D10.24.Consider Problem 10.23. Assume that, instead of connecting a capacitance alone, a series combination
of a resistor R
Z
= 2 k and a capacitor C
c
= 30 pF is connected as in the Problem E10.54 introducing
a new zero in the transfer function. What is the phase margin with F = 1? Compare the bandwidth of
the amplifiers in Problems 10.23 and 10.24.
790
I
x
I
z
, V
x
V
y
I
x
R
iX
, and I
y
0, R
oZ
,
L( s)
V
r
V
t
Z
3
Z
4
( Z
1
R
i X1
) ( Z
2
R
i X2
)
.
R
X
R
o
0, R
i
, C
i
0, Z
t
( s) .
Fig.P10.25
CCII
Y
I
y2
= 0
+V
z1
1
+V
o
X
Z
I
x2
Z
4
+V
r
+V
t
CCII
Y
X
I
y2
= 0
Z
Z
1
Z
2
Z
3
(1) (2)
I
x1
I
z1
= I
x1
I
z2
= I
x2
P10.26
+
-
A
d1
C
2
C
1
R
1
R
2
+V
o
+
-
R
4
A
d2
R
5
R
3
+V
t
+V
r
+
-
CFA
R
1
+V
o
R
2
R
4
R
3
C
1
C
2
P10.27
SECTION 10.4
10.25. The oscillator circuit shown in Fig. P10.25 may use either an inverting (CCII
-
) or a noninverting
(CCII
+
) current conveyors. Assume that both conveyors (1) and (2) are ideal except for the input
resistance in the X-port, and they are described by the following equations:
To find the loop-gain, open the loop at ,@ apply a test voltage V
t
, and find the return voltage. Show
that the loop-gain is
10.26. In the modified form of the Wien-bridge oscillator, shown in Fig. P10.26, the op-amps are ideal.
Assume that R
2
= R
4
and C
2
= C
1
= C. Find the loop-gain using the cut indicated in the figure.
10.27. The oscillator shown in Fig. P10.27 uses a CFA. Assume that CFA is ideal described by
Find the loop-gain by opening the loop at .@
SECTION 10.5
D10.28.Consider the Wien-bridge oscillator of Fig. 10.5.5. Design the circuit to realize f
o
= 10 MHz. Choose
791
A
d
( s)
10
5
( 1 0.016s)
,
o
1
C R
1
R
2
,
Fig. P10.31.
+
-
+
-
A
d2
+V
o
R
1
C
1
R
5
R
4
R
2
C
2
R
3
A
d1
Fig. P10.30.
+
-
A
d
C
1
R
2
R
4
+V
o
R
3
R
1
C
1
C = 100 pF. Assume that you use the VOA AD8047/8 from Analog Devices Inc. for which you can
download the SPICE model. Incorporate the model in PSPICE and simulate the oscillator and verify
the design performance.
D10.29.Assume that the op-amp in the circuit of Fig. E10.6(b) is ideal except for its finite frequency dependent
gain of
find the expected the frequency of oscillation of your design.
D10.30.Assume that the op-amp in the circuit of Fig. P10.30 is ideal and develop the set of equations for the
frequency of oscillation and the condition for oscillation. Choose R
1
16R
2
and C
2
5 C
1
and design
the circuit with a frequency of oscillation f
o
= 10 kHz. If the op-amp is ideal except for its frequency
dependent gain of Problem 10.29, what is the expected frequency of oscillation in your design?
10.31. The circuit shown in Fig. P10.31 is another form of a quadrature oscillator. Assume that the op-amps
are ideal. Develop the design equations for the frequency and condition of oscillation.
10.32. A modified form of the Wien-bridge oscillator is shown in Fig. P10.26. Assume that we choose R
2
=
R
4
and C
2
= C
1
= C and that the op-amps are ideal. Show that the frequency of oscillation is
and the condition for oscillation is (R
3
/R
5
) 1. Note that R
1
can be varied to control the frequency of
oscillation, and this circuit can be used as a variable frequency oscillator. Assume that R
2
= R
4
= R
5
=
2 k, R
3
= 2.2 k, and C
1
= C
2
= 0.1 F. If R
1
varies from 30 to 3.3 M, find the frequency range
for f
o
.
D10.33.Design the variable frequency oscillator of Fig. P10.26 to achieve the frequency range of 1 kHz to
792
A
d
( s)
10
5
( 1 0.016s)
,
case ( a):
1
Z
1
C
1
s,
1
Z
2
G
2
,
1
Z
3
G
3
C
3
s, and
1
Z
4
G
4
C
4
s,
case ( b):
1
Z
1
G
1
,
1
Z
2
C
2
s,
1
Z
3
G
3
C
3
s, and
1
Z
4
G
4
C
4
s,
R
i n
50 , R
i
, C
i
0, Z
t
( s)
( 310
6
)
( 1 16.510
6
s)
.
Assume that the op-amps are ideal during the design process. However, you are expected to 10 kHz.
evaluate the effects of the nonideal properties of the op-amps on the oscillators performance. For this
purpose, assume that the op-amps are ideal except for the finite frequency dependent gain of
Estimate the expected change in the frequency oscillation over the specified frequency range with an
increment of 1 kHz. The above frequency dependent gain represents the difference mode gain of the
741-type op-amp. The classroom version of PSPICE has the model for this op-amp. Using this model,
simulate the circuit in PSPICE and find the expected frequencies over the same range and verify your
theoretical analysis.
10.34. Consider the oscillator circuit shown in Fig. P10.25 in which the impedances are chosen as follows:
and
Develop the equations for the frequency and the condition of oscillation in each case.
10.35. Choose R
1
16R
2
and C
2
4C
1
in the circuit of Fig. P10.27. Assume ideal model for the CFA and
design the circuit to obtain a frequency of oscillation of 10 MHz. Assume that the model parameters
of the CFA are
Estimate the actual frequency of oscillation.
SECTION 10.6
10.36. A particular quartz crystal has series resonance at 2.015 MHz and a parallel resonance at 2.018 MHz
with a Q-factor of 50,000. If C
p
= 4 pF, find the values of L, C
s
, and r.
D10.37.In the circuit of Fig. 10.6.5, assume that both MOSFETs have = V
t
= 1 V, and K = 40 0.01 V
1
,
A/V
2
. If V
DD
= 5 V and C
1
= what is the lower limit for the value of C
2
? 100 pF,
D10.38.Consider the oscillator circuit shown in Fig. P10.38. Assume that the VOA is internally frequency
compensated, and its gain is
793
A
d
( s)
1
s
,
o
1
KRC
, and
K
1 ( K
o
)
2
> 1.
R
x
50 , R
i
, C
i
1.5 pF, Z
t
( s)
( 90010
3
)
( 1 69210
9
s)
.
Fig. P10.38.
R
1
R
+V
o
C
R
2
-
+
A
d
Fig. P10.39.
R
1
R
+V
o
C
R
2
-
+
CFA
where is the time-constant of the VOA. The VOA is otherwise ideal. Find the loop-gain and show
that the frequency of oscillation and the condition of oscillation are
where K = (1+R
2
/R
1
). Assume that = 1.224 ns for an op-amp. Design the circuit for a frequency of
oscillation of 10 MHz.
D10.39.The circuit shown in Fig. P10.39 using a CFA can be used to realize oscillators in the range of several
tens of MHz using the modern monolithic IC devices. Assume that the CFAs model parameters are
Choose C = 10 pF and R
2
= 750 . Design the circuit for a frequency of 91 MHz. The above
parameters are those of CFA AD8001, from Analog Devices Inc. Download the SPICE model of this
CFA, simulate the oscillator in PSPICE, and determine the frequency of oscillation?

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Microelectronics: Analysis and Design April 13, 2004 Sundaram Natarajan

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