1.

Explain with a learning curve, how the cost of processor varies with time along with
factors influencing the cost

2. Find the number of dies per 200 cm wafer of circular shape that is used to cut die that is
1.5cm side and compare the number of dies produced on the same wafer if die is 1.25cm
3. Define Amdahls law. Derive an expression for CPU clock as a function of instruction count
clocks per instruction and clock cycle time.
4. Define computer architecture .Illustrate the seven dimensions of an ISA
5. What is dependability? Explain two main measures of dependability
6. Given the following measurements:
Frequency of FP operations =25% Average CPI of FP operations =4.0
Average CPI of other instructions =1.33 Frequency of FPSQR=2%
CPI of FPSQR =20
Assume that the two design alternative are to decrease the CPI of FPSQR to 2 or to decrease the
average CPI of all FP operations to 2.5.Compare the two design alternatives using the processor
performance equations.
7. Explain in brief measuring, reporting and summarizing performance of computer system 8M
8. Assume a disk subsystem with the following components and MTTF:
10 disks, each rated at 1000000-hour MTTF
1 SCSI controller ,500 000 hour MTTF
1Power supply ,200 000 hour MTTF
1 fan ,200 000 hour MTTF
1 SCSI cable, 1,000,000 hour MTTF
Using the simplifying assumptions that the lifetimes are exponentially disturbed and that failures are
independent ,compute the MTTF of the system as a whole
9. List and explain four important technologies ,which have led to the improvement in computer system.

10. The given data presents the power consumptions of several computers system components

Component Product Performance Power
Processor Sun Niagara 8-core 1.2 GHz 72-79 W
DRAM Kingston 1GB 184 pin 3.7 W
Hard drive Diamond Max 7200 rpm 7.9 W read
4.0 W idle

i)Assuming the maximum load for each component , a power supply efficiency of 70%,what wattage
must the servers power supply deliver to a system with a Sun Niagara 8 core chip,2 GB 184 pin
Kingston DRAM and 7200 rpm hard drives?
ii)How much power will the 7200 rpm disk drive consume ,if it is idle roughly 40 % of the time?
iii)Assume that for the same set of requests ,a 5400 rpm disk will require twice as much time to read data
as a 10800 rpm disk.What percentage of time would the 5400 rpm disk drive be idle to perform the same
transaction as in part (ii)
11. WE will run two applications on dual Pentium processor ,but the resource requirements are not the
same. The first application needs 80% of the resources and the other only 20% of the resources.
i)Given that 40% of the first application is parallelizable ,how much speed up will we achieve with
that application ,if run in isolation?
ii)Given that 99% of the second application is parallelizable ,how much speed up will this application
observe ,if run in isolation?
iii)Given that 40% of the first application is parallelizable ,how much overall system speedup would
you observe ,if we parallelized it?
12. Define the computer architecture .Explain the response time, throughput elapsed time and processor
clock.

c) Two code sequences for a particular machine are considered by a compiler designer.
Instruction class CPI for this instruction class
A 1
B 2
C 3
The compiler designer considers 2 code sequence that require the following instruction counts for a
particular high level language statement
Code sequence Instructions counts for instruction class
A B C
1 20 10 20
2 40 10 10

i)Which code sequence executes most of the instruction?
ii)What is the CPI for each sequence?
iii)Which will be faster?

UNIT 2
1 List pipeline hazard. Explain any one in detail.
2. List and explain five different ways of classifying exception in a computer system
3. An unpipelined machine has 10ns clock cycle and it uses four cycles for ALU operation
and branches ,five cycles for memory operations. Assume that relative frequencies of these
operations are 40%,20%, and 40% respectively. Suppose due to clock skew and set up,
pipelining the machine adds 1 ns overhead to the clock. Find the speed up from pipelining.


4. What are the major hurdles of pipelining ?Illustrate the data hazard briefly
5. With a neat block diagram, explain how an instruction can be executed in 4 or 5 clock
cycles in MIPS data path,without the pipeline register.

6. Explain how pipeline is implemented in MIPS.
7. Explain different techniques in reducing pipeline branch penalties
9. Consider the unpipelined processors in RISC.Assume that it has 1ns clock cycle and that it
uses 4 cycles for ALU operations and branches and 5 cycles for memory operations.
Assume that the relative frequencies of these operations are 40%,20%, and 40%
Respectively. Suppose that due to clock skew and set up ,pipelining the processor adds
0.2 ns of overhead to the clock. Ignoring any latency impact ,how much speedup in the
instruction execution rate will we gain from a pipeline?
10. With a neat diagram ,explain the classic five-stage pipeline for RISC processor.
11. What are the major hurdles of pipelining ?Illustrate the branch hazards in detail
12. Consider the following calculations: X=Y+Z ; a= b*c .Assume the calculations are done us
using registers. Show ,using 5 stage pipeline, how many clock pulses are required for direct
operations. By recording with stalls show how many clock pulses are required and saving in
the number of clock pulses to solve data hazard.
13. With a neat block diagram ,explain how an instruction can be executed in 4 or 5 clock cycles
in
MIPS data path, without the pipeline register.
14. List and explain five different ways of classifying exception in a computer system.