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A-D & D-A Conversion Page 1 of 4 SHAHEER TARIQ

Quantization Error: Quantization error is the noise introduced by quantization in an ideal ADC. It is a rounding error
between the analog input voltage to the ADC and the output digitized value. The noise is non-linear and signal-dependent.
Resolution: The resolution of the converter indicates the number of discrete values it can produce over the range of analog
values. The resolution determines the magnitude of the quantization error and therefore determines the maximum
possible average signal to noise ratio for an ideal ADC without the use of oversampling. The values are usually stored
electronically in binary form, so the resolution is usually expressed in bits.
Offset Error: In this situation the ADC interprets the analog input voltage as greater than its actual value due to faulty
comparator circuit.
Settling Time is defined as the time it takes a DAC to settle within LSB of its final value when a change occurs in input
code.
Linearity of a converter is a measure of the precision with which the linear I/O relationship is satisfied. A Linear Error is
the deviation from the ideal straight line output of the converter. These errors can sometimes be mitigated by calibration,
or prevented by testing. In LSB, its value is
Accuracy of a converter is a measure of the difference between the actual output voltage and the expected output voltage.
It is specified as a percentage of full scale or maximum output voltage.
ADCs:
Counter-Ramp ADC:
The basic idea is to connect the output of a free-running
binary counter to the input of a DAC, then compare the
analog output of the DAC with the analog input signal to
be digitized and use the comparator's output to tell the
counter when to stop counting and reset.
As the counter counts up with each clock pulse, the DAC
outputs a slightly higher (more positive) voltage. This
voltage is compared against the input voltage by the
comparator. If the input voltage is greater than the DAC
output, the comparator's output will be high and the
counter will continue counting normally. Eventually,
though, the DAC output will exceed the input voltage,
causing the comparator's output to go low. This will cause
two things to happen: first, the high-to-low transition of
the comparator's output will cause the shift register to
"load" whatever binary count is being output by the counter, thus updating the ADC circuit's output; secondly, the counter
will receive a low signal on the active-low LOAD input, causing it to reset to 00000000 on the next clock pulse.
The effect of this circuit is to produce a DAC output that ramps up to whatever level the analog input signal is at, output
the binary number corresponding to that level, and start over again. The fact that the circuit's need to count all the way
from 0 at the beginning of each count cycle makes for relatively slow sampling of the analog signal, places the digital-ramp
ADC at a disadvantage to other counter strategies.

A-D & D-A Conversion Page 2 of 4 SHAHEER TARIQ

Successive Approximations ADC:
A successive-approximation ADC uses a comparator to
successively narrow a range that contains the input voltage.
At each successive step, the converter compares the input
voltage to the output of an internal digital to analog
converter which might represent the midpoint of a selected
voltage range. At each step in this process, the
approximation is stored in a successive approximation
register (SAR). For example, consider an input voltage of 6.3
V and the initial range is 0 to 16 V. For the first step, the input
6.3 V is compared to 8 V (the midpoint of the 016 V range).
The comparator reports that the input voltage is less than 8
V, so the SAR is updated to narrow the range to 08 V. For
the second step, the input voltage is compared to 4 V
(midpoint of 08). The comparator reports the input voltage
is above 4 V, so the SAR is updated to reflect the input voltage
is in the range 48 V. For the third step, the input voltage is compared with 6 V (halfway between 4 V and 8 V); the
comparator reports the input voltage is greater than 6 volts, and search range becomes 68 V. The steps are continued
until the desired resolution is reached.
Parallel Comparator (Flash type) ADC:
It is formed of a series of comparators, each one comparing the input
signal to a unique reference voltage. The comparator outputs connect
to the inputs of a priority encoder circuit, which then produces a
binary output. Vref is a stable reference voltage provided by a precision
voltage regulator as part of the converter circuit. As the analog input
voltage exceeds the reference voltage at each comparator, the
comparator outputs will sequentially saturate to a high state. The
priority encoder generates a binary number based on the highest-
order active input, ignoring all other active inputs.
Not only is the flash converter the simplest in terms of operational
theory, but it is the most efficient of the ADC technologies in terms of
speed, being limited only in comparator and gate propagation delays.
Unfortunately, it is the most component-intensive for any given
number of output bits. This three-bit flash ADC requires seven
comparators. With each additional output bit, the number of required
comparators doubles. Considering that eight bits is generally considered the minimum necessary for any practical ADC
(255 comparators needed!), the flash methodology quickly shows its weakness.
An advantage of the flash converter, is the ability for it to produce a non-linear output. With equal-value resistors in the
reference voltage divider network, each successive binary count represents the same amount of analog signal increase,
providing a proportional response.
ADC Conversion Time
Counter Ramp 2
n
x Clock pulse period
Successive Approximations (n + 1) x Clock pulse period
Flash Depends on Propagation time of encoders (very fast)
n = Number of bits.
A-D & D-A Conversion Page 3 of 4 SHAHEER TARIQ


DACs:
Binary Weighted Resistor:
The binary-weighted DAC, which contains individual
electrical components for each bit of the DAC
connected to a summing point. These precise voltages
or currents sum to the correct output value. This is one
of the fastest conversion methods but suffers from
poor accuracy because of the high precision required
for each individual voltage or current. Such high-
precision components are expensive, so this type of
converter is usually limited to 8-bit resolution or less.
Switched resistor DAC contains of a parallel resistor
network. Individual resistors are enabled or bypassed
in the network based on the digital input.

R-2R Ladder Network:
The R-2R ladder DAC which is a binary-weighted DAC that
uses a repeating cascaded structure of resistor values R
and 2R. This improves the precision due to the relative
ease of producing equal valued-matched resistors (or
current sources). However, wide converters perform
slowly due to increasingly large RC-constants for each
added R-2R link.
Advantages of R-2R network method:
Involves only two resistor values.
Greater accuracy for larger number of bits.











A-D & D-A Conversion Page 4 of 4 SHAHEER TARIQ


Sample & Hold Circuit:
Sample and Hold circuit is an analog
device that samples (captures, grabs)
the voltage of a continuously varying
analog signal and holds (locks, freezes)
its value at a constant level for a
specified minimum period of time.
Sample and hold circuits and related
peak detectors are the elementary
analog memory devices. They are
typically used in analog-to-digital converters to eliminate variations in input signal that can corrupt the conversion process.
Reason for the use of Sample & Hold circuit with ADCs: They hold the signal voltage at the sampled value for the period
of conversion.

Acquisition Time: The time required for the switch to open completely after the occurrence of the hold signal.
Aperture Time: The time required for the switch to close and the hold capacitor to charge.
Droop Rate: The rate of change of the output voltage when the control signal is in the hold state. The droop rate is due to
leakage currents flowing on or off the hold capacitor and therefore the droop rate is less for large capacitors.