Low Operating Voltage and Short Settling Time

CMOS Charge Pump for MEMS Applications

David S. Hong and Mourad N. El-Gama1
Microelectronics and Computer Systems Laboratory, McGill University
3480 University Street, Montreal, Quebec, Canada H3A 2A7
mourad@macs.ece.mcgill .ca

Abstract - A 16-stage constant-threshold-voltage type charge

pump was designed and fabricated in a standard CMOS 0.18-pm
process. With an input clock voltage of less than 1 2 V , the
maximum possible output voltage is 14.8 V, with a 65 psec rise
time. The charge pump employs metal-insulator-metal (MIM)
capacitors in order to minimize the chip area (0.8 x 0.9 mm’).
This circuit is intended for generating on-chip actuation voltages
for microelectro-mechanical devices and systems (MEMS). CLK & CLK &
(a) (b)
1. INTRODUCTION I I
Charge pumps are used to generate high DC voltages from low Figure 1 (a) Ideal, and (b) Practical voltage doubler
voltage supplies. l%y are used in many electronic systems: For circuit models.
exampleynon-volatile memories, such as flash memories, need
higher voltages than nominal for programming. Volatile memo- standard CMOS technology - the technology of choice for high
ries use high voltages to achieve faster operating speeds. LCD density, low cost, and low power integrated systems.
screens require above supply voltages to control the contrast, etc. Section 11 describes the basic operation of a capacitive charge
An emerging trend in the semiconductor industry is the use of pump. The Dickson charge pump, based on ideal diodes, is then
micro-electro-mechanical systems (MEMS) to replace specific introduced, along with a straightforward CMOS implementation.
devices used in conventional integrated circuits. For example, The shortcomings of the latter, and possible improvements, are
extensive R&D activities are ongoing to replace the semicnn- then discussed, leading to the design used in this paper. Section Ill
ductor-based switches used for switching between different bands discusses practical implementation and layout issues of the main
in a wireless receiverkansmitter, by RF MEMS switches [I]. The building blocks. Finally, section IV reports experimental results
latter are expected to have less insertion loss and higher linearity, from a prototype chip.
resulting in an important overall improvement in performance.
Another device of interest for RF and millimeter wave applica- 11. CAPACITIVE CHARGE PUMPS
tions is the variable capacitor (varicap). RF MEMS based vari-
Principle of Operation
caps are expected to allow very wide tuning ranges, lower loss,
better isolation, etc. [2]. This would result in an overall reduction A small DC voltage can be multiplied by many factors, through
in power consumption, which is a very important aspect in the the synchronization of the charging and discharging of capacitors,
design of today’s portable systems. Over the last ten years, the in order to produce a much larger voltage. The concept is de-
quest for lower power has resulted in a dramatic decrease in the scribed in Figure la, which depicts a circuit that can ideally dou-
supply voltages used in integrated circuits (e.g. from 5 V and ble the input voltage VDD. When CLK is high, S2 is connected to
higher, down to 1.8 V and lower [3]-[6]). Since the actuation ground, and SI is closed, shorting C, to VDD. After sufficient
voltages of most MEMS devices are relatively high, integrating time, the voltage Vcr across capacitor C, becomes equal to VDD.
them with today’s low-voltage IC’s requires the use of on-chip At the next phase, when CLK is low, S2 is shorted to VDD and SI
charge pumps. The important characteristics of those charge is opened. Since the charges originally accumulated on the ca-
pumps are the following: pacitor have no path to get discharged, the voltage across the
capacitor will remain equal to VDD, resulting in the output volt-
i) To be able to operate from a very low voltage supply age rising to
(0.5 V to 1.5 V).
ii) To have a rise time faster than the response time of the ,,‘! = VDD + Vc,,p= 2 . VDD . (1)
MEMS device (e.g. IO0 ps for a typical RF MEMS
switch). Using a more realistic circuit model, as shown Figure Ib, stray
capacitances C, will degrade the performance of the circuit
iii) To he able to generate enough high voltages (e.g. I O V to
compared to this ideal behavior. Specifically, charges will be lost
15 V).
through C, at the edges of the abrupt transitions, in the form of a
The objective of this work is to design such a charge pump in a

0-7803-776I-3/03/$17.00 02003 IEEE

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 VDD~ Y Y _I U
Input output

CLK
-
CLK
I A 4-stage Dickson charge pump with ideal
(a)
Figure 2
diodes.

leakage current The output voltage can therefore be more

accurately described by

V,, = VDD t VDD .

[ cc -
c,+c, h1. (2)
m
@)

wherefcLK is the clock frequency, also known as the 'pumping'
frequency.
The Dickson Charge Pump
Many researchers have analyzed and improved capacitive
charge pump designs in order to maximize gain andlor optimize
efficiency ([7]-[I I]). Nevertheless, they all stem from the Dick-
son charge pump that was originally conceived based on ideal
diodes 1121. By employing the principle in Figure 1, a 4-stage
Dickson charge pump can be constructed as shown in Figure 2.
Assuming a constant forward-bias voltage V, across all diodes,
it can he shown that the output voltage of an N-stage Dickson
charge pump can be expressed by
V,, = VDD+ N .VG -V, ,
where the pumping gain V , must be greater than zero, and is
defined as
where V,, is the peak-to-peak pumping voltage. Equation (3)
can be simplified to
V,,,, = VDD+ N .(ecLKV d ) - V, ,
- (5)
provided that the sizes of the coupling capacitors C, are much
larger than those of the stray capacitances C ,
c, >> c, ,
and that the overall sum of the leaking currents and of the output
current is negligible. This would he the case for the devices of
interest in this work, namely RF MEMS switches and varicaps.
CMOS Charge Pumps
The Dickson charge pump in Figure 2 can be implemented in
CMOS by replacing the diodes with diode-connected MOS tran-
sistors. However, due to the body effect in the MOS devices, a
change in the source-body voltage V, of each diode will occur at
Figure 3 (a) Schematic of a PMOS-only charge transfer
block (CTB). (b) A 4-stage constant threshold
voltage charge pump.
each pumping stage, resulting in a variation of the effective
threshold voltage Vr. Equation (4) can he updated to take this
effect into account for an N-stage charge pump, resulting in
where
(3)
The main problem with this implementation is the increasing
threshold voltage Vrfi,. Since VTfl+,,is larger than V,,, there will
he a value Nmaxwhere the pumping gain V,,,, will cease to be
greater than zero. In other words, a charge pump with ",+I
stages will no more generate higher voltages than an N,,stage
design.
Constant Threshold Voltage Charge Pumps
This type of charge pumps mitigates the limitation of the
varying threshold voltage encountered in the basic CMOS Dick-
son design [9]. The main idea is to control the threshold voltage
change, through an adaptive body voltage reference. As shown in
Figure 3a, by connecting the body terminal through auxiliary
transistors MSx and MDx, the problem of increasing threshold
(6) voltages can he minimized.
The body voltage is set by the auxiliary transistors MSx and
MDx in each charge transfer block (CTB). When Mx is forward
biased, MDx becomes forward-biased as well, and it sets the body
potential to he approximately equal to the potential of the drain of
Mx. When Mx is reverse-biased, MSx connects the body voltage to
the source of Mx. Since the source-body voltage in each CTB
stage no longer increases, the threshold voltage V , will remain
relatively constant throughout the chain. Hence, the charge pump
equation becomes identical to that of an ideal-diode Dickson

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 output!-' .Input
I P-Substrate
Figure 4 Cross-section views of a charge transfer block
implemented using (a) NMOS-only, and (h)
PMOS-only transistors.
charge pump as follows
V,,, = VDD + N . (ccLK- V T ) - V, .
Using the circuit in Figure 3a as the basic building block, i t i s
possible to cascade as many stages as necessary (Figure 3b), with
the final output voltage being proportional to the number ofthe
cascaded stages.
111. I M P L E M E N T A T I O N IN A STANDARD CMOS
PROCESS
Figure 4 shows possible implementations o f one charge trans-
fer block, both employing NMOS-only or PMOS-only transistors.
The NMOS-only implementation requires the access to a CMOS
technology with a triple-well feature. This requirement has the
disadvantage o f higher cost and higher risk o f latch-up. A PMOS
implementation i s preferred. The three transistors in a
PMOS-only charge transfer block can share the same n-well, and
will be separated from the n-wells of the other blocks. As shown
i n Figure 4, the n-well can he biased by the auxiliary transistors,
allowing a reasonable level of control ofthe body voltage.
IV. EXPERIMENTAL & S I M U L A T I O N RESULTS
A 16-stage constant V , charge pump was fabricated in a stan-
dard CMOS 0.18-pm technology. I t employs metal-insula-
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threshold charge pump.
meial-insulator-metal (hllM) type capacitors i o m i n i m i ~ cihe chip
area. The values of the coupling capacitors were 5.3 pF, and a
27 pl: on-chip capacilur was used as the output load A die pho-
tograph ufthe chip i s shuu,n in Figure 5
Figurc 7 shotis the measurcd pomer up translent responsc for
supply \ultigo I'D/> varpng iron1 11 5 \', up to 1.2 V. The up-
iimum operaling cluck frequency i s approximately 75 MHz.
Huue\cr. the circuii si111 opvratcd with pumping frequenac5
(9)
ranging from as low as 100 k l l z up to 75 .Mllz The lower the
clock frequency, thc slouer the cliargiiig tinic and the lower the
effxtive V C gain as cxprewd in equation (4) t o r clock
frequenaes shwc 75 W k . the output voltage s a n s decreasing
fruni its initial value, due to the lack o f sufricieni time to charge
ihc capnciiors between pulses.
Risr and hll t m c measuremenis are ploited in Figure 6. The
hstt achie\ed loa-to-high d t l i n g time (10% to 90%) u i t h a
I kK2 load \vas approximately 65 GS, uhile the high-to-low tnn-
sitwn takes appruximatcly 500 ps The n j e m e periormance i s
expected tu hr. even <honer In a Mt..MS application. since no
current bc leaking into the MEMS device. At the same iinie,
~ 1 1 1 1
the fall time I, expected to be much longer l h i s might slightly
affect the tuning of a MIiVS varicap. houever. most ME.MS
suitches ui11 not bu affected by ihis, unless the chargc pump
voltage drups uncxpectcdl! beluiv the actuation vdiagc, which in
Lnlikcly Ihe output signd u a s round to have appruximaiely
150 inV u t ripple peak-tu-peak. ai maximum DC uutput voltagc
o f 14.8 V T h i s rcprcsent, about I .O Yo ofrippling The maximum
u u t p ~ tp w e r delivemblc intu a I .\IQ rcssti\e load I\ q ~ i t v r i -
matsly 220 .W.
According to siniulatiun. a l0P0 difkrcnce in the value of the
mdrinium ;ichievahle oul@uiDC \,olVagc was ubserved. 'This I\
attributed to various process vinations Finslly, simulation
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showed a + I O % variance in the output voltage for a temperature
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Output Voltage Range - 0 V t o 14.8V
171 1. Shin, ILY. Chung, Y. 1. Park, and H. S.Min. “A New Charge Pump
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V. CONCLUSION 1998.
A low-voltage and short settling time charge p u m p w a s fahri- 191 C.-C Wang and J:C. Wu, “Efficiency lmprovcment in Charge Pump
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ACKNOWLEDGMENT [ I l l T. TanzawaandT. Tanaka,”ADynamicAnalysisaftheDicksanCharge
The authors would like to thank NSERC, MICRONET, and Pump Circuit,” IEEE J. Solid-State Circuits, Vol. 32, No. 8,
ReSMiQ for their financial support, and the Canadian Micro- pp. 1231-1240, Aug. 1997.
electronic Corporation (CMC) for chip fabrication. [I21 I. F. Dickson, “On-Chip High-Voltage Generation in NMOS lntegratcd
Circuits Using an Improved Voltage Multiplier Techniquc,” IEEE J.
Solid-Slate Circuits, Vol. SC-I 1, pp. 374-378, Mar. 1976.
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