1.a.

SRAM
Advantage:
Internal latches that store the binary information.
Information stored remains valid as long as power is applied.
Easier to use, shorter read and write cycles, no refresh is required.
Storage cells in static RAM memory are made of flip-flops and therefore do not require
refreshing in order to keep their data.
Faster speed that data can be written and read.
SRAM modules are also much simpler compared to DRAM, which makes it easier for most
people to create an interface to access the memory


Disadvantage:
The problem with the use of flip-flops for storage cells is that each cell requires at least 6
transistors to build, and the cell holds only 1 bit of data. In recent years, the cells have been
made of 4 transistors, which still is too many. The use of 4-transistor cells plus the use of CMOS
technology has given birth to a high-capacity SRAM, but its capacity is far below DRAM.

DRAM
Advantage:
Binary information stored in the form of electric charges on capacitors. A DRAM module only
needs a transistor and a capacitor for every bit of data where SRAM needs 6 transistors.
DRAM module can have almost 6 times more capacity with a similar transistor count to an
SRAM module.

Actually it's possible to use even less hardware to store a bit, and that's what DRAM
does: it stores a bit as a voltage level in a capacitor. This makes that you can get a lot
more data in a square mm of DRAM than in an SRAM. Unfortunately the capacitor
voltage leaks away, so the DRAM has to be refreshes continuously.

Low price.
Must be periodically recharged by refreshing.
Larger storage capacity in a single memory chip.

Disadvantage:
The additional circuitry and timing needed to introduce the refresh creates some complications
that makes DRAM memory slower and less desirable than SRAM.
Higher power used by DRAM memory, this difference is very significant in battery powered
devices.

Summary:
1. SRAM is static while DRAM is dynamic
2. SRAM is faster compared to DRAM
3. SRAM consumes less power than DRAM
4. SRAM uses more transistors per bit of memory compared to DRAM
5. SRAM is more expensive than DRAM
6. Cheaper DRAM is used in main memory while SRAM is commonly used in cache memory


1.b.
SRAM:
Four transistors is not bad to store a bit of data. If you would use a couple of gates you'd need at
least 8. (A 2-input NAND gate consists of 4 transistors.)
An SRAM cell is basically two inverters connected back to back, so that they one
keeps the level of the other alive. One inverter consists of 2 transistors, so that's 4 in total.

DRAM: Symbolic representation of a 1 bit cell
During a write, S1 and S2 are closed
During a read, S2, S3 and S4 are closed
Feedback enables write-after-read and refresh
Switches are actually MOSFETs which are controlled by internal circuitry
Voltage on capacitor is converted to a 0 or 1 by using the Sense Amplifer






1.c.
Programmable ROMs (PROMs):
Contain a fusible-link that can be programmed just one-time using a higher system voltage.
Electrically Erasable PROMs (EEPROMs):
Floating gate can be reset by an external voltage instead of a UV light source
1.d. DRAM block diagram
|
-------------------------------------
A
15
| |
----------------------------
|
| A
14
| | |







A
7
/

A8

A9

A10

A11

A12

A13

A14

A15
64KX8

1.e.

RAM Structure:
m words with each word with n bits array of mXn
0 1 2 n-1
1 - 1 2 n-1
2 - 1 2 n-1
. .
. .
. .
m-1 - 1 2 n-1


Micro operations:
DA AA AB MB FS MD RW
R1<- R2 R3 = 001 010 011 0 0101 0 1
R4 <- sl R6 = 100 000 110 0 1110 0 1
R7 <- R7 + 1 = 111 111 000 1 0001 0 1
R1 <- R0 + 2 = 001 000 000 1 0010 0 1


Show the diagram of the hardware that implements the register transfer statement
C3: R2<- R1, R1<-R2


The outputs of four registers, R0, R1, R2 and R3, are connected through 4-to-1 line
multiplexers to the inputs of a fifth register R5. Each register is eight bits long. The required
transfers are dictated by four timing variables (T0 through T3) in a timed sequence as
follows:
T0 : R5 = R0
T1 : R5 = R1
T2 : R5 = R2
T3 : R5 = R3
The timing variables are mutually exclusive, which means that only one variable is equal to 1
at any given time, while the other three are equal to 0. Draw a block diagram showing the
hardware implementation of the register transfers. Include the connections necessary from
the four timing variables to the selection inputs of the multiplexers and to the load control
input of register R5.


4x2 Enc.
T3T2T1T0 S1S0
0001 00
0010 01
0100 10
1000 11



(T0 XOR T1) XOR
(T2 XOR T3)
3. Using 4-bit registers R1, r2, AND gates, OR gates, INV draw one bit slice of the logic
diagram for:
C0: r2 <- 0 clear R2 synchronously with clock
C1: r2 <- R1 Transfer R1 to R2
C2: R2 <- ~R2 complement R2

4. C1: R1 <- R1 + R2 add R2 to R1
~C1C2: R1 <- R1 + 1 increment R1
a. Using 4-bit counter with parallel load and 4-bit adder



b. Using 4-bit adder + external gates


5. Implementation Using Buses
NOV. 2009
5.1. Ca : R0 <- R1
Cb : R3 <- R1, R1 <- R4, R4 <- R0
Cc : R2 <- R3, R0 <- R2
Cd : R2 <- R4, R4 <- R2
a. Destination <- Source(s)
R0 <- r1, r2
R1 <- r4
R2 <- r3, r4
R3 <- r1,
R4 <- r0, r2
b. Source -> Destination(s)
R0 -> r4,
R1 -> r0, r3
R2 -> r0, r4
R3 -> r2,
R4 -> r2, r1
c. To transfers to occur simultaneously: Need minimum of 3 buses since Cb has 3 transactions
from 3 different sources at a time.
d. Block diagram between them


5.2.

(c) Clearly show all the register transfers implemented in each of the two clock cycles. Also
show the values of any logic select lines ad load enable lines used.
Source -> Destination
R0
R1 -> r0, r2, r11
R2 - > R4
R3 -> r6, r8
R4 -> r9, r10

Since only 4 sources are used in two clock cycles then we need 4/2 = 2 buses

c)
CC

1
Select
S1 S0
0 0
Load
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
1 0 1 0 1 0 0 0 0 0 0 1
register transfer

R0 <- R1, R2 <- R1,
R11 <- R1, R4 <- R2
2 1 1 0 0 0 0 0 0 1 0 1 1 1 0 R0 <- R1, R2 <- R1,

S1 S0
5.3.

4 sources are used so if we use two buses then it will take two clock cycles.


5.4.