2
1
m being the effective mobility, C
ox
the gate oxide
capacitance per unit area, V
GS
the gatetosource bias,
V
TH
the threshold voltage and W and L the width and
length of the device respectively.
In a bulk transistor, n is given by
n 1
e
si
C
ox
X
d max
%1:4 to 1:6; typically 2
where X
d max
is the maximum depletion width in
strong inversion.
In a SOI FD MOS transistor, on the other hand, the
body effect is given by
n 1
e
si
t
si
C
oxb
C
ox
e
si
t
si
C
oxb
h i %1:05 to 1:1 typically 3
where C
ox
, C
oxb
and t
si
are the gate oxide capacitance,
the buried oxide capacitance and the silicon lm
thickness, respectively. From the above equations, it
follows that the saturation drain current may be 30
40% higher in a FD SOI device than in a bulk device
with similar parameters [3].
A more accurate model for submicron devices
would include velocity saturation and series resistance
effects [15]. These tend to somewhat degrade the
superior current drive capability of FD SOI
MOSFETs as short channel lengths are considered.
It has been shown however that nonoptimally
designed FD SOI transistors still present a 25%
current drive improvement over comparable bulk
devices for gate lengths down to 0.2 mm which could
be restored to superior values after correct device
structure optimization [16].
The subthreshold swing (inverse subthreshold
slope) of a MOSFET is also affected by the body
effect. Indeed, the subthreshold swing is given by the
following expression [3]:
S(mV/dec) n
kT
q
ln10 4
if the inuence of the interface traps is neglected. The
low value of n in FD SOI devices yields an
improvement of the subthreshold slope over bulk
devices. Almost ideal subthreshold swings of 60 mV/
dec at room temperature corresponding to the
predicted n values have been experimentally demon
strated for optimally designed FD SOI MOSFETs
with channel lengthes down to 0.2 mm [17]. As a
result, a lower threshold voltage can be used in SOI
devices without jeopardizing the OFF leakage current,
Fig. 2. Experimental drain current vs. gate voltage characteristics
of n and pchannel SOI MOSFETs with symmetrical low threshold
voltages (W=L 3 mm=3 mm, V
DS
100 mV, V
THn
0:4 V,
V
THp
0:45 V).
Fig. 1. Cross section of an n ( p)channel thinlm SOI MOS
transistor.
FullyDepleted SOI CMOS Technology 215
and ON drive current much higher than in bulk
devices can be obtained, in particular for reduced
supply voltage.
As far as analog micropower circuits are con
cerned, it is known that the maximum performance
may be obtained when the value of the transconduc
tance/drain current ratio g
m
=I
D
is the largest. This
condition appears in the weak inversion regime for
MOS transistors [18]. The value of g
m
=I
D
can be
rewritten as:
g
m
I
D
dI
D
I
D
dV
G
ln10
S
q
nkT
5
The low bodyeffect coefcient of SOI devices thus
allows for obtaining nearoptimal micropower designs
(g
m
=I
D
values of 35 V
1
are obtained, while g
m
=I
D
reaches only values of 25 V
1
in bulk MOSFETs).
[9,10,19]
In strong inversion, the g
m
=I
D
becomes (for long
channel devices):
g
m
I
D
2 ? m ? C
ox
? W=L
n ? I
D
s
6
and will still remain higher in FD SOI than in bulk
MOSFETs with similar technological characteristics.
Experimental SOI and bulk nMOSFET g
m
=I
D
characteristics are compared in Fig. 3.
c. Modeling
Several analytical modeling alternatives exist for the
electrical simulation of FD SOI CMOS circuits. The
best known SOI SPICE model [20] was originally
developed for 5 Vdigital application. It has recently
been proved efcient for the reliable simulation of
LVLP digital circuits down to a 1 Vsupply voltage
[21]. However, as it is a strong inversionbased model,
it is inadequate for reliable analog design. It indeed
suffers from the troubles common to this family of
models such as unproper modeling of moderate
inversion current, discontinuous transition from
triode to saturation, discontinuities of the current
and charge derivatives (i.e. the smallsignal con
ductance and capacitance parameters) between the
different regions of operation, unphysical overshoot
of the transconductance/drain current ratio in mod
erate inversion, etc. . . [22]. On the contrary, efcient
analog design, and especially for LVLP applications,
requires a model valid from weak to strong inversion
and nonsaturation to saturation conditions with
smooth continuous transitions. The EKV model
recently developed for bulk MOSFETs provides
such properties [23]. It has been proved that it can
successfully be extended to FD SOI MOSFETs
[10,24]. In particular the good agreement between
measured and modeled g
m
=I
D
characteristics is
demonstrated in Fig. 3 for both bulk and SOI devices.
The EKV model will be used throughout the rest of
this paper.
3. LVLP Digital Circuits
A simple analysis can be used to demonstrate the
potential of FD SOI technology for LPLV CMOS
applications. Simulation will be performed next with
the EKV model. Using this model, the characteristics
of transistors and simple circuit elements can readily
be modeled. Fig. 4 presents the I
D
V
G
characteristics
of bulk and fully depleted SOI nchannel MOSFETs
plotted using the EKV model. The varying parameter
between the different curves is the (uniform) dopant
concentration in the channel region, ranging from
10
16
to 1.2 10
17
cm
3
. The gate oxide thickness is
15 nm and the channel length is 1 mm. It can be seen
that, for any given threshold voltage, the SOI device
presents a lower OFF (at V
G
0 V) current and a
higher ON current (at V
G
1 V) that a bulk device
Fig. 3. Experimental (symbols) and modeled (lines) Transcon
ductance over drain current ratios vs. Normalized drain current in
saturation: (a) Bulk (6) and SOI (s) measurements, (b) EKV
model with n 1:1 (  ) or 1.5 ().
216 D. Flandre et al.
does. The I
ON
=I
OFF
ratio in bulk and SOI saturated
MOSFETs is presented in Fig. 5 as a function of
threshold voltage. Again, it can be seen that the SOI
transistor presents better switching characteristics
than the bulk device, regardless of the value of the
threshold voltage. The I
ON
=I
OFF
ratio advantage of the
SOI device becomes smaller as the threshold voltage
is reduced, but it still is ten times larger than in the
bulk transistor for a threshold voltage of 250 mV.
In order to estimate the ``ultimate'' theoretical
reduction of supply voltage and power consumption
the EKV model has been used to calculate the power
needed to discharge a constant load capacitor by a
MOSFET in a realistic circuit environment. A
constant discharge time constant of 100 psec has
been chosen, which is consistent with a typical value
of 250 MHz for the clock frequency. The load
capacitor of the transistor being a combination of
the next gate input capacitance (which is almost the
same in SOI and in bulk) and of drain/source
diffusion, polysilicon and metal line capacitances,
the value of the load capacitance was chosen to be
25% higher in bulk than in SOI. This value is quite
conservative, since the improvement of speed
performance of SOI over bulk observed in the
literature is in the 30 to 100% range, which tends to
indicate capacitance reduction much over 25% [25].
Similarly, a previous study indicates that compared to
bulk, a reduction of total node capacitances by a factor
of 2 is statistically observed in SOI, when the layout is
optimized taking full advantage of the absence of
wells and substrate/well bias contacts to bring n and
pMOSFETs closer and minimize the interconnection
length and number [26].
The average power dissipated by the device is
given by the sum of the static and dynamic power
dissipations
P
total
P
stat
P
dyn
I
OFF
V
DD
a f C
L
V
2
DD
7
where V
DD
is the supply voltage, f the input signal
frequency, C
L
the load capacitance and a the degree of
activity of the gate. An activity of 1% is assumed here,
and both SOI and bulk devices operate at the same
clock frequency. The algorithm used for calculating
the power consumption is the following. In a rst step,
the current I
ON
required to discharge the load
capacitor with a time constant of 100 psec is
estimated. This current is obtained for a gate voltage,
V
G
, equal to V
DD
. Knowing the magnitude of I
ON
and
the value of V
G
at which I
ON
is obtained, one curve
from Fig. 4 can be identied as being the one which
will discharge the load capacitor with the required
time constant. This curve being selected, I
OFF
and the
threshold voltage (Fig. 6) can be extracted. Finally the
static and dynamic power consumption can readily be
obtained from equation (7).
The results of this computation are presented on
Fig. 7. The dynamic power consumption increases
naturally as the square of the supply voltage. The
static power consumption is given by the I
OFF
? V
DD
product. As the supply voltage is reduced, the
threshold voltage decreases (Fig. 6) and, hence, I
OFF
increases. As a result, the static power consumption
increases when the supply voltage is reduced, until it
Fig. 4. Semilog plot of drain current vs. gate voltage in bulk and
SOI MOSFETs for ten values of channel doping concentration
(10
16
to 10
17
cm
3
for the bulk device and 3610
16
to
1:2610
17
cm
3
for the SOI device). The gate oxide thickness is
15 nm.V
DS
100 mV=m
n
500 cm
2
=V ? s, W=L 1 mm=0:6 mm.
Fig. 5. I
ON
V
G
1V=I
OFF
V
G
0 V ratio in bulk and SOI
MOSFETs as a function of threshold voltage. V
DS
1 V.
FullyDepleted SOI CMOS Technology 217
reaches a maximum before dropping to zero as the
supply voltage tends to zero volt. The following
additional observations can be made. Firstly, the
dynamic power consumption of the SOI device is 25%
lower than that of the bulk transistor, which is quite
logical considering our previous assumption on the
load capacitance values. Secondly, the static power
consumption is lower in SOI than in bulk, which
results from the better I
ON
=I
OFF
ratio of SOI devices.
Finally, the point of minimum power dissipation
occurs for a lower supply voltage in SOI than in bulk,
at which point the consumption is twice as small in
SOI than in bulk, eventhough the load capacitance
was chosen to be only 25% lower in SOI than in bulk.
These results depend of course on the values chosen
for the clock frequency and the gate activity factor.
For higher values of these parameters, the dynamic
power consumption will completely dominate the
overall consumption, but, in any case, the consump
tion of the SOI device remains lower than that of the
bulk device.
This brief analysis of gate switching enlights the
benets which lowvoltage lowpower CMOS digital
circuits can draw from the low bodyeffect coefcient
of FD SOI MOSFETs and reduced load capacitance in
SOI CMOS designs. Based on this analysis one may
furthermore extrapolate that threshold voltages of
about 0.3 V may be compatible with the realization of
highspeed lowpower FD SOI CMOS digital circuits
operated at supply voltages reduced down to 11.2 V.
4. LVLP Analog Building Blocks
a. The CMOS Analog Switch
The CMOS analog switch combining parallel nMOS
and pMOS transistors with complementary inverted
gate signals is a key block of sampleddata analog
circuits. A well known problem of this structure is
that the switch onresistance increases when the
supply voltage is lowered. It may even peak to very
high values for midrange input signals when V
DD
is
decreased below a value which can be estimated by
2:V
TH
=2 n, assuming identical threshold voltage
and body effect parameters for n and pMOSFETs
[27]. FD SOI CMOS featuring reduced values for
these parameters clearly allows for correct switch
operation at much lower voltages than in bulk [8,10].
We have rened the analysis using the EKV model,
with similar bulk and SOI parameter sets as above and
minimal switch dimensions (i.e. W=Ln 1,
W=Lp 2:5), in order to compute as a function of
V
DD
, rst the maximum permissible threshold voltage
which keeps the onresistance below 50 kO (Fig. 8),
then the resulting switch offcurrent (Fig. 9). A 50 kO
maximum onresistance is a typical value corre
sponding to a maximum settling error of 0.01% for a
500 kHz clock frequency and a 2 pF capacitance. We
observe that the required bulk threshold voltages
become extremely low for reduced V
DD
. The
corresponding bulk offcurrent then exceeds the
Fig. 6. Nchannel threshold voltage as a function of supply
voltage for given capacitance discharge time.
Fig. 7. Power consumption of a bulk or SOI CMOS gate as a
function of supply voltage.
218 D. Flandre et al.
maximum admissible current which limits to 0.01%
the relative error due to the discharge of the
capacitance during the holding phase. Therefore we
believe that low threshold bulk CMOS processes do
not represent a viable solution for sampleddata
analog circuits. Double threshold processes are
required with chargepump circuits to boost the
switch gate signal above the supply voltage. On the
contrary FD SOI CMOS technology offers the
simplest solution to the problem of the lowvoltage
CMOS switch, when using a threshold voltage of
0.33 V compatible with both maximum onresistance
and offcurrent switch typical specications for a
supply voltage of 1.2 V.
b. Operational Transconductance Ampliers
(OTA)
The better g
m
=I
D
of FD SOI MOSFETs may be
directly used to increase the performance of CMOS
OTAs as illustrated by the analysis of the intrinsic gain
stage consisting of a common source MOS transistor
loaded by an ideal current source I
D0
and a
capacitance C
L
. The DCopenloop gain and transition
frequency are indeed given by
A
vo
g
m
I
D0
? V
A
8
and
f
T
g
m
I
D0
?
I
D0
2 ? p ? C
L
9
where g
m
is the active device smallsignal transcon
ductance and V
A
the Early voltage parameter
corresponding to a smallsignal output conductance
g
d
in saturation equal to I
D0
=V
A
.
Larger g
m
=I
D
ratios increase the DC openloop
gain and can be exploited to either enhance f
T
for
constant DC current dissipation or reduce power for
constant f
T
[9,10].
In the case of practical 2stage OTAs, the DCopen
loop gain will be further enhanced since it results from
the product of the g
m
=I
D
ratios of all stages.
Considering closedloop stability specications (i.e.
the phase margin at the transition frequency), these
will be eased in SOI technology because the reduction
of parasitic node capacitances helps repelling the non
dominant OTA internal poles to higher frequencies.
FD SOI CMOS singlestage OTAs and twostage
Fig. 8. Maximum admissible symmetrical threshold voltage of
the n and pchannel devices of a minimaldimension CMOS
switch for a maximum onresistance of 50 kO as a function of the
supply voltage. The computation was performed using the EKV
model with n 1:1 in the SOI case, n 1:5 in the bulk case and
m
n
? C
ox
50 mA/V
2
and m
p
? C
ox
20 mA/V
2
in both cases.
Fig. 9. Bulk and SOI CMOS switch offcurrents resulting from
the threshold voltages of Fig. 8 as a function of the supply
voltage. The computations were based on the EKV model using
the same parameters as in Fig. 8. Also represented is the limit
corresponding to a relative error of 10
4
due to the discharge of a
2 pFcapacitance during a 1 msholding phase.
FullyDepleted SOI CMOS Technology 219
Miller OTAs have previously been demonstrated to
signicantly outperform bulk CMOS counterparts for
supply voltages above 3 V [810].
A yet unstudied characteristic of FD SOI CMOS
OTAs concerns the noise performance, of particular
interest in lowvoltage opamp implementations in
order to retain adequate signaltonoise ratios. In this
preliminary study, we will focus on the thermal noise
analysis. The inputreferred thermal noise power
spectral density of a differential pair is given by:
S
V
2 ?
g ? n ? kT
g
m
10
where g is a factor ranging from 2 in weak inversion to
8/3 in strong inversion [23]. It is then clear that for a
constant f
T
? C
L
and hence g
m
specication, S
V
will be lower in SOI than in bulk due to the reduction
of the n body factor and the possible use of devices in
weaker inversion.
The inputreferred power spectral density added by
a current mirror is:
S
V;mirror
2 ?
g
m;mirror
g
m
2
?
g ? n ? kT
g
m;mirror
2 ?
g ? n ? kT
g
m
2
?
g
m;mirror
I
D0
? I
D0
11
This equation shows that for constant f
T
and g
m
, we
can either use the same g
m
=I
D
mirror
in bulk and SOI
and obtain lesser added noise in SOI due to the
reduction of n and I
D0
, or achieve similar noise
performance in bulk and SOI using higher
g
m
=I
D
mirror
in SOI which will improve the input
range and output swing. In this case, the possible
increase of g
m
=I
D
mirror
in SOI can be larger than a
factor of 2 when compared to bulk as will be discussed
later.
To demonstrate the feasibility and the performance
of lowvoltage FD SOI CMOS OTAs, the design of the
typical 1stage OTA of Fig. 10 using high g
m
=I
D
ratios
for all the transistors was rst investigated. The OTA
design parameters and experimental characteristics
under a 1.2 Vsupply voltage and 3 mAtotal current
bias are given in Table 1. They are also compared to
the estimated characteristics of a bulk CMOS
implementation with as similar as possible f
T
and
phase margin performance. Due to the increase of the
body factor and parasitic capacitances, this can only
be achieved at the expense of an increase of the
current bias and a decrease of the DC openloop gain
and output swing, since the g
m
=I
D
ratios and transistor
widths have to be reduced. For the same reasons we
estimate that the input range will be lower in bulk than
in SOI by an amount similar to the output swing
reduction if the threshold voltages are identical. The
output swing can be further reduced by the V
TH

difference if larger threshold voltages are used in bulk
for the leakage current considerations.
The second implementation presented here is that
of the cascoded OTA of Fig. 11. The highest possible
g
m
=I
D
values were used for the active transistors, i.e.
input differential pair g
m
=I
D
28 and output
cascode g
m
=I
D
30 devices, in order to optimize
the performance for minimal supply current con
Fig. 10. 1stage CMOS OTA architecture.
Fig. 11. Cascoded CMOS OTA architecture.
220 D. Flandre et al.
sumption. These upper values are limited by stability
considerations because as we increase g
m
=I
D
for a
xed current, the transistor sizes and capacitances are
increased and the phase margin hence decreased. The
bias current and mirror transistors are operated in
stronger inversion g
m
=I
D
8.
This OTA experimentally achieved a 103 dBDC
openloop gain and a 271 kHztransition frequency
over a 12.3 pFload capacitance with a 60
phase
margin and a total bias current of only 2 mA under a
3 Vsupply voltage, in accordance with the targeted
and simulated specications. The output swing was
almost equal to 2 V. We estimated that to achieve a
similar f
T
performance with same C
L
and phase
margin, the bulk implementation could have only used
g
m
=I
D
ratios of 19 and 17 for the input differential pair
and output cascode devices respectively and would
then have dissipated 45% more supply current for a
DC openloop gain reduced by 8 dB. Furthermore, we
simulated that for higher transition frequencies, the
FD SOI benets over bulk increase up to a reduction
of the supply current by a factor larger than 3.5 and an
improvement of the gain by more than 20 dB for f
T
equal to 10 MHz (Fig. 12), even though the active
device g
m
=I
D
values have to be reduced towards
strong inversion (13 and 3.5 in SOI and bulk
respectively at 10 MHz). Similar results were partly
demonstrated in a previous analysis of Miller OTAs
[10]. In these estimations, the g
m
=I
D
ratios of both SOI
and bulk current mirrors were taken constant and
equal to 5.
Concerning the output swing and noise perfor
mance, the results of the above analysis as a function
of f
T
were used to compute the total inputreferred
thermal noise power spectral density in bulk and SOI
from equations (10)(11). The bulk to SOI noise ratio
ranges from 1.54 for 100 kHz to 3.11 for 10 MHz. To
achieve the same thermal noise performance, lower
g
m
=I
D
values could be used in bulk for the current
Table 1. Experimental SOI and simulated bulk design parameters and performance of the 1stage CMOS OTA of Fig. 10 C
L
10 pF. The
bulk simulations used the same technology parameters as SOI simulations in good agreement with the measurements, except for the body effect
and junction capacitances. The gate oxide thickness is 30 nm. The n body factor was equal to 1.1 in SOI and 1.5 in bulk, while the drain
extension bottom capacitance per unit area C
jpn
and sidewall capacitance per unit length C
jswpn
of a p(n)type device were equal to, in the SOI
case, C
jn
C
jp
0:06 fF=mm
2
, C
jswn
C
jswp
0:05 fF=mm and in the bulk case, C
jn
0:18 fF=mm
2
, C
jp
0:4 fF=mm
2
, C
jswn
0:4 fF=mm,
C
jswp
0:5 fF=mm typically.
SOI Bulk
(W/L) 12 30/3 27/3
(W/L) 34 33/3 23/3
(W/L) 56 66/3 46/3
(W/L) 78 30/3 17/3
g
m
=I
D
12 25.8 18
g
m
=I
D
36 22.3 14.5
g
m
=I
D
78 22.7 14
I
DD
(mA) 3 4.32
f
T
(kHz) 350 350
A
v0
(dB) 44 41
phase margin (
) 85.6 85.4
output swing (V) 0.9 0.75
Fig. 12. Comparison of simulated total current dissipation and
DC openloop gain performance of the bulk and SOI cascoded
CMOS OTAs of Fig. 11 (with Bmirror ratio equal to 2) as a
function of the transition frequency. The computations were based
on the EKV model using similar sets of parameters as in Fig. 8
and Table 1.
FullyDepleted SOI CMOS Technology 221
mirrors according to equation (11): the higher the
transition frequency, the higher bulk to SOI bias
current ratio, the lower the bulk mirror g
m
=I
D
for same
noise and the larger the output swing reduction in bulk
when compared to SOI. In our case this output swing
reduction can be up to several volts, even for low f
T
,
resulting in unpractical designs.
5. LVLP Microwave Mosfets
Recently, it has been demonstrated that the use of SOI
(SIMOX) wafers on highresistivity Si substrates
(5000 or 10,000 O? cm) yields MOSFETs which
offer interesting microwave performances. Indeed,
unitygain frequencies f
T
of 14 and 23.6 GHz and
maximum oscillation frequencies f
max
of 21 and
32 GHz have been reported for gate lengths of 1 and
0.25 mm, respectively [11,28]. Such devices can be
integrated with strip lines or slot lines to implement
MMIC circuits [12,29]. These transistors were
fabricated using a dedicated MOS process, called
MICROX
TM
, which uses nonstandard CMOS fea
tures, such as a metal gate and airbridge
metallization. The devices which will be described
next were fabricated, contrarily to the MICROX
TM
process, using a standard fullydepleted SOI CMOS
process with N