Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University
ECEN689: Special Topics in High-Speed
Links Circuits and Systems
Spring 2012
Lecture 7: Equalization Introduction & TX FIR Eq
Announcements
Exam 1 is March 7
5:45-7:10PM (10 extra minutes)
Closed book w/ one standard note sheet
8.5x11 front & back
Bring your calculator
Covers material through lecture 6
Previous years exam 1s are posted on the
website for reference
2
Agenda
Equalization theory and circuits
Equalization overview
Equalization implementations
TX FIR
RX FIR
RX CTLE
RX DFE
TX FIR Equalization
FIR filter in time and frequency domain
MMSE Coefficient Selection
Circuit Topologies
Equalization overview paper posted on website

3
High-Speed Electrical Link System
4
Link with Equalization
5
S
e
r
i
a
l
i
z
e
r
D
TX
[N:0]
TX Clk
Generation
(PLL)
TX FIR
Equalization
RX Clk
Recovery
(CDR/Fwd Clk)

RX CTLE + DFE
Equalization
D
e
s
e
r
i
a
l
i
z
e
r
D
RX
[N:0]
Channel
f
6
Channel Performance Impact
7
Channel Performance Impact
Channel Equalization
8
Equalization goal is to flatten the frequency response out to the
Nyquist Frequency and remove time-domain ISI
TX FIR Equalization
TX FIR filter pre-distorts transmitted pulse in
order to invert channel distortion at the cost of
attenuated transmit signal (de-emphasis)
9
L
L L
L
L
L
L
L
L
1x 4x 2x 1x
1/4 1 1/2 1/4
IDACs
&
Bias
Control
sgn
-1
sgn
0
sgn
1
sgn
2
50
Out-P
Out-N
4:2
MUX
2
2
2
2 1
D
0
D
1
D
2
D
3
V
DDA
=1.2V V
DD
=1.0V
V
DDIO
=1.0V
V
DDA
=1.2V
1
1
1
C2 (5GHz)
From on-chip PLL
2
(
2
.
5
G
b
/
s
)
(10Gb/s)
(5Gb/s)
ESD
L
L L
L
L
L
L
L
L
LL
LL LL
LL
LL
LL
LL
LL
LL
1x 4x 2x 1x
1/4 1 1/2 1/4
IDACs
&
Bias
Control
sgn
-1
sgn
0
sgn
1
sgn
2
50
Out-P
Out-N
4:2
MUX
2
2
2
2 1
D
0
D
1
D
2
D
3
V
DDA
=1.2V V
DD
=1.0V
V
DDIO
=1.0V
V
DDA
=1.2V
1
1
1
C2 (5GHz)
From on-chip PLL
2
(
2
.
5
G
b
/
s
)
(10Gb/s)
(5Gb/s)
ESD
( ) ( ) ( ) ( ) ( ) | | |
.
|

\
|
+ + + =

2
2 1 0 1 0
2 1 0 1
TERM
out
R
D I D I D I D I V
A Low Power 10Gb/s Serial Link Transmitter in 90-nm
CMOS, A. Rylyakov et al., CSICS 2005
I
-1
I
0
I
1
I
2

D(1) D(0) D(-1) D(-2)
6Gb/s TX FIR Equalization Example
Pros
Simple to implement
Can cancel ISI in pre-
cursor and beyond filter
span
Doesnt amplify noise
Can achieve 5-6bit
resolution

Cons
Attenuates low
frequency content due
to peak-power limitation
Need a back-channel
to tune filter taps
10
RX Equalization #1: RX FIR
Pros
With sufficient dynamic range, can amplify
high frequency content (rather than
attenuate low frequencies)
Can cancel ISI in pre-cursor and beyond
filter span
Filter tap coefficients can be adaptively
tuned without any back-channel

Cons
Amplifies noise/crosstalk
Implementation of analog delays
Tap precision
11
w
-1
z
-1
x w
0
z
-1
x
z
-1
x w
n-1
z
-1
w
n
x
D
EQ
D
in
Analog Delay Elements
*
*D. Hernandez-Garduno and J . Silva-Martinez, A CMOS 1Gb/s 5-Tap Transversal Equalizer based on 3
rd
-Order Delay Cells,"
ISSCC, 2007.
RX Equalization #2: RX CTLE
12
D
in
- D
in
+
V
o
- V
o
+
Pros
Provides gain and
equalization with low
power and area
overhead
Can cancel both pre-
cursor and long-tail ISI

Cons
Generally limited to 1st
order compensation
Amplifies noise/crosstalk
PVT sensitivity
Can be hard to tune
RX Equalization #3: RX DFE
13
z
-1
clk

x
w1
z
-1
x
w2
z
-1
x
wn-1
z
-1
x
wn
D
in
D
RX
Pros
No noise and crosstalk
amplification
Filter tap coefficients
can be adaptively tuned
without any back-
channel

Cons
Cannot cancel pre-
cursor ISI
Critical feedback timing
path
Timing of ISI
subtraction complicates
CDR phase detection
Equalization Effectiveness
Some observations:
Big initial performance boost with 2-tap TX eq.
With only TX eq., not much difference between 2 to 4-tap
RX equalization, particularly DFE, allows for further performance
improvement
Caution hard to build fast DFEs due to critical timing path
14
I
n
c
r
e
a
s
i
n
g

E
q
u
a
l
i
z
a
t
i
o
n

Channel Responses
Link with Equalization
15
S
e
r
i
a
l
i
z
e
r
D
TX
[N:0]
TX Clk
Generation
(PLL)
TX FIR
Equalization
RX Clk
Recovery
(CDR/Fwd Clk)

RX CTLE + DFE
Equalization
D
e
s
e
r
i
a
l
i
z
e
r
D
RX
[N:0]
Channel
f
Channel Equalization
16
Equalization goal is to flatten the frequency response out to the
Nyquist Frequency and remove time-domain ISI
TX FIR Equalization Time Domain
17
z
-1
z
-1
z
-1
w
-1
w
0
w
1
w
2
TX
data
z
-1 w
n
( )
2 1
274 . 0 595 . 0 131 . 0

+ = z z z W : 10Gbps For
| |
| | | | | |
| | | | | | ... 1 1 1 ... 274 . 0 595 . 0 131 . 0 ... 1 1 1 ...
... 190 . 0 190 . 0 190 . 0 ... 274 . 0 595 . 0 131 . 0 ... 1 1 1 ...
274 . 0 595 . 0 131 . 0
=
=
=
Polarity) ng Alternati w/ Taps (Sum Response Frequency Nyquist
Taps) (Sum Response Frequency Low
W
TX FIR Equalization Freq. Domain
18
z
-1
z
-1
z
-1
w
-1
w
0
w
1
w
2
TX
data
z
-1
w
n
( )
2 1
274 . 0 595 . 0 131 . 0

+ = z z z W : 10Gbps For
( )
( )
s s
fT j
fT j fT e z
z z z W
s

2 sin ) 2 cos(
274 . 0 595 . 0 131 . 0
2
2 1
+ = =
+ =

w/
( )
( ) ( ) dB f W j z
f
4 . 14 190 . 0 0 1 ) 0 sin( 0 cos = = = + =
= 0 Response Frequency Low
( ) dB
T
f W j z
T
f
s
s
0 1
2
1
1 ) sin( cos
2
1
=
|
|
.
|

\
|
= = + =
|
|
.
|

\
|
=

Response Frequency Nyquist
Equalizer has 14.4dB of frequency peaking
Attenuates DC at -14.4dB and passes Nyquist frequency at 0dB
Note: Ts=Tb=100ps
TX FIR Coefficient Selection
One approach to set the TX FIR coefficients is a
Minimum Mean-Square Error (MMSE) Algorithm
19
( )
( )
( )
( )
( ) ( )
( ) ( )
( )
( )
( ) ( )
( ) ( )
( )
( )
( )
( )
(
(
(
(

(
(
(
(
(
(

(
(
(
(
(
(

=
(
(
(
(

+ + 1
...
1
0
1 0 ... 0 0 0
2 1 ... 0 0 0
... ... ... ... ... ...
0 0 ... 0 0 1
0 0 ... 0 0 0
1 0 ... 0 0 0
2 1 ... 0 0 0
... ... ... ... ... ...
0 0 ... 0 0 1
0 0 ... 0 0 0
3
...
1
0
l c
c
c
n w
n w n w
w w
w
k h
k h k h
h h
h
k n l y
y
y
l input symbols, c
channel output vector, y
Rows = k+n+l-2
where k = channel pulse model length
TX Eq w Matrix
Rows = n+l-1 where n = tap number
Columns = l = input symbol number
Channel h Matrix
Rows = k+n+l-2
Columns = n+l-1
TX FIR Coefficient Selection
Multiplying input symbols by TX Eq., wc=w*c
20
( )
( )
( )
( )
( ) ( )
( ) ( )
( )
( )
( ) ( )
( ) ( )
( )
( )
( )
( )
(
(
(
(

(
(
(
(
(
(

(
(
(
(
(
(

=
(
(
(
(

+ + 1
...
1
0
1 0 ... 0 0 0
2 1 ... 0 0 0
... ... ... ... ... ...
0 0 ... 0 0 1
0 0 ... 0 0 0
1 0 ... 0 0 0
2 1 ... 0 0 0
... ... ... ... ... ...
0 0 ... 0 0 1
0 0 ... 0 0 0
3
...
1
0
l c
c
c
n w
n w n w
w w
w
k h
k h k h
h h
h
k n l y
y
y
Total system
( )
( )
( )
( )
( ) ( )
( ) ( )
( )
( )
( )
( )
(
(
(
(

+
(
(
(
(
(
(

=
(
(
(
(

+ + 1
...
1
0
1 0 ... 0 0 0
2 1 ... 0 0 0
... ... ... ... ... ...
0 0 ... 0 0 1
0 0 ... 0 0 0
3
...
1
0
l n wc
wc
wc
k h
k h k h
h h
h
k n l y
y
y
We desire the output vector, y, to be ISI free
( )
( )

+ + =
+ + = =
=
1 # tap precursor Eq # sample cursor - pre Channel
1 # tap precursor Eq # sample cursor - pre Channel
n n y
n n y
y
des
des
des
, 0
, 1
Lone-Pulse Equalization Example
21
With lone-pulse equalization,
l=1 input symbols, i.e. c=[1]
( )
( )
( )
| | 1
2
1
0
0.0067 0 0
0.0090 0.0067 0
0.0097 0.0090 0.0067
0.0152 0.0097 0.0090
0.0162 0.0152 0.0097
0.0224 0.0162 0.0152
0.0360 0.0224 0.0162
0.0526 0.0360 0.0224
0.0917 0.0526 0.0360
0.1775 0.0917 0.0526
0.3437 0.1775 0.0917
0.0812 0.3437 0.1775
0.0052 0.0812 0.3437
0.0023 0.0052 0.0812
0.0010 0.0023 0.0052
0.0004 0.0010 0.0023
0 0.0004 0.0010
0 0 0.0004
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
(
(
(
(

(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(

=
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(

w
w
w
Y
des

Channel pulse matrix H with 5 pre-
cursor samples and 10 post-cursor
samples, 3 columns for 3 eq taps
3-tap Eq
Matrix, W
Symbol Matrix,
C for
Lone Pulse
Y
des
(5+1+1=7)=1
Channel pre-
cursor samples
Equalization pre-
cursor taps
TX FIR Coefficient Selection
Differentiating this w.r.t. tap matrix taps to find taps which yield
minimum error norm
2

22
input pulse with
des des C des
Y HW Y HW Y Y E = = =
We can calculate the error w.r.t. a desired output
H Y H H W
H Y H H W E
dW
d
T
des
T T
T
des
T T
=
= = 0 2 2
2
Solving for optimum TX Eq taps, W
( )
des
T T
ls
Y H H H W
1
=
des
T
des
T
des
T T
Y Y HW Y HW H W E + = 2
2
Computing the error matrix norm
2

This will yield a W matrix to produce a value of 1 at the output cursor,
i.e. an FIR filter with gain
Need to normalize by the total abs(tap) sum for TX FIR realization
( )
( )
( )

=
=
n
i
ls
ls
lsnorm
n W
n W
n W
1
TX FIR Tap Resolution
23
Using the above MMSE algorithm for the Refined
Server Channel at 10Gb/s
( )
| |
| | 274 . 0 595 . 0 131 . 0
1 1
274 . 0 595 . 0 131 . 0
2 1

+ =

post main pre
z z z W
Generally, TX DAC resolution is limited to between
4 to 6bits
Mapping these equalization coefficients with this
resolution may impact performance
(
(
(
(

=
(
(
(
(

=
0.2745 -
0.5949
0.1307 -
1.7184 -
3.7245
0.8180 -
6.2609 by g normalizin
lsnorm ls
W W
TX FIR Circuit Architectures
Direct FIR vs Segmented DAC
Direct FIR
Parallel output drivers for output taps
Each parallel driver must be sized to
handle its potential maximum current
Lower power & complexity
Higher output capacitance
Segmented DAC
Minimum sized output transistors to
handle peak output current
Lowest output capacitance
Most power & complexity
Need mapping table (RAM)
Very flexible in equalization
24
Segmented DAC
Direct FI R
[Zerbe]
[Zerbe]
Direct FIR Equalization
25
L
L L
L
L
L
L
L
L
1x 4x 2x 1x
1/4 1 1/2 1/4
IDACs
&
Bias
Control
sgn
-1
sgn
0
sgn
1
sgn
2
50
Out-P
Out-N
4:2
MUX
2
2
2
2 1
D
0
D
1
D
2
D
3
V
DDA
=1.2V V
DD
=1.0V
V
DDIO
=1.0V
V
DDA
=1.2V
1
1
1
C2 (5GHz)
From on-chip PLL
2
(
2
.
5
G
b
/
s
)
(10Gb/s)
(5Gb/s)
ESD
L
L L
L
L
L
L
L
L
LL
LL LL
LL
LL
LL
LL
LL
LL
1x 4x 2x 1x
1/4 1 1/2 1/4
IDACs
&
Bias
Control
sgn
-1
sgn
0
sgn
1
sgn
2
50
Out-P
Out-N
4:2
MUX
2
2
2
2 1
D
0
D
1
D
2
D
3
V
DDA
=1.2V V
DD
=1.0V
V
DDIO
=1.0V
V
DDA
=1.2V
1
1
1
C2 (5GHz)
From on-chip PLL
2
(
2
.
5
G
b
/
s
)
(10Gb/s)
(5Gb/s)
ESD
( ) ( ) ( ) ( ) ( ) | | |
.
|

\
|
+ + + =

2
2 1 0 1 0
2 1 0 1
TERM
out
R
D I D I D I D I V
A Low Power 10Gb/s Serial Link Transmitter in 90-nm
CMOS, A. Rylyakov et al., CSICS 2005
I
-1
I
0
I
1
I
2

D(1) D(0) D(-1) D(-2)
Segmented DAC Example
26
[Casper I SSCC 2006]
Row = 4-bit data pattern
Column = 6-bit weighting
4 filtered bits
(parallel) at 6-bit
resolution
Sized only to
deliver maximum
total current
Next Time
RX FIR
RX CTLE
RX DFE
Alternate/Future Approaches
27