IEEE 2007 Custom Intergrated Circuits Conference (CICC)

A 10Gb/s Equalizer with Decision Feedback for High

Speed Serial Links
Ali Kiaei" 2, Babak Matinpour2, Ahmad Bahai" 2, Thomas H. Lee'

'Stanford University, Stanford, CA 94305, USA

2National Semiconductor Corporation, Santa Clara, CA 95051, USA
Abstract-A 10Gb/s equalizer using both feedforward and
decision-feedback equalization is designed for high speed seriallinks. The chip is implemented in a standard 0.25jm SiGe
BiCMOS technology with 50 GHz peak ft, and packaged in a
commercial LLP package. Using a 4-stage feedforward and 2-tap
post-cursor cancellation, this equalizer achieves a total peak-topeak jitter of 27ps and 33ps for 10" and 20" of copper traces on
FR4, respectively. The transmitter uses NRZ signaling with no
pre-emphasis.
Keywords: decision-feedback, equalizer, serial-link, and
backplane communications

INTRODUCTION

Many high speed serial communications systems such as

SONET and Ethernet, have gradually evolved to operating
speeds as high as 10Gb/s. At multi-Gb/s data rates, however,
the transmission medium (generally backplane or cable),
limits the signal bandwidth.
Fig. 1 illustrates the transmission loss over 10, 20, and 30
inches of copper traces over FR4 material. The transmission
loss is dominated by the skin effect at lower gigahertz
frequencies and by dielectric loss at higher frequencies.
The frequency dependence of the amplitude of the channel
response, as well as its non-linear phase, introduces ISI to the
transmitted signal. Any impedance mismatches and/or
discontinuities because of the package parasitics, connectors,
backplane vias, etc. increase the ISI and limit the data rate
even more. In addition to the above-mentioned transmission
channel non-idealities, the signal degrades further as a result
of cross-talk. In the case of parallel transmission lines on a
backplane, the worst-case occurs when the adjacent channel
has a reverse flow of data (the second link has a transmitter at
the receiver end of the first link). In this case of near-end
cross-talk (NEXT), as well as far-end cross talk (FEXT), the
amount of interference generally increases with the frequency,
because of higher coupling factors (capacitive and inductive)
betweenthe transmission lines at higher frequencies.
A linear equalizer, whose frequency response is similar to
the inverse of the channel response, reduces the ISI and makes
the signal detectable. Unfortunately, linear equalizers boost
not only the high frequency content of the signal, but also the
undesired cross-talk. This characteristic is especially
troublesome since there is more cross-talk at higher
frequencies.A

Using a decision-feedback equalizer (DFE) is a non-linear

approach to reducing the ISI without excessively boosting the

cross-talk.

Decision-feedback cancellation has been previously

published at data rates as high as 6.25Gb/s [1-2]. This work
describes a combination of feedforward equalization (FFE)
decision
back
equaltr
ost(FFE)
and decision-feedback equalization with true first post-cursor
cancellation at 10Gb/s.
r

CIRCUIT ARCHITECTURE
As illustrated in Fig. 2, the equalizer consists of an FFE and
a DFE. The feedforward equalizer reduces the pre-cursor ISI,
while the DFE removes the post-cursor ISI. The DFE has two
post-cursor cancellation taps.
C
-10

2030

_-.---.-.

-60-

70

-o

-90

6miMicrostrip-1 Oin-Loss.s4p
6milMcrostrip-2Oin-Loss.s4p

i |------ --

15
15
Frequency (GHz)
Fig. 1. Transmission loss: lOOQ differential transmission line.
Out (non-retimed)

Drive
FFE

--------------------------------------------

Driver

-LK

Boost

Control

DFE

Fig. 2. Circuit architecture.

1-4244-1623-X/07/$25.00 0C2007 IEEE

MP-26-1

285

A. Feedforward Equalizer
The frequency response of a transmission line on backplane
can be approximated by:
Jo td
H(jw) _ 1expW-

ja
- ___

and td = length

- J tan

(1)

Here, W is the width, and L and C are the inductance and

capacitance per unit length of the transmission line; tand is the
loss tangent of the dielectric and cG is the metal conductivity; td
is the line delay and exp(-jwtd) is the ideal transfer function of
the channel when there is no metal or dielectric losses (cT = co;
tand= 0).
There is a high frequency roll-off in the magnitude of the
channel frequency response as a result of the metal and
dielectric losses (see Fig. 1).
As shown in Fig. 3, a high frequency boost network using
capacitive bypassing across resistive degeneration is used to
compensate the channel's high frequency roll-off. A firstorder approximation of the boost circuit's transfer function is:

where

REE

1+
g=RE

H(WoLO)

Lo

=1+

=RE CE (1-

)
Boost

at higher boosts.

A certain amount of high frequency boost is needed to

reduce the pre-cursor ISI in order to prevent error propagation
in the DFE; the DFE can only remove post-cursor ISI. Too
much boost, however, is not desirable because of the crosstalk amplification and higher group delay variation.
The inputs of all four stages of the FFE are ac-coupled to
minimize the dc offset. The boost networks have a loss at low
frequencies to avoid saturation at higher frequencies. This loss
has an adverse effect on the noise figure, but in most practical
cases, noise is not the major contributor to the total jitter.
A IOOQ resistor provides differential termination at the
input of the first stage (see Fig. 4). Lbond is the bondwire
inductance and Ctot is the total capacitance of the single-ended
input. The total input capacitance includes contributions by
the input transistor, the ESD diodes, and the bonding pad.
Ctot can be adjusted so that:

(5)

= 50Q

bond

RE CE

compared to lower boost settings, resulting in higher data jitter

A 3-bit word controls the value of the degeneration resistor

and capacitor (RE and CE) and, therefore, the locations of pole
and zero of the equalizer. The high frequency asymptotic gain
boost is approximately:
Boost

(o)

Satisfying the condition in (5) minimizes the discontinuity

at the input and therefore minimizes the reflections (SI,)
across the frequency band of interest.

s+p

_a

((co)
o
HI

There is more group-delay variation at higher boost settings

where

I=WLl_ 2o

AG==H(C)

AGD

g(RE

Vcc

RL

RL

i3

3Q

The FFE consists of four cascaded stages of the boost

network. The peak boost occurs at 5-7GHz [3]. The FFE
provides 3-18dB of high frequency boost at 5GHz, for bits
settings of 000 to 111. The frequency response rolls off at
higher frequencies because of ever-present additional high
frequency poles of the circuit.
By changing the locations of the poles and zeros, it is
possible to match the magnitude of the equalizer's frequency
response to the inverse of the channel response with
reasonable accuracy. However, their phases will generally not
match well.
The non-linear phase of the overall frequency response of
the channel plus that of the FFE results in a non-uniform

frequency band of interest spans from approximately 1/20 of

the data rate (assuming that the longest string of consecutive
ones or zeros is 10 bits) to half of the baud rate (not
considering any harmonics). ..... 3
The group delay variation of the boost circuit, across this
band of interest can be approximated by:

M P-26-2

Q,

0-

INp

2RE

Q2

Nn

2R

CE/2
l

OiTn
b)

OLTp
lb

lb

lb.

Fig. 3. High frequency boost circuit.

=Q\H
Din

Cbig

Lhb-d

FEE

50Ll t
Fig. 4. Input interface.

286

''1'1
|
1-n

'-0 ,'

GK(1<

V\

It.lil20;

X IX

CL1

CILOt=

Fig. 5. DFE core block diagram.

VCC
$R i
>'

DIP

Dln D2

CKp 0-

Itapt)
Itap

At the rising edge of CK, when the decision do is about to be

the ISI contributions of the previous bits (decisions), d-l
.made,
d,
and d-2 should have been deducted from the input line, each
LW
LWwith a different weight, proportional to their ISI contributions.
ISI cancellation is performed in the current domain by using a
multiplexing tap circuit, shown in Fig. 6.
/
D muaor)
|
-The
multiplexing tap circuit works on both rising and falling
CElX
edges of the clock, and in fact is shared between the two
ap
<halves of the DFE core. The tap circuits use a slightly skewed
clock to allow the latches to settle, before the decisions are fed
back.
The DFE output (x,) can be approximated by:
i()(ldl+t -)pt
(6)
)
x1 + t2 d2
(6
where t1 and t2 are the tap weights, xi is the FFE output, d-l
and d-2 are the two previous binary decisions and p(t) is the
pulse response of the tap circuit.
The tap value is set by the tail current of the multiplexing
tap circuit. The sign of each tap, however, is fixed and is
based on the polarity of the connection of the multiplexing tap
circuit to the x0 node. The first post-cursor tap value is
assumed to be always negative. For the second post-cursor
D2n
cancellation, two multiplexing tap circuits are used to
accommodate both positive and negative tap values. The tap
values
depend on the channel pulse response. When the tap
C
values are optimized, the total jitter will be less on the x0
(1

compared to xi.

The half-rate implementation of the DFE core relaxes the

speed requirements of the sampling and feedback circuits. The
first post-cursor cancellation tap is the speed bottleneck,
because there is a very small amount of time (lOOps), after a
Fig. 6. Multiplexing tap
decision is made, to pass it through the feedback network and
deduct the ISI before the next sampling time. This period
VCC
includes the latch and tap circuit's settling time.
The resistor load in Fig. 5 and 6 is a common load shared by
all
circuits connected to the DFE output (x,).
> _>outitl
There is a multiplexer at the end of the DFE core, which
.i *Outp >
merges the decisions from the top rail with those on the
bottom rail to create a full-rate stream of binary data. This
retimed
Dp
Dn
C
output, along with the non-retimed DFE output (x,) is
buffered and is available off-chip.
The half-rate clock is generated by using a frequency
CKn
CKp
divider with an input clock synchronized to the data. Flipflops are back-to-back latches with inverted clocks. The high
lb e
speed latch is shown in Fig. 7.
The output drivers consist of successive stages of buffers
with the final one driving the 1OOQ differential load. The
and differential output swing is
output impedance is
7 Highspeedlatch
Fig.Fig.High
speed latch.
25OmV peak-to-peak. The buffer stages are ac-coupled to
decrease dc offset.
The FFE and DFE core consume 4mA and 7mA from a
B. Decision Feedback Equalizer
2.5V supply, respectively. The output drivers for the retimed
Fig. 5 illustrates the DFE block diagram. The data is
and non-retimed outputs consume 13mA each and the
sampled at both rising and falling edges of a half-rate clock,
clocking circuits consume 1 ImA. The chip size (including
(5GHz). Odd samples thus appear along the bottom rail, while
drivers) is 1.8xl.3mm2. Fig. 8 shows the die micrograph.
the even samples appear along the top rail. These decisions are
shifted with flip-flops so that they will be available for ISI
cancellation.
-

1OOQ

M P-26-3

287

Mesrehd eyietdiagrams at non-retimed output, 20" FR4. Left:

w~~~~~~~~~~~~~~~~ig.hu
10.

11

Fig 8.. Deio.ga.

..

=
The DFE cancellation decreases the total peak-to-peak jitter
Fig. 9ER
1. diagrams at
shsbether mhn 0-2 orth euaizd heMeasured
hane.
Fig.1eye

Cle_ Dislay opetiesAbor

s
10Gb/s. Theretimed output, 20" FR4.
thenon-retimedoutputeyediagramwithandwh D. a

of coppxma
ery
channelr s0
trc1o0npRsacpan.Thsi
TeFFE
boostcoantrol,
fabrcate ina
ismoat the loetsaettiong, whic preoviesin
BR
e than Die
eye diagrams at te r

T.

The

ish

fograthe

~f~eypIy
BiCMOS The DFE
1-ndr 0.25pm S~iG
d ou fr XIs, 2
.

Rer
uleclv
fln
Mredcnthtoa
~ cros-al atPrnAC..NOWLED...MENT.
PGRtB IOGOH DJRt:9.97
5GHzPRE
I
to0.73U1.alzr

h total
pektopa jite
DF1aclainSerae
~ ~
~
~
~ ~ ~
~~~~~~cne1to
~ ~
the
20"
from
nices
for
This is
n
thooiotaf
tor amps,iresutingio
i 1shows
Fig.e7dps
diarame
thperey
bchpannel.

from-al 0.37U1on tonae

eye-opening~~~~~~~~~~~~~

paottr generatr ussax pseum 1dorno bit seqenc With thE

aprxmtl
of
FEi esigned andhig
anpsA 10Gb/s equealier withfFEmandc dmo
jitter~~~~~
For lthis,chanelaolmosttesaeaouto
iG
iMS h
eye-opening fabricatom0.UI
sp edsrainkastadr..5i
F
c lsnd iof bka EN i
Fig. 10 shows the eye diagram for Te20" tche. The FE
0
............... .............

: :. . : :. . . . . .
........................................ S:

the retimed output, so there will be no and.

The jitter on this
output is contributed by the clock jitter and the output driver.
The driver jitter due to the noise and bandwidth limitations Of
the chip/board interface is approximately i0ps.

The authors thank National Semiconductor Labs members,

Jerry Socci and Yongseon Koh for their help and support.
REFERENCES

[1] R. Payne, et al., "A 6.25Gb/s Binary Adaptive DFE with First Post-Cursor

W-A; ~~~~~of Technical Papers, pp. 68-69, Feb. 2005.

TheDFEcancellationdecreasesthet[]aAVrzghai,C.aan,i"t/.....
from

to27psresultingn

hi.

Fig. 9. Measured eye diagrams at non-retimed output, 10" FR4. Left:

without DFE; Right: with DFE.

M P-26-4

a et a

.....4

s reiv

wiDth

e...r An.a.....r

e ad O

Monitor in 0.1 pm CMOS," Symposium on VLSI Circuits Digest of

TechnicalPapers, pp. 202-205, June2004.

288