MTP75N03HDL

Preferred Device

Power MOSFET
75 Amps, 25 Volts, Logic Level
NChannel TO220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a draintosource diode with a fast recovery time. Designed for
lowvoltage, highspeed switching applications in power supplies,
converters and PWM motor controls, and inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional
safety margin against unexpected voltage transients.
SPICE Parameters Available
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified

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75 AMPERES
25 VOLTS
RDS(on) = 9 m
NChannel
D

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Symbol

Value

Unit

DrainSource Voltage

VDSS

25

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

25

Vdc

VGS

15
20

Vdc
Vpk

75
59
225

Adc

PD

150
1.0

Watts
W/C

TJ, Tstg

55 to
175

EAS

280

mJ

Rating

GateSource Voltage
Continuous
Single Pulse (tp 10 ms)
Drain Current Continuous
Continuous @ 100C
Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Operating and Storage Temperature
Range
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
IL = 75 Apk, L = 0.1 mH, RG = 25 )
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8 from case for 10
seconds

ID
ID
IDM

MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain

Apk
TO220AB
CASE 221A
STYLE 5
1

MTP75N03HDL
LLYWW
1
Gate

2
Drain

C/W
RJC
RJA

1.0
62.5

TL

260

3
Source

MTP75N03HDL
LL
Y
WW

= Device Code
= Location Code
= Year
= Work Week

ORDERING INFORMATION
Device

Package

Shipping

MTP75N03HDL

TO220AB

50 Units/Rail

Preferred devices are recommended choices for future use

and best overall value.

Semiconductor Components Industries, LLC, 2000

September, 2004 Rev. XXX

Publication Order Number:

MTP75N03HDL/D

MTP75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Symbol

Characteristic

Min

Typ

Max

25

Unit

OFF CHARACTERISTICS
(Cpk 2.0) (Note 3.)

DrainSource Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mA)
Temperature Coefficient (Positive)

V(BR)DSS

Vdc
mV/C

Zero Gate Voltage Drain Current

(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V)

IGSS

Adc

100
500

100

1.0

1.5

2.0

nAdc

ON CHARACTERISTICS (Note 1.)

Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mA)
Temperature Coefficient (Negative)

(Cpk 3.0) (Note 3.)

Static DrainSource OnResistance

(VGS = 5.0 Vdc, ID = 37.5 Adc)

(Cpk 2.0) (Note 3.)

VGS(th)

Vdc
mV/C

RDS(on)

DrainSource OnVoltage (VGS = 10 Vdc)

(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125C)

6.0

9.0

0.68
0.6

gFS

15

55

mhos

Ciss

4025

5635

pF

Coss

1353

1894

Crss

307

430

td(on)

24

48

VDS(on)

Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance

(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2.)
TurnOn Delay Time
Rise Time
TurnOff Delay Time

(VDS = 15 Vdc, ID = 75 Adc,

VGS = 5.0
5 0 Vdc,
Vdc
Rg = 4.7 )

Fall Time
Gate Charge
(VDS = 24 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc)

tr

493

986

td(off)

60

120

tf

149

300

QT

61

122

Q1

14

28

Q2

33

66

Q3

27

54

0.97
0.87

1.1

trr

58

ta

27

tb

30

QRR

0.088

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage

(IS = 75 Adc, VGS = 0 Vdc)

(IS = 75 Adc, VGS = 0 Vdc,
TJ = 125C)

Reverse Recovery Time

(IS = 75 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge
1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values.
Max limit Typ
Cpk =
3 x SIGMA

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2

VSD

Vdc

ns

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS

VGS = 10 V

5V

8V

120

4.5 V

150

TJ = 25C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

150

4V

6V

90
3.5 V
60
3V

30

VDS 10 V

120

90
60
100C

TJ = 55C

2.5 V
0

0.2

0.4 0.6 0.8

1
1.2
1.4 1.6
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.8

0
1.5

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

TJ = 100C

25C

0.006

55C
0.004

0.002

30

60

90

120

2
2.5
3
3.5
4
VGS, GATETOSOURCE VOLTAGE (VOLTS)

4.5

Figure 2. Transfer Characteristics

VGS = 5 V

0.008

150

0.009
TJ = 25C
0.008

0.007

VGS = 5 V

0.006
10 V
0.005
0.004

ID, DRAIN CURRENT (AMPS)

75
50
100
ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

25

10000

1.6

1.2
0.8

0.4

125

150

TJ = 125C

VGS = 10 V
ID = 37.5 A
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE

(NORMALIZED)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

0.01

25C

30

100C

1000

100

10
25C
VGS = 0 V

50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with

Temperature

5
10
15
20
25
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

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3

30

MTP75N03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
15000

C, CAPACITANCE (pF)

12000

VDS = 0 V

VGS = 0 V

TJ = 25C

Ciss

9000
Crss
Ciss

6000

Coss

3000
0
10

Crss
5

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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4

28

24
QT
20

5
Q2

Q1

VGS
16
12

3
TJ = 25C
ID = 75 A

1
0

4
VDS

Q3
0

10

50
20
30
40
QT, TOTAL GATE CHARGE (nC)

60

0
70

10000

t, TIME (ns)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP75N03HDL

tr

1000

tf
td(off)

100

10

TJ = 25C
ID = 75 A
VDD = 15 V
VGS = 5 V

td(on)

10

100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

high di/dts. The diodes negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

I S , SOURCE CURRENT (AMPS)

75
TJ = 25C
VGS = 0 V

60
45

30
15
0
0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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5

MTP75N03HDL
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
Transient
Thermal
ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 s. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) TC)/(RJC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

280

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE

AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

100
100 s
1 ms

10

10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

1
0.1

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
nonlinearly with an increase of peak current in avalanche
and peak junction temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.

dc

200
160
120
80
40
0
25

100

10

ID = 75 A

240

50

75

100

125

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

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6

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

1.0

0.1

D = 0.5

0.2
0.1
P(pk)

0.05
0.02

t1

0.01

SINGLE PULSE
0.01
1.0E05
1.0E04

t2
DUTY CYCLE, D = t1/t2
1.0E03

1.0E02

1.0E01

t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

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7

RJC(t) = r(t) RJC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

MTP75N03HDL
PACKAGE DIMENSIONS
TO220 THREELEAD
TO220AB
CASE 221A09
ISSUE AA

SEATING
PLANE

T
B

F
T

DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

Q
1 2 3

H
K
Z
L

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

G
D
N

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

STYLE 5:
PIN 1.
2.
3.
4.

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

GATE
DRAIN
SOURCE
DRAIN

ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
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MTP75N03HDL/D

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