Ask The Applications Engineer 24-40

ANALOG DEVICES TECHNICAL REFERENCE BOOKS
Published by Analog Devices

Nonlinear Circuits Handbook
Transducer Interfacing Handbook
Mixed-Signal Design Seminar Notes
Amplifier Applications Guide
System Applications Guide
Linear Design Seminar Notes
Practical Analog Design Techniques
High-Speed Design Seminar Notes
ADSP-21000 Family Applications Handbook
Published by Prentice Hall (available from Analog Devices)
Analog-Digital Conversion Handbook
Digital Signal Processing in VLSI
DSP Applications Using the ADSP-2100 Family (Vols. 1 & 2)
Ask The Applications Engineer

Analog Devices, Inc., 1997
All rights reserved
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ii
30th Anniversary Reader Bonus
TABLE OF CONTENTS
Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
1. Multi troubles, Trouble from the start, About log compensation resistors . . . . . . . . . . . . . James Bryant
2. When it comes to trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant
3. V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant
5. Used correctly, high-speed comparators provide many useful circuit functions . . . . . . . . . . John Sylvan
6. Op-amp issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant
7. Op-amp issuesNoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant 10

8. Op-amp issuesNoise (continued), How grainy is current flow? . . . . . . . . . . . . . . . . . . . James Bryant 12
9. Seminars and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chris Hyde 14
Supply decoupling, non-idealities of resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant 14
10. PC-board tracks and ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant 16
11. Voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant 18
12. Grounding (again) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Walt Kester 20
Time references, More on Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant 22
13. Confused about amplifier distortion specs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Walt Kester 23
14. High-frequency signal contamination . . . . . . . . . . . . . . . . . . . . . . James Bryant, with Herman Gelbach 26
A Reader Notes (re-High-frequency signal contamination) . . . . . . . . . . . . . . . . . . . . . . . . Leroy Cordill 28
15. Using sigma-delta converters, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oli Josefsson 29
16. Using sigma-delta converters, part II, and questions on noise in converters . . . . . . . . . . . Oli Josefsson 33
17. Must a 16-bit converter be 16-bit monotonic and settle to 16 ppm? . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dave Robertson and Steve Ruscak 39
18. Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peter Checkovich 40
19. Interfacing to serial converters, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eamon Nash 42
20. Interfacing to serial converters, part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eamon Nash 44
21. Capacitance and capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Steve Guinta 46
22. Current-feedback amplifiers, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erik Barnes 50
23. Current-feedback amplifiers, part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erik Barnes 52
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
Ask The Applications Engineer1

by James Bryant
MULTI TROUBLES
Q. My multiplexed ADC system is misbehaving . . .
A. Before you go any further, have you grounded all unused
multiplexer channels?
Q. No. But how did you know?
A. Because the floating terminal is one of the commonest causes
of problems in systems containing CMOS multiplexers.
Unused MUX inputs and outputs (whether integrated into a
multiplexed ADC or part of a self-contained MUX chip) can
pick up signals from stray fields and inject them into the
devices substrate, turning on spurious substrate devices.
Then, even when the unused channel is turned off, the
performance of the on-channel may be badly degraded (at the
unlikely extreme, the injection may turn on a spurious fourlayer device and destroy some chips).
Whenever a MUX is used, all its inputs and outputs must be
connected to a potential between its supply rails. The best way to
deal with unused channels is to ground them, but they may be
connected to a more-convenient potential within the rails. b
TROUBLE FROM THE START

Q. To save power, my ADC is powered up only to make a measurement.
The system is very accurate in continuous operation, but
unpredictable when power is strobed. Why?
A. When an ADCs power is switched on only to perform a
conversion, it may misbehave for three reasons: slow reference
turn-on, random initial logic states, and system latch-up.
For various reasonsthermal stabilization, capacitance
charging, slow starting of regenerative current mirrors using
PNP transistors in band-gap references it is not uncommon
for some voltage references to have relatively large errors for
many milliseconds after power-up. Such errors in an ADCs
external or internal reference during conversion lead to
inaccurate results.
Busy signal is always present on power-up the problem is almost

certain to be recognizedand addressedduring the design
of the system; but if the Busy signal is only occasionally present
on power-up the system may latch unpredictably. As a rule,
control signals to an ADC during start-up should not depend
b
on the logical state of Busy.
ABOUT LOG COMPENSATION RESISTORS

Q. Designs of logarithmic circuits*, including those using the AD538
Y[Z/X] m unit: (for example, Figure 6 from the AD538
Multifunction Unit data sheet) call for kT/q compensation
resistors. What are they and where do I get them?
A. The VBE difference across two opposed silicon junctions,
one carrying a current, I, and the other a current, IREF, is
(kT/q) ln (I/IREF). Here, k/q is the ratio of Boltzmanns constant
to the charge on an electron (about 1/11,605 K/V), and T is
the absolute temperature in kelvins.
Although employing similar junctions in isothermal pairs
eliminates the effects of temperature-sensitivity of reverse
saturation current, the kT/q term is still temperature-dependent.
To eliminate this dependency in the application, the
logarithmic voltage must be used in a circuit whose gain is
inversely proportional to the absolute temperature of the
junctions. Over a reasonable range of temperatures near
20C, this may be arranged by the use of a gain-setting 1-k
resistor having a positive temperature coefficient of
approximately 3,400ppm/Cand keeping it at the same
temperature as the junctions.
A 3,500 ppm/C resistor is available from Tel Laboratories,
154G Harvey Road, Londonderry, New Hampshire 03053
(603)-625-8994, Telex: (710)-220-1844, designated Q-81, and
from the Precision Resistor Co. Inc., 10601, 75th. St., Largo,
Florida 33543 [(813)-541-5771 Telex: 821788], as the PT146.
Analog Devices offices in most European countries are aware
b
of local suppliers of these resistors.
At turn-on, a typical ADCs logic will be in a random state; for

a conversion triggered at that time, the ADC may not be able
to perform correctly. With one conversion triggered, the logic
should return to its correct pre-conversion statebut cases
exist where two conversion cycles are necessary before the ADC
is certain to perform a valid conversion. Hence, a good general
rule is to perform two dummy conversions after powerup
before relying on the results. (It is also well to recall that some
ADCs react badly to having a conversion triggered before the
previous conversion is complete; when this happens, one or
two dummy conversions may be needed to return the logic
to a known state.)
If an ADCs external logic is arranged so that the end of the
ADC Busy signal starts a delay which ends with the start of
the next conversion, it is important to realize that if the
converter powers up in the Busy state, the Busy signal may
remain latched up until a conversion Start pulse has been
received. In this case, such a system cannot self-start. If the
Analog Dialogue 22-2 (1988)
*Much useful information about logarithmic and other analog function

circuits can be found in the Nonlinear Circuits Handbook, published by
Analog Devices ($5.95), P.O. Box 9902, Norwood MA 02062.
See The Best of Analog Dialogue 19671991, pp. 164-167.
of full-scale range). Depending on the architecture used, this

bipolar offset (BOS) may or may not be affected by the gain
trim. If it is so affected, equation (1) becomes:
by James Bryant
OP = K (IP BOS)
WHEN IT COMES TO TRIMMING . . .

Q. I need some advice about trimming offsets and gains.
A. Dont!unless you must. Good alternatives include (a) using
headache-free devices, components, and circuits that meet the
specs without trimming; (b) taking advantage of digital
technology in system applications to make trim corrections in
software. Savings provided on occasion by trim potentiometers,
in conjunction with loosely specd devices, can turn out to be
illusory when you consider the effects of circuit design,
temperature, vibration, and life on performance and stability
as well as additional paperwork and complexity trimming
entails.
Q. Nevertheless, how do I trim the offset and gain errors in analog
circuitry?
A. In the correct order and with the correct inputs. If you consider
the transfer characteristic of the circuit being trimmed the
method to use is generally straightforward.
The simplified ideal transfer characteristic of a linear analog
circuit (such as an amplifier, ADC or DAC) is given by the
equation:
OP = K IP
(1)
where OP is output, IP is input, and K is a scale factor (Note

that this simplification hides an enormous number of issues:
quantization error in an ADC; dimensionality of K if the input
and output are in different forms [e.g. voltage in / current out];
intentional offsets; and many others.)
In a real (non-ideal) circuit, offset and gain errors, OS (referred
to the input) and K, respectively, also appear in the equation,
which becomes:
OP = (K + K) (IP + OS)
(2)
OP = (K IP) + [(K OS) + (K IP) + (K OS)]
(3)
Equations (2) and (3) are incomplete in that they assume only
one offsetat the inputbut this is the most-common case.
Systems with separate input and output offsets will be
considered later.
From (3) we see that it not possible to trim gain directly when
an unknown offset is present. Offset must be trimmed first.
With IP set at 0, the offset trim is adjusted until OP is also 0.
Gain may then be trimmed: with an input near to full scale
(FS), the gain trim is adjusted to make the output obey
equation (1).
Q. But what about bipolar ADCs and DACs?
A. Many ADCs and DACs may be switched between unipolar
and bipolar operation; such devices, wherever possible, should
have their offset and gain trimmed in the unipolar mode.Where
it is not possible, or where the converter is to operate only in
the bipolar mode, other considerations apply.
A bipolar converter may be considered as a unipolar converter
with a large offset (to be precise, an offset of 1 MSBone-half
(4)
In this case offset is trimmed at analog zero, after which gain is

trimmed near FSpositive or negative, but usually positive.
This is normally the method used for DACs where the bipolar
offset is within the DAC.
If the bipolar offset is not affected by the gain trim:
OP = K IP BOS
(5)
Here offset is trimmed at FS negative and gain is trimmed at

(or very near tosee below) FS positive. This method is used
for most ADCs and for DACs where bipolar offset is obtained
by the use of op amps and resistors external to the DAC.
Naturally, the method suggested on the data sheet should
always be followed, but where a data sheet is unobtainable, in
general, offset should be trimmed at analog zero for DACs
and FS negative for ADCsand near FS positive for both.
Q. Why do you keep saying near to full scale?
A. Amplifiers and DACs may be trimmed at zero and full scale.
In the case of a DAC, all-1sthe largest digital input
possibleshould produce an output 1 LSB below full scale,
where full scale is considered as some constant times the
reference; this follows since the output of a DAC is the
normalized product of the reference and the digital input.
ADCs are not trimmed at zero and FS. The output of an
ideal ADC is quantized, and the first output transition (from
00 . . . 00 to 00 . . . 01) takes place 1/2 LSB above the nominal
value of all 0s. Thereafter transitions take place every 1-LSB
increase in analog input until the final transition takes place
1 1/2 LSB below FS. A non-ideal ADC is trimmed by setting
its input to the nominal value of a desired transition and then
adjusting until the ADC output flickers between the two values
equally.
The offset of an ADC is therefore trimmed with an input
corresponding to the first transition (i.e., 1/2 LSB above zero
or above FS negativewhich is near zero or near FS
negative); and the gain is then trimmed at the last transition
(i.e. 1 1/2 LSB below FS positivewhich is near FS positive).
This procedure results in an interaction between the gain and
offset errors during offset trim but it should be too slight to be
significant.
Q. Are there any other anomalies resulting in a need to trim near,
rather than at full scale?
A. Synchronous voltage-to-frequency converters (SVFCs) are
liable to injection locking phenomena when their output
frequency is harmonically related to their clock frequency,
i.e., when their output is very close to 1/2, 1/3 or 1/4 of
clock frequency. FS for an SVFC is 1/2 clock frequency.
The presence of a trim tool can exacerbate the problem. It
is therefore advisable to trim the gain of an SVFC at around
95% of FS.
Ask The Applications Engineer 2

Q. What about circuits requiring both input and output offset
trim?
A. Circuits such as instrumentation and isolation amplifiers often
have two stages of dc gain, and the gain of the input stages can
be variable. Thus a two stage amplifier, with an input offset,
IOS, an output offset, OOS, a first stage gain of K, and a
unity-gain output stage, has (for zero input) an output, OP,
of:
OP = OOS + K IOS
(6)
From (6) it is evident that if the gain is constant we need only

adjust either IOS or OOS to null the total offset (although if
the input uses a long-tailed pair of bipolar transistors we will
get a better offset temperature coefficient if we trim bothfor
FET long-tailed pairs this is not necessarily the case). If the
first stage gain is to be varied, both offsets must be trimmed.
This is done by an iterative procedure. With zero input, and
gain set to maximum, the input offset is adjusted until the
output is also zero. The gain is then reduced to its minimum
value and the output offset adjusted until the output is zero
again. The two steps are repeated until no further adjustment
is necessary. Gain trimming should not be done until both
IOS and OOS are pulled; the actual values of the high and low
gains used in offset trim are unimportant.
Q. What circuitry should I use for gain and offset trims?
A. Many amplifiers (and a few converters) have terminals for
trimming gain and offset. Many more do not.
Offset trim is normally performed with a potentiometer
connected between two assigned terminals, and its wiper is
connected (sometimes via a resistor) to one of the supplies.
The correct connections and component values will be given
on the device data sheet. One of the commonest differences
between op-amps is the value of offset correction potentiometer
and which supply it should be connected to.
Where separate terminals are not provided for offset trim, an
offset-adjusting constant can usually be added to the input
signal. Two basic possibilities are shown in Figures 1a and 1b.
Where the correction is being made to a system where a
differential input op amp is used as an inverter (the commonest
case) the method of la is best to correct for device offsetsbut
not system offsets. In the single-ended connection, method 1b
will work for system offsets but should be avoided where
possible for small device offsets, because it often requires a
very large value of summing resistance, compared to the

signal-input resistances, in order to (i) avoid loading the
summing point excessively, (ii) scale the correction voltage
properly and produce enough attenuation to minimize the
effects of differential supply-voltage drifts. It is often helpful
to use resistances between the supplies and the potentiometer
to increase trim resolution and reduce dissipation.
Where gain trim is provided for in a circuit, it will generally
consist of a variable resistor. Details of its value and connection
will appear on the data sheet of the device. Where gain trim is
not required, this resistor may be replaced by a fixed resistor
having half the resistance of the maximum value of the
recommended trim potentiometer.
Where gain trim is not provided it is not always achievable
externally without an additional variable-gain stage. For
example, consider a DAC using a ladder network. If the ladder
network is used in the current mode (Figure 2a), the input
impedance at the reference terminal does not vary with digital
code, and the gain of the DAC may be trimmed with a small
variable resistor in series with either the reference input or the
feedback resistor. However, if the DAC is used in the voltage
mode (Fig 2b), then the reference input impedance is code
dependent, and gain may only be trimmed by varying the
reference voltagewhich is not always possibleor the gain
of the buffer amplifier.
The possibility of trimming gain in circuits not furnished with
gain-trim circuitry, therefore, will depend on individual cases;
b
each must be assessed on its own merits.
a. CMOS DAC connected for current steering. Input impedance is constant.
a. Voltage applied to non-inverting input.
b. Current summed at inver ting input.

Figure 1. Two connections for offset adjustment.
b. The same DAC connected for voltage output.

Figure 2. Comparing basic DAC circuits.

by James Bryant
V/F CONVERTERS
Q. How do I send an analog signal a long distance without losing
accuracy?
A. An excellent solution to this common problem is to ship the
signal as frequency using a voltage-to-frequency converter (VFC),
a circuit whose output is a frequency proportional to its input.
It is relatively easy to send a frequency signal over a long
transmission path without interference via optical isolators,
optical fibre links, twisted-pair or co-axial lines, or radio links.
If the data must be digital, the receiver will consist of a
frequency counter, easily implemented in a single-chip microcomputer. Frequency is reconverted to analog voltage by a
frequency-to-voltage converter (FVC)generally a VFC
configured to perform its inverse function, often using a
phase-locked loop.
Q. What are the advantages and disadvantages of the two types?

A. The multivibrator is simple and cheap, demands little power,
and has unity mark-space (M-S) outputvery convenient with
some transmission media. But it is less accurate than the
charge-balance type and cannot integrate negative input
transients.
The charge-balance type is more accurate, and negative input
transients are integrated to contribute to the output. It has
more-demanding supply requirements and a lower input
impedance, and its output is a pulse train, not a unity M-S
square wave.
Q. What are the important types of error in a VFC?
Q. How does a VFC work?

A. There are two common types: multivibrator-(AD537) and
charge-balance (AD650) VFCs.*
In the multivibrator type, the input voltage is converted to a
current which charges and discharges a capacitor. The switching
thresholds are set by a stable reference, and the output, which
has unity mark-space ratio, is a frequency proportional to the
input.
The charge-balance VFC uses an integrator, a comparator and
a precision charge source. The input is applied to the integrator,
which charges. When the integrator output reaches the
comparator threshold, the charge source is triggered and a fixed
charge is removed from the integrator. The rate at which charge
is removed must balance the rate at which it is being supplied,
so the frequency at which the charge source is triggered will
be proportional to the input to the integrator.
A. The same three as in most precision circuitry: offset errors,

gain errors and linearity errorsand their variation with
temperature. As with most precision circuitry, offset and gain
can be trimmed by the user, but linearity cannot. However,
the linearity of VFCs is normally very good (if the capacitors
are properly chosensee below).
Q. How do you trim gain and offset in a VFC?
A. The procedure suggested by theory is to trim offset first at
zero frequency and then gain at full scale (FS). But this can
give rise to problems in recognizing zero frequency, which is
the state when the VFC is just not oscillating. It is therefore
better to trim offset with a small input (say 0-1% FS) and
adjust for a nominal frequency, then trim gain at FS, and then
repeat the procedure once or twice.
For example, suppose a VFC is being used with FS of 100 kHz
at 10-volt input. Ideally, 10 V should give 100-kHz output and
10-mV input should give 100 Hz. Offset is, therefore, trimmed
for 100 Hz with 10 mV applied; gain is then trimmed to give
100 kHz at 10 V. But gain error affects the 10-mV offset trim
slightly, so the procedure may have to be repeated to reduce
the residual error.
If a VFC is used with software calibration a deliberate offset is
often introduced so that the VFC has a definite frequency for
zero input voltage. The microcomputer measures the VFC
outputs at 0 V and FS inputs and computes the offset and
scale factor. It may also be necessary to reduce the gain so that
the VFC cannot try to exceed its maximum rated frequency.
*Data sheets are available for any of the Analog Devices products mentioned
here. An Application Note: Operation and Applications of the AD654 V-to-F
Converter, is also available without charge.

Q. What circuit precautions are necessary when using a VFC?
A. Apart from the usual precautions necessary with any precision
analog circuitry (grounding, decoupling, current routing,
isolation of noise, etc., a subject for a book, not a paragraph)
the main precautions necessary when using a VFC are the
choice of capacitor and separation of the input and output.
The phase-locked-loop FVC illustrated differs from any other

PLL in only one respect: the voltage-controlled oscillator of
the normal PLL, which must be monotonic but not necessarily
linear, has been replaced by a VFC with a linear control law.
In the servo system, negative feedback keeps the VFCs output
frequency equal to the input frequency. The output voltage,
the VFCs input, is accurately proportional to the input
frequency.
The critical capacitors in a precision VFC (the multivibrators

timing capacitor, and the monostable timing capacitor in a
charge-balance type) must be stable with temperature variation.
Furthermore, if they suffer from dielectric absorption, the VFC
will be nonlinear and may have poor settling time.
Designing PLL systems is beyond the scope of this discussion,1

but if a 4000-series CMOS PLL, the 4046, is used just as a
phase detector (its VCOs transfer characteristic is not sufficiently
linear), we can build the FVC shown here, with an AD654
VFC.
If a capacitor is charged, discharged and then open-circuited

it may recover some charge. This effect, known as dielectric
absorption (DA), can reduce the precision of VFCs or samplehold amplifiers using such capacitors. VFCs and SHAs should
therefore use Teflon or polypropylene, or zero- temperaturecoefficient (NPO, COG) ceramic capacitors with low DA.
Coupling between output and input of a VFC can also affect
its linearity. To prevent problems, decoupling practices and
the usual layout precautions should be observed. This is
critically important with opto couplers, which require high
current drive (10-30 mA).
Q. How do you make a frequency-to-voltage converter?
A. There are two popular methods: the input frequency triggers
the monostable of a charge-balance VFC that has a resistor in
parallel with its integration capacitor; or the input frequency
can be applied to the phase/frequency comparator of a phaselocked loop (PLL), which uses a VFC (of either type) as its
oscillator. The basic principle of the first type is illustrated
below.
Q. What is a synchronous VFC?

A. A charge-balance VFC with improved linearity and stability,
where the monostable is replaced by a bistable, driven by an
external clock. The fixed time during which the precision
current discharges the integrator is one clock period of the
external clock.
A further advantage of the SVFC is that the discharge does
not start when the integrator passes the comparator threshold
(at a non-critical rate), but on the next clock cycle. The SVFC
output is synchronous with a clock, so it is easier to interface
with counters, Ps, etc.; it is especially useful in multichannel
systems: it eliminates problems of interference from multiple
asynchronous frequency sources.
There are two disadvantages. Since the output pulses are
synchronized to a clock they are not equally spaced but have
substantial jitter. This need not affect the user of a SVFC for
a/d conversion, but it does prevent its use as a precision
oscillator. Also, capacitive coupling of the clock into the
comparator causes injection-lock effects when the SVFC is at
2/3 or 1/2 FS, causing a small (4-6 bit at 18-bit resolution at
1-MHz clock) dead zone in its response. Poor layout or device
design can worsen this effect.
For each cycle of the input frequency, a charge, Q, is delivered

to the leaky integrator formed by R and C. At equilibrium, an
equal charge must leak away during each period, T (= 1/f), of the
input, at an average rate, I = V/R. Thus, V = Q?f?R.
Though the mean voltage is independent of C, the output ripple
is inversely dependent on C. The peak-to-peak ripple voltage,
V, is given by the equation, V= Q/C. This indicates that
ripple is independent of frequency (assuming that the charge,
Q, is delivered in a short time relative to the period of the
input). The settling time of this type of FVC is determined by
the exponential time constant, RC, from which the time to
settle within a particular error band may be calculated.
From these equations, we see that the characteristics of this
type of FVC are interdependent, and it is not possible to
optimize ripple and settling time separately. To do this we
must use a PLL.
Despite these difficulties the improvement in performance

produced by the abolition of the timing monostable makes the
SVFC ideal for the majority of high-resolution VFC
applications.
Q. Can you have a synchronized FVC?
A. Yes, and with very good performance; it is best done with an
FVC- connected SVFC and a clock that is common to both
ends of the transmission path. If the input signal to a
synchronized FVC is not phase related to the clock, severe
timing problems can arise, which can only be solved by the
use of additional logic (two D flip-flops) to establish the correct
b
phase relationship.
1
See Gardner, F. M, Phase-lock Techniques, 2nd ed., New York: Wiley, 1979, for
more detail; also Analog Devices Analog-Digital Conversion Handbook.

High-speed comparators provide many useful circuit
functions when used correctly.
by John Sylvan
Question: Why cant I just use a standard op amp in a high-gain or
open-loop configuration as a voltage comparator?
You canif you are willing to accept response times in the tens of
microseconds. Indeed, if in addition you require low bias-currents,
high-precision and low offset voltages, then an op amp might be a
better choice than most standard voltage comparators. But since
most op amps have internal phase/frequency compensation for
stability with feedback, its difficult to get them to respond in
nanoseconds. On the other hand, a low-cost popular comparator,
the LM311, has a response time of 200 ns.
For example, after a high-to-low transition on the AD790, its

built-in hysteresis requires the input voltage (positive input) to
increase by 500 V to produce a low-to-high transition.
If my comparator does not have internal hysteresis, can I add it
externally?
Yes, with external positive feedback. This is done by feeding a
small fraction of the output of the comparator back to the positive
input. This simple technique is shown in Figure 1. The hysteresis
voltage from the lower transition point to the upper transition point
will depend on the value of the feedback resistor, RF, the source
resistance, RS, low output level, Vlow and high output level, Vhigh.
The low and high transition points are set by:
V low
RS
RS
and V high
RS + RF
RS + RF
Also the output of an operational amplifier is not readily matched

to standard logic levels. Without external clamping or level-shifting,
an op amp operating as a comparator will swing to within a few
volts of the positive and negative supplies, which is incompatible
with standard TTL or CMOS logic levels.
My comparator oscillates uncontrollably.Why does this happen?
Examine the power-supply bypassing. Even a few inches of PC
trace on the supply lines can add unacceptable dc resistance and
inductance. As a result, transient currents while the output is
switching may cause supply-voltage fluctuations, which are fed
back to the input through the ground and supply lines. Install
low-loss capacitors (0.1F ceramic capacitors) as close as possible
to the supply pins of the comparator to serve as a low-impedance
reservoir of energy during high-speed switching.1
Ive installed bypass capacitors, but I still cant keep my high-speed
comparator from oscillating. Now whats the problem?
Figure 1. Applying external hysteresis to a comparator.

Figure 2 shows how adding external hysteresis can clean up a
comparators response. Figure 2a shows the response of a
comparator with bipolar output swing without hysteresis. As the
triangular-wave input (trace A) passes through the transition point
(ground), the device oscillates vigorously (and couples a portion
of the oscillation into ground and the signal-source). Figure 2b
depicts the response of the same comparator with 5 mV of external
hysteresis applied; it shows a much cleaner transition.
It could be the comparators ground connection. Make sure that

the ground lead is as short as possible and connected to a lowimpedance ground point to minimize coupling through lead
inductance. Use a ground plane if possible and avoid sockets.
5V
COMPARATOR
OUTPUT
Another cause of the oscillation may be a high source impedance

and stray capacitance to the input. Even a few thousand ohms of
source impedance and picofarads of stray capacitance can cause
unruly oscillations. Keep leads short, including the ground clip of
your scope probe. For best measurement results use the shortest
possible ground lead to minimize its inductance (< 1").
With a slowly moving input signal, my comparator seems to chatter
as it passes through the transition voltage.Why cant I obtain a single
clean transition from the device?
A comparators high gain and wide bandwidth are typically the
source of this problem. Any noise is amplified, and as the signal
passes through the transition region, the noise can cause a fastresponding amplifiers output to bounce back and forth. Also,
since the devices sensitivity (i.e., gain) is higher during a transition,
the tendency to oscillate due to feedback increases. If possible,
filter the signal to minimize noise accompanying it. Then try
using hysteresis which, like backlash in gear trains, requires the
input to change by a certain amount before a reversal occurs.
1
A useful discussion of comparator foibles can be found in Troubleshooting

Techniques Quash Spurious Oscillations, by Bob Pease, EDN, September 14,
1989, pp. 152-6
14Hz 1V pk-pk
TRIWAVE
No external hysteresis
5V
COMPARATOR
OUTPUT
14Hz 1V pk-pk
TRIWAVE
5 mV external hysteresis
Figure 2. Hysteresis helps clean up comparator response.

A problem encountered with external hysteresis is that output
voltage depends on supply voltage and loading. This means the
hysteresis voltage can vary from application to application; though
this affects resolution, it need not be a serious problem, since the
hysteresis is usually a very small fraction of the range and can
tolerate a safety margin of two or three (or more) times what one
might calculate. Swapping in a few comparators can help
confidence in the safety margin. Dont use wirewound resistors
for feedback; their inductance can make matters worse.
Whats the difference between propagation delay and prop-delay
dispersion? Which of the two specifications is of most concern?
Propagation delay is the time from when the input signal crosses
the transition point to when the output of the comparator actually
switches. Propagation-delay dispersion is the variation in prop delay
as a function of overdrive level. If youre using a comparator in
pin-drive electronics in an automatic test system, then prop-delay
dispersion will determine the maximum edge resolution. In
contrast, propagation delay can be considered as a fixed time offset
and therefore compensated for by other techniques.
I have a +5-volt system and dont want to add an additional supply
voltage; can I use my comparator with a single supply?
Yes, but to establish the threshold use an adequately bypassed
stable reference source well within the common-mode range of
the device. The signal level is also to be referenced to this source.
Can you suggest a circuit that performs autozeroing when the comparator
is off-line to minimize drift?
Try the circuit shown in Figures 3 and 4. In the Calibrate mode,
the input is disconnected and the positive input of the comparator
is switched to ground. The comparator is connected in a loop with
a pair of low-voltage sources of opposing polarity charging a
buffered capacitor in response to the comparators output state.
If the comparators minus input terminal is above ground, then
the comparator output will be low, the 1-F capacitor will be
connected to the negative voltage (365 mV) and the voltage from
the buffer amplifier will ramp down until it is below the plus input
(ground)plus hysteresis and any offsetsat which point the
comparator switches. If it is below ground, the comparators output
will be high, the capacitor will be connected to the positive voltage
(+365 mV), the output from the buffer amplifier ramps up. In the
final state, each time the comparator switches (when the ramped
change exceeds the hysteresis voltage), the polarity of the current
is reversed; thus the capacitor voltage averages out the offsets of
the buffer and comparator.
At the end of the Calibrate cycle, the JFET switch is opened, with
the capacitor charged to a voltage equal to the offsets of the
comparator and buffer the hysteresis voltage. At the same time,
the Calibrate signal goes low, disabling the feedback to the polarity
b
switch and connecting the input signal to the comparator.
I sometimes see unexpected behavior in my comparator.What could be

the cause of this problem?
Examine the common-mode range of the input signal. Unlike
operational amplifiers, that usually operate with the input voltages
at the same level, comparators typically see a large differential
voltage swings at their inputs. If the inputs exceed the devices
specified common-mode range (even though within the specified
signal range), the comparator may respond erroneously. For proper
operation, ensure that both input signals do not exceed the
common-mode range of the specific comparator. For example,
the AD790 has a +VS differential input range, but its commonmode range is from VS to 2 volts below +VS.
COMPARATOR
OUTPUT
0-VLOGIC
VOLTAGE AT
AD790 INPUT
TERMINAL
5V ph-ph
TRIWAVE (5kHz)
(AD790 +INPUT)
Figure 4. Comparator output, buffer output, and comparator

input.
Figure 3. Autozeroed comparator integrates out offsets during calibration cycle.

by James Bryant
OP-AMP ISSUES
Q. Why are there so many different types of operational amplifier?
A. Because there are so many parameters that are important in
different applications, and because it is impossible to optimize
all of them at once. Op amps may be selected for speed, for
noise (voltage, current or both), for input offset voltage and
drift, for bias current and its drift, and for common-mode
range. Other factors might include power: output, dissipation,
or supply, ambient temperature ranges, and packaging.
Different circuit architectures and manufacturing processes
optimize different performance parameters.
Q. Is there any common factor in the design of op-amps?
A. Yesmost classical (voltage input) op-amps are three-stage
devices, consisting of an input stage with differential input and
differential outputwith good common-mode rejection
followed by a differential-input, single-ended output stage
having high voltage-gain and (generally) a single-pole frequency
response; and, finally, an output stage, which usually has unity
voltage gain.
Q. So where are the differences?

A. There are many possible variations on this basic design. One
of the most fundamental is the structure of the input stage.
This stage is almost always a long-tailed pairthat is to say, a
pair of amplifying devices connected as in the figurebut the
choice of devices has a profound effect on the input parameters
of the op amp. The figure was drawn with thermionic tubes to
avoid any suggestion of partiality in favour of any particular
semiconductor device. Since thermionic devices at present are
not generally available in IC chip form, a monolithic op-amp
will have an input stage built with bipolar or field-effect
transistors.
A long-tailed pair built with bipolar transistors is shown in the

next figure. Its strong features are its low noise and, with
suitable trimming, low voltage offset. Furthermore, if such a
stage is trimmed for minimum offset voltage it will inherently
have minimum offset drift. Its main disadvantage stems from
the proportionality of the emitter and base currents of the
transistors; if the emitter current is large enough for the stage
to have a reasonable bandwidth, the base currentand hence
the bias currentwill be relatively large (50 to 1,000 nA in
general-purpose op-amps, as much as 10 A in high-speed
ones).
The bias currents in the inverting and non-inverting inputs

are unipolar and well matched (their difference is called offset
current), and they decrease in a minor way with increasing
temperature. In many applications, the accurate matching may
be used to compensate for their high absolute value. This figure
shows a bias compensation circuit where the bias current in
the non-inverting input flows in Rc (known as the bias
compensation resistor); this compensates for the voltage drop
as the bias current in the inverting input flows through R2. Rc
is made nominally equal to the parallel combination of R1 and
R2.it can be trimmed to minimize error due to non-zero
offset current).
Such bias compensation is only useful when the bias currents

are well-matched. If they are not well-matched, a bias
compensation resistor may actually introduce error.
If a bipolar input stage is required without the drawback of
such a high bias current, a different form of bias compensation
may be used by the chip designer (next figure). The same
long-tailed pair is used, but the major portion of the current
required by each base is supplied by a current generator on
the chip. This can reduce the external bias current to 10 nA or
less without affecting the offset, temperature drift, bandwidth
or voltage noise. Bias current variation with temperature is
quite low.
There are two disadvantages to such an architecture: the

current noise is increased and the external bias currents are
not well matched (indeed, they may actually flow in opposite
directions, or change polarity as chip temperature changes).
For many applications these features are no drawback; indeed,
one of the most popular low-offset op-amp architectures, the
OP-07, uses just such an architecture, as do the OP-27, OP-37
and the AD707, which has a guaranteed offset voltage of only
15 V. Bias-compensated amplifiers of this type are often
recognizable when their data sheets explicitly specify bipolar
bias current, for example, 4.0 nA.
Where bias currents of even a few nanoamps are intolerable,
bipolar transistors are usually replaced by field-effect devices.
In the past, MOSFETs have been somewhat noisy for op-amp

input stages, although modern processing techniques are
overcoming this drawback. Since MOSFETS also tend to have
relatively high offset voltages, junction FETs (JFETs) are used
for high-performance low-bias-current op amps. A typical JFET
op-amp input stage is shown in this figure.
The bias current of a JFET bears no relationship to the current

flowing in the device, so even a wideband JFET amplifier may
have a very low bias currentvalues of a few tens of
picoamperes are commonplace, and the AD549 has a
guaranteed bias current of less than 60 fA (one electron per
three microseconds!) at room temperature.
The qualification at room temperature is criticalthe bias
current of a JFET is the reverse leakage current of its gate
diode, and the reverse leakage current of silicon diodes
approximately doubles with every 10C temperature rise. The
bias current of a JFET op-amp is thus not stable with
temperature. Indeed, between 25C and 125C, the bias
current of a JFET op-amp increases by a factor of over 1,000.
(The same law applies to MOSFET amplifiers, because the
bias current of most MOSFET amplifiers is the leakage current
of their gate-protection diodes.)
The offset voltage of a JFET amplifier may be trimmed during
manufacture, but minimum offset does not necessarily
correspond to minimum temperature drift. It has therefore been
necessary to trim offset and drift separately in JFET op-amps,
which results in somewhat larger values of voltage offset and
drift than are available from the best bipolar amplifiers (values
of 250 V and 5 V/C are typical of the best JFET op-amps).
Recent studies at Analog Devices, however, have resulted in a
patented trimming method which is expected to yield much
better values in the next generation of JFET op-amps.
We thus see that there are trade-offs between offset voltage,
offset drift, bias current, bias current temperature variation,
and noise in operational amplifiersand that different
architectures optimize different features. The table compares
the features of the three commonest op-amp architectures. We
should note one more category, typified by the new AD705,
using bipolar superbeta input transistors; it combines low offset
voltage and drift with low bias current and drift.
CHARACTERISTICS OF OP-AMP INPUT STAGES
OFFSET VOLTAGE
OFFSETDRIFT
BIAS CURRENT
BIAS MATCH
SIMPLE
BIPOLAR
BIAS-COMPENSATED
BIPOLAR
LOW
LOW
HIGH
EXCELLENT
BIAS/TEMP VARIATION
LOW
LOW
LOW
MEDIUM
POOR (CURRENT CAN
BE IN OPPOSITE
DIRECTIONS
LOW
NOISE
LOW
LOW
FET
MEDIUM
MEDIUM
LOW-VERY LOW
FAIR
BIAS DOUBLES FOR

EVERY 10C RISE
FAIR
Q. What other features of op amps should the user know about?

A. A common problem encountered with JFET op-amps is phase
inversion. If the input common-mode voltage of a JFET
op-amp approaches the negative supply too closely, the
inverting and non-inverting input terminals reverse functions.

Negative feedback becomes positive feedback and the circuit
may latch up. This latchup is unlikely to be destructive, but
power may have to be switched off to correct it. This figure
shows the effect of such phase inversion in a circuit where
latch-up does not occur. The problem may be avoided by using
bipolar amplifiers, or by restricting the common-mode range
of the signal in some way.
A more serious form of latchup can occur in both bipolar and

JFET op-amps if the input signal becomes more positive or
negative than the respective op-amp power supplies. If the input
terminals go more positive than +Vs + 0.7 V or more negative
than Vs 0.7 V, current may flow in diodes which are normally
biased off. This in turn may turn on thyristors (SCRs) formed
by some of the diffusions in the op- amp, short-circuiting the
power supplies and destroying the device.
To avoid such destructive latch-up it is important to prevent
the input terminals of op-amps from ever exceeding the power
supplies. This can have important implications during device
turn-on: if a signal is applied to an op-amp before it is powered
it may be destroyed at once when power is applied. Whenever
there is a risk, either of signals exceeding the voltages on the
supplies, or of signals being present prior to power-up of the
op-amp, the terminals at risk should be clamped with diodes
(preferably fast low-forward-voltage Schottky diodes) to
prevent latchup from occurring. Current-limiting resistors may
also be needed to prevent the diode current from becoming
excessive (see the figure).
This protection circuitry can cause problems of its own.

Leakage current in the diode(s) may affect the error budget of
the circuit (and if glass-encapsulated diodes are used, their
leakage current may be modulated at 100 or 120 Hz due to
photoelectric effects if exposed to fluorescent ambient lighting,
thus contributing hum as well as dc leakage current); Johnson
noise in the current-limiting resistor may worsen the circuits
noise performance; and bias current flowing in the resistor may
produce an apparent increase in offset voltage. All these effects
must be considered when designing such protection.
The important subjects of noise, interference, bypassing, and
grounding demand discussionbut were out of space! Well come
back to them again in future chats; meanwhile you may want to
take a look at some of the references in the footnotes on pages 193-4 of
The Best of Analog Dialogue, 1967-1991.
b

by James Bryant and Lew Counts
OP-AMP ISSUESNOISE
Q. What should I know about op-amp noise?
A. First, we must note the distinction between noise generated in
the op amp and its circuit components and interference, or
unwanted signals and noise arriving as voltage or current at any
of the amplifiers terminals or induced in its associated circuitry.
Interference can appear as spikes, steps, sine waves, or random
noise, and it can come from anywhere: machinery, nearby
power lines, r-f transmitters and receivers, computers, or even
circuitry within the same equipment (for example, digital
circuits or switching-type power supplies). Understanding it,
preventing its appearance in your circuits neighborhood,
finding how it got in, and rooting it out, or finding a way to
live with it is a big subject. Its been treated in these pages in
the past; those, and a few additional references, are mentioned
in the Bibliography.
If all interference could be eliminated, there would still be
random noise associated with the operational amplifier and its
resistive circuits. It constitutes the ultimate limitation on the
amplifiers resolution. Thats the topic well begin to discuss
here.
Q. O.K.Tell me about random noise in op amps.Where does it come from?
A. Noise appearing at the amplifiers output is usually measured
as a voltage. But it is generated by both voltage- and current
sources. All internal sources are generally referred to the input,
i.e., treated as uncorrelatedor independentrandom noise
generators (see next question) in series or parallel with the
inputs of an ideal noisefree amplifier: We consider 3 primary
contributors to noise:
a noise voltage generator (like offset voltage, usually shown in

series with the noninverting input)
two noise-current generators pumping currents out through the

two differential-input terminals (like bias current).
If there are any resistors in the op-amp circuit, they too generate
noise; it can be considered as coming from either current
sources or voltage sources (whichever is more convenient to
deal with in a given circuit).
Op-amp voltage noise may be lower than 1 nV/Hz for the
best types. Voltage noise is the noise specification that is more
usually emphasized, but, if impedance levels are high, current
noise is often the limiting factor in system noise performance.
That is analogous to offsets, where offset voltage often bears
the blame for output offset, but bias current is the actual guilty
party. Bipolar op-amps have traditionally had less voltage noise
than FET ones, but have paid for this advantage with
substantially greater current noisetoday, FET op-amps, while
retaining their low current noise, can approach bipolar
voltage-noise performance.
Q. Hold it! 1 nV/Hz? Where does Hz come from? What does it

mean?
A. Lets talk about random noise. Many noise sources are, for
practical purposes (i.e., within the bandwidths with which the
designer is concerned), both white and Gaussian. White noise
is noise whose power within a given bandwidth is independent
of frequency. Gaussian noise is noise where the probability of
a particular amplitude, X, follows a Gaussian distribution.
10
Gaussian noise has the property that when the rms values of
noise from two or more such sources are added, provided that
the noise sources are uncorrelated (i.e., one noise signal cannot
be transformed into the other), the resulting noise is not their
arithmetic sum but the root of the sum-of-their-squares (RSS).*
The RSS sum of three noise sources, V1, V2, and V3, is
V O = V 12 +V 22 +V 32
Since the different frequency components of a noise signal are

uncorrelated, a consequence of RSS summation is that if the
white noise in a brick-wall bandwidth of f is V, then the noise
in a bandwidth of 2 f is V 2 +V 2 = 2V . More generally, if
we multiply the bandwidth by a factor K, then we multiply the
noise by a factor K. The function defining the rms value of
noise in a f = 1 Hz bandwidth anywhere in the frequency
range is called the (voltage or current) spectral density function,
specified in nV/Hz or pA/Hz. For white noise, the spectral
density is constant; it is multiplied by the square root of the
bandwidth to obtain the total rms noise.
A useful consequence of RSS summation is that if two noise
sources are contributing to the noise of a system, and one is more
than 3 or 4 times the other, the smaller is often ignored, since
42 = 16 = 4, while 42 +12 = 17 = 4.12
[difference less than 3%, or 0.26 dB]

32 = 9 = 3, while 32 +12 = 10 = 3.16
[difference less than 6%, or 0.5 dB]

The source of the higher noise has become the dominant source.
Q. O.K. How about current noise?
A. The current noise of simple (i.e. not bias-current-compensated)
bipolar and JFET op-amps is usually within 1 or 2 dB of the
Schottky noise (sometimes called the shot noise) of the bias
current; it is not always specified on data sheets. Schottky noise
is current noise due to random distribution of charge carriers
in the current flow through a junction. The Schottky noise
current, In, in a bandwidth, B, when a current, I, is flowing is
obtained from the formula
I n = 2I qB
Where q is the electron charge (1.6 1019 C). Note that 2I q
is the spectral density, and that the noise is white.
This tells us that the current noise spectral density of simple
bipolar transistor op-amps will be of the order of 250 fA/Hz,
for Ib = 200 nA, and does not vary much with temperature
and that the current noise of JFET input op-amps, while lower
(4 fA/Hz at Ib, = 50 pA), will double for every 20C chip
temperature increase, since JFET op-amps bias currents
double for every 10C increase.
Bias-compensated op-amps have much higher current noise
than one can predict from their input currents. The reason is
that their net bias current is the difference between the base
current of the input transistor and the compensating current
source, while the noise current is derived from the RSS sum of
the noise currents.
Traditional voltage-feedback op-amps with balanced inputs almost
always have equal (though uncorrelated) current noise on both
[*Note the implication that noise power adds linearly (sum of squares).]

their inverting and non-inverting inputs. Current-feedback, or
transimpedance, op-amps, which have different input structures
at these two inputs, do not. Their data sheets must be consulted
for details of the noise on the two inputs.
The noise of op-amps is Gaussian with constant spectral
density, or white, over a wide range of frequencies, but as
frequency decreases the spectral density starts to rise at about
3 dB/octave. This low-frequency noise characteristic is known
as 1/f noise since the noise power spectral density goes
inversely with frequency (actually 1/f g). It has a 1 slope on a
log plot (the noise voltage (or current) 1/f spectral density
slopes at 1/2). The frequency at which an extrapolated 3 dB/
octave spectral density line intersects the midfrequency
constant spectral density value is known as the l/f corner
frequency and is a figure of merit for the amplifier. Early
monolithic IC op-amps had 1/f corners at over 500 Hz, but
today values of 2050 Hz are usual, and the best amplifiers
(such as the AD-OP27 and the AD-OP37) have corner
frequencies as low as 2.7 Hz. 1/f noise has equal increments
for frequency intervals having equal ratios, i.e., per octave or
per decade.
Q. Why dont you publish a noise figure?
A. The noise figure (NF) of an amplifier (expressed in dB) is a
measure of the ratio of the amplifier noise to the thermal noise
of the source resistance.
on the horizontal scale. Lets read the chart for the ADOP27:
The horizontal line indicates the ADOP27s voltage noise level
of about 3 nV/Hz is equivalent to a source resistance of less
than about 500 . Noise will not be reduced by (say) a 100-
source impedance, but it will be increased by a 2-k source
impedance. The vertical line for the ADOP27 indicates that,
for source resistances above about 100 k, the noise voltage
produced by amplifiers current noise will exceed that contributed
by the source resistance; it has become the dominant source.
Remember that any resistance in the non-inverting input will

have Johnson noise and will also convert current noise to a
noise voltage; and Johnson noise in feedback resistors can be
significant in high-resistance circuits. All potential noise sources
must be considered when evaluating op amp performance.
Vn = 20 log { [Vn(amp)+Vn(source)]/Vn(source)}
Q. You were going to tell me about Johnson noise.
It is a useful concept for r-f amplifiers, which are almost always

used with the same source resistance driving them (usually
50 or 75 ), but it would be misleading when applied to op
amps, since they are used in many different applications with
widely varying source impedances (which may or may not be
resistive).
A. At temperatures above absolute zero, all resistances have noise

due to thermal movement of charge carriers. This is called
Johnson noise. The phenomenon is sometimes used to measure
cryogenic temperatures. The voltage and current noise in a
resistance of R ohms, for a bandwidth of B Hz, at a temperature
of T kelvins, are given by:
Q. What difference does the source impedance make?

A. At temperatures above absolute zero all resistances are noise
sources; their noise increases with resistance, temperature, and
bandwidth (well discuss basic resistance noise, or Johnson noise,
in a moment). Reactances dont generate noise, but noise
currents through them will develop noise voltages.
If we drive an op-amp from a source resistance, the equivalent
noise input will be the RSS sum of the amplifiers noise voltage,
the voltage generated by the source resistance, and the voltage
caused by the amplifiers I n flowing through the source
impedance. For very low source resistance, the noise generated
by the source resistance and amplifier current noise would
contribute insignificantly to the total. In this case, the noise at
the input will effectively be just the voltage noise of the op-amp.
If the source resistance is higher, the Johnson noise of the source
resistance may dominate both the op-amp voltage noise and
the voltage due to the current noise; but its worth noting that,
since the Johnson noise only increases with the square root of
the resistance, while the noise voltage due to the current noise
is directly proportional to the input impedance, the amplifiers
current noise will always dominate for a high enough value of
input impedance.When an amplifiers voltage and current noise
are high enough, there may be no value of input resistance for
which Johnson noise dominates.
This is demonstrated by the figure nearby, which compares
voltage and current noise noise for several Analog Devices op
amp types, for a range of source-resistance values. The diagonal
line plots vertically the Johnson noise associated with resistances
V n = 4kTRB and I n = 4kTB / R
Where k is Boltzmanns Constant (1.38 1023 J/K). A handy

rule of thumb is that a 1-k resistor has noise of 4 nV/Hz at
room temperature.
All resistors in a circuit generate noise, and its effect must always
be considered. In practice, only resistors in the input(s) and,
perhaps, feedback, of high-gain, front-end circuitry are likely
to have an appreciable effect on total circuit noise.
Noise can be reduced by reducing resistance or bandwidth,
but temperature reduction is generally not very helpful unless
a resistor can be made very coldsince noise power is
proportional to the absolute temperature, T = C + 273.
b
(to be continued)
REFERENCES
Barrow, J., and A. Paul Brokaw, Grounding for Low- and High-Frequency
Circuits, Analog Dialogue 23-3, 1989.
Bennett, W. R., Electrical Noise. New York: McGraw-Hill, 1960.
Freeman, J. J., Principles of Noise. New York: John Wiley & Sons, Inc., 1958.
Gupta, Madhu S., ed., Electrical Noise: Fundamentals & Sources. New York: IEEE
Press, 1977. Collection of classical reprints.
Motchenbacher, C. D., and F. C. Fitchen, Low-Noise Electronic Design. New
York: John Wiley & Sons, Inc., 1973.
Rice, S.O., Math Analysis for Random Noise Bell System Technical Journal 23
July, 1944 (pp 282332).
Rich, Alan, Understanding Interference-Type Noise, Analog Dialogue 16-3,
1982.
- - - , Shielding and Guarding, Analog Dialogue 17-1, 1983.
Ryan, Al, and Tim Scranton, DC Amplifier Noise Revisited, Analog Dialogue
18-1, 1984.
van der Ziel, A. Noise. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1954.
b
11

by James Bryant
OP-AMP ISSUES
(Noise, continued from the last issue, 24-2)
Q. What is noise gain?
A. So far we have considered noise sources but not the gain of the
circuits where they occur. It is tempting to imagine that if the
noise voltage at the input of an amplifier is Vn and the circuits
signal gain is G, the noise voltage at the output will be GVn;
but this is not always the case.
Consider the basic op-amp gain circuit in the diagram. If it is
being used as an inverting amplifier (B), the non-inverting input
will be grounded, the signal will be applied to the free end of
R i and the gain will be R f/R i . On the other hand, in a
non-inverting amplifier (A) the signal is applied to the
non-inverting input and the free end of Ri is grounded; the
gain is (1 + Rf/Ri)
A
Ri
Rf
VOUT
V1
SIGNAL
GAIN
B
A
B
Vn
A:
(1 +
B:
Rf
Ri
Rf
Ri
AMPLIFIER
NOISE GAIN
(1 +
Rf
(1 +
Rf
Ri
Ri
)
)
The amplifiers own voltage noise is always amplified in the

non-inverting mode; thus when an op-amp is used as an
inverting amplifier at a gain of G, its voltage noise will be
amplified by the noise gain of (G+ 1). For the precision
attenuation cases, where G<1, this may present problems. (A
common example of this is an active filter circuit where
stopband gain may be very small but stop-band noise gain is
at least unity.)
Only the amplifier voltage noiseand any noise developed by
the noninverting-input current noise flowing in any impedance
present in that input (for example, a bias-current compensation
resistor)is amplified by the noise gain. Noise in Ri, either
Johnson noise or arising from inverting input noise current, is
amplified by G in the same way as the input signal, and Johnson
noise voltage in the feedback resistor is not amplified but is
buffered to the output at unity gain.
Q. Whats popcorn noise?
A. Twenty years ago this column would have spent a great deal of
space discussing popcorn noise, which is a type of low frequency
noise manifesting itself as low level (but random amplitude)
step changes in offset voltage occurring at random intervals.
When played through a loudspeaker it sounds like cooking
popcornhence the name.
While no integrated circuit process is entirely free from the
problem, high levels of popcorn noise result from inadequate
processing techniques. Today its causes are sufficiently well
understood that no reputable op-amp manufacturer is likely
to produce op-amps where popcorn noise is a major concern
to the user. {Oat-bran noise is more likely to be an issue in
situations where cereal data is concerned[:-)]}
Q. Pk-pk noise voltage is the most convenient way to know whether
noise will ever be a problem for me. Why are amplifier manufacturers
reluctant to specify noise in this way?
12
A. Because noise is generally Gaussian, as we pointed out in the

last issue. For a Gaussian distribution it is meaningless to speak
of a maximum value of noise: if you wait long enough any
value will, in theory, be exceeded. Instead it is more practical
to speak of the rms noise, which is more or less invariantand
by applying the Gaussian curve to this we may predict the
probability of the noise exceeding any particular value. Given
a noise source of V rms, since the probability of any particular
value of noise voltage follows a Gaussian distribution, the noise
voltage will exceed a pk-pk value of 2 V for 32% of the time,
3 V for 13% of the time, and so on:
% of time pk-pk
Pk-pk value
value is exceeded
2 rms
32%
4 rms
4.6%
6 rms
0.27%
6.6 rms
0.10%
8 rms
60 ppm
10 rms
0.6 ppm
12 rms
2 109 ppm
14 rms
2.6 1012 ppm
So if we define a peak value in terms of the probability of its

occurrence, we may use a peak specificationbut it is more
desirable to use the rms value, which is generally easier to
measure. When a peak noise voltage is specified, it is frequently
6.6 rms, which occurs no more than 0.1% of the time.
Q. How do you measure the rms value of low-frequency noise in the
usually specified band, 0.1 to 10 Hz? It must take a long time to
integrate. Isnt this expensive in production?
A. Yes, it is expensive, butAlthough its necessary to make many
careful measurements during characterization, and at intervals
thereafter, we cannot afford the time it would take in production
to make an rms measurement. Instead, at very low frequencies
in the 1/f region (as low as 0.1 to 10 Hz), the peak value is
measured during from one to three 30-second intervals and
must be less than some specified value. Theoretically this is
unsatisfactory, since some good devices will be rejected and
some noisy ones escape detection, but in practice it is the best
test possible within a practicable test time and is acceptable if
a suitable threshold limit is chosen. With conservative
weightings applied, this is a reliable test of noise. Devices that
do not meet the arbitrary criteria for the highest grades can
still be sold in grades for which they meet the spec.
Q. What other op-amp noise effects do you encounter?
A. There is a common effect, which often appears to be caused
by a noisy op amp, resulting in missing codes. This potentially
serious problem is caused by ADC input-impedance
modulation. Heres how it happens:
Many successive-approximation ADCs have an input
impedance which is modulated by the devices conversion clock.
If such an ADC is driven by a precision op amp whose
bandwidth is much lower than the clock frequency, the op amp
cannot develop sufficient feedback to provide a stiff voltage
source to the ADC input port, and missing codes are likely to
occur. Typically, this effect appears when amplifiers like the
OP-07 are used to drive AD574s.

It may be cured by using an op amp with sufficient bandwidth
to have a low output impedance at the ADCs clock frequency,
or by choosing an ADC containing an input buffer or one whose
input impedance is not modulated by its internal clock (many
sampling ADCs are free of this problem). In cases where the
op amp can drive a capacitive load without instability, and the
reduction of system bandwidth is unimportant, a shunt
capacitor decoupling the ADC input may be sufficient to effect
a cure.
Q. Are there any other interesting noise phenomena in high-precision
analog circuits?
A. The tendency of high-precision circuitry to drift with time is a
noise-like phenomenon (in fact, it might be argued that, at a
minimum, it is identical to the lower end of 1/f noise). When
we specify long-term stability, we normally do so in terms of
V/1,000 hr or ppm/1,000 hr. Many users assume that, since
there are, on the average, 8,766 hours in a year, an instability
of x/1,000 hr is equal to 8.8 x/yr.
This is not the case. Long-term instability (assuming no longterm steady deterioration of some damaged component within
the device), is a drunkards walk function; what a device did
during its last 1,000 hours is no guide to its behavior during
the next thousand. The long-term error mounts as the squareroot of the elapsed time, which implies that, for a figure of
x/l,000 hr, the drift will actually be multiplied by 8.766, or
about 3 per year, or 9 per 10 years. Perhaps the spec should
be in V/1,000 hr.
In fact, for many devices, things are a bit better even than this.
The drunkards walk model, as noted above, assumes that
the properties of the device dont change. In fact, as the device
gets older, the stresses of manufacture tend to diminish and
the device becomes more stable (except for incipient failure
sources). While this is hard to quantify, it is safe to say that
provided that a device is operated in a low-stress environment
its rate of long-term drift will tend to reduce during its lifetime.
The limiting value is probably the 1/f noise, which builds up as
the square-root of the natural logarithm of the ratio, i.e., 1n 8.8
for time ratios of 8.8, or 1.47 for 1 year, 2.94 for 8.8 years,
4.4 for 77 years, etc.
A READERS CHALLENGE:
Q. A reader sent us a letter that is just a wee bit too long to quote
directly, so well summarize it here. He was responding to the
mention in these columns (Analog Dialogue 24-2, pp. 20-21)
of the shot effect, or Schottky noise (Schottky was the first to
note and correctly interpret shot effectoriginally in vacuum
tubes1). Our reader particularly objected to the designation of
shot noise as solely a junction phenomenon, and commented
that we have joined the rest of the semiconductor and op-amp
engineering fraternity in disseminating misinformation.
In particular, he pointed out that the shot noise formula
In = 2q IB amperes,
where In is the rms shot-noise current, I is the current flowing
through a region, q is the charge of an electron, and B is the
bandwidthdoes not seem to contain any terms that depend
on the physical properties of the region. Hence (he goes on)
shot noise is a universal phenomenon associated with the fact
that any current, I, is a flow of electrons or holes, which carry

discrete charges, and the noise given in the formula is just an
expression of the graininess of the flow.
He concludes that the omission of this noise component in
any circuit carrying current, including purely resistive circuits,
can lead to serious design problems. And he illustrates its
significance by pointing out that this noise current, calculated
from the flow of dc through any ideal resistor, becomes equal
to the thermal Johnson noise current at room temperature when
only 52 mV is applied to the resistorand it would become
the dominant current noise source for applied voltages higher
than about 200 mV.
A. Since designers of low-noise op amps have blithely ignored
this putative phenomenon, whats wrong? The assumption that
the above shot noise equation is valid for conductors.
Actually, the shot noise equation is developed under the
assumption that the carriers are independent of one another.
While this is indeed the case for currents made up of discrete
charges crossing a barrier, as in a junction diode (or a vacuum
tube), it is not true for metallic conductors. Currents in
conductors are made up of very much larger numbers of
carriers (individually flowing much more slowly), and the noise
associated with the flow of current is accordingly very much
smallerand generally lost in the circuits Johnson noise.
Heres what Horowitz and Hill2 have to say on the subject:
An electric current is the flow of discrete electric charges,
not a smooth fluidlike flow. The finiteness of the charge
quantum results in statistical fluctuations of the current. If the
charges act independently of each other,* the fluctuating current
is . . .
I noise (rms) = InR = (2 qIdc B)1/2
where q is the electron charge (1.60 1019 C) and B is the
measurement bandwidth. For example, a steady current of
1 A actually has an rms fluctuation of 57 nA, measured in a
10-kHz bandwidth; i.e., it fluctuates by about 0.000006%.
The relative fluctuations are larger for smaller currents: A
steady current of 1 A actually has an rms current-noise
fluctuation, over 10 kHz, of 0.006%, i.e., 85 dB. At 1 pA dc,
the rms current fluctuation (same bandwidth) is 56 fA, i.e., a
5.6% variation! Shot noise is rain on a tin roof. This noise,
like resistor Johnson noise, is Gaussian and white.
The shot noise formula given earlier assumes that the charge
carriers making up the current act independently. That is
indeed the case for charges crossing a barrier, as for example
the current in a junction diode, where the charges move by
diffusion; but it is not true for the important case of metallic
conductors, where there are long-range correlations between charge
carriers. Thus the current in a simple resistive circuit has far less
noise than is predicted by the shot noise formula.* Another
important exception to the shot-noise formula is provided by
our standard transistor current-source circuit, in which negative
feedback acts to quiet the shot noise.
*Italics ours
1
Goldman, Stanford, Frequency Analysis, Modulation, and Noise. New York:
McGraw-Hill Book Company, 1948, p. 352.
2
Horowitz, Paul and Winfield Hill, The Art of Electronics, 2nd edition. Cambridge (UK): Cambridge University Press, 1989, pp. 431-2.
b
13

SEMINARS AND SUPPORT
by Chris Hyde
Q. Are performance, quality, reliability, price, and availability the only
important considerations in selecting products for use in the critical
portions of my designs?
A. There is one moresupport. A manufacturers support can be
an important factor in shortening the design cycle and
approaching optimal part selectionbut only if you take
advantage of it. Using it can make the difference between
getting your product to market on time or losing the edge and
market window to your competitors.
Q. What do you mean by support?
A. At Analog Devices, it basically means help for the designer. Its
constituents include:
(mostly) free literature and software [for example, accurate and
comprehensive data sheets, data books, selection guides,
tutorial and technical reference books, application notes and
guides, SPICE models and other useful disk-based material,
and serial publications such as Analog Dialogue and DSPatch]
advice and information from our applications engineers, on the
phone and in the field, to discuss the technical pros, cons,
advantages and pitfalls in using our products to solve your
design problems and selecting the right product from among
the many choices available
samples and evaluation boards from our sales and applications
engineers, to try out new productsespecially those at the
edges of the technologyand
seminars, practical tutorials in various aspects of analog-,
digital-, and mixed-signal processing.
Q. That sounds like a rather full plate.Whats in it for you?
A. Were really quite pragmatic. The products that we manufacture
aremore often than notstate of the art and often pace the
knowledge of the engineers who will benefit by applying them.
It is in Analog Devices best interest to assist these engineers
in learning how and why to apply these products.
Today, designers are at a crossroads and in need of new forms
of guidance. Analog Devices unique combination of abilities
in component design, processes, and functional integration,
our long-cultivated capability of combining analog and digital
functions on a single chip, our 25 years of experience in helping
designers deal with the unique problems of transitioning
between the analog and digital worldsand now our unique
contributions in digital signal processingcombine to put us
in the forefront of a revolution in system design.
The integration of these capabilities shows up in both the
products and the ability to provide support for customers using
them to deal with the signal-conditioning chain in its entirety.
The chain starts and ends with the analog signalto condition
it, convert it, process it in the digital domain, and convert the
result back to analog. The physical and electrical environment
is often hostile to signals, and there are many (often quite
subtle) things for the designer to consider. We are in a unique
14
position to help engineers from both analog and mixed

signal-processing technology.
Q. Id love to go to a real nuts-and-bolts seminar on this topic. Are you
planning one?
A. You read our mind. Every year, Analog Devices sponsors a
full-day technical course entitled, [. . . subject . . .] Seminar.
Presented by Analog Devices applications engineers, it is
designed to assist both analog and digital designers with many
of the trickier aspects of both analog and digital signal
processing. The seminar combines fundamental concepts,
advanced theory, and practical application. Readers who have
attended Analog Devices seminarsknow that it will not be a
product pitch (but naturally our discussions of practical
application will unabashedly take into account the characteristics of the devices we know best).
Q. When? Where? How much?
A. The widely advertised seminars are given in a variety of
locations throughout the United States and elsewhere in the
World, and portions thereafter to other groups as the
opportunity arises. The minimal cost includes lunch and all
materialsincluding a fresh and typically 500-page book of
Notes. These books form a library that is available for sale. To
register or obtain more information, consult the analog.com
web site. Its an excellent opportunity to get a taste of Analog
Devices support.
Q. What seminar books are available?
A. I thought youd never ask. Here are the most recent thru 1996:
High-speed design techniques (1996)
Practical analog design techniques (1995)
Linear design seminar (1994)
System applications guide (1993)
Amplifier applications guide (1992)
Mixed-signal design seminar (1991)
VARIOUS TOPICS
by James Bryant
Q. Tell me something about supply decoupling.
A. All precision analog integrated circuits, even low-frequency
ones, contain transistors having cutoff frequencies of hundreds
of MHz; their supplies must therefore be decoupled to the
ground return at high frequencyas close to the IC as feasible
to prevent possible instability at very high frequencies. The
capacitors used for such decoupling must have low selfinductance, and their leads should be as short as possible
(surface-mounted chip ceramic capacitors of 10- to 100 nF
are ideal, but leaded chip ceramics are generally quite effective
if the lead length is kept to less than 2 mm (see nearby figure).
Low-frequency decoupling is also important, since the PSR
(power-supply rejection) is normally specified at dc and will
deteriorate appreciably with increasing power-supply ripple
frequencies. In some high-gain applications, feedback through
the common power-supply impedance can lead to low
frequency instability (motorboating). However, lowfrequency decoupling at each IC is not often necessary.

IDEAL HF DECOUPLING HAS
C
GROUND
PLANE
IC
1. LOW INDUCTANCE CAPACITOR (MONOLITHIC CERAMIC)

2. MOUNTED VERY CLOSE TO THE IC
3. WITH SHORT LEADS
4. AND SHORT, WIDE PC TRACKS
IT MAY BE SHUNTED WITH A TANTALUM BEAD ELECTROLYTIC
TO PROVIDE GOOD LF DECOUPLING AS WELL.
THIS SORT OF THING IS USELESS!
Supply decoupling does more than prevent instability. An opamp is a four-terminal device (at least), since there must be a
return path for both input signals and the output circuit. It is
customary to consider the common terminal of both op-amp
supplies (for op-amps using + supplies) as the output signal
return path, but in fact, one of the supplies will be the de facto
return path at higher frequencies, and the decoupling of the
amplifiers supply terminal for this supply must take into
consideration both the necessity of normal high-frequency
decoupling and the routing of the output ground.*
Q. In Ask the Application Engineer, youre always describing
non-ideal behavior of integrated circuits. It must be a relief to use a
simple component like a resistor and know that you have a near-ideal
component.
A. I only wish that a resistor was an ideal component, and that
that little cylinder with wire ends behaved just like a pure
resistance. Real resistors also contain imaginary resistance
componentsin other words theyre reactive. Most resistors
have a small capacitance, typically 1-3 pF, in parallel with their
resistance, although some types of film resistors, which have a
spiral groove cut in their resistive film, may be inductive, with
inductances of a few tens or hundreds of nH.
RESISTORS ARE REACTIVE:
OR
OR
Of course, wirewound resistors are generally inductive rather

than capacitive (at least, at the lower frequencies). After all,
they consist of a coil of wire. It is commonplace for wirewound
resistors to have inductances of several microhenrys or tens of
microhenrys, and even so-called non-inductive wirewound
resistors, which consist of N/2 turns wound clockwise and N/2
turns wound anticlockwise, so that the inductances of the two
half windings cancel out, have a residual inductance of a
microhenry or even more. (For higher-resistance-value types,
above 10 k or so, the residual reactance may be capacitive
rather than inductive, and the capacitance will be higherby
up to 10 pFthan a standard film or composition resistor.)
These reactances must be considered carefully when designing

high frequency circuits which contain resistors.
Q. But many of the circuits you describe are for making precision
measurements at DC or very low frequencies. Stray inductance and
capacitance dont matter in such applications, do they?
A. They actually do. Since transistors (either discrete or within
ICs) have very wide bandwidths, if such circuits are terminated
with reactive loads, they may sometimes oscillate at frequencies
of hundreds or thousands of MHz; bias shifts and rectification
associated with the oscillations can have devastating effects on
low-frequency precision and stability.
Even worse, this oscillation may not appear on an oscilloscope,
either because the oscilloscope bandwidth is too low for such
a high frequency to be displayed, or because the scope probes
capacitance is sufficient to stop the oscillation. It is always wise
to use a wideband (LF to 1.5 GHz or more) spectrum analyzer
to verify the absence of parasitic oscillations in a system. Such
checks should be made while the input is varied throughout
its whole dynamic range, since parasitic oscillations may
sometimes occur over a narrow range of inputs.
Q. Are there any problems with the resistance of resistors?
A. The resistance of a resistor is not fixed but varies with
temperature. The temperature coefficient (TC) varies from a
few parts per million per degree Celsius (ppm/C) to thousands
of ppm/C. The resistors with the best stability are wirewound
or metal film types, and the worst are carbon composition.
Large temperature coefficients are sometimes useful (an
earlier Ask the Applications Engineer mentioned how a
+3,500-ppm/C resistor can be used to compensate for the
kT/q term in the equation for the behavior of a junction diode).
But in general, the variation of resistance with temperature is
likely to be a source of error in precision circuits.
If the accuracy of a circuit depends on the matching of two
resistors having different TCs, then, no matter how wellmatched at one temperature, they will not match at another;
and even if the TCs of two resistors match, there is no guarantee
that they will remain at the same temperature. Self-heating by
internal dissipation, or external heating from a warm part of
the system, will result in a mismatch of temperature, hence
resistance. Even with high quality wirewound or metal-film
resistors these effects can result in matching errors of several
hundred (or even thousand) ppm. The obvious solution is to
use resistors which are fabricated in close proximity on the
same substrate whenever good matching is necessary for system
accuracy. The substrate may be the silicon of a precision analog
IC or a glass or metal thin-film substrate. In either case, the
resistors will be well-matched during manufacture, will have
well-matched TCs, and will be at nearly the same temperature
because of their proximity.
(This discussion will be continued in a future issue.)
Analog Dialogue 22-2, 1988. p.29.
*This issue is developed in detail in the free application note, An IC amplifier

users guide to decoupling, grounding, and making things go right for a change,
by Paul Brokaw. [AN-202]
15
C=
A
Q. In the last issue of Analog Dialogue you told us about some of the
problems of a simple resistor. [More will appear in a future issue.]
Surely there must be some component that behaves exactly as I
expected it to. How about a piece of wire?
A. Not even that. You presumably expect your piece of wire or
length of PC track to act as a conductor. But room-temperature
superconductors have not yet been invented, so any piece of
metal will act as a low-valued resistor (with capacitance and
inductance, too) and its effect on your circuit must be
considered.
Q. Surely the resistance of a short length of copper in small-signal circuits
is unimportant?
A. Consider a 16-bit a/d converter with 5-k input impedance.
Suppose that the signal conductor to its input consists of
10 cm of typical PC track0.25 mm (0.010") wide and
0.038 mm (0.0015") thick. This will have a resistance of
approximately 0.18 at room temperature, which is slightly
less than 2 216 of 5 k; this introduces a gain error of
2 LSB of full scale.
OHM'S LAW PREDICTS 1 LSB DROP IN 5cm OF STANDARD
PCB TRACK BUT WHO BELIEVES OHM'S LAW?
0.18
10cm
16-BIT
ADC
SIGNAL
SOURCE
5k
0.25mm
WIDE
0.038mm
THICK
R
FOR 1oz COPPER
= 1.724 10 6 ohm-cm
A = plate area in mm2

d = plate separation in mm
Er = dielectric constant relative to air
Commonest type of PCB uses 1.5mm

glass-fiber epoxy material with Er = 4.7
Capacity of PC track over ground plane
is roughly 2.8pF/cm2
Q. Hold it! Whats a ground plane?

A. If one entire side of a PCB (or one entire layer, in the case of
a multi-layer PCB) consists of continuous copper which is used
as ground this is known as a ground plane. It will have the
least possible resistance and inductance of any ground
configuration. If a system uses a ground plane, it is less likely
to suffer ground noise problems.
Q. I have heard that ground planes are hard to manufacture.
A. Twenty years ago there was some truth in this. Today
improvements in PC adhesives, solder resists and wavesoldering techniques make the manufacture of ground-plane
PCBs a routine operation.
Q. You say that a system using a ground plane is less likely to suffer
ground noise problems.What remaining ground noise problems does
it not cure?
A. The basic circuit of a system having ground noise is shown in
the diagram. Even with a ground plane the resistance and
inductance will not be zeroand if the external current source
is strong enough it will corrupt the precision signal.
and
Y = 0.0038cm
Z
R=
Z
YX
= RESISTIVITY
Y
R
SIGNAL
0.45m/
0.45
SIGNAL
SOURCE
ADC
100
0.25
Z
= (OHMS/SQUARE) (# OF SQUARES)
X
One might argue that the problem would be reduced if PC

tracks were made widerand indeed, in analog circuitry its
almost always better to use wide tracks; but many layout drafters
(and PC Design programs) prefer minimum-width tracks for
signal conductor. In any case its especially important to
calculate the track resistance and its effect in every location
where it might cause a problem.
Q. Doesnt the capacitance of the extra width of track to metal on the
boards underside cause a problem?
A. Rarely. Although the capacitance of PC tracks is important
(even in circuits designed for low frequencies, since LF circuits
can oscillate parasitically at HF) and should always be
evaluated, the extra capacitance of a wider track is unlikely to
cause a problem if none existed previously. If it is a problem,
small areas of ground plane can be removed to reduce ground
capacitance.
16
pF
by James Bryant
0.00885 Er A
VOLTAGE DUE TO SIGNAL CURRENT

AND (PERHAPS) EXTERNAL CURRENT
FLOWING IN GROUND IMPEDANCE
EXTERNAL
CURRENT
SOURCE
The problem is minimized by arranging the PCB so that high

currents do not flow in regions where ground voltages can
corrupt precision signals. Sometimes a break or slot in a ground
plane can divert a large ground current from a sensitive area
but breaks in a ground plane can also reroute signals into
sensitive areas, so the technique must be used with care.
Q. How do I know what voltage drops are present in a ground plane?
A. They should generally be measured; however, it is sometimes
possible to calculate them from the resistance of the

ground plane material (standard 1 oz copper has resistance of
0.45 m/square) and the length through which currents flow,
but the calculation can be complicated. At DC and low
frequencies (dc-50 kHz), voltage drops can be measured
with an instrumentation amplifier such as the AMP-02 or
the AD620.
For example, 1 cm of 0.25-mm track has an inductance of

10 nH.
2R
L, R in mm
L
WIRE INDUCTANCE = 0.0002L
In
2L
0.75 H
R
EXAMPLE: 1cm of 0.5mm o.d. wire has an inductance of 7.26nH

(2R = 0.5mm, L = 1cm)
TO
PROBES
IN
AMP
L
OSCILLOSCOPE
1000
The amplifier is set to a gain of 1,000 and connected to an

oscilloscope with a gain of 5 mV/div. The amplifier may be
powered from the same supply as the circuit being testedor
from its own supplybut the grounds of the amplifier, its
supply if separate, and the oscilloscope must be connected to
the power ground of the circuit under test at the power supply.
The voltage between any two points on the ground plane may
then be measured by applying the probes to those points. The
combination of the amplifier gain and oscilloscope sensitivity
give a measurement sensitivity of 5 V/div. Amplifier noise
will swell the oscilloscope trace to a band about 3 V wide but
it is still possible to make measurements with about 1-V
resolutionsufficient to identify most low-frequency ground
noise problems; and identification is 80% of a cure.
Q. Are there any cautions about performing this test?
A. Any alternating magnetic fields which thread the probe leads
will induce voltages in them. This can be tested by shortcircuiting the probes together (and resistively to ground to
provide a bias current path) and observing the oscilloscope
trace; ac waveforms observed that result from inductive pickup
may be minimized by repositioning the leads or taking steps to
eliminate the magnetic field. It is also essential to ensure that
the ground of the amplifier is connected to the system ground;
without this connection the amplifier, with no return path for
bias current cannot work; grounding also ensures that this
connection does not disturb the current distribution that is
being measured.
STRIP INDUCTANCE = 0.0002L
The test is similar to the LF one but the spectrum analyzer

displays noise as an amplitude-frequency plot.While this differs
from time-domain information, sources of noise may be easier
to identify by their frequency signatures; in addition, the use
of a spectrum analyzer provides at least 60 dB more sensitivity
than is possible with a broadband oscilloscope.
Q. What about the inductance of wires?
A. The inductance of wire- and PC-track leads should not
be overlooked at higher frequencies. Here are some
approximations for calculating the inductance of straight wires
and runs.
In
2L
W+H
+ 0.2235
W+H
+ 0.5 H
L
EXAMPLE: 1cm of 0.25mm PC track has an inductance of 9.59 nH

(H = 0.038mm, W = 0.25mm, L = 1cm)
But inductive reactance is generally much less of a problem

than stray flux cutting inductive loops and inducing voltages;
loop area must be minimized, since voltage is proportional to
it. In wired circuits this is easily done using twisted pairs.
REDUCING LOOP INDUCTANCE
LOAD
SOURCE
LOAD
SOURCE
In boards, leads and return paths should be close together;

quite small changes in layout will often minimize the effect.
In this circuit, mutual inductance will couple energy from highlevel source A into low-level circuit B.
Q. What about measuring HF ground noise?

A. It is hard to make a suitable instrumentation amplifier with
wide bandwidth, so at HF and VHF a passive probe is more
suitable. This consists of a ferrite toroid (6-8 mm OD) wound
with two coils of 6-10 turns each. One coil is connected to the
input of a spectrum analyzer, the other to the probes, to make
a high-frequency isolating transformer.
5mV/div
Reducing area and increasing separation will minimize the

effect.
Usually, all that is necessary is to minimize loop area and
maximize the distance between potentially interfering loops.
Occasionally magnetic shielding is required, but it is expensive
and liable to mechanical damage; avoid it whenever possible.
REFERENCES
The Best of Analog Dialogue 1967-1991. Norwood MA: Analog
Devices (1991), pp. 120-129, 193-195. Contains many additional
references.
Mixed-Signal Design Seminar Notes. Norwood MA: Analog Devices
b
(1991). Contains additional References.
17

by James Bryant
All analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) require a reference signal, usually a voltage.
The digital output of the ADC represents the ratio of the input to
the reference, the digital input to a DAC defines the ratio of its
analog output to its reference. Some converters have their
references built-in, some require an external reference, but all must
have a voltage (or current) reference of some sort.
Most early applications of data converters were in dc
measurements of slowly varying signals, where the exact timing of
the measurement was unimportant. Today most data-converter
applications are in sampled data systems, where large numbers of
equally spaced analog samples must be processed and spectral
information is as important as amplitude information. Here the
quality of the frequency or time reference (the sampling clock
or reconstruction clock) is comparable in importance to that of
the voltage reference.
VOLTAGE REFERENCES
Q. How good must a voltage reference be?
A. It depends on the system. Where absolute measurements are
required, accuracy is limited by the accuracy with which the
reference value is known. In many systems, however, stability
or repeatability are more important than absolute accuracy;
and in some sampled-data systems the long-term accuracy of
the voltage reference is scarcely important at allbut errors
can be introduced by deriving reference from a noisy system
supply.
Monolithic buried-Zener references (for example the AD588
and AD688) can have initial accuracy of 1 mV in 10 V (0.01%
or 100 ppm) and a temperature coefficient of 1.5 ppm/C.
They are accurate enough to use untrimmed in 12-bit systems
(1 LSB = 244 ppm) but not in 14- or 16-bit systems. With the
initial error trimmed to zero, they can be used in 14- and 16-bit
systems over a limited temperature range. (1 LSB = 61 ppm, a
40C temperature change in an AD588 or AD688).
For higher absolute accuracy, the temperature of the reference
may need to be stabilized in a thermostatically controlled oven
and calibrated against a standard. In many systems, while 12-bit
absolute accuracy is unnecessary, 12-bit or higher resolution
may be required; here, less accurate (and less costly) bandgap
references may be used.
Q. What do you mean by buried Zener and bandgap?
A. These are the two commonest types of precision references
used in integrated circuits.
The buried or subsurface Zener is the more stable and
accurate. It consists of a diode with the correct value of
reverse-breakdown voltage, formed below the surface level of
the integrated-circuit chip, then covered by a protective
diffusion to keep the breakdown below the surface.
TOP DIFFUSION
BREAKDOWN
REGION
ZENER
DIFFUSION
SIMPLE ZENER DIODE
18
BURIED
BREAKDOWN
REGION
ZENER
DIFFUSION
BURIED (OR SUBSURFACE)

ZENER DIODE
At the surface of a silicon chip there are more impurities,

mechanical stresses and crystal-lattice dislocations than within
the chip. Since these contribute to noise and long-term
instability, the buried breakdown diode is less noisy and much
more stable than surface Zenersit is the preferred on-chip
reference source for accurate IC devices.
However, its breakdown voltage is normally about 5 V or more
and it must draw several hundred microamperes for optimum
operation, so the technique is not suitable for references which
must run from low voltage and have low power consumption.
For such applications, the bandgap reference is preferred. It
develops a voltage with a positive temperature coefficient to
compensate for the negative temperature coefficient of a
transistors Vbe, maintaining a constant bandgap voltage. In
the circuit shown,* Q2 has 8 times the emitter area of Ql; the
pair produces a current proportional to their absolute
temperature (PTAT) in R1, developing a PTAT voltage in series
with the Vbe of Q1, resulting in a voltage, Vz, which does not
vary with temperature and can be amplified, as shown. It is
equal to the silicon bandgap voltage (extrapolated to
absolute zero).
Bandgap references are somewhat less accurate and stable than
the best buried-Zener references, but temperature variation of
better than 3 ppm/C may be achieved.
+V IN
R8
R7
VOUT = V Z 1 +
I 2 > I1
R4
R5
R4
Q2
8A
VBE
2I1 = I1 + I2
Q1
A
V Z = VBE + V1
VBE
(Q1)
R2
R1
V1 = 2
R5
R1
R2
= VBE + 2
= VBE + 2
VBE
R1
R2
VBE
R 1 kT
R2
In
J1
J2
= 1.205V
COM
Q. What precautions should I take when using voltage references?

A. Remember the basics of good analog circuit design: beware of
voltage drops in high impedance conductors, noise from
common ground impedances, and noise from inadequately
decoupled supply rails. Consider in which direction the
reference current is flowing, and be careful of capacitive loads.
Q. I know about the effects of voltage drop and noise, but do references
have to supply large-enough currents for voltage drop in conductors
to be significant?
A. Generally, references are internally buffered; most will source
and sink 5-10 mA. Some applications may require currents of
this order or greater; an example is where the reference serves
as the system reference; another is in driving the reference input
of a high speed flash ADC which, has very low impedance. A
current of 10 mA flowing in 100 m will experience a voltage
drop of 1 mV, which may be significant. The highestperformance voltage references, such as the AD588 and
AD688, have Kelvin (force-sense) connections for both their
output and output ground terminals. By closing a feedback
*From Analog Dialogue 9-1 (1975) also The Best of Analog Dialogue, 1967 to
1991, p. 72.

loop around the sources of error, these connections avoid the
effects of voltage drops; they also correct gain and offset errors
when current-buffer amplifiers are used to drive substantial
loads or sink currents flowing in the wrong direction. The sense
terminal should be connected to the output side of the buffer
amplifier, preferably at the load.
RS (or a current source) must be chosen so that for all expected

values of negative supply and reference load current the groundand output-terminal currents are within ratings.
Q. What about capacitive loads?
A. Many references have output amplifiers that become unstable
and may oscillate when operated with large capacitive loads;
so it is inadvisable to connect high capacitance (several F or
more) to the output of a reference to reduce noise, but 1-10 nF
capacitors are often recommendedand some references (e.g.,
AD588) have noise-reduction terminals to which capacitance
can be safely connected. If force-sense terminals are available,
it may be possible to tailor loop dynamics under capacitive
load. Consult data sheets and manufacturers Application
Engineers to be sure. Even if the circuit is stable, it may not be
advisable to use large capacitive loads since they increase the
turn-on time of the reference.
Q. Dont references turn on as soon as power is applied?
Q. What do you mean by flow in the wrong direction?

A. Consider a +5-V reference operated from a +10-V supply. If
its 5-volt output terminal is loaded by a resistor to ground,
current will flow out of the terminal. If the resistor is instead
connected to the +10-V supply, current will flow into the
terminal. Most references will allow net current flow in either
direction; but some will source current but not sink itor will
sink much less than can be sourced. Such devices, identifiable
by the way their output current is specified on the data sheet,
may not be used in applications where substantial net current
must flow into the reference terminal. A common example is
the use of a positive reference as a negative reference.
+6V +30V
VIN
VOUT 6
AD586
GND
4
5V
RS
4k
15V
Q. Why not just buy a negative reference?

A. Because most single voltage-output references are positive
references. Two-pin active references, of course, can be used
for either polarity; they are used in the same way as Zener
diodes (and they are usually bandgap devices).
For a three-terminal positive reference to be used as a negative
reference, it must be able to sink current. Its output terminal
is connected to ground and its ground terminal (which becomes
the negative-reference terminal) is connected to the negative
supply via a resistor (or a constant current source). The positive
supply pin must generally be connected to a positive supply at
least a few volts above ground. But some devices can provide
negative reference in the two-terminal mode: the positive and
output terminals are connected together to ground.
A. By no means. In many references the current that drives the

reference element (Zener or bandgap) is derived from the
stabilized output. This positive feedback increases dc stability
but leads to a stable off state that resists startup. On-chip
circuitry to deal with this and facilitate startup is normally
designed to draw minimal current, so many references come
up somewhat slowly (1-10 ms is typical). Some devices are
indeed specified for faster turn-on; but some are even slower.
If the designer needs reference voltage very quickly after power
is applied to the circuit, the reference chosen must have a
sufficiently fast turn-on specification; and noise reduction
capacitance should be minimized. Reference turn-on delay may
limit the opportunities for strobing the supplies of data
conversion systems in order to conserve system power. The
problem must still be considered even if the reference is built
into the converter chip; it is also important in systems of this
type to consider the power-up characteristics of the converter
as well [discussed in Ask The Applications Engineer1,
Analog Dialogue 22-2 (1988), p. 29].
High-precision references may require an additional period of
thermal stabilization after turn-on before the chip reaches
thermal stability and thermally induced offsets arrive at their
final values. Such effects will be mentioned on the data sheet
and are unlikely to exceed a few seconds.
Q. Does using these high precision references instead of its internal
reference make a converter more accurate?
A. Not necessarily. For example, the AD674B, a high-speed
descendant of the classical AD574, has a factory-trimmed
calibration error of 0.25% ( l0 LSB) max, with an internal
reference guaranteed accurate to within +100 mV (1%). Since
0.25% of 10 V = 25 mV, full scale is 10.000 V + 25 mV. Suppose
that an AD674B with a 1% high internal reference (10.1 V)
had been factory-trimmed for 10.000 V full scale, by a 1%
gain increase. If an accurate 10.00-V AD588 system reference
were to be connected to the devices reference input, full scale
would become 10.100 V, at 4 times the specified max error.
Q. Please discuss the role of the clock as a system reference.
A. Oops, were out of space! This question introduces a topic that
merits thoughtful discussion. Well do it in a future issue. b
19

GROUNDING (AGAIN)
by Walt Kester
Q. Ive read your data sheets and application notes and also attended
your seminars, but Im still confused about how to deal with analog
(AGND) and digital (DGND) ground pins on an ADC.Your data
sheets usually say to tie the analog and digital grounds together at
the device, but I dont want the ADC to become my systems star
ground point. What do I do?
A. First of all, dont feel bad that you are confused about what to
do with your analog and digital grounds. So are lots of folks!
Much of the confusion comes from the labeling of the ADC
ground pins in the first place. The pin names, AGND and
DGND, refer to whats going on inside the component itself
and do not necessarily imply what you should do with them
externally. Let me explain.
Inside an IC that has both analog and digital circuits, such as
an ADC, the grounds are usually kept separate to avoid
coupling digital signals into the analog circuits. The diagram
shows a simple model of an ADC. There is really nothing the
IC designer can do about the wirebond inductance and
resistance associated with connecting the pads on the chip to
the package pins. The rapidly changing digital currents produce
a voltage at point B which will inevitably couple into point A
of the analog circuits through the stray capacitance. Its the IC
designers job to make the chip work in spite of this. However,
you can see that in order to prevent further coupling, the AGND
and DGND pins should be joined together externally to the
same low impedance ground plane with minimum lead lengths.
Any extra external impedance in the DGND connection will
cause more digital noise to be developed at point B; it will, in
turn, couple more digital noise into the analog circuit through
the stray capacitance. Though an extremely simple model, this
serves to illustrate the point.
VA
A
V D1
VD2
ADC
IC
DIGITAL
LOGIC
ICs
C STRAY
V IN
DIGITAL
CIRCUITS
ANALOG
CIRCUITS
A
B
IA
CSTRAY
ID
AGND
= ANALOG
GROUND PLANE
GND
DGND
= DIGITAL
GROUND PLANE
Q. O.K., youve told me to join the AGND and DGND pins of the IC
together to the same ground planebut I am maintaining separate
analog and digital ground planes in my system. I want them tied
together only at one point: the common point where the power supply
returns are all joined together and connected to chassis ground. Now
what do I do?
20
A. If you have only one data converter in your system, you could
actually do what the data sheet says and tie your analog and
digital ground systems together at the converter. Your system
star ground point is now at the data converter. But this may be
extremely undesirable, unless you initially planned your system
with this thought in mind. If you have several data converters
located on different PCBs, the concept breaks down, because
the analog and digital ground systems are joined at each
converter on a number of PCBs. This is a perfect invitation for
ground loops!
Q. I think Ive figured it out! If I must join the AGND and DGND
pins together at the device, and I want to maintain separate system
analog and digital grounds, I tie both AGND and DGND to either
the analog ground plane or the digital ground plane on the PCB,
but not both. Right? Now, which one should it be, since the ADC is
both an analog and a digital device?
A. Correct! Now, if you connect the AGND and DGND pins
both to the digital ground plane, your analog input signal is
going to have digital noise summed with it, because it is
probably single-ended and referenced to the analog ground
plane.
Q. So the right answer is to connect both AGND and DGND pins to
the analog ground plane? But doesnt this inject digital noise on my
nice quiet analog ground plane? And isnt the noise margin of the
output logic degraded because it now referenced to the analog ground
plane, and all the other logic is referenced to the digital ground plane?
I plan to run the ADC outputs to a backplane tristate data bus
which is going to be pretty noisy to begin with so I think I need all
the noise margin I can get.
A. Well, nobody ever said life was easy or fair! You have reached
the right conclusion by traveling a rocky road, but the problems
you suggestdigital noise on your analog ground plane and
reduced noise margin on your ADC outputsreally arent as
bad as they seem; they can be overcome. It is clearly better to
let a few hundred millivolts corrupt the digital interface than
to apply the same corrupting signal to the analog input where
the least-significant-bit for a 16-bit, 10-V-input-range ADC is
only 150 V! First of all, the digital ground currents on DGND
pins cant really be that bad, or they would have degraded the
internal analog parts of the ADC in the first place! If you bypass
the power pins of the ADC to the analog ground plane, using
a good-quality high-frequency ceramic capacitor for high
frequency noise (say 0.1 F), you will isolate these currents to
a very small region around the IC, and they will have minimal
effect on the rest of your system.
You will incur some reduction in digital noise margin, but it is
usually acceptable with TTL or CMOS logic if its less than a
few hundred millivolts or so. If your ADC has single-ended
ECL outputs, you may want to put a push-pull gate on each
digital outputi.e., one with both true and complementary
outputs. Tie the grounds of this gate package to the analog
ground plane and connect the logic signals differentially across
the interface. Use a differential line receiver at the other end
which is grounded to the digital ground plane. The noise
between the analog and digital ground planes is now commonmodemost of it will be rejected at the output of the differential
line receiver. You could use the same technique with TTL or
CMOS, but there is usually enough noise margin not to require
differential transmission techniques.

However, one thing you said troubles me greatly. In general, it
is unwise to connect the ADC outputs directly to a noisy data
bus. The bus noise may couple back into the ADC analog input
through the stray internal capacitancewhich may range from
0.1 to 0.5 pF. It is much better to connect the ADC outputs
directly to an intermediate buffer latch located close to the
ADC. The buffer latch is grounded to your digital ground plane,
so its output logic levels are now compatible with those of the
rest of your system.
0.1F
VA
VD1
V D2
0.1F
ADC
0.1F
BUFFER
LATCH
TO NOISY
DATA BUS
A
A
Q. I think I understand now, but why on earth didnt you just call all
the ground pins of your ADC AGND in the first place; then none of
this would have come up in the first place?
A. Perhaps. But what if the incoming-inspection person connects
an ohmmeter between these pins and finds out that they are
not actually connected together inside the package? The whole
lot will probably be rejectedand the IC may be blown!
Furthermore, there is a tradition associated with ADC data
sheets which says we must label the pins to indicate their true
function, not what we would like them to be.
Q. O. K. Now, here comes a question Ive been saving as your ultimate
test! I have a colleague who designed a system with separate analog
and digital ground systems. My colleague says that, with the ADCs
AGND pin connected to the analog ground plane and the DGND
pin connected to the digital ground plane, the system is working
fine! How do you explain this?
A. First of all, just because a practice is not recommended doesnt
necessarily mean you cant get away with it some of the time
and thereby be lulled into a false sense of security. (This is one
of the lesser-known of Murphys Laws). Some ADCs are less
sensitive to external noise between the AGND and DGND
pins, and it may be that your colleague picked one of those by
accident. There could be other explanationswhich would
require that we explore your colleagues definition of working
finebut the point is that the ADCs specifications are not
guaranteed by the manufacturer under those operating
conditions. With a complex component like an ADC, it is
impossible to test the device under all possible operating
circumstances, especially those which arent recommended in
the first place! Your friend got lucky this time, but you can be
sure that Murphys law will ultimately catch up with him (or
her) if this practice is continued in future system designs.
Q. I think I understand the ADC grounding philosophy now, but what
about DACs?
A. The same philosophy applies. The DACs AGND and DGND
pins should be tied together and connected to the analog
ground plane. If the DAC has no input latches, the registers
driving the DAC should be referenced and grounded to the
analog ground plane to prevent digital noise from coupling

into the analog output.
Q. What about mixed-signal chips which contain ADCs, DACs, and
DSPs such as your ADSP-21msp5O voiceband processor?
A. The same philosophy applies. You should never think of a
complex mixed-signal chip, such as the ADSP-21msp50, as
being only a digital chip! The same guidelines weve just been
discussing should be applied. Even though the effective
sampling rate of the 16-bit sigma-delta ADC and DAC is only
8 ksps, the converters operate at an oversampling frequency of
1 MHz. The device requires an external 13-MHz clock, and
an internal 52- MHz processor clock is generated from it with
a phase-locked loop. So you see, successful application of this
device requires an understanding of design techniques for both
precision- and high-speed circuits.
Q. What about the analog and digital power-supply requirements of
these devices? Should I buy separate analog and digital power supplies
or use the same supply?
A. This really depends on how much noise is on your digital
supply. The ADSP-21msp50, for example, has separate pins
for the +5- V analog supply and the +5-V digital supply. If you
have a relatively quiet digital supply, you can probably get away
with using it for the analog supply too. Be sure to properly
decouple each supply pin at the device with a 0.1-F ceramic
capacitor. Remember to decouple to the analog ground plane,
not the digital ground plane! You may also want to use ferrite
beads for further isolation. The diagram below shows the proper
arrangement. A much safer solution is to use a separate +5-V
analog supply. You can generate the +5 V from a quiet +15-V
or +12-V supply using a three-terminal regulator, if you can
b
tolerate the extra power dissipation.
REFERENCES [not available from Analog Devices unless noted]
1. Ralph Morrison, Grounding and Shielding Techniques in Instrumentation, Third
Edition. New York: Wiley-lnterscience, 1986.
2. Henry W. Ott, Noise Reduction Techniques in Electronic Systems, Second
0.1F
DIGITAL
SUPPLY
0.1F
A
L
A
L
VD
L = FERRITE
BEAD
VA
MIXED SIGNAL
DEVICE
AGND
DGND
Edition. New York: Wiley-Interscience, 1988.

3. High-Speed Design Seminar, 1996. Norwood MA: Analog Devices, Inc.
4. Mixed-Signal Design Seminar, 1991. Norwood MA: Analog Devices, Inc.
5. Paul Brokaw, An I.C. Amplifier Users Guide to Decoupling, Grounding
and Making Things Go Right for a Change. AN-202. Free from Analog
Devices.
6. Jeff Barrow, Avoiding Ground Problems in High Speed Circuits, R.F.
Design, July, 1989.
7. Paul Brokaw and Jeff Barrow, Grounding for Low- and High-Frequency
Circuits, Analog Dialogue 23-3, 1989. Free from Analog Devices.
8. The Best of Analog Dialogue1967-1991. Norwood MA: Analog Devices,
Inc. Free from Analog Devices.
21
by James Bryant
TIME REFERENCES (continued from 26-1AA-11)
Q. Why do you say that the clock of a system is a reference?
A. This comment does not necessarily apply to the conversion
clock of an ADC; it applies principally to the sampling clock
of a sampled-data system. In these systems, the signal is
required to be sampled repeatedly at predictable (usually equal)
intervals for storage, communication, computational analysis,
or other types of processing. The quality of the sampling clock
is a system-performance-limiting factor.
A. The phase noise of the sampling clock is often ignored, because

the limiting factor on system performance used to be the
aperture jitter of the of the sample-holdbut if we consider
the system as a whole, aperture jitter is just one component of
the total phase noise in the sampling clock chain.With modern
sampling ADCs the aperture jitter may be less important than
other components of phase noise.
SNR = 20 log 10
90
tph = 2ps
A. Dont use the crystal oscillator circuitry in your microprocessor

or DSP processor as the source of your sampling clock. If at all
possible, do not use a logic gate in a crystal oscillator. Crystal
oscillators made with logic gates generally overdrive the crystal;
this is bad for its long term stability, and usually introduces
worse phase noise than would a simple transistor oscillator. In
addition, digital noise from the processoror from other gates
in the package if a logic gate is used as an oscillatorwill appear
as phase noise on the oscillator output.
Q. But crystal oscillators are very stable, arent they?
A. Ideally, use a single transistor or FET as your crystal oscillator
and buffer it with a logic gate. This logic gate, and the oscillator
itself, should have a well-decoupled supply; the other gates in
the package should not be used because logic noise from them
will phase-modulate the signal. (They may be used for dc
applications but not for fast-switching operations.)
If there is a divider between the crystal oscillator and the
sampling clock input of the various ADCs, the divider power
supply should be decoupled separately from the system logic
to keep power supply noise from phase-modulating the clock.
The sampling clock line should be kept away from all logic
signals to prevent pickup from introducing phase noise. Equally,
it should be kept away from low-level analog signals lest it
corrupt them.
Q. You have told me not to use the clock oscillator of my processor as
the sampling clock source.Why not? Isnt it sensible to use the same
oscillator for both, since there will then be a constant phase
relationship between the signals?
A. True. But in such cases, it is often better to use a single discrete
low-noise oscillator to drive the processor clock input and the
sampling clock divider through separate buffers (though they may
share a package) than to use the oscillator in the processor. In
medium-accuracy systems with low sampling rates it may be
possible to use the processors internal oscillatorbut check
with the diagram below).
Q. Just how serious is this problem of noise on a sampling clock? I
hardly ever see it mentioned in articles on sampled data systems.
22
SNR dB
Q. But crystal oscillators are very stable, arent they?
Q. How can I ensure that my sampling clock has low phase noise?
14
80
tph = 10ps
70
A. They have good long-term stability, but they are often used in
ways which introduce short-term phase noise. Phase noise is
also introduced by designers who, instead of using crystal
oscillators, use R-C relaxation oscillators (such as the 555 or
the 4046)which have a great deal of phase noise.
1
2fta
60
12
10
tph = 50ps
50
tph = 250ps
40
30
ENOB
ODDS N ENDS (Continued from earlier issues)
tph = 1250ps
20
10
0
1
10
20
30
50
70
100
FREQUENCY OF FULLSCALE SINEWAVE INPUT MHz
The diagram shows the effect of the total phase jitter of the
sampling clock on signal-to-noise ratio (SNR) or effective
number of bits (ENOB). This jitter has the rms value of tph,
which is made up of the root-sum-of-squares of the phase jitter
on the sampling clock oscillator, the phase jitter introduced by
pickup during transmission of the sampling clock through the
system, and the aperture jitter of the SHA in the sampling
ADC. This diagram may be somewhat unsettling, as it shows
just how little phase noise is required to corrupt a
high-resolution sampled-data system.
MORE ON TRIMMING
Q. I dont have enough range to adjust the offset of my circuitand it
seems to have rather more drift than Id expected.
A. Ill bet the amplifier is a bipolar type and you are using its
offset-trim terminals to trim other circuit voltages.
Q. How did you guess?
A. The range of offset adjustment of an op amp is normally 2 to
5 times the maximum expected offset of the lowest grade of
the device (in some early op amps, it was much larger, but
such a wide range is not ideal). If the lowest grade has a VOS
(max) of 1 mV, then the likely adjustment range with the
recommended circuit is 2 to 5 mV.
If the external voltage you are attempting to compensate for is
larger than this (referred to the op amps input), you will not
be able to do so with the amplifiers offset-trim terminals.
Furthermore, if you are using a bipolar-input op amp, it is
inadvisable to use these terminals for external offset correction
because drift will be increased. Heres why: the input stage
thermal drift is proportional to the internal offset; if this
has been trimmed to a minimum, the drift will also be a
minimum. If you then trim the amplifier to compensate for an
external offset, drift will no longer be minimized. However,
FET-input op amps have separately trimmed offset and drift,
their offset adjustment terminals may thus be used for small
b
system adjustments.

CONFUSED ABOUT AMPLIFIER DISTORTION SPECS?
The expression for THD+N is similar; simply add the noise in

root-sum-square fashion (Vnoise = rms value of noise voltage
over the measurement bandwidth).
by Walt Kester
Q. Ive been looking at your amplifier data sheets and am confused
about distortion specifications. Some amplifiers are specified in terms
of second- and third-harmonic distortion, others in terms of total
harmonic distortion (THD) or total harmonic distortion plus
noise (THD+N), still others have some of these specifications as
well as two-tone intermodulation distortion and third-order
intercept. Can you please clarify?
A. Because the amplifier is fundamental to a wide range of uses,
it is natural that many application-specific specifications have
evolved as new amplifiers have been developed to meet those
needs. Soas you so rightly pointed outdistortion may be
specified in various ways; the spec depends on how distortion
is defined by users for the particular application. Some distortion specifications are fairly universal, while others are primarily associated with specific frequency ranges and applications.
But there is some standardization of the basic definitions, so
lets talk about them first. Harmonic distortion is measured
by applying a spectrally pure sine wave to an amplifier in a
defined circuit configuration and observing the output spectrum. The amount of distortion present in the output is usually
a function of several parameters: the small- and large-signal
nonlinearity of the amplifier being tested, the amplitude and
frequency of the input signal, the load applied to the output of
the amplifier, the amplifiers power supply voltage, printed
circuit-board layout, grounding, power supply decoupling, etc.
So you can see that any distortion specification is relatively
meaningless unless the exact test conditions are specified.
Harmonic distortion may be measured by looking at the output spectrum on a spectrum analyzer and observing the values
of the second, third, fourth, etc., harmonics with respect to
the amplitude of the fundamental signal. The value is usually
expressed as a ratio in %, ppm, dB, or dBc. For instance,
0.0015% distortion corresponds to 15 ppm, or 96.5 dBc. The
unit dBc simply means that the harmonics level is so many
dB below the value of the carrier frequency, i.e., the
fundamental.
Harmonic distortion may be expressed individually for each
component (usually only the second and third are specified),
or they all may be combined in a root-sum-square (RSS)
fashion to give the total harmonic distortion (THD).
THD =
THD =
V 22 + V 32 + V 42 + L + V n2 + Vnoise 2
Vs
It should be evident that THD+N THD if the rms noise

over the measurement bandwidth is several times less than the
THD, or even the worst harmonic. It is worth noting that if
you know only the THD, you can calculate THD+N fairly
accurately using the amplifiers voltage- and current-noise
specifics. (Thermal noise associated with the source resistance
and the feedback network may also need to be computed).
But if your rms noise level is significantly higher than the level
of the harmonics, and you are only given the THD+N
specification, you cannot compute the THD.
Special equipment is often used in audio applications for a
more-sensitive measurement of the noise and distortion. This
is done by first using a bandstop filter to remove the
fundamental signal. The total rms value of all the other
frequency components (harmonics and noise) is then measured
over an appropriate bandwidth. The ratio to the fundamental
is the THD + N spec.
Q. How are the distortion specs looked at over the various frequency
ranges and applications?
A. I think the best way is to start at the low frequency end of the
spectrum and work our way up; that will make it easier to see
the underlying method.
Audio-frequency amplifiers are a good place to start. Types
used here (such as the OP-275*) are optimized for low noise
and low distortion within the audio bandwidth (20 Hz to
20 kHz). In audio applications, total harmonic distortion plus
noise (THD+N) is usually measured with specialized equipment such as the Audio Precision System One. The output
signal amplitude is measured at a given frequency (e.g.,
1 kHz); then, as above, the fundamental signal is removed
with a bandstop filter and the system measures the rms value
of the remaining frequency components, which contain both
harmonics and noise. The noise and harmonics are measured
over a bandwidth that will catch the highest harmonics, usually about 100 kHz. The measurement is swept over the frequency range for various conditions. THD+N results for
OP-275 are plotted here as a function of frequency.
V 22 + V 32 + V 42 + L + V n2
Vs
where
Vs = signal amplitude (rms volts)
V2 = second harmonic amplitude (rms volts)
Vn = nth harmonic amplitude (rms volts)
The number of harmonics included in the THD measurement
may vary, but usually the first five are enough. You see, the
RSS process causes the higher-order terms to have negligible
effect on the THD, if they are 3 to 5 times smaller than the
largest harmonic [ 0.10 2 + 0.032 = 0.0109 = 0.104 0.10].
23
A. Actually, we are not trying to be misleading here.The distortion

is at the limits of measurement of the available equipment,
and the noise is even lowerby 20 dB! Here is the measured
THD of the AD797 as a function of frequency.
100
0.001
110
0.0003
120
0.0001
THD %
THD dB
90
MEASUREMENT
LIMIT
130
100
300
1k
3k
10k
FREQUENCY Hz
30k
100k
300k
The measurement was made with a spectrum analyzer by first

filtering out the fundamental sine-wave frequency ahead of
the analyzer. This is to prevent overdrive distortion in the
spectrum analyzer. The first five harmonics were then
measured and combined in a root-sum-square fashion to get
the THD figure. The legend on the graph indicates that the
measurement-equipment floor is about 120 dB; hence at
frequencies below 10 kHz, the THD may be even less.
For noise, multiply the voltage noise spectral density of the
AD797 (1 nV/Hz) by the square root of the measurement
bandwidth to yield the devices rms noise floor. For a 100-kHz
bandwidth, the noise floor is 316 nV rms, corresponding to a
signal-to-noise ratio of 140 dB for a 3-V rms output signal.
VOUT = 2V pp
50
2nd
RL = 50 or 100
60
70
3rd
80
RL = 100
90
3rd
RL = 50
100
0.1
A. Because of the increasing need for wide dynamic range at high

frequencies, most wideband amplifiers now have distortion
specifications. The data sheet may give individual values for
the second and third harmonic components, or it may give
THD. If THD is specified, only the first few harmonics
contribute significantly to the result. At high frequencies, it is
often useful to show the individual distortion components
separately rather than specifying THD. The AD9620 is a
600-MHz (typical 3-dB bandwidth) low distortion unity-gain
buffer. Here are graphs of the AD9620s second and third
harmonic distortion as a function of frequency for various
loading conditions.
24
2
4 6 10
FREQUENCY MHz
20
40 60 100
Q. What are two-tone intermodulation products, and how do they differ

from harmonic distortion?
A. When two tones are applied to an amplifier that is non-linear,
the nonlinearity causes them to modulate one another,
producing intermodulation distortion (IMD) in the form of
frequencies known as intermodulation products. (For the
mathematical development of this concept, see Reference 1).
For two tones at frequencies, f1 and f2 (where f2 > f1), the
second- and third-order IM products occur at the following
frequencies:
Second Order: f1 + f2, f2 f1
Third Order: 2f1 + f2, 2f2 + f1, 2f2 f1, 2f1 f2
If the two tones are fairly close together, the third-order IMD
products at the difference frequencies, 2f2 f1 and 2f1 f2, may
be especially troublesome becauseas the figure shows they
are hard to filter out. Notice that the other second- and
third-order IMD productswhich occur at substantially
higher or lower frequenciescan be filtered (if the only
frequencies of interest are in the neighborhood of f1 and f2).
SECOND- AND THIRD-ORDER
INTERMODULATION PRODUCTS
f1 f2
2 = SECOND-ORDER IMD PRODUCTS

3 = THIRD-ORDER IMD PRODUCTS
NOTE: f 1 = 5MHz, f 2 = 6MHz
2
f 2f1
Q. How is distortion specified for high frequency amplifiers?
0.6
0.2
AMPLITUDE
Q. I noticed that Analog Devices recently introduced another low-noise,

low-distortion amplifier (AD797) and that it is specified in THD,
not THD+N. The actual specification quoted at 20 kHz is
120 dB.What gives?
40
DISTORTION dBc
The signal level is 3 V rms, and the amplifier is connected as a

unity-gain follower. Notice that a THD+N value of 0.0008%
corresponds to 8 ppm, or 102 dBc. The input voltage noise of
the OP-275 is typically 6 nV/Hz @ 1 kHz and, integrated
over a 100-kHz bandwidth, yields an rms noise level of 1.9 V
rms. For a 3-V rms signal level, the corresponding signal-tonoise ratio is 124 dB. Because the THD is considerably greater
than the noise level, the THD component is the primary
contributor.
2
3
2f1 f2
2f 2f 1
f2+f 1
2f1
2f 2
7
10 11 12
FREQUENCY MHz
3
3f 1 2f 2+f 1
3
2f1 +f 2 3f 2
15 16 17 18
Two-tone intermodulation-distortion specifications are of

especial interest in r-f applications and are a major concern in
the design of communications receivers. IMD products can
mask out small signals in the presence of larger ones. Although
IMD has been rarely specified in op amps operating at
frequencies less than 1 MHz, many of todays dc op amps are
wideband types that can operate usefully at radio frequencies.
For this reason, it is becoming common to see IMD
specifications on fast op amps.
Q. What are the second- and third-order intercept points, and what is
their significance?

A. Usually associated with r-f applications, these specs provide
figures of merit to characterize the IMD performance of the
amplifier. The higher the intercept power, the higher the input
level at which IMD becomes significantand the lower the
IMD at a given signal level.
Heres how it is derived: Two spectrally pure tones are applied
to the amplifier. The output signal power in a single tone (in
dBm) and the relative amplitudes of the second-order and thirdorder products (referenced to a single tone) are plotted (and
extrapolated) here as a function of input signal power.
SECOND-ORDER
INTERCEPT
INT 2
INT 3
Another parameter that may be of interest is the 1-dB

compression point, shown in the figure. This is the point at
which the output signal has started to limit and is attenuated
by l dB from the ideal input/output transfer function.
The figure below is a plot of the third-order intercept power
values for the AD9620 buffer amplifier as a function of input
frequency. Its data can be used to approximate the actual value
of the third order intermodulation products at various
frequencies and signal levels.
THIRD-ORDER
INTERCEPT
1dB COMPRESSION
50
50
1dB
POINT
INTERCEPT +dBm
OUTPUT POWER (PER TONE) dBm
INTERCEPT POINTS, GAIN COMPRESSION, IMD
the IMD products with respect to the output power actually

delivered into the 50- load rather than the actual op-amp output
power.
FUNDAMENTAL
(SLOPE = 1)
SECOND-ORDER IMD
(SLOPE = 2)
THIRD-ORDER IMD
(SLOPE = 3)
50
40
TEST CIRCUIT
30
INPUT POWER (PER TONE) dBm
Beyond a certain level, the output signal begins to soft-limit,

or compress (coinciding with the increasing visibility of IMD
products). If you extend the second- and third-order IMD
lines, they will intersect the extension of the output/input line;
these intersections are called the second- and third-order
intercept points. The projected output power values
corresponding to these intercepts are usually referenced to the
output power of the amplifier in dBm.
Since the slope of the third-order IMD amplitudes is known
(3 dB/dB), if the intercept is also known, the third-order
products at any input (or output) level can be approximated.
For a higher intercept, the line moves to the right (same slope),
showing lower 3rd-order products for a given input level.
Many r-f mixers and gain blocks have 50- input and output
impedances. The output power is simply the power that the
device transfers to a 50- load. The output power is calculated
by squaring the rms output voltage (Vo) and dividing by the load
resistance, RL. The power is converted into dBm as follows:
2
V0
RL
Output power = 10 log 10
d Bm
1mW
Since an op amp, on the other hand, is a low-output-impedance

device, for most r-f applications, the output of the op amp
must be source- and load-terminated. This means that the
actual op amp output power has to be 3 dB higher than the
power delivered to the load, as calculated from the above
formula. In this type of application, it is customary to define
20
dc
50
100
150
FREQUENCY MHz
Assume the op amp output signal is at 20 MHz with 2 V

peak-to-peak into a 100- load (50- source and load
terminations). The voltage into the 50- load is therefore 1 volt
peak-to-peak, with a power of 2.5 mW, corresponding to
+4 dBm. The value of the third-order intercept at 20 MHz
from the graphis +40 dBm.This permits a graphical solution,
as shown below. For an output level of +4 dBm, the third-order
IMD products, based on an extrapolation of the slope of 3
back from the intercept, amount to 68 dBm, or 72 dB below
the signal.
+40
+20
1dB/dBUNITY
SLOPE
THIRD-ORDER
INTERCEPT
+4dBm
+20
0
POWER dBm
If you go through the mathematical analysis [1], you will find

that if device nonlinearity can be modeled by a simple powerseries expansion, the second-order IMD amplitudes tend to
increase by 2 dB for every l dB of signal increase. Similarly,
the third-order IMD amplitudes increase 3 dB for every 1 dB
of signal increase. Starting with a low-level two-tone input signal
and taking a few IMD data points, you can draw (and
extrapolate) the second- and third-order IMD lines shown on
the diagram.
+40
OUTPUT POWER dBm
THIRD-ORDER
IM PRODUCTS
IMD N = INT N(N1) NP OUT ,
WHERE: N = ORDER OF THE IMD
IMD N = N TH -ORDER IMD PRODUCT (dBm)
20
INT N = N TH -ORDER INTERCEPT POINT (dBm)
40
P OUT = OUTPUT POWER INTO THE LOAD (dBm)

3dB/dB
SLOPE 2ND ORDER IMD: IMD 2 = INT 2 2P OUT
60
68dBm
3RD ORDER IMD: IMD 3 = 2INT 3 3P OUT

IN THIS EXAMPLE:
IMD 3 = 2 40dBm 3 4dBm = 68dBm
80
This analysis assumes that the op-amp distortion can be

modeled with a simple power series expansion as described in
Reference 1. Unfortunately, op amps dont always follow simple
models (especially at high frequencies), so the third-order
intercept specification should primarily be used as a figure of
b
merit, rather than a substitute for measurements.
REFERENCES
1. Robert A. Witte, Distortion Measurements Using a Spectrum Analyzer,
RF Design, September 1992, pp. 75-84. (not available from ADI)
2. High Speed Design Seminar, 1996. Norwood, MA: Analog Devices, Inc.
3. 1992 Amplifier Applications Guide. Norwood, MA: Analog Devices, Inc.
25

by James Bryant (ADI Europe)
with Herman Gelbach (The Boeing Company)
HIGH-FREQUENCY SIGNAL-CONTAMINATION
Q. Ive heard that RF can make low-frequency circuits do strange
things. Whats that all about?
A. I was once summoned to France because an Analog Devices
Voltage-Frequency Converter (VFC), the AD654, suffered
from unacceptable variation of accuracy. I had measured the
offending parts in my own laboratory and found them to be
stable and within specification, but when I returned them to
the customer with my test jig he was unable to reproduce my
results. While considering a site visit to confirm my suspicions,
I discovered that the restaurant La Cognette in the town
where our customer was located had three stars in the Guide
Michelin, and the chef was a Maitre Cuisinier de Francea
title not lightly bestowed. The visit to the customer became
doubly necessary. Herman, who was in England to look at data
offsets in a Boeing wind tunnel test, offered to come and help
he said it was the interesting technical problem (but just before
he offered I saw him earnestly consulting the Guide Michelin).
To drive from the Analog Devices office in Newbury in the
South of England to the centre of France involves six hours of
driving, a six hour ferry crossing of the English Channel, and
a change from the correct side to the right side of the road.
Nevertheless, driving is better than flying, because one can
take more test gear (and the portable ham-radio station as
wellwe are both hams).
As we approached the customers works we passed an enormous
short-wave transmitting antenna, and then another, and yet
another. We began to guess what might be wrong, and when
we entered the laboratory I was carrying a hand-portable
two-metre ham transceiver (an HT or handy-talky) in my
jacket pocket.
The AD654 was indeed behaving unstably, as the customer
had claimed. The VFCs output frequency varied by an
equivalent offset of tens of mV over the space of a few minutes.
I quietly reached into my pocket and pressed the transmit
button of my HT. The output frequency jumped by an
equivalent of 150 mV, thus demonstrating the problem to be
high-frequency pickup. More-formal measurements a little later
showed that the local transmitters (of the French Overseas
Broadcast organization) produced high-frequency (HF) field
strengths within our customers works of tens or hundreds
of mV/m.
Many problems of instability in precision measurement circuitry can be traced to high-frequency interference, but unless
there is a loudspeaker in the system that might unexpectedly
burst into hard rock music from the nearby radio station, it is
common for engineers to overlook this source of inaccuracy and
blame the manufacturer of the amplifiers or data converters.
Furthermore, this case was unusual in that it took a highpowered signal to affect the AD654, which is single-ended and
also relatively insensitive to RFit is much more common to
see with a differential amplifier in-amp. Both inputs of these
types of amplifier have high input impedances to common;
26
they are therefore far more vulnerable and are affected by

low-level RF, such as radiation from a personal computer (PC).
[This phenomenon is detailed in the Analog Devices
system-design seminar notes, available for sale as System
Application Guide (1993).]
An important factor is that, in instrumentation amplifiers,
common-mode rejection decreases with increasing frequency,
starting to roll off at quite low frequenciesand distortion
increases with frequency. Thus, not only are high-frequency
common-mode signals not rejected; they are distorted,
producing offsets. For some applications, where RF interference
is a strong possibility, the AD830 difference amplifier has
wideband common-mode rejection and is designed for
line-receiver applications; it may be a useful substitute for an
instrumentation amplifier.
Sensors are often connected to their signal-conditioning
electronics by long cables. Radio engineers have a term for
such long pieces of wire; they call them antennas. The long
feeders from sensors to their electronics will behave in the
same way and will serve as antennas, even if we do not wish
them to do so. It does not matter if the sensor case is
groundedat high frequencies the reactances of the case and
feeders will allow the system to behave as an antenna, and any
high- frequency signals (E-field, M-field, or E-M-field) which
it encounters will appear across any impedances. The most
likely place for them to end up is at the amplifier input.
Precision low-frequency amplifiers can rarely cope with large
HF signals, and the result is errorcommonly a varying offset
error.
Q. But this couldnt happen to me!
A. Never believe it wont happen to you! An easy free lunch can
always be obtained by persuading an innocent to bet on his or
her circuit being free of such problems. Using a ham radio HT
on the two-metre (144-148-MHz) band, one watt at a distance
of one meter for one second will win you your free lunch
almost every time. But a less-dramatic test can be equally
convincing.
Disconnect the sensor and its leads. Short-circuit the amplifier
input terminals to each other and to the amplifier circuit
common (probably ground) with the shortest possible links
and measure the amplifier output; observe its stability over a
few minutes. Now remove the short-circuit, replace the sensor
leads and place them in their normal operating environment.
Disable the excitation and short-circuit the signal leads at the
sensor end. Again measure the amplifier output, and its
variation with time. Weep quietly.
It is often possible to see what is happening by using a highfrequency oscilloscope (or a spectrum analyzer, which is more
sensitive but less easy to interpret) to measure the HF noise,
both normal mode and common-mode, at the amplifier input;
but normal mode measurements must be treated with some
suspicion, because the oscilloscope itselfand its power- and
probe leadsmay themselves introduce signals and invalidate
the measurement. The effect of the oscilloscope may be
minimized by using a simple broadband transformer between
the measurement point and the oscilloscope input, as shown
in the figure; but such a transformer has fairly low impedance
and will load the circuit being measured.

FERRITE
TOROID
SIGNAL
TO OSCILLOSCOPE
OR SPECTRUM ANALYSER
TO MEASUREMENT
POINT
GUARD
PIN
GUARD
Common-mode signals can be observed quite easily by

disabling any sensor excitation and connecting the oscilloscope
ground to the ground at the board input and joining all the
sensor leads together and to the oscilloscope input. All too
often this signal will have an amplitude of several hundred
millivolts and contain components from low frequencies to tens
or hundreds of MHz.
The world is full of HF noise sources: ham radio operators,
police, people with portable phones, garage door openers, the
sun, supernovas, switching power-supply and logic signals
(e.g., PCs). Since we cannot eliminate HF noise in the
environment, we must filter it out of low-frequency signals
before they arrive at precision amplifiers.
The simplest type of protection can be used when the signal
bandwidth is only a few Hz. A simple RC low-pass filter
inserted ahead of an amplifier will afford both normal-mode
and common-mode HF protection. A suitable circuit is shown
in the figure. There are two important issues to be considered
in the choice of components: the resistances R and R9 (shown
as 1 k in the diagram, a value suitable for amplifier bias
currents of a few nA or less) must be chosen so that they do
not increase the offset appreciably as the amplifier bias current
flows in them. The normal-mode time constant, (R + R9)C2,
must be much larger than the common-mode time constants,
RC1 and R9C19, otherwise the common-mode time constants
would have to be very carefully matched to avoid an imbalance
that would convert the common-mode to a signal between the
differential inputs.
The guard line is connected to ground at the source end and

at the other end to the amplifiers guard pin (or a comparable
derived voltage), which represents what the amplifier thinks
is common mode, via a capacitor. The high-frequency commonmode signal will appear (by definition) across the bottom
winding, and will induce an equal common-mode voltage in
the other two, subtracting the common-mode voltage in series
with each line and effectively cancelling the HF common-mode
signal at the amplifier inputs.
There are, of course, potential problems. A capacitor in series
with the transformer is almost essential in the guard circuit to
block DC and LF and prevent transformer core saturation by
low-frequency currents in the guard circuit. The impedance
looking into the amplifier guard terminal must be much lower
than the impedance of the transformer windings; and at very
high frequencies the capacitances of the transformer will allow
signal leakage or may cause phase shift. These issues set
incompatible constraints on the design of the transformer, if it
must deal with a very wide range of common-mode frequencies.
In such a case double cancellation using two separate
transformers as shown might be consideredthe one nearer
the amplifier having high inductance (and correspondingly high
capacitance) and the other having good VHF efficiency.
HF TRANSFORMER
(LOW C)
MF TRANSFORMER
SIGNAL
GUARD
PIN
R 1k
C1
0.01F
C1
0.01F
GUARD
C2
0.1F
R 1k
If the signal bandwidth is wider, such simple filters will not be

suitable because they remove the desired HF normal-mode
signals as well as the unwanted HF common-mode signals.
Large HF common-mode signals are very likely to suffer
common-modenormal mode conversion (as well as minor
rectification, producing low-frequency errors) if they get to
the amplifier, so it is necessary to use a filter which will reject
HF common-mode signals but will pass DC and HF
normal-mode signals.
Such a filter is shown below. It was devised many years ago by
Bill Gunning of Astrodata and is related to the phantom
circuit used in long-distance telephone circuits. It uses a tightly
coupled trifilar transformer having three windings in an
accurate 1:1:1 ratio. An AC voltage across any winding will
also be present on the others.
Other approaches are also possible: the amplifier can be sited

closer to the sensor and the long leads be replaced by leads (or
optical fibre) carrying digital data, which is less vulnerable;
more shielding is often (but not always) helpful; and sometimes
(but rarely) it is possible to reduce the possibility of unexpected
HF signals (even if you keep away the hams and police, there
is always the possibility of the unexpected pizza delivery truck
radioing to its base . . .)
The most important consideration, though, is awareness of
the possibility of HF interference and readiness to tackle it. If
designs are always made in the expectation of unwanted HF,
chances are excellent that precautions will be adequateits
when you dont expect it that the trouble starts.
Q. How did it work out with the French customer?
A. His problem was cured with two resistors, three capacitors and
a piece of grounded copper foil. We went off to La Cognette
b
to celebrate.
27
A Reader Notes
HIGH-FREQUENCY SIGNAL CONTAMINATION
by Leroy D. Cordill*
I found your article on high-frequency signal contamination (Ask
The Application Engineer14, Analog Dialogue 27-2, 1993)
interesting and would like to offer some additional comments.
EMI/EMC requirements are becoming more important to
designers of industrial equipment as analog signal sensitivities are
increased while more RF generators (higher-frequency digital
circuits) are incorporated into the same equipment. Therefore, I
would like to see a good application note relating to the issue of RF
susceptibility produced by someone such as Analog Devices. By
good, I feel it should cover:
a. rules of thumb about the types of circuits where you will
likely have trouble
b. some explanation of the phenomenon
c. general grounding/shielding approaches for equipment
d. fix type approaches to minimizing the effects when items
from (c) cant be implemented
e. bench-level testing techniques.
(At least Im not aware of any such application note in existence;
maybe one exists and I havent found it.) Based on my own
experience, I offer the following comments on the above five areas:
Regarding (a), I generally see the problem with low-level input or
preamp circuits involving a voltage gain of 50 V/V or more. In my
case, the signals are usually from thermocouples, RTDs, pressure
sensors, etc., and the required signal bandwidth is less than 100 Hz.
And Im trying to maintain signal integrity suitable for conversion
by a 10-to-14-bit A/D converter.
For (b), my model of the effect is that the error gets created by
rectification of the rf at the base-emitter junctions at the inputs of the
op amp, and essentially becomes a large input offset voltage for the
op amp. This introduces errors into dc-coupled circuits that cannot
be corrected for by any usual low-pass filtering of the signal.
One observation I have made regarding this susceptibility problem
is that it is primarily related to bipolar-type op amps (741, 5558,
OP05, OP07, OP27, AD708, OP220, etc.) If I swap to a FETinput op amp (TL082, TL032, OP80, OP42, AD845) the error
will largely disappear. (Due to other considerations, this is not usually
a permanent solution, but helps to identify error sources during
EMC testing.)
Also involved is the RF impedance at the two input nodes of the op
amp. If (in a typical inverting configuration) the feedback path has
a capacitor for low-pass filtering, it aggravates the problem as one
input node of the op amp sees more of the RF than the other. If this
is the situation, Im not sure a wide-bandwidth op amp would help
(regarding suggestions for using an AD830). Even without an
intentional discrete capacitor in the feedback loop, PC-board layout
makes it difficult to count on matched impedances at the two inputs.
*RR 3 Box 8910, Bartlesville OK 74003. Leroy Cordill, a design engineer with
Applied Automation, Inc., has been involved in designing process gas
chromatographs for about 20 years. His areas of design have included system
architecture, analog, digital, and serial communication circuits, as well as GC
detectors and valves.
28
Regarding (c), a good RF ground to the chassis is important for

the signal common; but I find the shielding/grounding aspects of
the equipment design relate more to the ESD requirements than
RF (continuous-wave) susceptibility problems. I also try not to
rely on these (shielding/grounding) to a great extent, since I find
them very uncontrollable during the life of a piece of fieldcustomizable equipment.
For (d), my best, most consistent prescription is placing a small
capacitor directly across the input pins on bipolar op amps. I have
used 100-1000 pF for this purpose in various circuits; it usually
significantly reduces or eliminates the problem up to the level of
interference that I plan for. I have found that with this in place on
the critical parts of the circuit, the requirements for extreme care in
grounding and shielding of cables are greatly reduced.
Regarding (e), I agree that a small walkie-talkie is useful, but
primarily as a go/no-go test on the equipment when it is all
assembled, in the enclosure, etc. However, for pc board or circuitlevel work, I have two problems with the walkie-talkie technique:
(1) you will get many unkind remarks from the guy on the next
bench over if hes trying to breadboard a low-level circuit and is not
ready for EMI testing yet; and (2) if you start attaching leads to
various points in the circuit to determine where the problems are,
and then apply RF in a radiated fashion, you have so many antennae,
both to your circuit and to the various test gear, that you will have
no idea what is happening.
I prefer to use an RF signal generator and apply the interference in
a conducted fashion. This allows much better control of which items
get RF applied to them. I dont use a lot of RF power, as I usually
connect the output of the generator directly to some connector or
cable supplying the low-level signal of interest, or in some cases the
body of a sensor. A few hundred millivolts of RF signal is generally
sufficient to identify problem circuits. I manually sweep from about
10 MHz to 100 MHz. While this is not a quantitative type of test, it
is a very useful qualitative technique.
Some of the RF generators I have used for this are older model
unitsusually acquired at garage sales for $5 to $20 each:
RCA WV-50B
Advance Schools, Inc., Model IGB-102
Heathkit Model IG-102 (same as above)
Precise Model 630
I hope this may be useful, and, as I mentioned would like to see a
good application note put together on this subject by someone who
can add some additional information regarding performance
implications of adding a capacitor on the op-amp inputs for various
circuit configurations.
Thanks to Mr. Cordill for a useful contribution to the Dialogue, and for
throwing down the gauntlet to our Application Engineers. They have
accepted the challenge; so keep your eyes on the Worth Reading page
in future issues. Having said that, we feel obliged to point out that the
challenge is to get it together in one place; much of the material he
suggests already exists in the Analog Devices literature (and elsewhere).
For example, the System Applications Guide devotes pages 1-13 thru
1-55 to remote sensor application problemsincluding an exhaustive
discussion of RFI rectification in high-accuracy circuits. Other good sources
include the Applications Reference Manual, Chapter 3 and Bibliography
of the Transducer Interfacing Handbook, and Part 5 and Bibliography of
the Analog-Digital Conversion Handbook.
b
Q: How do I make sure that a one-pole RC filter will suffice for my

applicationand establish the time constant of the filter?
by Oli Josefsson
USING SIGMA-DELTA CONVERTERSPART 1
Q: Id like to use sigma-delta A/Ds but have some questions because
they seem markedly different from what Ive been using. To start
with, what issues do I need to consider when designing my
antialiasing filter?
A: A major benefit of oversampling converters is that the filtering
required to prevent aliases can be quite simple. To understand
why this is the case and what the filter constraints are, lets
look at the basic digital signal processing that takes place in
such a converter. For the purpose of anti-alias filter design we
can think of a sigma-delta converter as a conventional highresolution converter, sampling at a rate much faster than the
Nyquist sampling rate, followed by a digital decimator/filter;
the fact that the input into the digital decimator is 1-bit serial
with a noise-shaping transfer function is irrelevant.
The input signal is sampled at Fms, the modulator input
sampling rate, which is much faster than twice the maximum
input signal frequency (the Nyquist rate). The figure shows
what the frequency response of a decimation filter may look
like; frequency components between fb and Fmsfb are greatly
attenuated. Thus, the digital filter can be used to filter out all
energy from the converter within [0, Fmsfb] that does not fall
within the bandwidth of interest [0, fb]. However, the converter
can not distinguish between signals appearing at the input that
are in the range [0, fb] and those in the ranges, [kFms fb], where
k is an integer. Any signals (or noise) in those ranges get aliased
down to the bandwidth of interest [0,fb] via the sampling
process; the decimation filter, which works only on the digitized
samples, cannot be of any help attenuating these signals.
MAGNITUDE dB
REPEATS AT INTEGER
MULTIPLES OF Fms
fb
Fms
Fms fb
Fms
Lets assume that we have an application where the bandwidth

of interest is 0 to 20 kHz, and signals in this range must
not be attenuated more than 0.1 dB, or a ratio of 0.9886
[dB = 20 log10 (ratio) for voltage and 10 log10 (ratio) for power].
From the formula for attenuation of a single-pole filter,
ratio =
1+ 2 fRC
RC
( )
(2 f ) (ratio )
1 ratio
2
> 0.99 at f = 20 kHz
1.2110 6 s
Choosing RC = 1.0 s, to allow for component tolerances, the

3-dB frequency will be 159 kHz. We can now calculate the
attenuation the filter will provide in the frequency bands,
kFms fb, that alias down to the baseband. Assuming that the
AD1877 has a modulator sampling rate of 3.072 MHz (and
output sampling rate of 48 kHz), the first frequency band
occurs at 3.052 MHz to 3.092 MHz. The attenuation of
the RC filter at these frequencies is approximately 25.7 dB
(about 0.052) over the whole band. Over the second band
(6.124 MHz to 6.164 MHz), the attenuation is 31.8 dB
(0.026). We know that the noise in these two bands (and all
higher bands up the scale) that escapes through the filter to
the A/D input will be aliased down to the baseband and get
added as root sum-of-the-squares (rss) of their rms values,
i.e., n12 + n22 + . . . + ni 2 . For values given in dB, the formulas
shown the Appendix can provide results directly in dB, avoiding
the intermediate step of computing the ratios.
Thus it is the input noise energy in these bands [kFms fb] that
must be removed by the antialiasing filter before the input signal
is sampled by the converter.
Q: So if I were to use the AD1877, which has a dynamic range of
90 dB, the antialiasing filter will need attenuation well above 90 dB
at Fms fb ( 3 MHz)?
A: Not quite. You are assuming that the A/D has full-scale input
at frequencies close to the modulator sampling rate; this is
simply not the case in most systems. The only signal input of
concern for aliasing is normally just noise from sensors and
circuitry preceding the converter. The noise is usually low
enough for a simple RC filter to suffice as an antialias filter.
A: Your application will typically specify a maximum allowable

attenuation of an input signal that falls within the bandwidth
of interest. This in turn puts a minimum on the 3-dB point of
the RC filter. Lets take a look at an example using the ADl877
to illustrate this point further and to show how one might verify
that a single-pole filter will provide enough filtering.
For white noise, the noise spectral density is constant as a

function of frequency, and each frequency range has the same
bandwidth, so each band contributes an equal amount of noise
to the input of the filter. We can therefore find the effective
attenuation of the RC filter by adding the attenuation of the
different frequency bands in rss fashion. The noise contribution
from the first two bands, for example, is the same as the
contribution from a single frequency band with attenuation of
0.052 2 + 0.026 2 = 0.058, or 24.7 dB, compared with

25.7 dB for the first band. How many bands do we need to
consider when calculating the total aliased noise? For this case,
the rss sums of the first 3, 4, 5, and 6 bands are, respectively,
24.2, 24.0, 23.9, 23.8 dB. The first band is therefore quite
dominant; its attenuation is within 2 dB of the attenuation for
all bands. It is usually sufficient to take only the first band into
account unless the noise is exceptionally large or has a
non-white spectrum; in addition, the A/D itself, though fast,
has limited bandwidth; it tends to reject high-order bands.
29
= 59 nV / Hz
3.092 MHz 3.052 MHz
This is the maximum post-filter spectral density allowed. To

find the maximum prefilter spectral density (MPSD), with the
effective filter attenuation of 20 dB (i.e., 0.1) established
previously, M.P.S.D. = 10 59 nV/Hz = 0.59 V/Hz.
Clearly your system has to be pretty noisy in the 3-6-9-12-MHz
regions in order for a simple RC filter not to suffice; however,
as always, one must be careful of ambient rf pickup.
Q: As I understand it, the noise floor of sigma-delta converters may
exhibit some irregularities. Any thoughts on that?
A: Most sigma-delta converters exhibit some spikes in the noise
floor, called idle tones. In general, these spikes have low energy,
not enough to substantially affect the S/N of the converter.
Despite that, however, many applications cannot tolerate spikes
in the frequency spectrum that extend much beyond the white
noise floor. In audio applications, the human ear, for example,
does an excellent job of detecting tones in the absence of large
input signals even though the tones are well below the
integrated (0-20-kHz) noise of the system.
There are two sources of idle tones. Their most common cause
is voltage-reference modulation.To understand this mechanism
a basic understanding of sigma-delta converters is needed. Here
is a one minute crash course on sigma-delta converters (to
probe further please consult[1]).
As the block diagram shows, a basic sigma-delta A/D converter
consists of an oversampling modulator, followed by a digital
filter and a decimator. The modulator output swings between
two states (high and low, or 0 and 1, or +1 and 1), and the
average output is proportional to the magnitude of the input
signal. Since the modulator output always swings full-scale
(1 bit), it will have large quantization errors. The modulator,
however, is constructed so as to confine most of the
quantization noise to the portion of the spectrum beyond fb,
the bandwidth of interest.
F
INTEGRATION
+
30
1/s
V REF
MAGNITUDE dB
fi
SHAPED QUANTIZATION
NOISE
fb
Fms
Fms fb Fms fi
Fms
As shown, the spectral sticks (single frequencies) at fi and

Fms fi correspond to an input signal, while the shaded area
shows how the quantization noise has been pushed (shaped)
beyond the bandwidth of interest, fb.
The digital filter, which is often an n-tap FIR filter, takes the
high-speed low-resolution (1-bit) modulator output and
performs a weighted average of n modulator outputs in a
manner dictated by the desired filter characteristics. The output
of the filter is a high-resolution word, which becomes the A/D
output. The digital filter is designed to filter out everything
between fb and Fmsfb, where Fms is the sampling rate of the
modulator. Cleaning out all the noise in between fb and Fmsfb
makes it possible to reduce the sampling rate to values between
Fms and 2fb without causing any spectra to overlap (i.e., aliasing).
Conceptually, reducing the sample rate, i.e., decimation, can
be thought of as only sending every dth digital filter output to
the A/D output, where d is the decimation factor. This will
bring the spectral images close together, as shown in the figure,
which makes the output look like an output from a non
oversampled converter. The upper figure shows the output of
the modulator after digital filtering but prior to decimation.
The lower figure shows the spectral output after decimation
the final A/D output.
In real converters, digital filtering and decimation are intimately
combined for economy in design and manufacture. Thus, the
terms digital filter and decimator are used interchangeably
to describe the digital circuitry processing the modulator output
to produce the output of the converter.
DIGITAL FILTER OUTPUT
BEFORE DECIMATION
Fi
Fb
Fms Fi Fms
Fms
FINAL CONVERTER OUTPUT
Fi
Fs Fs Fi Fs
ms
MODULATOR
ANALOG
INPUT
INPUT
SIGNAL
SPECTRUM
MAGNITUDE
11.8 V
N.S.D. <
MODULATOR
OUTPUT
SPECTRUM
MAGNITUDE
Now that the attenuation is in hand, we can consider the noise

magnitude itself: Lets be conservative (by about 50%) and
take the effective filter attenuation to be 20 dB (i.e., 0.1 V/V).
To be able to calculate the maximum allowed noise spectral
density when using a single pole filter, an estimate should be
made of the maximum performance degradation that aliased
noise can contribute. From the dynamic specs of the AD1877
we find that the total noise power internal to the converter is
90 dB below (32 ppm of) full-scale input. If the whole system
is to be within, say, 0.5 dB of this spec, the total aliased noise
power cant exceed the rss difference between 90 dB and
89.5 dB or 99.1 dB (11.1 106). Using this information,
and the fact that the input scale of the AD1877 is 3 V p-p, we
find that aliased noise must not exceed 3/(22) V 11.1 106
= 11.8 V rms. If all this noise were assumed lumped in a single
aliased band, and noting that rms noise = noise spectral density
(N.S.D.) BW,
1-BIT
DAC
COMPARATOR
DIGITAL
FILTERING
1-BIT
AND
AT F ms DECIMATION
n-BIT DIGITAL
OUTPUT
AT F s << F ms
O.K., now back to idle tones. Lets start by looking at the

output of the modulator when a dc signal is applied to the input.
For an exact mid-scale dc input level, the output of the modulator is equally likely to be high (1) or low (0), in other words,

the pulse density is 0.5, very likely to result in bitstream patterns
like 010101. These regular patterns mean that the output spectrum will have a spike at Fms/2 (upper figure). If the dc input
now moves somewhat off midscale, the modulator output bit
pattern will change accordingly. The spectrum of the modulator
output will now show spikes at Fms/2 F and Fms/2 + F, with
F proportional to the dc change from midscale (lower figure).
MAGNITUDE
CONCENTRATION OF
ENERGY AT Fms /2
Fms
Fms
MAGNITUDE
Fms
2
f
Fms
2
Fms
+ f
A: Follow the layout recommendations and bypassing schemes

recommended by the manufacturer of the converter. This
applies not only to the voltage reference, but to power supplies
and grounding as well. It is the manufacturers responsibility
to minimize the voltage-reference corruption that takes place
inside the converter, but it is up to the system designer to
minimize the external coupling. By following those guidelines,
the user should be able to reduce the coupling to a negligible
level. If, despite the proper design precautions, idle tones are
still an issue, there is yet another option that can be pursued.
As I explained previously, frequency of the idle tones is a
function of the dc input. This opens up the possibility of
introducing enough dc offset on the A/D input to move the
idle tones out of the bandwidth of interest to where they will
be filtered out by the decimation filter. If the user does not
want the dc offset to propagate through the system it can be
subtracted out by the processor that handles the data from the
A/D.
Q: What kind of a load does the input of sigma-delta converters present
to my signal conditioning circuitry?
Fms
With effective digital filtering, how can such tones possibly

find their way down to baseband? The answer is via the voltage
reference. The digital output is a measure of the ratio of the
analog input to the voltage reference. An x% change in the
magnitude of the voltage reference will result in a x% change
in the magnitude of the digital output word. Voltage-reference
change will, in effect, amplitude modulate the A/D output. Now,
we have clocks internal to the converter, and possibly also
externally, running at Fms/2. If small amounts of these clock
pulses get coupled onto the voltage reference line, they will
change it slightly and, in effect, modulate the tones at Fms/2 F
and Fms/2 + F. One of the difference frequencies created by this
modulation is at F, and it is clearly in the bandwidth of interest.
Nonlinearities may also create tones at multiples of F.
Q: From your explanation it seems that if I apply an ac signal to the
converter I do not have to worry about idle tones?
A: Well, any ac signal generally has a dc component associated
with it, which will have to be represented by the modulator
output, so the explanation above still applies. But if the total
dc input offset (i.e., internal converter offset plus external
offsets) in your system is exactly 0, the tones will be at dc (0 Hz).
There is another source of idle tones in lower-order (<3rdorder) modulators. The order of the modulator (number of
integrations) is a measure of how much quantization-noise
shaping takes place. Second-order modulators can actually
exhibit bit patterns that show up directly in the baseband, even
if voltage-reference modulation is not occurring. This is one of
the reasons why sigma-delta converters from Analog Devices
that are designed for ac applications use higher-order (3)
sigma-delta modulators.
Q: So what can I do to minimize the chances of idle tones interfering

with my A/D conversion?
A: It depends on the converter. Some sigma-delta converters have

a buffer at the input, in which case the input impedance is very
high and loading is negligible. But in many cases the input is
connected directly to the modulator of the converter. A
switched-capacitor sigma-delta modulator will have a simplified
equivalent circuit like that shown in the figure.
S1
S2
Switches S1 and S2 are controlled by the two phases of a clock

to produce alternating closures. While S1 is closed, the input
capacitor samples the input voltage. When S1 is opened, S2 is
closed and the charge on C is dumped into the integrator,
thus discharging the capacitor. The input impedance can be
computed by calculating the average charge that gets drawn
by C from the external circuitry. It can be shown that if C is
allowed to fully charge up to the input voltage before S1 is
opened then the average current into the input is the same as
if there were a resistor of 1/(FswC) ohms connected between
the input and ground, where Fsw is the rate at which the input
capacitor is sampling the input voltage. F sw is directly
proportional to the frequency of the clock applied to the
converter. This means that the input impedance is inversely
proportional to the converter output sample rate.
Sometimes other factors, such as gain, can influence the input
impedance. This is the case for the 16/24-bit AD771x family
of signal conditioning A/Ds. The inputs of these converters
can be programmed for gains of 1 to 128 V/V. The gain is
adjusted using a patented technique that effectively increases
Fsw (but keeps the converter output sample rate constant) and
combines the charges from multiple samples. The input
impedance of these converters is, for example, 2.3 M when
the devices external clock is 10 MHz and the input gain is 1.
With input gain of 8, the input impedance is reduced to 288 k.
31

These impedances, as noted earlier, represent the average
current flow into or out of the converters. However, they are
not the impedances to consider when determining the
maximum allowable output impedance of the A/D driver
circuitry. Instead, one needs to consider the charging time of
the capacitor, C, when S1 is closed. For dc applications the
driver circuit impedance has only to be low enough so that the
capacitor, C, will be charged to a value within the required
accuracy before S1 is opened.The impedance will be a function
of how long S1 is closed (proportional to the sampling rate),
the capacitance, C and CEXT in parallel with the input (unless
CEXT >> C).The table shows allowable values of external series
resistance with fCLKIN = 10 MHz which will avoid gain error of
1 LSB of 20 bitsfor various values of gain and external
capacitance on the AD7710.
For converters that have a differential input, a differential

version of this circuit may be used, as shown in the figure below.
Since one input is positive with respect to ground while the
other is negative, one input (the negative one) needs to be
supplied negative charge while the other needs to get rid of
negative charge when the input capacitors are switched on line.
Connecting a capacitor between the two inputs enables most
of the charge that is needed by one input to be effectively
supplied by the other input. This minimizes undesirable charge
transfers to and from the analog ground.
VIN +
DIFFERENTIAL
INPUT
Typical external series resistance which will not

introduce 20-bit gain error
A/D CONVERTER
WITH A DIFFERENTIAL
SWITCHED CAPACITOR
INPUT
VIN
External Capacitance (pF)

Gain 0
50
100
100
500
145 k
34.5 k 20.4 k 5.2 k 2.8 k 700
70.5 k 16.9 k 10 k
2.5 k 1.4 k 350
31.8 k 8.0 k
4.8 k
1.2 k 670
170
8-128 13.4 k 3.6 k
2.2 k
550
80
300
5000
For ac applications, such as audio, where the modulator sample

rate is around 3 MHz for 64 oversampling, the input capacitor
voltage may not have enough time to settle within the accuracy
indicated by the resolution of the converter before the capacitor
is switched to discharging. It actually turns out that as long as
the input capacitor charging follows the exponential curve of
RC circuits, only the gain accuracy suffers if the input capacitor
is switched away too early.
The requirement of exponential charging means that an op
amp can not drive the switched capacitor input directly. When
a capacitive load is switched onto the output of an op amp, the
amplitude will momentarily drop. The op amp will try to correct
the situation and in the process hits its slew rate limit (non
linear response), which can cause the output to ring excessively.
To remedy the situation, an RC filter with a short time constant
can be interposed between the amplifier and the A/D input as
shown in the figure. The (low) resistance isolates the amplifier
from the switched capacitor, and the capacitance between the
input and ground supplies or sinks most of the charge needed
to charge up the switched capacitor. This ensures that the op
amp will never see the transient nature of the load. This
additional filter can also provide antialiasing.
AMPLIFIER
APPENDIX
RSS addition of logarithmic quantities: The root-sum square
of two rms signals, S1 and S2, has an rms value of S12 + S22 .
One often needs to calculate the rss sum of two numbers that are
expressed in dB relative a given reference. To do this one has to
take the antilogs, perform the rss addition, then convert the result
back to dB. These three operations can be combined into one
convenient formula: If D1 and D2 are ratios expressed in dB
[negative or positive] their sum, expressed in dB, is
10 log10 10D1/10 + 10D2/10

Similarly, to find the difference between two rms quantities,
x = S22 S12
the result, x, expressed in dB, is
10 log10 10D2/10 10D1/10
References (not available from Analog Devices):

1
Oversampling Delta-Sigma Data ConvertersTheory, Design, and
Simulation, edited by J.C. Candy and G.C. Temes, IEEE Press,
Piscataway, NJ, 1991.
2
J. Vanderkooy and S.P. Lipshitz, Resolution Below the Least

Significant Bit in Digital Systems with Dither, J. Audio Eng.
Soc., vol. 32, pp. 106-113 (1984 Mar.); correction ibid., p.889
(1984 Nov.).
A.H. Bowker and G.J. Lieberman, Engineering Statistics, Prentice

Hall, Englewood Cliffs, NJ, 1972.
ADC
VIN
32
To be continued. Topics to be covered in the next installment include

multiplexing, clock signals, noise, dither, averaging, spec clarifications

by Oli Josefsson
the new data. The AD1879, for example, an 18-bit audio A/D
converter, has a 4096-tap FIR filter which, when running at
3.072 MHz, has a 1.33-ms settling time.
USING SIGMA-DELTA CONVERTERSPART 2
X [n]
This is a continuation of a discussion of sigma-delta converters begun in

the last issue.We covered antialiasing requirements, idle tones, and loading
on the signal source.
Q: What happens if my input signal is beyond the input range of the
sigma-delta converter? I remember hearing something about the
converter becoming unstable?
A: The modulator can become temporarily unstable if it is driven
with inputs outside the recommended range. However, this
instability is invisible to the user, since decimators are generally
designed to simply clip the digital output and show either
negative or positive full scale, just as one would expect with a
conventional converter.
Q: The specifications for sigma-delta converters assume a certain input
clock rate and therefore a specific sampling rate. Can I safely use
the converter with a higher or lower clock frequency?
A: While the specs are measured at a particular sampling frequency,
we often specify a range of input clock frequencies that the
device can be operated with. This translates into a range of
possible sampling rates. If you plan to go much beyond that
range you can expect some performance degradation. If you
sample at higher rates than specified, the internal switchedcapacitor circuits may not be able to settle to the required
accuracy before a new clock edge comes along. With too slow
a sampling rate, capacitor leakage will degrade performance.
The digital filter characteristics of the converter (group delay,
cutoff frequency, etc.) scale with sampling rate; so too do the
input impedance (unless the input is buffered) and power
consumption.
Q: I am planning to use a sigma-delta converter to digitize several signals
by using a multiplexer at the input of the converter. Is that a problem?
A: While sigma-delta converters have a certain appeal due to their
ease of antialiasing, they do not lend themselves well to
applications for multiplexed ac signals. The reason for this is
that the output of a sigma-delta converter is a function not
only of the latest analog input but also of previous inputs. This
is mostly due to the memory that the digital filter has of previous
inputs, but the modulator has some memory as well. In a
multiplexing application, after switching from one input to
another, all information the filter has about the old input needs
to be flushed out before the converter output word represents
the new input.
Most decimation filters in sigma-delta converters intended for
ac applications are FIR filters, principally because of their linear
phase-response. For FIR filters, it is easy to calculate the time
it takes to rid the filter of any information about the old input.
The figure shows the structure of a FIR filter; the number of
clock cycles required to clock all old data points out (i.e., the
filter settling time) is equal to k, the number of taps in the
filter. While data corresponding to a new input is propagating
through the filter and replacing the earlier data, the output of
the filter is calculated from a combination of the old data and
a1
a2
Z 1
a3
Z 1
a4
ak
y [n]
y(n) = a1 x(n) + a2 x(n1) + a3 x(n2) +... + ak x(nk+1)
The effective sampling rate for sigma-delta converters in

multiplexed applications is quite low because of this need to
wait for the old signal to be flushed out before capturing a
valid data point for the new input.Traditional converters, which
convert directly, or in a small number of stages, are therefore a
much better choice in applications requiring the capture of
multiple ac channels.
For a multichannel dc application where time is available to
wait after switching between channels, or if the application
does not require frequent changes between channels, the use
of a sigma-delta converter can be very feasible. In fact, Analog
Devices offers 16-24-bit converters with multiplexers on the
input (AD771x family) specifically for such applications.
Q: Does this also explain why sigma-delta converters are not suitable
for some control applications?
A: Yes. Since delays in control loops must be minimized for
stability, sigma-delta converters are not suitable for control
applications where they add a relatively long time delay.
However, the actual delay is predictable; in applications that
involve relatively slow signals, the converter phase delay, and
therefore the effect on pole and zero locations of the control
loop, may be negligible. However, even if this is the case, a
traditional non-oversampling converter may still be a much
better choice for the application, because a sigma-delta
converter would need to run at a much faster sampling rate
than a traditional converter in order to have the same phase
delay. This will unnecessarily burden the circuitry that
processes the A/D data.
Q: Are there any other issues I should be aware of when using sigmadelta converters?
A: In addition to the general guidelines on grounding, power supply
bypassing, etc., that apply to all converters, there are a couple
of points worth remembering when designing with sigma-delta
converters. The first issue involves their input. As mentioned
earlier, some sigma-delta converters (such as the AD1877) have
buffers on the input; others (such as the AD1879), without a
buffer, present a switched-capacitor load, which needs periodic
current transients to charge the input capacitor. It is important
that the circuitry driving the converter be as close to the
converter as possible to minimize the inductance in the leads
between the external circuitry and the switched-capacitor node.
This reduces the settling time of the input and minimizes
radiation from the input to other parts of the circuit board.
33

Another issue has to do with interference from clock signals
affecting the A/D conversion. As I noted earlier, the digital
decimation filter cant provide any filtering of signals whose
frequencies are close to multiples of the modulator sampling
rate. To be precise, the passbands are [kFms fb]s where k is an
integer, Fms is the modulator sampling rate, and fb is the
decimator cutoff frequency.
If Nrms is the rms value of the converter noise and VLSB is the
size of the LSB in volts (= Vspan/2b, where b is the number of
bits in the output word) the peak to peak noise in terms of
LSBs, NB, is
Besides the consequences for anti-aliasing discussed earlier,

the decimator cutoff frequencies have a bearing on the selection
of clock frequencies for devices that operate in the same system
as the converter. These frequency bands (i.e., the passbands)
embody the converters greatest vulnerability to interference
(inductive or capacitive coupling, power supply noise, etc.),
because any signals in these frequency bands that manage to
get into the modulator will not be subjected to attenuation in
the filter. Therefore one is wise to avoid using clock frequencies
that fall in these bands to minimize the possibility of interfering
with the conversionunless they are synchronous with the
converter clock.
If the signal-to-noise ratio of a converter expresses noise power
Q: I recently evaluated a dual-supply A/D converter; one of the tests I

did was to ground the input and look at the output codes on a LED
register. To my big surprise I got a range of output codes instead of a
single code output as I expected?
A: The cause is circuit noise. When the dc input is at the transition
between two output codes, just a little circuit noise in even the
finest dc converters will ensure that two codes will appear at
the output. This is a fact of life in the converter world. In many
instances, as in your case, the internal noise may be large
enough to cause several output codes to appear. Consider, for
example, a converter with peak-to-peak noise of just over
2 LSB. When the input of this converter is grounded, or a
clean dc source is connected to the input, we will always see
threeand sometimes even fourcodes appear at the output.
The circuit noise prevents the voltage being sampled from being
confined to a voltage bin that corresponds to one digital code.
Any external noise on the A/D input (including a noisy signal),
on the power supplies, or on the control lines will add to the
internal circuit noiseand possibly result in more bits toggling.
Q: Is there a way to determine how many codes I can expect to appear
when I apply a dc signal to a converter?
A: It would not be hard in the ideal case where you knew the
noise distribution, the exact size of the codes where the dc
input is at and where within a code quantum the input lies (in
the center, on the edge of two codes, etc.). But in reality you
dont have this information. However, knowing some of the ac
specifications (S/N, dynamic range, etc.) of the converter, you
can make an estimate. From these specs you can find the
magnitude of the rms converter noise relative to full scale. The
noise will in all likelihood have a Gaussian amplitude
distribution, so the standard deviation (sd) of the distribution
equals the rms value. This also means that the codes that appear
will not have equal probability of occurring. Using the fact
that 99.7% of a Gaussian distribution occurs within 3
standard deviations from the mean, we can estimate the peakto-peak noise voltage at six times the standard deviation.
34
6 Nrms 6 2b Nrms
=
VLSB
Vspan
relative to full scale, rms signal V span / (2 2) , we have

NB = 3 2b 10SNR/20
2
How many codes show up at the output depends where the
mean of the input, i.e., the dc input value, is with respect to
code transitions. If the mean is close to the boundary between
two output codes, more codes are likely to appear than if the
mean is half way between two output codes. It can easily be
shown that NC, the number of codes appearing for a particular
value of NB, is either INT(NB)+1 or INT(NB)+2, depending
on the dc input value [INT(NB) is the integer portion of NB].
And dont be surprised to see even more codes from the lessprobable noise amplitudes > 3 standard deviations.
How many bits will NC cause to toggle on the output? The

number of bits needed to represent NC codes is
INT
log NC
+ 0.5
log 2
We can, however, see many more bits toggle, since the number
of bits toggling is a function of the actual value of the converters
dc input. Consider, for example, that a one-code transition
from an output word of 1 to 0 on a 2s-complement-coded
converter involves inverting all the output bits.
Lets look at an example using the AD1879, an 18-bit sigmadelta converter with dynamic range of 103 dB. From the
definition of dynamic range we have
103 = 20 log S
Nrms
From the AD1879 data sheet, we find that the rms value of a
full-scale input signal, S, is 6/2 V rms. This allows us to solve
for Nrms which turns out to be 30 V. We next find the LSB
size by dividing the full input range by the number of possible
output codes:
VLSB = 12
= 45.8 V
218
Thus NB is 3.9. We can therefore expect either 4 or 5 different
codes to appear at the AD1879 output when the input is
grounded (ground corresponds to a midscale input for the
AD1879).
PROBABILITY
QUESTIONS ON NOISE IN CONVERTERS
NB =
VDC
n
n+1
n+2
n+3
n+4
INPUT
n+5
n+6
To make all this real, lets continue our example involving the
AD1879. Consider two cases, one where the input lies midway
between two output codes and one when the input is on the
transition between two codes. From the calculations above,
we found that the standard deviation (sd) of the noise (the
rms value) was 30 V. The size of one LSB in terms of sd is
45.78 V
= 1.524
30.0 V
NUMBER OF INSTANTS
In the case where the dc input is midway between code

transitions, as shown below, it is clear that any noise that falls
within 0.5 LSBs to +0.5 LSBs from the input will result in
the correct code at the A/D output. This corresponds to the
noise being confined to a range of (0.5 1.524) sd to
(+0.5 1.524) sd from its mean (0). From standard tables one
can find that the noise will fall in this range 55.4% of the time.
If the noise falls within 0.5 LSBs to 1.5 LSBs, the output will
be one code too high. Again from standard tables one can find
that this will occur 21.2% of the time. Continuing in this
manner one can calculate the whole histogram showing the
distribution of output codes.
500
400
20.7%
(21.2%)
20.3%
(21.2%)
300
200
0.9%
(1.1%)
0.7%
(1.1%)
100
0
NUMBER OF INSTANTS
57.4%
(55.4%)
600
28
27
26
25
24
OUTPUT CODE
43.9%
(43.6%)
500
23
22
46.0%
(43.6%)
400
300
200
5.6%
(6.4%)
4.4%
(6.4%)
100
26
25
24
23
22
OUTPUT CODE
0.1%
(0%)
21
20
The upper figure shows an actual measurement where the dc

input happened to be 25 LSBs. Five output codes, ranging
from 27 to 23, appeared. 1024 measurements were taken
and the percentage distribution of each code is shown on top
of each column. The calculated distribution is listed in brackets
on top of each column. As can be seen, the experimental results
agree well with the calculated values. The lower figure shows
a case where the dc input is close to the boundary between
two codes. By following a similar procedure, one can calculate
how the histogram should look. Again the experimental and
calculated values are in excellent agreement. Note that the
actual applied dc input is slightly above the border between

the two codes, whereas the calculations assume it is exactly on
the border.
The biggest weakness of this estimating technique is the fact
that in conventional converters the code width (the amount
the dc input has to be increased to increase the digital output
by one bit) varies from code to code. This means that if the dc
input is in an area where codes are narrow, we can expect more
bits to be toggling than in an area where the codes are wide.
This method also assumes that the circuit noise within the
converter stays constant, whether the applied signal is ac or
dc. This is not exactly true in many cases.
The estimate will probably be more accurate when used with
sigma-delta converters (except for dead bands), because
neither of the two factors mentioned above is an issue in such
converters.
Q: Ah, now I understand why there are multiple codes at the output.
But why not discard the bits that toggle and only bring out the bits
that stay steady, since the others are really indeterminate? Isnt that
the real resolution of the converter?
A: Many converters are designed for ac or dynamic applications
where THD (total harmonic distortion) and THD+N (total
harmonic distortion+noise) are the most important specs. The
design therefore focuses on minimizing harmonic distortion
for high- and low-level input signals, while keeping the noise
to acceptable levels. As it turns out, these requirements
somewhat contradict the requirements for a good dc converter,
which is optimized for precision conversion of slow moving
signals where harmonic distortion is not an issue. It is actually
desirable to have some noise (called dither) superimposed on
the input signal to minimize distortion at very low input signal
levels; dither can also be used to improve dc accuracy where
repeated measurements can be made.
To understand how this may be, lets start by looking at
quantization noise. The output of an ideal A/D converter has
finite accuracy because of the finite number of bits available to
represent the input voltage. Each one of the 2b quanta
represents with one single value all values in the analog range
from 0.5 LSB to +0.5 LSB of its nominal input value. The
A/D output can therefore be thought of as a discrete version of
the analog input plus an error signal (quantization noise).When
a large and varying input signal (dozens, hundreds, or
thousands of LSBs in amplitude) is applied to a converter, the
quantization noise has very little correlation with the input
signal. It is, in other words, approximately white noise. The
figure shows the quantization noise of a perfect A/D converter
at various instants of time when the input signal is a sinusoid
of about 100 LSBs in amplitude.
0.5
0.4
0.3
ERROR IN LSBs
One can take this estimation one step further: If the standard
deviation (the rms value) of a Gaussian distribution and the
mean (the mean of the noise is 0 in this case) are known, one
can use standard tables for the Gaussian distribution to
calculate what percent of the time the noise will fall into a
voltage interval corresponding to a specific output code. A
histogram can be estimated, showing the distribution of codes
at the output. Also the process can be reversed: a histogram
showing the distribution of noise codes at a given value of dc
output permits one to estimate the S/N ratio for a converter.
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
35

When the A/D input is very low in amplitude, so that the
amplitude does not change more than a fraction of a LSB
between samples, the samples stay in the same quantum, and
are therefore constant for a few sample periods. This is depicted
in the figure below, which shows a sinusoidal input signal that
has an amplitude of only 1.5 LSBs, the A/D output and the
quantization noise. Note that the quantization error follows
the input waveform exactly while the samples are staying
constant. The longer the samples stay constant, the more the
quantization noise looks like the input waveform, i.e., the
correlation between the input signal and the quantization noise
increases. While the rms of the quantization error may not have
changed, the quantization error will take on a non-uniform
spectral shape. In fact, the correlated quantization noise shows
up as harmonics in the A/D spectrum.
INPUT VOLTAGE IN LSBs
1.5
signal is often about 1/3 LSB rms (2 LSBs peak-to-peak if the

noise is Gaussian). Clearly, this will result in a converter that
will have more than two codes at the output when the input is
grounded. We saw an example earlier involving the AD1879
which had either four or five codes appear on the output
depending on the dc input level.
The figure below shows the simulated output of an A/D
converter with an undithered low level input signal. The
quantization noise is a function of the input signal magnitude
at the sample instant.This correlation between the quantization
noise and the input signal shows up as a cluster of harmonically
related sticks in the A/D output spectrum. Note that the
magnitude scale in the figure is referenced to the input signal
(not full scale input).
0
5
10
1.0
15
0.5
20
25
0
30
0.5
35
40
1.0
OUTPUT CODE
45
1.5
50
1.5
55
1.0
60
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.5
0
0.5
1.0
1.5
1.5
INPUT SIGNAL
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
The right-hand figure shows the A/D output after a dither signal
that is 4 dB above the quantization noise floor is added to the
input. In this case the quantization noise depends on the
magnitude of the dither signal at the instant when a sample is
taken. Since the value of the dither doesnt depend on the input
signal, the quantization noise becomes uncorrelated to the input
and the harmonics in the A/D spectrum are eliminated, but at
the cost of an overall increase in the noise floor.
1.0
LSBs
0.5
QUANTIZATION
ERROR
0
0.5
1.0
1.5
Another way to look at this phenomenon is to consider the

case when the (sinusoidal) input signal is only around 1 LSB
in size and the digital output resembles a square wave. Square
waves are rich in harmonics! The harmonics, or noise
modulation products, are very objectionable in many converter
applications, especially audio.
To get around this problem, a technique called dithering is
used to trade correlated quantization noise for white noise,
which is less offensive to the human ear than correlated noise.
Dithering is done by using circuit elements to add random
noise to the input signal. While this will result in an increase of
the total converter noise, the added noise breaks up the simple
square wave patterns in the output code.The quantization error
will not be a function of the input signal but of the instantaneous
value of the dither noise. Thus the dither decorrelates the
quantization noise and the input signal. The size of the dither
36
Instead of actually adding noise to the A/D input, dithering

can be accomplished by using the thermal noise of the converter
as the dither signal and calculating enough output bits to ensure
a decorrelated quantization noise.
Though I have used A/D converters in my examples, the idea
of using dither also applies to D/A converters as well. Dither is
applied to D/A converters by adding the output of a digital
noise generator to the digital word sent to the D/A.
Q: But in dc applications, I want to make an accurate measurement
each time and may not be able to tolerate the uncertainty of having
a few LSBs of error in a particular measurement.
A: If you need n-bit dc accuracy in each conversion and you have
problems finding a suitable n-bit converter, you have two
options. One is to use an (n+2)-bit converter and simply ignore
the two LSBs. However, if your hardware has the capability
(and time) to do some signal processing, you can enhance the
resolution of a noisy (dithered) dc converter and, in fact, get
more than n-bit accuracy out of an n-bit converter if the
accuracy is limited by noise.
To understand why this may be so, think of an ideal n-bit
converter. For a particular value of dc input, you will get one
digital code at the output. However, you do not know where
the input lies within the code quantum (i.e., in the middle,

close to the upper transition, etc.). That may be sufficiently
accurate for your application, but if you add noise to the input
of the converterso that several codes can appear at the
outputyou will find that the code distribution contains
information to place the dc value of the input more exactly.
In the earlier examples involving the AD1879, we saw how the
code distribution looks when the input is in the vicinity of a
code transition; the two most-frequent output codes are the
ones on either side of the transition. Their average is therefore
a good estimate of where the input lies. In fact, taking the
average of a lot of conversions, while the input stays put, is an
excellent way of enhancing the resolution of the converter. One
has to be careful, when processing the converter output, to
allow the output word length to grow without introducing
roundoff errors. Otherwise one actually injects unwanted
noisecalled requantization noiseinto the final output. Note
that filtering out the noise is only just that; it will have no effect
on other error sources of the converter, such as integral and
differential nonlinearity.
This concept of resolution enhancement is an interesting one
and is not restricted to the dc domain. One can actually trade
resolution for bandwidth in the ac domain and combine the
outputs of several converters or to construct a more-accurate
output. The basic principle is that signal repetitions (which
are self-correlated) add linearly, while repetitions of random
noise produce root-square increases. Thus, a fourfold increase
in number of samples increases S/N by 6 dB.
Q: You mentioned a couple of converter ac specifications above. I am
somewhat confused about how S/N, THD+N,THD, S/THD,
S/THD+N, and dynamic range are measured on A/D and D/A
converters and how they relate to each other. Can you shed any light
on this?
A: Your confusion is quite understandable. There is unfortunately
no industry standard on exactly how these quantities are
measured and therefore, what exactly they mean. Sometimes
manufacturers are guilty of choosing the definition that portrays
their part favorably.
Most often data sheets include a note on the testing conditions
and how the different specs were calculated. The best advice I
can give is to read these very carefully. By simple calculations
you can often convert a specification for one part to a number
that allows a fair comparison to a specification for another part.
Most specifications are not expressed in absolute units, but as
relative measurements or ratios. Noise, for example, is not
specified in rms volts, but as SNR, or the ratio between signal
power and noise power under particular test conditions. These
ratios are usually expressed in decibels, dB, and occasionally
as percentages (%). A power ratio, x, expressed in bels, is
defined as log10x; multiply by 10 if expressed in decibels (one
tenth of a bel): 10 log 10 x. SNR is therefore equal to
10 log10 (signal power/noise power) dB. Evaluated in terms of
rms voltage quantities, SNR = 20 log10(Vsignal/Vnoise).
Armed with this knowledge, lets see whether we can make
sense out of the multiple specifications you mentioned above
(many of which are redundant). Those specifications seek to
describe how the imperfections of the converter affect the
characteristics of an ac signal that gets processed by the
converter. For dc applications, a listing of the magnitude of
the actual imperfections suffices, but these can only suggest ac

performance. For example, integral nonlinearity is a major
factor in determining large-signal distortion (along with glitch
energy for D/As) while differential nonlinearity governs smallsignal distortion. To accurately determine the ac performance,
at least two types of tests are performed in the case of A/Ds.
The tests are as follows:
a) Full-scale sine
A sinusoidal signal approaching full-scale is applied to the
converter. The signal is large enough so that converters
imperfections cause significant harmonic components to occur
at multiples of the input signal frequency. The harmonics will
show up in the output spectrum, along with noise. A common
performance measure is the relative magnitude of the harmonic
components, usually expressed in dB. Relative to what? Two
possibilities are the applied input signal and the full scale of
the converter (which in most cases is different from the applied
input signal). Referring the harmonics to full scale will clearly
yield a lower (more attractive) number than referring them to
the rms value of the actual input signal. This reference issue
causes a lot of confusion when dynamic specifications are
evaluated, because there is no universally accepted standard
for what each performance measure should be referred to. The
best advice I can give you is: never assume anything; read
manufacturers data sheets very carefully.
Sometimes the magnitudes of the individual harmonics are
specified, but most often only the total harmonic distortion
(THD) is specified. The THD measures the total power of the
harmonics and is found by adding the individual harmonics in
rss fashion. The formula then for THD when referred to the
input signal is
H (i)
m
20 log10
H (i)
m
rms
i=2
or 10 log10
rms
i=2
S2
where H(i)rms refers to the rms value of ith harmonic component

and S to the rms value of the input signal. Usually, harmonics
2 through 5 are sufficient. Note that the input-frequency, or
fundamental, component is the first harmonic. To refer any
harmonic to full scale, add x dB to the formula above, where x
is the magnitude of the input signal relative to full scale. This
simple conversion formula can be applied to other
specifications, but take care to observe proper polarity of the
log quantities.
Nowadays, clear distinction is usually made between total
harmonic distortion plus noise (THD+N) and THD. This has
not always been the case. THD+N includes not only the
harmonics that are generated in the conversion, but also the
noise. The formula for THD+N when referred to the input
signal is:
H (i)
m
20 log10
N 2rms +
rms
i=2
or
H (i)
m
10 log10
N 2rms +
i=2
2
rms
37

where Nrms is the rms value of the integrated noise in the
bandwidth specified for the measurement.
Another commonly used specification is signal to noise-plusdistortion (S/[N+D], or S/[THD+N]), also called sinad.
This is essentially the inverse of THD+N, when referred to the
signal; its dB number is the same, but with opposite polarity.
Another performance measure describing the test results is
the signal to noise ratio, S/N or SNR, which is a measure of
the relative noise power, most useful for estimating response
to small signals in the absence of harmonics. If S/N is not
specified, but THD and THD+N are provided, relative to the
input signal, THD can be rss-subtracted from THD+N to obtain
the noise to signal ratio [= 1/(S/N]. If the numbers are given
in dB, the rss subtraction formula for logarithmic quantities in
the Appendix can be used as follows
SNR = 10 log10 10 THD+N /10 10THD/10

to yield the input signal power relative to noise power expressed
in dB.
b) Low-level sine
The second test usually performed is to apply a sinusoidal signal
well below full scale to the converter (usually 60 dB). At this
input level, sigma-delta converters usually exhibit negligible
nonlinearities, so only noise (no harmonic components)
appears in the spectrum. At this level, S/N = S/N+D
= THD+N = THD, when all are referred to the same level.
As a result, one specification indicating the noise level suffices
to describe the result of this test. This specification called
dynamic range (inversely, dynamic-range distortion), specifies
the magnitude of the integrated noise (and harmonics if they
exist) over a specific bandwidth relative to full scale, when a
60-dB input signal is applied to the converter.
Conventional (i.e. not sigma-delta) converters can exhibit
harmonics in their output spectrum even with low-level input
signals because all the codes may not have equal width
(differential nonlinearity). In some such instances, the S/N,
which ignores harmonics, measured with a 60-dB input signal,
is different from dynamic range.
Frequently one sees THD+N at 60-dB and dynamic range
specified for the same converter. These really are, as explained
above, redundant since they only differ in the reference used.
The only twist on dynamic range is that sometimes, when audio
converters are specified, a filter that mimics the frequency
response of the human ear is applied to the converter output.
This processing of the converter output is called A-weighting
(because an A-weighting filter is used); it will effectively
decrease the noise floor, and therefore increase the signal-tonoise ratio, if the noise is white.
Everything discussed above applies to both A/D and D/A
converters, with the possible exception of signal to noise ratio.
Sometimes (particularly for audio D/A converters) S/N is a
measure of how quiet the D/A output is when zero (midscale)
code is sent to the converter. Under these conditions, the S/N
expresses the analog noise power at the D/A output relative to
full scale output.
38
Its important to note that the performance measures above

are affected by: bandwidth of the measurement, the sampling
frequency, and the input signal frequency. For a fair comparison
of two converters, one has to make sure that these test
conditions are similar for both.
Image Filtering Question

Q: I intend to use Analogs AD1800 family of audio D/A converters
for a digital audio playback application. I understand that using an
interpolator ahead of the D/A will make it easier to filter the
D/A output, assuming I want to get rid of all the images at the D/A
output. But is it really necessary to filter the output, since all the
images will be above the audible range as long as sampling is at
>40 kHz?
A: Good question. The audio equipment (audio amplifiers,
equalizers, power amplifiers, etc.) that may eventually receive
the output of your D/As are typically built to handle 20-Hz to
20-kHz signals. Since they are not intended to respond at
frequencies much beyond 20 kHzand in effect themselves
function as filtersthey may not have the necessary slew rate
and gain to handle incoming signals from an unfiltered D/A
output having significant energy well above 20 kHz. With their
slew-rate and gain limitations, the amplifiers are driven into
nonlinear regions, generating distortion. These distortion
products are not limited to high frequencies but can affect the
20-Hz to 20-kHz range as well. Attenuating the high frequency
signals at the DAC will therefore reduce the possibility of
distortion. CD players often include filters steep enough to
reduce the total out-of-band energy to >80 dB below full scale.
APPENDIX
RSS addition of logarithmic quantities: The root-square sum
of two rms signals, S1 and S2, has an rms value of
S12+ S22 .
One often needs to calculate the rss sum of two numbers that are
expressed in dB relative a given reference. To do this one has to
take the antilogs, perform the rss addition, then convert the result
back to dB. These three operations can be combined into one
convenient formula: If D1 and D2 are ratios expressed in dB, their
sum, expressed in dB, is
10 log10 10D1/10 + 10D2/10

Similarly, to find the difference between two rms quantities,
x = S22 S12
the result, x, expressed in dB, is
10 log10 10D2/10 10D1/10
References:
[1] Oversampling Delta-Sigma Data ConvertersTheory, Design, and
Simulation, edited by J.C. Candy and G.C. Temes, IEEE Press,
Piscataway, NJ, 1991.
[2] J. Vanderkooy and S.P. Lipshitz, Resolution Below the Least
Significant Bit in Digital Systems with Dither, J.Audio Eng.
Soc., vol. 32, pp. 106-113 (1984 Mar.); correction ibid., p.889
(1984 Nov.).
[3] A.H. Bowker and G.J. Lieberman, Engineering Statistics,
Prentice Hall, Englewood Cliffs, NJ, 1972.

MUST A 16-BIT CONVERTER BE 16-BIT MONOTONIC AND
SETTLE TO 16 PPM?
by Dave Robertson and Steve Ruscak

Q. I recently saw a data sheet for a low-cost 16-bit, 30 MSPS D/A
converter. On examination, its differential nonlinearity (DNL) was
only at the 14 bit level, and it took 35 ns (1/28.6 MHz) to settle to
0.025% (12 bits) of a full scale step. Isnt this at best a 14 bit, 28
MHz converter? And if the converter is only 14-bit monotonic, the
last two bits dont seem very effective; why bother to keep them?
Can I be sure theyre even connected?
A. Thats a lot of questions. Lets take them one at a time, starting
with the last one. You can verify that the 15th and 16th bits are
connected by exercising them and observing that 0..00, 0..01,
0..10, and 0..11 give a very nice 4-level output staircase, with
each step of the order of 1/65,536 of full scale. You can see that
they would be especially useful in following a waveform that
spent some of its time swinging between 0..00 and 0..11, or
providing important detail to one swinging through a somewhat
wider range. This is the crux of the resolution spec, the ability of
the DAC to output 216 individual voltage levels in response to
the 65,536 codes possible with a 16-bit digital word.
Systems that must handle both strong and weak signals require
large dynamic range. A notable example of this is the DACs
used in early CD player designs. These converters offered 1620 bits of dynamic range but only about 14 bits of differential
linearity. The somewhat inaccurate representation of the digital
input was far less important than the fact that the dynamic range
was much wider than that of LP records and allowed both loud
and soft sounds to be reproduced with barely audible noise
and that the converters low cost made CD players affordable.
The resolution is what makes a 16-bit DAC a 16-bit DAC.
Resolution is closely associated with dynamic range, the ratio of
the largest signal to the smallest that can be resolved. So dynamic
range also depends on the noise level; the irreducible noise
level in ideal ADCs or DACs is quantization noise.
Q. What is quantization noise?
A. The sawtooth-wave-shaped quantization noise of an ideal n-bit
converter is the difference between a linearly increasing analog
value and the stepwise-increasing digital value. It has an rms
value of 1/(2n+13) of span, or (6.02 n + 10.79) dB (below p-p
full scale). For a sine wave, with peak-to-peak amplitude
equal to the converters span, rms is 2/4, or
9.03 dB, of span, so the full-scale signal-to-noise ratio of an ideal
n-bit converter, expressed in dB, becomes the classical
6.02 n + 1.76 dB.
(1)
As the analog signal varies through a number of quantization
levels, the associated quantization noise resembles superimposed white noise. In a real converter, the circuit noise
produced by the devices that constitute it adds to quantization
noise in root-sum-of-squares fashion, to set a limit on the
amplitude of the minimum detectable signal.
Q. But I still worry about that differential nonlinearity spec. Doesnt
14-bit differential nonlinearity mean that the converter may be nonmonotonic at the 16-bit level, i.e., that those last two bits have little
influence on overall accuracy?
*The AD768 is an example of such a DAC.
A. Thats true, but whether to worry about it depends on the

application. If you have an instrumentation application that really
requires 16-bit resolution, 1/2-LSB accuracy for all codes, and
1-LSB full-scale settling in 31.25 ns (well get to that discussion
shortly), this isnt the right converter. But perhaps you really
need 16-bit dynamic range to handle fine structure over small
ranges, as in the above example, while high overall accuracy is
not neededand is actually a burden if cost is critical.
What you need to consider in regard to DNL in signal-processing
applications is 1) the noise power generated by the DNL errors
and 2) the types of signals that the D/A will be generating. Lets
consider how these might affect performance.
In many cases, DNL errors occur only at specific places along
the converters transfer function.These errors appear as spurious
components in the converters output spectrum and degrade
the signal-to-noise ratio. If the power in these spurs makes it
impossible to distinguish the desired signal, the DNL errors are
too large. Another way to think about it is as a ratio of the quantity
of good codes to bad codes (those having large DNL errors).
This is where the type of signal is important.
The various applications may concentrate in differing portions of
the converters transfer function. For example, assume that the
D/A converter must be able to produce very large signals and
very small signals. When the signals are large, there is a high
proportion of DNL errors. But, in many applications, the signalto-noise ratio will be acceptable because the signal is large.
Now consider the case where the signal is very small. The
proportion of DNL errors that occur in the region of the transfer
function exercised by the signal may be quite small. In fact, in
this particular region, the spurs produced by the DNL errors
could be at a level comparable to the converters quantization
noise. When the quantization noise becomes the limiting factor
in determining signal-to-noise ratio, 16 bits of resolution will
really make a difference (12 dB!) when compared to 14 bits.
Q. OK, I understand. Thats why theres such a variety of converters out
there, and why I have to be careful to interpret the specs in terms of my
application. In fact, maybe data sheets that have a great number of
typical plots of parameters that are hard to spec are providing really
useful information. Now, how about the settling-time question?
A. Update rate for a D/A converter refers to the rate at which the
digital input circuitry can accept new inputs, while settling time
is the time the analog output requires to achieve a specified
level of accuracy, usually with full-scale steps.
As with accuracy, time-domain performance requirements differ
widely between applications. If full accuracy and full-scale steps
are required between conversions, the settling requirements will
be quite demanding (as in the case of offset correction with
CCD image digitizers). On the other hand, waveform synthesis
typically requires relatively small steps from sample to sample.
The solid practical ground is that full-scale steps in consecutive
samples mean operation at the Nyquist rate (half the sampling
frequency), which makes it extremely difficult (how about
impossible?) to design an effective anti-imaging filter.
Thus, DACs used for waveform reconstruction and many other
applications* inevitably oversample. For such operation, full-scale
settling is not required; and in general, smaller transitions require
less time to settle to a given accuracy. Oversampled waveforms,
taking advantage of this fact, achieve accuracy and speed greater
b
than are implied by the full-scale specification.
39

SETTLING TIME
by Peter Checkovich
Q. Why is settling time important?
A. Op amp settling time is a key parameter for guaranteeing the
performance of data acquisition systems. For accurate data
acquisition, the op amp output must settle before the A/D
converter can accurately digitize the data. However, settling
time is generally not an easy parameter to measure.
Over the years, the techniques and equipment used to measure
the settling time of op amps have been barely able to keep up
with the performance of the devices themselves. As each new
generation of op amps settles to better accuracy in shorter time,
greater demands have been placed on test equipment, its
designers, and its users. A major dilemma, often causing disagreement among engineers, is whether some combination of
techniques and equipment actually measures the device under
test (DUT) or just some limiting property of the test setup. So
there is continual development of new test equipment and techniques in an effort to specify this ever-demanding parameter.
In a data-acquisition system, the output of an op amp should
settle to within 1 LSB [i.e., 2-nFS] of final value of the A/D
that it drives within a time period dictated by the sampling
rate of the system. To settle within 1 LSB of full scale implies
the settling accuracy of the A/D is 1/2 LSB. Thus, a 10-bit
system will require the op amp to settle to half of one part in
1024, or approximately 0.05%. A 12-bit system will require
settling to half of one part in 4096 (0.01%). The requirements
for 14-bits and greater are yet more demanding. Settling-time
values such as 0.1% and 0.01% are the most widely specified.
Although a larger full-scale signal range will increase the size
of the LSB, easing the problem somewhat, it is not a feasible
approach for high-frequency systems. Most high frequency A/Ds
have a full-scale span of 1 V or, at most, 2 V. For a 10-bit system
with a 1-V full scale signal, an LSB is about 1 mV. For a 12-bit
system, an LSB is approximately 250 V. To resolve the settling
characteristics for a full-scale transition, dynamic ranges
approaching four orders of magnitude must be handled. With
settling times of new op amps [e.g., the AD9631 and AD9632]
dropping to the 20 ns to 10 ns range, the measurement of settling
time presents quite a challenge.
Q. How is settling time measured?
A. A key requirement over the years has been the need to drive the
input of the op amp with a fast, precise signal source, often
referred to as a flat-top generator. As the name implies, such a
generator would have a sharp transition between two levels of
known amplitude at time, t0, should have minimal overshoot
(or undershoot) and then remain flat for the remainder of the
measurement time. In this case flat means significantly flatter
than the error to be measured in the amplifier.
The great accuracy is required to be certain that any output
signal from the op amp is entirely due to its settling response
and not its response to a signal that is present at the input after
the step transition. Any active device in the path of this signal
would require better settling characteristics than the DUT.
40
Such generators are in practice very difficult to develop. A rather

low-tech device has served for quite some time as a means
for generating a flat-top transition; the contact opening of a
mercury-wetted-contact relay connected to a stable lowimpedance voltage source can be used to produce a rather clean
(and surprisingly fast) flat-topped pulse. The figure shows a
simple circuit that performs this function. For a negative-going
transition, with the relay closed, a dc voltage, VSTEP, is applied
to the input of the DUT and a 50- resistor to ground. When
the relay opens, the input node rapidly discharges to ground,
creating the input transition. The open relay contact ensures
that all other elements are totally isolated from the amplifier
input; the input level is held constant (grounded through 50 )
for as long as the relay remains open.
VSTEP
MERCURY-WETTED-CONTACT
RELAY
DUT
50
Next problem: directly measuring the output requires handling

a large dynamic range. If the DUT is configured as an inverter,
a subtractor circuit can be created that only looks at the error
signal and does not have to handle the entire dynamic range of
the output. This figure shows a circuit used for measuring the
16-bit settling time of the AD797800 ns typical to 0.0015%.
226
4.26k
A2
AD829
VERROR 5
250
6
7
2x
HP2835
2x
HP2835
0.47F
0.47F
+VS
VS
1k
1k
1k
100
FLAT-TOP
GENERATOR
VIN
20pF
1k
NOTE:
USE CIRCUIT
BOARD
WITH GROUND
PLANE
A1
AD797
DUT
3
6
51pF
7
4
1F
1F
0.1F
0.1F
+VS
VS
A1, the DUT in this circuit, is configured for a gain of 1. The

voltage divider from input to output forms a second false
summing node that will replicate the signal at the amplifiers
summing node. The 100- potentiometer is used to null the dc
voltage.The wiper of the potentiometer is clamped by the diodes
at the input of A2 to limit saturation effects in this amplifier.
The output is also similarly clamped.
Since the pre- and post-transition voltages at the output of A2
will be the same (i.e., the difference will be zero), the settling

characteristics of this amplifier due to a step change are not
important for measuring A1. Thus, the output of A2 can be
measured to find the settling time of A1.
strategies to produce thermal symmetry, but this is easier for lowlevel high-precision devices than those designed for high-speed,
because of the large, rapid swings of power that occur.
This technique requires that the DUT be configured as an

inverting amplifier. The circuit can be made to work at other
gains, but the resistor values and setting of the dc balance
potentiometer will have more influence on the measurement.
In particular, the new dielectrically isolated processes (like

XFCB) that have worked wonders for improving the raw speed
of the op amps can have some difficulty in minimizing the
presence of thermal tails. This is because the process provides
each transistor a separate dielectric tub. While this dielectric
isolation reduces the parasitic capacitance and greatly speeds
up electrical performance, it also provides thermal insulation
that slows the dissipation of heat to the substrate.
If there is a gain error in this system, it will show up as a dc

offset in the error waveform. The calculation can be adapted for
a DUT with any gain, either inverting or non inverting. It also
can compensate for a signal generator that itself has a low
frequency settling tail. The DUT response to a low frequency
input will not be influenced by that settling time.
Because such oscilloscopes are designed primarily for speed, in
order to determine errors at higher resolutions, averaging must
be used. For example, if the A/D used in the oscilloscope has
only 8 bit resolution, but accuracy better than 8 bits, a number
of cycles can be averaged to increase the effective resolution of
the measurement.
Q. Any more?
A. Yet a third way to measure settling time is to look at the output
directly. A Data Precision Data 6000 can directly digitize signals
of up to 5 V with 16-bit accuracy and 10-ps resolution. The
only fly in the ointment is that the instrument relies on repetitive
sampling with a comparator probe. The waveform is built up
one bit at a time for each of the sample points. As a result,
obtaining a settling characteristic can be very time consuming.
This is especially so when using a relay-type flat top generator
with a 1-kHz upper frequency.
Q. Why do data sheets sometimes define short term and long term settling
characteristics?
A. The traditional definition of settling time is the time from the
input transition to the time when the amplifier output enters
the specified error zone and does not leave again. This concept
is relatively uncomplicated and straightforward. However, there
are some cases where the initial settling is fast, followed by an
extended period of settling to the final value. Single-supply
amplifiers may exhibit this characteristic in the vicinity of the
lower rail. Of greater prevalence for large transients, a thermal
tail is a slow drift that continues for a relatively long time after
rapid settling to apparently excellent initial accuracy.
Thermal tails are produced when voltage level changes within
the op amp caused by a step transition create temperature
gradients among the transistors. Matched transistors will not
track well while they are at temporarily different temperatures.
The thermal time constant of the chip determines how long it
takes for equilibrium to return. Op amps are designed to prevent
or reduce these effects by careful placement of devices and
The seriousness of long tails depends on the application. For

example, some systems sample at rates compatible with the initial
short-term settling time and are not seriously affected by longer
term drifts. Communication systems and others, where the
frequency domain properties of the converted signal are most
important, are examples of such systems. Although long-term
settling errors can produce variations in gain and offset, the
long-term thermal tails will have minimal contribution to the
distortion products of the digitized signal. For these systems,
frequency domain measurementssuch as distortion
productsare more important than time domain measurements,
such as settling time.
On the other hand, systems such as video and scanners might
produce a step input, followed by a long-duration plateau of
constant value. During this time, repetitive A/D conversions of
the op amp output signal will track the long-term settling
characteristic. For these systems it is important to understand
the long term settling characteristics of the op amp.
The figures below illustrate the long- and short-term settling
patterns for the AD8036, a unity-gain-stable high-speed clamp
amp that is a good candidate for an A/D driver in high speed
systems. The figure at left shows that after the initial large
transition, the output is still about 0.09% from its long-term
final value. However, the right-hand figure shows, on a 300
faster scale, that after about 16 ns the output has entered a local
0.01% short-term settling region which can be usefully sampled
by some systems. The distortion of the AD8036 is extremely
low (2nd and 3rd harmonics down by more than 65 dB with
500- load) so it would be a good candidate in systems where
b
this kind of performance is critical.
0.4
0.05
0.3
0.04
0.2
0.03
0.1
0.02
ERROR %
A. Another technique for measuring settling time uses the

computing power of a digital oscilloscope. It calculates a
waveform that represents the settling error as the instantaneous
difference between the acquired input and output signals of the
DUT and compares them with the values for an ideally settling
device. The resulting waveform is the error of the DUT.
ERROR %
Q. Any other techniques?
0.1
0.2
0.01
0
0.01
0.3
0.02
0.4
0.03
0.5
0.04
0.6
0.05
0
4
6
8 10 12 14
SETTLING TIME - s
16
18
10
15
20
25
30
35
40
45
SETTLING TIME ns
Reference: Demrow, Robert, Settling time of operational

amplifiers, in The Best of Analog Dialogue, 1967 to 1991, pages
32-42.
Analog-Digital Conversion Handbook. Norwood, MA; Analog Devices,
1986, pp. 312-317 and 436-439 (DAC settling time).
41

INTERFACING TO SERIAL CONVERTERSI
by Eamon Nash
Q. I need data converters to fit in a tight space, and I suspect that a
serial interface will help. What do I need to know to choose and use
one?
A. Lets start by looking at how a serial interface works and then
compare it to a parallel interface. In doing this we will dispel
some myths about serial data converters.
RFS1
TFS1
SCLK1
DSP
ADC
ADSP-2105
AD7890
DR1
DT1
SLCK
DATA OUT
DATA IN
LEADING
ZERO
A2
A2
A1
A0
DB11
DB10
DB0
A1
A0
CONV
STBY
DONT
CARE
DONT
CARE
The figure shows an AD7890 8-Channel multiplexed 12-bit

serial A/D converter (ADC) connected to the serial port of an
ADSP-2105 digital signal processor (DSP). Also shown is the
timing sequence that the DSP uses to communicate with the
ADC. The 12 bits that constitute the conversion result are
transmitted as a serial data stream over a single line. The data
stream also includes three additional bits that identify the input
channel that the AD7890s multiplexer is currently selecting.
To distinguish the bits of the serial data stream from one
another, a clock signal (SCLK) must be provided, usually by
the DSP; However, sometimes the ADC supplies this clock as
an output. The DSP usually (but not always) supplies an
additional framing pulse that is active either for one cycle at
the beginning of the communication or, as shown (TFS/RFS),
for the duration of the transmission.
In this example, the DSPs serial port is used to program an
internal 5-bit register in the ADC. The registers bits control
such functions as selecting the channel to be converted, putting
the device in power-down mode, and starting a conversion. It
should be evident that the serial interface, in this case, must
be bi-directional.
A parallel ADC, on the other hand, connects directly (or
possibly through buffers) to the data bus of the processor it is
interfaced with. The figure shows the AD7892 interfaced to
an ADSP-2101. When a conversion is complete, the AD7892
interrupts the DSP, which responds by doing a single read of
the ADCs decoded memory address.
The key difference between serial and parallel data converters

lies in the number of interface lines required. From a space
saving point of view, serial converters offer a clear advantage
because of reduced device pin-count. This makes it possible to
package a 12-bit serial ADC or DAC in an 8-pin DIP or SO
package. More significantly, board space is saved because serial
interface connections require fewer PCB tracks.
Q. My digital-to-analog converters have to be physically remote from
the central processor and from one another. What is the best way to
approach this?
A. Initially, you must decide whether to use serial or parallel DACs.
With parallel DACs, you could map each one into a memory
mapped I/O location, as shown in the figure. You would then
program each DAC by simply doing a Write command to the
appropriate I/O location. However, this configuration has a
significant disadvantage. It requires a parallel data bus, along
with some control signals, to all of the remote locations. Clearly,
a serial interface, that can have as few as two wires, is much
more economical.
ADDRESS BUS
DECODE LOGIC
CS 0
DAC 0
CS 1
CS N
DAC 1 ... DAC N
DATA BUS
Serial converters cannot in general be mapped into a processors

memory. But a number of serial DACs could be connected to
the serial I/O port of the processor. Then, other ports on the
processor could be used to generate Chip Select signals to
enable the DACs individually. The Chip Select signals will
require a line from each device to the interface. But there may
be a limit to the number of lines on the processor that can be
configured to transmit Chip Select signals.
One way of getting around this problem is to use serial DACs
that can be daisy-chained together. The figure shows how to
connect multiple DACs to a single I/O port. Each DAC has a
Serial Data Out (SDO) pin that connects to the Serial Data In
(SDI) pin of the next DAC in the chain. LDAC and SCLK are
fed in parallel to all the DACs in the chain. Because the data
clocked into SDI eventually appears at SDO (N clock cycles
later), a single I/O port can address multiple DACs. However,
the port must output a long data stream (N bits per DAC times
the number of devices in the chain). The great advantage of
this configuration is that device decoding is not needed. All
devices are effectively at the same I/O location. The main
drawback of daisy chaining is accessibility (or latency). To
change the state of even a single DAC, the processor must still
output a complete data stream from the I/O port.
TIMER
DMA13DMA0
DAC 0
ADDRESS
DECODE
LOGIC
LDAC
DMD15DMD0
TO
LDAC
DAC 3
DAC
REGISTER
AD7892
SDI
tCONV
tACCESS
42
LDAC
DB11DB0
ADSP-2101
DATA OUT
DAC
REGISTER
DAC 1
3-STATE
tHOLD
VALID DATA
CLOCK
3-STATE
INPUT
REGISTER
SDO
SDI
INPUT
REGISTER
SDO
TO
SDI
DAC 3
TO
CLK
DAC 3

Q. If serial data converters save so much space and wire, why arent
they used in every space-sensitive application?
A. A major disadvantage of serial interfacing is the tradeoff of
speed for space. For example, to program a parallel DAC, just
place the data on the data bus and clock it into the DAC with
a single pulse. However, when writing to a serial DAC, the bits
must be clocked in sequentially (N clock pulses for an N-bit
converter) and followed by a Load pulse. The processors I/O
port spends a relatively large amount of time communicating
with a serial converter. Consequently, serial converters with
throughput rates above 500 ksps are uncommon.
Q. My 8-bit processor doesnt have a serial port. Is there a way to interface
a serial 12-bit ADC like the AD7893 to the processors parallel bus?
A. It can of course be done using an external shift register, which
is loaded serially (and asynchronously), then clocked into the
processors parallel port. However, if the sense of the question
is without external logic, the serial ADC can be interfaced
as if it were a 1-bit parallel ADC. Connect the converters
SDATA pin to one of the processors data bus lines (it is
connected to D0 in the diagram). Using some decode logic,
the converter can be mapped into one of the processors
memory locations so that the result of the conversion can be
read with 12 successive Read commands. Then additional
software commands integrate the LSBs of the 12 bytes that
were read into a single 12-bit parallel word.
MICROPROCESSOR
ADDRESS BUS
ADDRESS
DECODER
AD7893
WR
RD
D7
D6
D5
DATA BUS D4
(1 BIT USED) D3
D2
D1
D0
SCLK
SDATA
This technique, which is sometimes referred to as bit banging,

is very inefficient from a software perspective. But it may be
acceptable in applications in which the processor runs much
faster than the converter.
Q. In the last example, a gated version of the processors write signal
was used to start conversions on the AD7893. Are there problems
with that approach?
A. I am glad you spotted that. In this example, a conversion can
be initiated by doing a dummy write to the AD7893s mapped
memory location. No data is exchanged, but the processor
provides the write pulse needed to begin the conversion. From
a hardware perspective, this configuration is very simple
because it avoids the need to generate a conversion signal.
However, the technique is not recommended in ac dataacquisition applications, in which signals must be sampled
periodically. Even if the processor is programmed to do periodic
writes to the ADC, phase jitter on the Write pulse will seriously
degrade the attainable signal-to-noise ratio (SNR). The gating
process may make the Write signal jitter even worse. A sampling
clock phase jitter level of as little as 1 ns, for example, would
degrade the SNR of an ideal 100-kHz sine wave to about 60 dB
(less than 10 effective bits of resolution).There is also an additional

danger that overshoot and noise on the sampling signal will further
degrade the integrity of the analog to digital conversion.
Q. When should I choose a converter with an asynchronous serial
interface?
A. An asynchronous link allows devices to exchange unclocked
data with each other. The devices must initially be programmed
to use the identical data formats. This involves setting a
particular data rate (usually expressed in baud, or bits per
second). A convention, that defines how to initiate and end
transmissions, is also necessary. We do this using identifiable
data sequences called start and stop bits. The transmission may
also include parity bits that facilitate error detection.
RXD
RXD
TXD
TXD
COM PORT
AD1B60
ADM232
PC
The figure shows how the AD1B60 Digitizing Signal

Conditioner interfaces to a PCs asynchronous COM Port. This
is a 3-wire bidirectional interface (the ground lines have been
omitted for clarity). Notice that the receive and transmit lines
exchange roles at the other end of the line.
An asynchronous data link is useful in applications in which
devices communicate only sporadically. Since start and stop
bits are included in every transmission, a device can initiate
communication at any time by simply outputting its data. The
number of connections between devices is reduced because
clocking and control signals are no longer necessary.
Q. The data sheet of an ADC I am considering recommends using a
non-continuous clock on the serial interface. Why?
A. The specification probably requires that the clock be kept
inactive while the conversion is in progress. Some ADCs require
this because a continuous data clock can feed through to the
analog section of the device and adversely affect the integrity
of the conversion. A continuous clock signal can be
discontinued during conversion if the I/O port has a framing
pulse; it is used as a gating signal that enables the serial clock
to the converter only during data transfer.
Q. What makes a device SPI or MICROWIRE compatible?
A. SPI (Serial Peripheral Interface) and MICROWIRE are serial
interface standards developed by Motorola and National
Semiconductor, respectively. Most synchronous serial
converters can be easily interfaced to these ports; but in some
cases additional glue logic may be necessary.
Q. O.K. I decided to put prejudice aside and use a serial ADC in my
current design. I have just wired it up as the data sheet specifies.
When my micro reads the conversion result, the ADC always seems
to output FFFHEX. Whats happening?
A. Perhaps you are having a communications problem. We need
to look at the connections between the ADC and the
processorand at how the timing and control signals have been
set up. We also need to look at the Interrupt structure. The
next installment will return to this issue, discussing the
problems encountered when designing serial interfaces. b
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
43

INTERFACING TO SERIAL CONVERTERSII
by Eamon Nash
Q. At the end of our discussion in the last issue, I was having a problem
establishing communication between my ADC and my
microcontroller. If you recall, the microcontroller always seemed to
be reading a conversion result of FFFHEX regardless of the voltage
on the analog input.What could be causing this?
A. There are a number of possible timing-related error sources.
You could start trouble-shooting this problem by connecting
all of the timing signals either to a logic analyzer or to a multichannel oscilloscope (at least three channels are needed to look
at all signals simultaneously).What you would see on the screen
would look similar to the timing diagram in the figure below.
First make sure that a Start Conversion command (CONVST)
is being generated (coming either from the micro or from an
independent oscillator). A frequent mistake is to apply a
CONVST signal with the wrong polarity. The conversion is
still performed, but not when you expect it to be. It is also
important to remember that there is usually a minimum pulse
width requirement on the CONVST signal (typically about
50 ns). The standard Write or Read pulse from fast
microprocessors may not satisfy this requirement. If too short,
the pulse width can be extended by inserting software Wait
states.
t1
tCONV
SCLK
DATA OUT
DB11
DB10
DB0
Make certain that the micro is waiting for the conversion to be

completed before the Read cycle begins. Your software should
either be taking note of the time required to convert or be
waiting for an End of Conversion (EOC) indicator from the
ADC to generate an interrupt in the micro. Make sure that the
polarity of the EOC signal is correct, otherwise the ADC will
cause an interrupt while the conversion is in progress. If the
micro is not responding to the interrupt, you should examine
the configuration of the interrupt in your software.
It is also important to consider the state of the serial clock line
(SCLK) while it is not addressing the converter. As I mentioned
in our previous discussion, some DACs and ADCs do not
operate correctly with continuous serial clocks. In addition to
this, some devices require that the SCLK signal always idles in
one particular state.
Q. O.K. Ive found and corrected some bugs in my software and things
seem to be improving. The data from the converter are changing as
I vary the input voltage but the conversion results seem to have no
recognizable format.
44
A. Once again there are a number of possible error sources. The

ADC will be outputting its conversion result either in straight
binary or in twos complement format (BCD data converters
are no longer widely used). Check that your micro is configured
to accept the appropriate format. If the micro cant be
configured to accept twos complement directly, you can convert
the data to straight binary by exclusive-oring the number with
100 . . . 00 binary.
Normally the leading edge of the serial clock (either rising or
falling) will enable the data out of the ADC and onto the data
bus. The trailing edge then clocks the data into the micro. Make
sure that both micro and ADC are operating under the same
convention and that all Setup and Hold times are being met. A
conversion result that is exactly half or double what one would
expect is a tell-tale sign that the data (especially the MSB) is
being clocked on the wrong edge. The same problem would
manifest itself in a serial DAC as an output voltage that is half
or double the expected value.
0V
UNDERSHOOT > 0.3V
N
P
The digital signals driving the converter should be clean. In

addition to causing possible long-term damage to the device,
overshoot or undershoot can cause conversion and
communication errors. The figure shows a signal with a large
overshoot spike driving the clock input of a single-supply
converter. In this case, the clock input drives the base of an
PNP transistor. As is usual practice, the P-type substrate of
the device is internally connected to the most negative potential
availablein this case, ground. An excursion of more than 0.3
volts below ground on the SCLK line is sufficient to begin
turning on a parasitic diode between the N-type base and the
P-type substrate. If this happens frequently, over the long term,
it may lead to damage to the device.
In the short term, though not causing damage, energizing the
normally inert substrate affects other transistors in the device
and can lead to multiple clock pulses being detected for each
pulse applied. The resulting jitter is a serious matter in serial
convertersbut is less of a problem in parallel converters,
because the Read and Write cycles generally depend upon the
first applied pulse; subsequent pulses are ignored. However,
the noise performance on both serial and parallel converters
can suffer if signals of this kind are present during conversion.
The figure shows how overshoot can be easily reduced. A small
resistor is placed in series on the digital line that is causing the
problem. This resistance will combine with Cpar, the parasitic
capacitance of the digital input, to form a low-pass filter which
should eliminate any ringing on the received signal. Typically
a 50- resistor is recommended, but some experimentation
may be necessary. It may also be necessary to add an external
capacitance from the input to ground if the internal capacitance

of the digital input is insufficient. Here again, experimentation
is necessarybut a good starting point would be about 10 pF.
ADC/DAC
DIGITAL
INPUT
SIGNAL
TO INTERNAL
CIRCUITRY
50
CPAR
CEXT
Q. You mentioned that clock overshoot can degrade the noise

performance of a converter. Is there anything else I can do from an
interfacing point of view to get a good signal to noise ratio?
A. Because your system is operating in a mixed-signal environment
(i.e., analog and digital), the grounding scheme is critical. You
probably know thatbecause digital circuitry is noisyanalog
and digital grounds should be kept separate, joined at only
one point. This connection is usually made at the power supply.
In fact, if the analog and digital devices are powered from a
common supply, as might be the case in a +5 V or +3.3 V
single-supply system, there is no choice but to connect the
grounds back at the supply. But the data sheet for the converter
probably has an instruction to connect the pins AGND and
DGND at the device! So how can one avoid creating a ground
loop that can result if the grounds are connected in two places?
The figure below shows how to resolve this apparent dilemma.
The key is that the AGND and DGND labels on the converters
pins refer to the parts of the converter to which those pins are
connected. The device as a whole should be treated as analog.
So after the AGND and DGND pins have been connected
together, there should be a single connection to the systems
analog ground. True, this will cause the converters digital
currents to flow in the analog ground plane, but this is generally
a lesser evil than exposing the converters DGND pin to a noisy
digital ground plane. This example also shows a digital buffer,
referred to digital ground, to isolate the converters serial data
pins from a noisy serial bus. If the converter is making a pointto-point connection to a micro, this buffer may be unnecessary.
TO OTHER
DIGITAL CIRCUITS
VD
SYSTEM
POWER
VA
ADC/DAC
QUIET
DIGITAL
NOISY SERIAL
DATA BUS
VD
BUFFER
LATCH
SYSTEM
GROUND
AGND DGND
DIGITAL GROUND/POWER PLANE

ANALOG GROUND/POWER PLANE
D
TO OTHER
DIGITAL CIRCUITS
The figure also shows how to deal with the increasingly

common challenge of powering a mixed-signal system with a
single power supply. As in the grounding case, we run separate
power lines (preferably power planes) to the analog and digital
portions of the circuit. We treat the digital power pin of the
converter as analog. But some isolation from the analog power
pin, in the form of an inductor, is appropriate. Remember that
both power pins of the converter should have separate
decoupling capacitors. The data sheet will recommend
appropriate capacitors, but a good rule of thumb is 0.1 F. If
space permits, a single 10-F capacitor per device should also
be included.
Q. I want to design an isolated serial interface between an ADC and a
microcontroller using opto-isolators.What should I be aware of when
using these devices?
A. Opto-isolators (also known as opto-couplers) can be used to
create a simple and inexpensive high-voltage isolation barrier.
The presence of a galvanic isolation barrier between converter
and micro also means that analog and digital system grounds
no longer need to be connected. As shown in the figure, an
isolated serial interface between the AD7714 precision ADC
and the popular 68HC11 microcontroller can be implemented
with as few as three optoisolators.
+5V
68HC11
+5V
10k
4N25
MISO
425
AD7714
DATA OUT
10k
425
4N25
DATA IN
MOSI
10k
425
SCLK
4N25
SCLK
AGND
DGND
The designer should be aware, though, that the use of

optoisolators having relatively slow rise and fall times with
CMOS converters can cause problems, even when the serial
communication is running at a slow speed.
CMOS logic inputs are designed to be driven by a definite
logic zero or logic one. In these states, they source and sink
a minimal amount of current. However, when the input
voltage is in transition between logic zero and logic one (0.8 V
to 2.0 V), the gate will consume an increased amount of
current. If the opto-isolators used have relatively slow rise
and fall times, the excessive amount of time spent in the
dead-band will cause self-heating in the gate. This self-heating
tends to shift the threshold voltage of the logic gate upwards,
which can lead to a single clock edge being interpreted by
the converter as multiple clock pulses. To prevent this
threshold jitter, the lines coming from the optoisolators
should be buffered using Schmitt trigger circuits, to deliver
b
fast, sharp edges to the converter.
45

by Steve Guinta
CAPACITANCE AND CAPACITORS
I. Understanding the Parasitic Effects In Capacitors:
Q. I need to understand how to select the right capacitor for my
application, but Im not clear on the advantages and disadvantages
of the many different types.
A. Selecting the right capacitor type for a particular application
really isnt that difficult. Generally, youll find that most
capacitors fall into one of four application categories:
AC coupling, including bypassing (passing ac signals while
blocking dc)
decoupling (filtering ac or high frequencies superimposed on
dc or low frequencies in power, reference, and signal circuitry)
active/passive RC filters or frequency-selective networks
analog integrators and sample-and-hold circuits (acquiring and
storing charge)
+
AC COUPLING
FILTERS
DECOUPLING
SAMPLE-HOLD
1
0
Even though there are more than a dozen or so popular

capacitor typesincluding poly, film, ceramic, electrolytic,
etc.youll find that, in general, only one or two types will be
best suited for a particular application, because the salient
imperfections, or parasitic effects on system performance
associated with other types of capacitors will cause them to be
eliminated.
Q. What are these parasitic effects youre talking about?
A. Unlike an ideal capacitor, a real capacitor is typified by
additional parasitic or non-ideal components or behavior,
in the form of resistive and inductive elements, nonlinearity,
and dielectric memory. The resulting characteristics due to
these components are generally specified on the capacitor
manufacturers data sheet . Understanding the effects of these
parasitics in each application will help you select the right
capacitor type.
RL
C
RESR
RDA
LESL
CDA
Model of a Real Capacitor

Q. OK, so what are the most important parameters describing nonideal capacitor behavior?
A. The four most common effects are leakage (parallel resistance),
equivalent series resistance (ESR), equivalent series inductance
(ESL), and dielectric absorption (memory).
46
Capacitor Leakage, RP: Leakage is an important parameter

in ac coupling applications, in storage applications, such as
analog integrators and sample-holds, and when capacitors are
used in high-impedance circuits.
IL
C
(a) IDEAL MODEL
RP
(b) LEAKAGE MODEL
In an ideal capacitor, the charge, Q, varies only in response to

current flowing externally. In a real capacitor, however, the
leakage resistance allows the charge to trickle off at a rate
determined by the R-C time constant.
Electrolytic-type capacitors (tantalum and aluminum),
distinguished for their high capacitance, have very high leakage
current (typically of the order of about 5-20 nA per F) due to
poor isolation resistance, and are not suited for storage or
coupling applications.
The best choices for coupling and/or storage applications are
Teflon (polytetrafluorethylene) and the other poly types
(polyproplene, polystyrene, etc).
Equivalent Series Resistance (ESR), RS: The equivalent
series resistance (ESR) of a capacitor is the resistance of the
capacitor leads in series with the equivalent resistance of the
capacitor plates. ESR causes the capacitor to dissipate power
(and hence produce loss) when high ac currents are flowing.
This can have serious consequences at RF and in supply
decoupling capacitors carrying high ripple currents, but is
unlikely to have much effect in precision high-impedance, lowlevel analog circuitry.
Capacitors with the lowest ESR include both the mica and
film types.
Equivalent Series Inductance (ESL), LS: The equivalent
series inductance (ESL) of a capacitor models the inductance
of the capacitor leads in series with the equivalent inductance
of the capacitor plates. Like ESR, ESL can also be a serious
problem at high (RF) frequencies, even though the precision
circuitry itself may be operating at DC or low frequencies. The
reason is that the transistors used in precision analog circuits
may have gain extending up to transition frequencies (Ft) of
hundreds of MHz, or even several GHz, and can amplify
resonances involving low values of inductance. This makes it
essential that the power supply terminals of such circuits be
decoupled properly at high frequency.
Electrolytic, paper, or plastic film capacitors are a poor choice
for decoupling at high frequencies; they basically consist of
two sheets of metal foil separated by sheets of plastic or paper
dielectric and formed into a roll. This kind of structure has
considerable self inductance and acts more like an inductor
than a capacitor at frequencies exceeding just a few MHz.
A more appropriate choice for HF decoupling is a monolithic,
ceramic-type capacitor, which has very low series inductance.
It consists of a multilayer sandwich of metal films and ceramic
dielectric, and the films are joined in parallel to bus-bars, rather
than rolled in series.
A minor tradeoff is that monolithic ceramic capacitors can be
microphonic (i.e., sensitive to vibration), and some types may

even be self-resonant, with comparatively high Q, because of
the low series resistance accompanying their low inductance.
Disc ceramic capacitors, on the other hand, are sometime quite
inductive, although less expensive.
Q. Ive seen the term dissipation factor used in capacitor selection
charts.What is it?
A. Good question. Since leakage, ESR, and ESL are almost always
difficult to spec separately, many manufacturers will lump
leakage, ESR and ESL into a single specification known as
dissipation factor, or DF, which basically describes the
inefficiency of the capacitor. DF is defined as the ratio of energy
dissipated per cycle to energy stored per cycle. In practice, this
is equal to the power factor for the dielectric, or the cosine of
the phase angle. If the dissipation at high frequencies is
principally modeled as series resistance, at a critical frequency
of interest, the ratio of equivalent series resistance, ESR, to
total capacitive reactance is a good estimate of DF,
DF RSC .
Dissipation factor also turns out to be the equivalent to the

reciprocal of the capacitors figure of merit, or Q, which is also
sometimes included on the manufacturers data sheet.
Dielectric Absorption, RDA, CDA: Monolithic ceramic
capacitors are excellent for HF decoupling, but they have
considerable dielectric absorption, which makes them unsuitable
for use as the hold capacitor of a sample-hold amplifier (SHA).
Dielectric absorption is a hysteresis-like internal charge
distribution that causes a capacitor which is quickly discharged
and then open-circuited to appear to recover some of its charge.
Since the amount of charge recovered is a function of its
previous charge, this is, in effect, a charge memory and will
cause errors in any SHA where such a capacitor is used as the
hold capacitor.
Another thing to remember about high frequency decoupling

is the actual physical placement of the capacitor. Even short
lengths of wire have considerable inductance, so mount the
HF decoupling capacitors as close as possible to the IC, and
ensure that leads consist of short, wide PC tracks.
Ideally, HF decoupling capacitors should be surface-mount
parts to eliminate lead inductance, but wire-ended capacitors
are ok, providing the device leads are no longer than 1.5 mm.
CAP
CAP
IC
G
R
O
U
N
D
G
R
O
U
N
D
IC
P
L
A
N
E
P
L
A
N
E
RIGHT WAY
WRONG WAY
USE LOW INDUCTANCE CAPACITORS (MONOLITHIC CERAMIC)

MOUNT CAPACITOR CLOSE TO IC
USE SURFACE MOUNT TYPE
USE SHORT, WIDE PC TRACKS
II. Stray Capacitance:

A. Now that weve talked about the parasitic effects of capacitors
as components, lets talk about another form of parasitic known
as stray capacitance.
Q. Whats that?
A. Well, just like a parallel-plate capacitor, stray capacitors are
formed whenever two conductors are in close proximity to each
other (especially if theyre running in parallel), and are not
shorted together or screened by a conductor serving as a
Faraday shield.
C = 0.0085
ER
AREA A
A
d
C = CAPACITANCE IN pF
ER = DIELECTRIC CONSTANT RELATIVE TO AIR
A = AREA OF PARALLEL CONDUCTORS IN mm2
d = DISTANCE BETWEEN CONDUCTORS IN mm
A
B
C (NC)
Capacitor Model
A
C
TIME
Capacitors that are recommended for this type of application

include the poly type capacitors we spoke about earlier, i.e.,
polystyrene, polypropylene, or Teflon. These capacitor types
have very low dielectric absorption (typically <0.01%).
The characteristics of capacitors in general are summarized in
the capacitor comparison chart (page 21).
A note about high-frequency decoupling in general: The
best way to insure that an analog circuit is adequately decoupled
at both high and low frequencies is to use an electrolytic-type
capacitor, such as a tantalum bead, in parallel with a monolithic
ceramic one. The combination will have high capacitance at
low frequency, and will remain capacitive up to quite high
frequencies. Its generally not necessary to have a tantalum
capacitor on each individual IC, except in critical cases; if there
is less than 10 cm of reasonably wide PC track between each
IC and the tantalum capacitor, its possible to share one
tantalum capacitor among several ICs.
Stray or parasitic capacitance commonly occurs between

parallel traces on a PC board or between traces/planes on
opposite sides of a PC board. The occurrence and effects of
stray capacitanceespecially at very high frequenciesare
unfortunately often overlooked during circuit modelling and
can lead to serious performance problems when the system
circuit board is constructed and assembled; examples include
greater noise, reduced frequency response, even instability.
PARASITIC CAPACITANCE
PC TRACES
PC TRACES
1.5 mm
TYPICAL
GROUND PLANE
ADJACENT
BETWEEN TRACES
BETWEEN TRACES AND/OR

PLANES ON OPPOSITE SIDES
(a)
PC BOARD
TOP VIEW
(b)
PC BOARD
CROSS SECTIONAL VIEW
47

For instance, if the capacitance formula is applied to the case
of traces on opposite sides of a board, then for general purpose
PCB material (ER = 4.7, d = 1.5 mm), the capacitance between
conductors on opposite sides of the board is just under
3 pF/cm2. At a frequency of 250 MHz, 3 pF corresponds to a
reactance of 212.2 ohms!
KOVAR LID
CERAMIC
Q. How does it work?
Whatever the environmental noise level, it is good practice for

the user to ground the lid of any side brazed ceramic IC where
the lid is not grounded by the manufacturer. This can be done
with a wire soldered to the lid (this will not damage the device,
as the chip is thermally and electrically isolated from the lid).
If soldering to the lid is unacceptable, a grounded phosphorbronze clip may be used to make the ground connection, or
conductive paint can be used to connect the lid to the ground
pin. Never attempt to ground such a lid without verifying that it is,
in fact, unconnected; there do exist device types with the lid
connected to a supply rail rather than to ground!
A. Look at the Figure; it is an equivalent circuit showing how a

high-frequency noise source, VN, is coupled into a system
impedance, Z, through a stray capacitance, C. If we have little
or no control over Vn or the location of Z1, the next best solution
is to interpose a Faraday shield:
One case where a Faraday shield is impracticable is between

the bond wires of an integrated circuit chip. This has important
consequences. The stray capacitance between two chip bond
wires and their associated leadframes is of the order of 0.2 pF;
observed values generally lie between 0.05 and 0.6 pF.
Q. So how can I eliminate stray capacitance?

A. You can never actually eliminate stray capacitance; the best
you can do is take steps to minimize its effects in the circuit.
Q. How do I do that?
A. Well, one way to minimize the effects of stray coupling is to
use a Faraday shield, which is simply a grounded conductor
between the coupling source and the affected circuit.
CAPACITANCE, C
0.2pF
Z2 = 1/j C
VN
Z1
CIRCUIT IMPEDANCE
Z1
VCOUPLED = VN ( )
Z1 + Z2
VCOUPLED
VOLTAGE NOISE
COUPLED THROUGH
STRAY CAPACITANCE
As shown, below, the Faraday shield interrupts the coupling

electric field. Notice how the shield causes the noise and
coupling currents to return to their source without flowing
through Z1.
Consider a high-resolution converter (ADC or DAC), which

is connected to a high-speed data bus. Each line of the data
bus, (which will be switching at around 2 to 5 V/ns),will be
able to influence the converters analog port via this stray
capacitance; the consequent coupling of digital edges will
degrade the performance of the converter.
FARADAY
SHIELD
VN
Z1
CIRCUIT
IMPEDANCE
VCOUPLED
HIGH SPEED
DATA BUS
ANALOG
SECTION
CAPACITIVE NOISE
AND FARADAY SHIELDS
PARASITIC (STRAY)
CAPACITANCE
VN
Z1
CIRCUIT
IMPEDANCE
VCOUPLED
Another example of capacitive coupling is in side-brazed

ceramic IC packages. These DIP packages have a small, square,
conducting Kovar lid soldered onto a metallized rim on the
ceramic package top. Package manufacturers offer only two
options: the metallized rim may be connected to one of the
corner pins of the package, or it may be left unconnected. Most
logic circuits have a ground pin at one of the package corners,
and therefore the lid is grounded. But many analog circuits do
not have a ground pin at a package corner, and the lid is left
floating. Such circuits turn out to be far more vulnerable to
electric field noise than the same chip in a plastic DIP package,
where the chip is unshielded.
48
This problem may be avoided by isolating the data bus,

interposing a latched buffer as an interface. Although this
solution involves an additional component that occupies board
area, consumes power, and adds cost, it can significantly
b
improve the converters signal-to-noise.
BUFFER/
DATA LATCH
D-A
CONVERTER
HIGH SPEED
DATA BUS
ANALOG
SECTION
BUFFER/
DATA LATCH
A-D
CONVERTER

CAPACITOR COMPARISON CHART
TYPE
TYPICAL
DIELECTRIC
ABSORPTION
ADVANTAGES
DISADVANTAGES
NPO ceramic
<0.1%
Small case size

Inexpensive
Good stability
Wide range of values
Many vendors
Low inductance
DA generally low, but may not be specified

Limited to small values (10 nF)
Polystyrene
0.001%
to 0.02%
Inexpensive
Low DA available
Good stability
Damaged by temperature > +85C

Large case size
High inductance
Polypropylene
0.001%
to 0.02%
Inexpensive
Low DA available
Damaged by temperature > +105C

Large case size
High inductance
Teflon
0.003%
to 0.02%
Low DA available
Good stability
Operational above +125C
Relatively expensive
Large size
High inductance
MOS
0.01%
Good DA
Small
Operational above +125C
Low inductance
Limited availability
Available only in small capacitance values
Polycarbonate
0.1%
Good stability
Low cost
Wide temperature range
Large size
DA limits to 8-bit applications
High inductance
Polyester
0.3%
to 0.5%
Moderate stability
Low cost
Wide temperature range
Low inductance (stacked film)
Large size
DA limits to 8-bit applications
High inductance
Monolithic ceramic
(High K)
>0.2%
Low inductance
Poor stability
Poor DA
High voltage coefficient
Mica
>0.003%
Low loss at HF
Low inductance
Very stable
Available in 1% values or better
Quite large
Low values (<10 nF)
Expensive
Aluminum electrolytic
High
Large values
High currents
High voltages
Small size
High leakage
Usually polarized
Poor stability
Poor accuracy
Inductive
Tantalum electrolytic
High
Small size
Large values
Medium inductance
Quite high leakage

Usually polarized
Expensive
Poor stability
Poor accuracy
49

by Erik Barnes
that no current flows into the op amp (infinite input

impedance); both inputs will be at about the same potential
(negative feedback and high open-loop gain)).
CURRENT FEEDBACK AMPLIFIERSI
With
Vo = (VIN+ VIN)A(s)
and
V IN =
A. Before looking at any circuits, lets define voltage feedback,

current feedback, and transimpedance amplifier. Voltage
feedback, as the name implies, refers to a closed-loop
configuration in which the error signal is in the form of a
voltage. Traditional op amps use voltage feedback, that is, their
inputs will respond to voltage changes and produce a
corresponding output voltage. Current feedback refers to any
closed-loop configuration in which the error signal used for
feedback is in the form of a current. A current feedback op
amp responds to an error current at one of its input terminals,
rather than an error voltage, and produces a corresponding
output voltage. Notice that both open-loop architectures
achieve the same closed-loop result: zero differential input
voltage, and zero input current. The ideal voltage feedback
amplifier has high-impedance inputs, resulting in zero input
current, and uses voltage feedback to maintain zero input
voltage. Conversely, the current feedback op amp has a low
impedance input, resulting in zero input voltage, and uses
current feedback to maintain zero input current.
The transfer function of a transimpedance amplifier is expressed
as a voltage output with respect to a current input. As the
function implies, the open-loop gain, vO/iIN, is expressed in
ohms. Hence a current-feedback op amp can be referred to as
a transimpedance amplifier. Its interesting to note that the
closed-loop relationship of a voltage-feedback op amp circuit
can also be configured as a transimpedance, by driving its
dynamically low-impedance summing node with current (e.g.,
from a photodiode), and thus generating a voltage output equal
to that input current multiplied by the feedback resistance.
Even more interesting, since ideally any op amp application
can be implemented with either voltage or current feedback,
this same I-V converter can be implemented with a current
feedback op amp. When using the term transimpedance amplifier,
understand the difference between the specific currentfeedback op amp architecture, and any closed-loop I-V
converter circuit that acts like transimpedance.
Lets take a look at the simplified model of a voltage feedback
amplifier. The noninverting gain configuration amplifies the
difference voltage, (VIN+ VIN), by the open loop gain A(s)
and feeds a portion of the output back to the inverting input
through the voltage divider consisting of RF and RG. To derive
the closed-loop transfer function of this circuit, Vo/VIN+, assume
A(s)
VIN+
RG
50
RF
GAIN dB
VIN
VOLTAGE FEEDBACK
AMPLIFIER, NONINVERTING
GAIN CONNECTION
LG
substitute and simplify to get:
Vo
R
= 1 + F
VIN
R
BODE PLOT
NG
fCL
LOG f
where LG =
1
1+
LG
A(s)
R
1+ F
RG
The closed-loop bandwidth is the frequency at which the loop

gain, LG, magnitude drops to unity (0 dB). The term,
1 + R F/R G, is called the noise gain of the circuit; for the
noninverting case, it is also the signal gain. Graphically, the
closed-loop bandwidth is found at the intersection of the openloop gain, A(s), and the noise gain, NG, in the Bod plot.
High noise gains will reduce the loop gain, and thereby the
closed-loop bandwidth. If A(s) rolls off at 20 dB/decade, the
gain-bandwidth product of the amplifier will be constant. Thus,
an increase in closed-loop gain of 20 dB will reduce the closedloop bandwidth by one decade.
Z(s)
VIN+
+1
RO
VIN
VO
Z(s)
LG
BODE PLOT
R F+R O NG
I ERR
RG
RF
LOG f
CURRENT FEEDBACK
AMPLIFIER, NONINVERTING
GAIN CONNECTION
RF
fCL
Consider now a simplified model for a current-feedback

amplifier. The noninverting input is the high-impedance input
of a unity gain buffer, and the inverting input is its lowimpedance output terminal. The buffer allows an error current
to flow in or out of the inverting input, and the unity gain
forces the inverting input to track the noninverting input. The
error current is mirrored to a high impedance node, where it is
converted to a voltage and buffered at the output. The highimpedance node is a frequency-dependent impedance, Z(s),
analogous to the open-loop gain of a voltage feedback amplifier;
it has a high dc value and rolls off at 20 dB/decade.
The closed-loop transfer function is found by summing the
currents at the V IN node, while the buffer maintains
VIN+ = VIN. If we assume, for the moment, that the buffer has
zero output resistance, then Ro = 0
Vo V IN V IN
+
+ Ierr = 0 and Ierr =V 0 / Z (s )
RF
RG
Substituting, and solving for Vo/VIN+
Vo
R
= 1+ F
V IN +
RG
VO
A(s)
RG
V
RG + RF o
LOG
Q. Im not sure I understand how current-feedback amplifiers work as

compared with regular op amps. Ive heard that their bandwidth is
constant regardless of gain. How does that work? Are they the same
as transimpedance amplifiers?
1
1
1+
LG
, where LG =
Z (s)
RF
The closed-loop transfer function for the current feedback

amplifier is the same as for the voltage feedback amplifier, but
the loop gain (1/LG) expression now depends only on RF, the

feedback transresistanceand not (1 + RF/RG). Thus, the
closed-loop bandwidth of a current feedback amplifier will vary
with the value of RF, but not with the noise gain, 1 + RF/RG.
The intersection of RF and Z(s) determines the loop gain, and
thus the closed-loop bandwidth of the circuit (see Bod plot).
Clearly the gain-bandwidth product is not constantan
advantage of current feedback.
In practice, the input buffers non-ideal output resistance will
be typically about 20 to 40 , which will modify the feedback
transresistance. The two input voltages will not be exactly equal.
Making the substitution into the previous equations with
VIN = VIN+ IerrRo, and solving for Vo/VIN+ yields:
Vo
R
= 1+ F
V IN
RG
1
1+
1
LG
, where LG =
Z (s)
R
RF + Ro 1+ F
RG
The additional term in the feedback transresistance means that

the loop gain will actually depend somewhat on the closedloop gain of the circuit. At low gains, RF dominates, but at
higher gains, the second term will increase and reduce the loop
gain, thus reducing the closed-loop bandwidth.
It should be clear that shorting the output back to the inverting
input with RG open (as in a voltage follower) will force the
loop gain to get very large. With a voltage feedback amplifier,
maximum feedback occurs when feeding back the entire output
voltage, but the current feedbacks limit is a short-circuit
current. The lower the resistance, the higher the current will
be. Graphically, RF = 0 will give a higher-frequency intersection
of Z(s) and the feedback transresistancein the region of
higher-order poles. As with a voltage feedback amplifier, higherorder poles of Z(s) will cause greater phase shift at higher
frequencies, resulting in instability with phase shifts > 180
degrees. Because the optimum value of RF will vary with closedloop gain, the Bode plot is useful in determining the bandwidth
and phase margin for various gains. A higher closed-loop
bandwidth can be obtained at the expense of a lower phase
margin, resulting in peaking in the frequency domain, and
overshoot and ringing in the time domain. Current-feedback
device data sheets will list specific optimum values of RF for
various gain settings.
Current feedback amplifiers have excellent slew-rate
capabilities. While it is possible to design a voltage-feedback
amplifier with high slew rate, the current-feedback architecture
is inherently faster. A traditional voltage-feedback amplifier,
lightly loaded, has a slew rate limited by the current available
to charge and discharge the internal compensation capacitance.
When the input is subjected to a large transient, the input stage
will saturate and only its tail current is available to charge or
discharge the compensation node. With a current-feedback
amplifier, the low-impedance input allows higher transient
currents to flow into the amplifier as needed. The internal
current mirrors convey this input current to the compensation
node, allowing fast charging and dischargingtheoretically,
in proportion to input step size. A faster slew rate will result in
a quicker rise time, lower slew-induced distortion and
nonlinearity, and a wider large-signal frequency response. The
actual slew rate will be limited by saturation of the current
mirrors, which can occur at 10 to 15 mA, and the slew-rate
limit of the input and output buffers.
Q5
Q1
Q3
Q2
Q4
VIN+
Q7
Q6
VIN
Z(S)
+1
Q8
VO
SIMPLIFIED CURRENT FEEDBACK
AMPLIFIER, ILLUSTRATING INPUT
STAGE AND CURRENT MIRRORS.
Q. What about dc accuracy?

A. The dc gain accuracy of a current feedback amplifier can be
calculated from its transfer function, just as with a voltage
feedback amplifier; it is essentially the ratio of the internal
transresistance to the feedback transresistance. Using a typical
transresistance of 1 M, a feedback resistor of 1 k, and an
Ro of 40 ohms, the gain error at unity gain is about 0.1%. At
higher gains, it degrades significantly. Current-feedback
amplifiers are rarely used for high gains, particularly when
absolute gain accuracy is required.
For many applications, though, the settling characteristics are
of more importance than gain accuracy. Although current
feedback amplifiers have very fast rise times, many data sheets
will only show settling times to 0.1%, because of thermal
settling tails a major contributor to lack of settling precision.
Consider the complementary input buffer above, in which the
VIN terminal is offset from the VIN+ terminal by the difference
in VBE between Q1 and Q3. When the input is at zero, the two
VBEs should be matched, and the offset will be small from VIN+
to VIN. A positive step input applied to VIN+ will cause a
reduction in the VCE of Q3, decreasing its power dissipation,
thus increasing its VBE. Diode-connected Q1 does not exhibit
a VCE change, so its VBE will not change. Now a different offset
exists between the two inputs, reducing the accuracy. The same
effect can occur in the current mirror, where a step change at
the high-impedance node changes the VCE, and thus the VBE,
of Q6, but not of Q5. The change in VBE causes a current error
referred back to VIN, whichmultiplied by RFwill result in
an output offset error. Power dissipation of each transistor
occurs in an area that is too small to achieve thermal coupling
between devices. Thermal errors in the input stage can be
reduced in applications that use the amplifier in the inverting
configuration, eliminating the common-mode input voltage.
Q. In what conditions are thermal tails a problem?
A. It depends on the frequencies and waveforms involved.
Thermal tails do not occur instantaneously; the thermal
coefficient of the transistors (which is process dependent) will
determine the time it takes for the temperature change to occur
and alter parametersand then recover. Amplifiers fabricated
on the Analog Devices high-speed complementary bipolar (CB)
process, for example, dont exhibit significant thermal tails for
input frequencies above a few kHz, because the input signal is
changing too fast. Communications systems are generally more
concerned with spectral performance, so additional gain errors
that might be introduced by thermal tails are not important.
Step waveforms, such as those found in imaging applications,
can be adversely affected by thermal tails when dc levels change.
For these applications, current-feedback amplifiers may not
offer adequate settling accuracy.
Part II will consider common application circuits using current-feedback
b
amplifiers and view their operation in more detail.
51

by Erik Barnes
CURRENT FEEDBACK AMPLIFIERSII
Part I (Analog Dialogue 30-3) covers basic operation of the
current-feedback (CF) op-amp. This second part addresses
frequently asked questions about common applications.
Q. I now have better understanding of how a current feedback
op-amp works, but Im still confused when it comes to
applying one in a circuit. Does the low inverting input
impedance mean I cant use the inverting gain configuration?
A. Remember that the inverting mode of operation works
because of the low-impedance node created at the inverting
input. The summing junction of a voltage-feedback (VF)
amplifier is characterized by a low input impedance after the
feedback loop has settled. A current feedback op amp will, in
fact, operate very well in the inverting configuration because
of its inherently low inverting-input impedance, holding the
summing node at ground, even before the feedback loop has
settled. CF types dont have the voltage spikes that occur at
the summing node of voltage feedback op amps in highspeed applications. You may also recall that advantages of
the inverting configuration include maximizing input slew
rate and reducing thermal settling errors.
Q. So this means I can use a current feedback op-amp as a
current-to-voltage converter, right?
A. Yes, they can be configured as I-to-V converters. But there are
limitations: the amplifiers bandwidth varies directly with the
value of feedback resistance, and the inverting input current
noise tends to be quite high. When amplifying low level
currents, higher feedback resistance means higher signal-to(resistor-) noise ratio, because signal gain will increase
proportionally, while resistor noise goes as R. Doubling the
feedback resistance doubles the signal gain and increases
resistor noise by a only factor of 1.4; unfortunately the
contribution from current noise is doubled, and, with a current
feedback op amp, the signal bandwidth is halved. Thus the
higher current noise of CF op amps may preclude their use in
many photodiode-type applications. When noise is less critical,
select the feedback resistor based on bandwidth requirements;
use a second stage to add gain.
Q. I did notice the current noise is rather high in current feedback
amplifiers. So will this limit the applications in which I can use
them?
A. Yes, the inverting input current noise tends to be higher in CF
op amps, around 20 to 30 pA/Hz. However, the input voltage
noise tends to be quite low when compared with similar
voltage feedback parts, typically less than 2 nV/Hz, and
the feedback resistance will also be low, usually under 1 k.
At a gain of 1, the dominant source of noise will be the
inverting-input noise current flowing through the feedback
resistor. An input noise current of 20 pA/Hz and an RF of
750 yields 15 nV/Hz as the dominant noise source at the
output. But as the gain of the circuit is increased (by reducing
input resistance), the output noise due to input current noise
will not increase, and the amplifiers input voltage noise
will become the dominant factor. At a gain, of say, 10, the
contribution from the input noise current is only 1.5 nV/Hz
52
Q.
A.
Q.
A.
when referred to the input; added to the input voltage noise of

the amplifier in RSS fashion, this gives an input-referred
noise voltage of only 2.5 nV/Hz (neglecting resistor
noise). Used thus, the CF op amp becomes attractive for a low
noise application.
What about using the classic four-resistor differential
configuration? Arent the two inputs unbalanced and
therefore not suitable for this type of circuit?
Im glad you asked; this is a common misconception of CF opamps. True, the inputs are not matched, but the transfer
function for the ideal difference amplifier will still work out
the same. What about the unbalanced inputs? At lower
frequencies, the four-resistor differential amplifiers CMR is
limited by the matching of the external resistor ratios, with
0.1% matching yielding about 66 dB. At higher frequencies,
what matters is the matching of time constants formed by the
input impedances. High-speed voltage-feedback op amps
usually have pretty well matched input capacitances,
achieving CMR of about 60 dB at 1 MHz. Because the CF
amplifiers input stage is unbalanced, the capacitances may
not be well matched. This means that small external resistors
(100 to 200 ) must be used on the noninverting input of
some amplifiers to minimize the mismatch in time constants.
If careful attention is given to resistor selection, a CF op-amp
can yield high frequency CMR comparable to a VF op amp. If
higher performance is needed, the best choice would be a
monolithic high speed difference amplifier, such as the
AD830. Requiring no resistor matching , it has a
CMR > 75 dB at 1 MHz and about 53 dB at 10 MHz.
What about trimming the amplifiers bandwidth with a
feedback capacitor? Will the low impedance at the inverting
input make the current feedback op amp less sensitive to
shunt capacitance at this node? How about capacitive loads?
First consider a capacitor in the feedback path. With a voltage
feedback op amp, a pole is created in the noise gain, but a
pole and a zero occur in the feedback transresistance of a
current feedback op amp, as shown in the figure below.
Remember that the phase margin at the intersection of the
feedback transresistance and the open loop transimpedance
will determine closed-loop stability. Feedback
transresistance for a capacitance, CF, in parallel with RF, is
given by
sCF RF RG RO
1+
RF RF RG + RF RO + RG RO
Z F (s) = RF + RO 1+
1+ sCF RF
RG
The pole occurs at 1/2RFCF, and the zero occurs higher in

frequency at 1/[2(RF||RG||RO)CF]. If the intersection of ZF
and ZOL occurs too high in frequency, instability may result
from excessive open loop phase shift. If RF , as with an
integrator circuit, the pole occurs at a low frequency and very
little resistance exists at higher frequencies to limit the loop
gain. A CF integrator can be stabilized by a resistor in series
with the integrating capacitor to limit loop gain at higher
frequencies. Filter topologies that use reactive feedback, such
as multiple feedback types, are not suitable for CF op amps;
but Sallen-Key filters, where the op amp is used as a fixedgain block, are feasible. In general, it is not desirable to add
capacitance across RF of a CF op amp.
VIN+
LOG
+
+1
ZOL(S)
VO
RO
RF
RG
RF
RG
RF + RO 1 +
ZF(S)
LOG f
CF
fP
fZ
Another issue to consider is the effect of shunt capacitance at

the inverting input. Recall that with a voltage feedback
amplifier, such capacitance creates a zero in the noise gain,
increasing the rate of closure between the noise gain and open
loop gain, generating excessive phase shift that can lead to
instability if not compensated for. The same effect occurs with
a current feedback op amp, but the problem may be less
pronounced. Writing the expression for the feedback
transresistance with the addition of CIN:
R
sCIN RF RG RO
Z F (s) = RF + RO 1+ F 1+
R
R
R
+
R
R
+
R
R
G
F G
F O
G O
A zero occurs at 1/[2(RF||RG||RO)CIN], shown in the next

figure (fZ1). This zero will cause the same trouble as with a VF
amplifier, but the corner frequency of the zero tends to be
higher in frequency because of the inherently low input
impedance at the inverting input. Consider a wideband voltage
feedback op amp with R F = 750 , R G = 750 , and
CIN = 10 pF. The zero occurs at 1/[2(RFiRG)CIN], roughly
40 MHz, while a current feedback op-amp in the same
configuration with an RO of 40 will push the zero out to
about 400 MHz. Assuming a unity gain bandwidth of 500 MHz
for both amplifiers, the VF amplifier will require a feedback
capacitor for compensation, reducing the effect of CIN, but also
reducing the signal bandwidth. The CF device will certainly
see some additional phase shift from the zero, but not as much
because the break point is a decade higher in frequency. Signal
bandwidth will be greater, and compensation may only be
necessary if in-band flatness or optimum pulse response is
required. The response can be tweaked by adding a small
capacitor in parallel with RF to reduce the rate of closure
between ZF and ZOL. To ensure at least 45 of phase margin,
the feedback capacitor should be chosen to place a pole in the
feedback transresistance where the intersection of ZF and ZOL
occurs, shown here (fP). Dont forget the effects of the higher
frequency zero due to the feedback capacitor (fZ2).
VIN+
LOG
+
+1
RG
WITH
WITH
CIN CIN AND CF
RO
RF
CIN
ZOL(S)
VO
CF
RF + RO 1 +
ZF(S)
RF
RG
LOG f
fZ1
fP
fZ2
Load capacitance presents the same problem with a current

feedback amplifier as it does with a voltage feedback amplifier:
increased phase shift of the error signal, resulting in degradation
of phase margin and possible instability. There are several welldocumented circuit techniques for dealing with capacitive
loads, but the most popular for high speed amplifiers is a resistor
in series with the output of the amplifier (as shown below).
With the resistor outside the feedback loop, but in series with
the load capacitance, the amplifier doesnt directly drive a
purely capacitive load. A CF op amp also gives the option of
increasing R F to reduce the loop gain. Regardless of the
approach taken, there will always be a penalty in bandwidth,
slew rate, and settling time. Its best to experimentally optimize
a particular amplifier circuit, depending on the desired
characteristics, e.g., fastest rise time, fastest settling to a
specified accuracy, minimum overshoot, or passband flatness.
RS
VIN+
CL
RG
RL
RF
Q. Why dont any of your current feedback amplifiers offer true singlesupply operation, allowing signal swings to one or both rails?
A. This is one area where the VF topology is still favored for
several reasons. Amplifiers designed to deliver good current
drive and to swing close to the rails usually use commonemitter output stages, rather than the usual emitter followers.
Common emitters allow the output to swing to the supply
rail minus the output transistors V CE saturation voltage.
With a given fabrication process, this type of output stage
does not offer as much speed as emitter followers, due in
part to the increased circuit complexity and inherently higher
output impedance. Because CF op amps are specifically
developed for the highest speed and output current, they
feature emitter follower output stages.
With higher speed processes, such as ADIs XFCB (extra-fast
complementary bipolar), it has been possible to design a
common-emitter output stage with 160-MHz bandwidth and
160-V/s slew rate, powered from a single 5-volt supply
(AD8041). The amplifier uses voltage feedback, but even if,
somehow, current feedback had been used, speed would still
be limited by the output stage. Other XFCB amplifiers, with
emitter-follower output stages (VF or CF), are much faster
than the AD8041. In addition, single-supply input stages use
PNP differential pairs to allow the common-mode input range
to extend down to the lower supply rail (usually ground). To
design such an input stage for CF is a major challenge, not yet
met at this writing.
Nevertheless, CF op amps can be used in single-supply
applications. Analog Devices offers many amplifiers that are
specified for +5- or even +3-volt operation. What must be kept
in mind is that the parts operate well off a single supply if the
application remains within the allowable input and output voltage
ranges. This calls for level shifting or ac coupling and biasing to
the proper range, but this is already a requirement in most
single-supply systems. If the system must operate to one or
both rails, or if the maximum amount of headroom is demanded
in ac-coupled applications, a current feedback op amp may
simply not be the best choice. Another factor is the rail-to-rail
output swing specifications when driving heavy loads. Many
so-called rail-to-rail parts dont even come close to the rails
when driving back- terminated 50- or 75- cables, because of
the increase in VCESAT as output current increases. If you really
need true rail-to-rail performance, you dont want or need a
current feedback op amp; if you need highest speed and output
b
current, this is where CF op amps excel.
53
INDEX
Accuracy enhancement . . . . . . . . . . . . . . . . . . . . . . . . 36, 37
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 38, 39
A/D converters
buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 21
input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
noise and missing codes . . . . . . . . . . . . . . . . . . . . . . . . 12
oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38
power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
references, internal vs. external . . . . . . . . . . . . . . . . . . . 19
serial, interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
sigma-delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38
trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Amplifiers
bias and offset current . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
differential, long-tailed pair . . . . . . . . . . . . . . . . . . . . . . . 8
distortion specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25
drift, long-term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
feedback, voltage vs. current . . . . . . . . . . . . . . . . . . 50, 51
JFET input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
multiplicity of types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
noise (see Noise) . . . . . . . . . . . . . . . . . . . . . 10, 11, 12, 13
phase inversion error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
rectification in input stage . . . . . . . . . . . . . . . . . . . . 26, 27
signal contamination . . . . . . . . . . . . . . . . . . . . . . . . 26, 27
superbeta input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
local vs. system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
sigma delta converters . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Comparators
autozeroed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
hysteresis to stabilize . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
oscillation in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-53
and single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bias current,
and offset current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Faraday shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Feedback, voltage vs. current . . . . . . . . . . . . . . . . . . . . 50-53
Feedback capacitors, in current-feedback amplifiers . . 52-53
Filters
antialiasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 33
Floating inputs, need to tie . . . . . . . . . . . . . . . . . . . . . . . . . 1
F/V converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-49
comparators, bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . 6
decoupling, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 15
loading on references . . . . . . . . . . . . . . . . . . . . . . . . . . 19
parasitic effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-47
dielectric absorption . . . . . . . . . . . . . . . . . . . . . . . . . 47
dissipation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
equivalent series inductance, (ESL) . . . . . . . . . . . . . . 46
equivalent series resistance, (ESR) . . . . . . . . . . . . . . 46
leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
strays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-48
IC packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PC boards . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 47, 48
switched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 32
types, comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
conversion clock vs. sample clock . . . . . . . . . . . . . . . . . 22
D/A converters
accuracy vs. resolution . . . . . . . . . . . . . . . . . . . . . . . . . 39
current-steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
update rate vs. settling time . . . . . . . . . . . . . . . . . . . . . . 39
voltage-switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 34
Decoupling, supply . . . . . . . . . . . . . . . . . . . . . . 6, 14, 15, 47
Delta-sigma (see Sigma-delta)
Distortion
harmonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 24
intercept points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 25
intermodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 25
reduction with dither . . . . . . . . . . . . . . . . . . . . . . . 35, 36
root sum-of-squares . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25
Gain-bandwidth, in voltage- and current-feedback

amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 51
Gain, trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Grounding
analog vs. digital grounds . . . . . . . . . . . . . . . . . 20, 21, 45
factor in comparator oscillations . . . . . . . . . . . . . . . . . . . 6
mixed-signal chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hysteresis, comparators . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 7
Idle tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 31
Inductance, PC boards . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
low-frequency effects of . . . . . . . . . . . . . . . . . . 26, 27, 28
testing for susceptibility to . . . . . . . . . . . . . . . . 26, 27, 28
Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Log circuits, compensation resistors . . . . . . . . . . . . . . . . . . 1
Mixed-signal circuits
grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 21, 45
power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 45
Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Multiplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
sigma delta converter input . . . . . . . . . . . . . . . . . . . . . . 33
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11, 12, 13
1/f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 13
and dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
and long term drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
and missing codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
gain, noise- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 50
Gaussian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11, 12
in sigma-delta ADCs . . . . . . . . . . . . . . . . . . 29, 30, 35-38
interference . . . . . . . . . . . . . . . . . . . . . . . . . 10, 26, 27, 28
Johnson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 37, 38
phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
popcorn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 36, 39
random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11
root sum-of-squares (RSS) . . . . . . . . . . . . . . . . . . . 10, 29
Schottky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
vs. conductor noise . . . . . . . . . . . . . . . . . . . . . . . . . . 13
source impedance effects . . . . . . . . . . . . . . . . . . . . . . . . 11
temperature effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Nonlinearity, differential . . . . . . . . . . . . . . . . . . . . . . . . . . 39
capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
sink currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19, 22
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19
Resistors
ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
log temperature compensation . . . . . . . . . . . . . . . . . . . . 1
non-ideal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PC tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
temperature coefficients . . . . . . . . . . . . . . . . . . . . . . . . 15
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Root sum-of-squares (RSS)
distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
log quantities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32, 38
noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 29
Seminars and support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial converter interfacing . . . . . . . . . . . . . . . . . . . . . 42-45
asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 40, 41
thermal tails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 51
Sigma-delta converters . . . . . . . . . . . . . . . . . . . . . . . . . 29-38
antialiasing filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 34
idle tones in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 31
multiple output codes . . . . . . . . . . . . . . . . . . . . . . . 34, 35
practice issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 34
Signal-to-noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 38
Slew rate, in current-feedback amplifiers, . . . . . . . . . . . . . 51
Thermal tails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 51
Transimpedance amplifiers . . . . . . . . . . . . . . . . . . . . . 50-53
Trim circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
vs. system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
D/A converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
V/F converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Offset trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Optoisolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Oscillations, parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 15
Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38, 39
Unused channel, grounding . . . . . . . . . . . . . . . . . . . . . . . . . 1

Update rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Powerup problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Printed circuit boards
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 47, 48
ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 17
inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
track resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VBE, logarithmic relationship . . . . . . . . . . . . . . . . . . . . . . . . 1

V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
capacitors for . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
frequency to voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
interference effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
synchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-53
References
bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19
buried Zener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
vi
Wire, non-ideal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error processing S S I file
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by Steve Guinta
RES IS TANCE
Q. Id like to understand the differences between available resistor types and how to select the right one for a
particular application.
A. Sure, lets talk first about the familiar discrete or axiallead type resistors were used to working with in the lab;
then well compare cost and performance tradeoffs of the discretes and thin or thickfilm networks. Axial Lead
Types: The three most common types of axiallead resistors well talk about are carbon composition, or carbon film,
metal film and wirewound:
carbon compositionor carbon filmtype resistors are used in generalpurpose circuits where initial accuracy and
stability with variations of temperature arent deemed critical. Typical applications include their use as a collector or
emitter load, in transistor/FET biasing networks, as a discharge path for charged capacitors, and as pullup and/or
pulldown elements in digital logic circuits.
Carbontype resistors are assigned a series of standard values (Table 1) in a quasilogarithmic sequence, from 1 ohm to
22 megohms, with tolerances from 2% (carbon film) to 5% up to 20% (carbon composition). Power dissipation
ratings range from 1/8 watt up to 2 watts. The 1/4watt and 1/2watt, 5% and 10% types tend to be the most popular.
Carbontype resistors have a poor temperature coefficient (typically 5, 000 ppm/C); so they are not well suited for
precision applications requiring little resistance change over temperature, but they are inexpensiveas little as 3 cents
[USD 0.03] each in 1, 000 quantities.
Table 1 lists a decade (10:1 range) of standard resistance values for 2% and 5% tolerances, spaced 10% apart. The
smaller subset in lightface denote the only values available with 10% or 20% tolerances; they are spaced 20% apart.
Table 1. S tandard resistor values: 2%, 5% and 10%
10 16 27 43 68
11 18 30 47 75
12 20 33 51 82
13 22 36 56 91
15 24 39 62 100
Carbontype resistors use colorcoded bands to identify the resistors ohmic value and tolerance:
Table 2. Color code for carbontype resistors

digit
color
multiple # of zeros tolerance
silver
0.01
10%
gold
0.10
5%
black
brown
10
red
100
2%
orange
1k
yellow
10 k
green
100 k
blue
1M
violet
10 M
gray
white
none
20%
Metal film resistors are chosen for precision applications where initial accuracy, low temperature coefficient, and
lower noise are required. M etal film resistors are generally composed of Nichrome, tin oxide or tantalum nitride, and
are available in either a hermetically sealed or molded phenolic body. Typical applications include bridge circuits, RC
oscillators and active filters. Initial accuracies range from 0.1 to 1.0 %, with temperature coefficients ranging between
10 and 100 ppm/C. Standard values range from 10.0 ohms to 301 kohms in discrete increments of 2% (for 0.5% and
1% rated tolerances).
Table 3. S tandard values for filmtype resistors
1.00 1.29 1.68 2.17 2.81 3.64 4.70 6.08 7.87
1.02 1.32 1.71 2.22 2.87 3.71 4.80 6.21 8.03
1.04 1.35 1.74 2.26 2.92 3.78 4.89 6.33 8.19
1.06 1.37 1.78 2.31 2.98 3.86 4.99 6.46 8.35
1.08 1.40 1.82 2.35 3.04 3.94 5.09 6.59 8.52
1.10 1.43 1.85 2.40 3.10 4.01 5.19 6.72 8.69
1.13 1.46 1.89 2.45 3.17 4.09 5.30 6.85 8.86
1.15 1.49 1.93 2.50 3.23 4.18 5.40 6.99 9.04
1.17 1.52 1.96 2.55 3.29 4.26 5.51 7.13 9.22
1.20 1.55 2.00 2.60 3.36 4.34 5.62 7.27 9.41
1.22 1.58 2.04 2.65 3.43 4.43 5.73 7.42 9.59
1.24 1.61 2.09 2.70 3.49 4.52 5.85 7.56 9.79
1.27 1.64 2.13 2.76 3.56 4.61 5.96 7.72 9.98
M etal film resistors use a 4 digit numbering sequence to identify the resistor value instead of the color band scheme
used for carbon types:
Wirewound precision resistors are extremely accurate and stable (0.05%, <10 ppm/C); they are used in demanding
applications, such as tuning networks and precision attenuator circuits. Typical resistance values run from 0.1 ohms
to 1.2 M ohms.
High Frequency Effects: Unlike its ideal counterpart, a real resistor, like a real capacitor (Analog Dialogue 302), suffers from parasitics. (Actually, any twoterminal element may look like a resistor, capacitor, inductor, or
damped resonant circuit, depending on the frequency its tested at.)
Factors such as resistor base material and the ratio of length to crosssectional area determine the extent to which the
parasitic L and C affect the constancy of a resistors effective dc resistance at high frequencies. Film type resistors
generally have excellent highfrequency response; the best maintain their accuracy to about 100 M Hz. Carbon types
are useful to about 1 M Hz. Wirewound resistors have the highest inductance, and hence the poorest frequency
response. Even if they are noninductively wound, they tend to have high capacitance and are likely to be unsuitable
for use above 50 kHz.
Q. What about temperature effects? Should I always use resistors with the lowest temperature coefficients (TCRs)?
A. Not necessarily. A lot depends on the application. For the single resistor shown here, measuring current in a loop,
the current produces a voltage across the resistor equal to I x R. In this application, the absolute accuracy of
resistance at any temperature would be critical to the accuracy of the current measurement, so a resistor with a very
low TC would be used.
A different example is the behavior of gainsetting resistors in a gainof100 op amp circuit, shown below. In this type
of application, where gain accuracy depends on the ratio of resistances (a ratiometric configuration), resistance
matching, and the tracking of the resistance temperature coefficients (TCRs), is more critical than absolute accuracy.
Here are a couple of examples that make the point.
1. Assume both resistors have an actual TC of 100 ppm/C (i.e., 0.01%/C). The resistance following a temperature
change, T, is
R = R0(1+ TC
T)
For a 10C temperature rise, both Rf and Ri increase by 0.01%/C x 10C = 0.1%. Op amp gains are [to a very good
approximation] 1 + RF /RI. Since both resistance values, though quite different (99:1), have increased by the same
percentage, their ratiohence the gainis unchanged. Note that the gain accuracy depends just on the resistance ratio,
independently of the absolute values.
2. Assume that RI has a TC of 100 ppm/C, but RF s TC is only 75 ppm/C. For a 10C change, RI increases by
0.1% to 1.001 times its initial value, and RF increases by 0.075% to 1.00075 times its initial value. The new value of
gain is
(1.00075 RF )/(1.001 RI) = 0.99975 RF /RI
For an ambient temperature change of 10C, the amplifier circuits gain has decreased by 0.025% (equivalent to 1
LSB in a 12bit system). Another parameter thats not often understood is the selfheating effect in a resistor.
Q. Whats that?
A. Selfheating causes a change in resistance because of the increase in temperature when the dissipated power
increases. M ost manufacturers data sheets will include a specification called thermal resistance or thermal
derating, expressed in degrees C per watt (C/W). For a 1/4watt resistor of typical size, the thermal resistance is
about 125C/W. Lets apply this to the example of the above op amp circuit for fullscale input:
Power dissipated by RI is
E2/R = (100 mV)2/100 ohms = 100 W, leading to a temperature change of 100 W x 125C/W = 0.0125C, and a
negligible 1ppm resistance change (0.00012%).
Power dissipated by RF is
E2/R = (9.9 V)2/9900 ohms = 9.9 mW, leading to a temperature change of 0.0099 W x 125C/W = 1.24C, and a
resistance change of 0.0124%, which translates directly into a 0.012% gain change.
Thermocouple Effects: Wirewound precision resistors have another problem. The junction of the resistance wire
and the resistor lead forms a thermocouple which has a thermoelectric EM F of 42 V/C for the standard Alloy
180/Nichrome junction of an ordinary wirewound resistor. If a resistor is chosen with the [more expensive]
copper/nichrome junction, the value is 2.5 V/C. (Alloy 180 is the standard component lead alloy of 77% copper
and 23% nickel.)
Such thermocouple effects are unimportant in ac applications, and they cancel out when both ends of the resistor are
at the same temperature; however if one end is warmer than the other, either because of the power being dissipated in
the resistor, or its location with respect to heat sources, the net thermoelectric EM F will introduce an erroneous dc
voltage into the circuit. With an ordinary wirewound resistor, a temperature differential of only 4C will introduce a
dc error of 168 Vwhich is greater than 1 LSB in a 10V/16bit system!
This problem can be fixed by mounting wirewound resistors so as to insure that temperature differentials are
minimized. This may be done by keeping both leads of equal length, to equalize thermal conduction through them, by
insuring that any airflow (whether forced or natural convection) is normal to the resistor body, and by taking care
that both ends of the resistor are at the same thermal distance (i.e., receive equal heat flow) from any heat source on
the PC board.
Q. What are the differences between thinfilm and thickfilm networks, and what are the
advantages/disadvantages of using a resistor network over discrete parts?
A. Besides the obvious advantage of taking up considerably less real estate, resistor networkswhether as a separate
entity, or part of a monolithic ICoffer the advantages of high accuracy via laser trimming, tight TC matching, and
good temperature tracking. Typical applications for discrete networks are in precision attenuators and gain setting
stages. Thin film networks are also used in the design of monolithic (IC) and hybrid instrumentation amplifiers, and
in CM OS D/A and A/D converters that employ an R2R Ladder network topology.
Thick film resistors are the lowestcost typethey have fair matching (<0.1%), but poor TC performance (<100
ppm/C) and tracking (<10 ppm/C).They are produced by screening or electroplating the resistive element onto a
substrate material, such as glass or ceramic.
Thin film networks are moderately priced and offer good matching (0.01%), plus good TC (<100 ppm/C) and
tracking (<10 ppm/C). All are laser trimmable. Thin film networks are manufactured using vapor deposition.
Tables 4 compares the advantages/disadvantages of a thick film and several types of thinfilm resistor networks. Table
5 compares substrate materials.
Table 4. Resistor Networks
Type
Advantages
Disadvantages
Thick film
Low cost
Fair matching (0.1%)
High power
Poor TC (>100 ppm/C)
Laser-trimmable
Poor tracking TC
Readily available
(10 ppm/C)
Good matching (<0.01%)
Delicate
Good TC (<100 ppm/C)
Often large geometry
Good tracking TC (2
ppm/C)
Low power
Thin film on glass
M oderate cost
Laser-trimmable
Low capacitance
Thin film on ceramic

Good tracking TC (2
ppm/C)
M oderate cost
Laser-trimmable
Low capacitance
Suitable for hybrid IC
substrate
Thin film on silicon

Often large geometry
Good tracking TC (2
ppm/C)
M oderate cost
Laser-trimmable
Low capacitance
substrate
Table 5. S ubstrate Materials

S ubstrate
Advantages
Disadvantages
Glass
Low capacitance
Delicate
Low power
Large geometry
Ceramic
Low capacitance
Large geometry

substrate
Silicon
Sapphire
Suitable for monolithic
Low power
construction
Capacitance to substrate
Low capacitance
Low power
Higher cost
In the example of the IC instrumentation amplifier shown below, tight matching between resistors R1R1', R2R2', R3R3' insures high commonmode rejection (as much as 120 dB, dc to 60 Hz). While it is possible to achieve higher
commonmode rejection using discrete op amps and resistors, the arduous task of matching the resistor elements is
undesirable in a production environment.
M atching, rather than absolute accuracy, is also important in R2R ladder networks (including the feedback resistor)
of the type used in CM OS D/A converters. To achieve nbit performance, the resistors have to be matched to within
1/2n, which is easily achieved through laser trimming. Absolute accuracy error, however, can be as much as 20%.
Shown here is a typical R2R ladder network used in a CM OS digital analog converter.
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Ask The Applications Engineer-25

by Grayson King
OP AMPS DRIVING CAPACITIVE LOADS
Q. Why would I want to drive a capacitive load?
A. It's usually not a matter of choice. In most cases, the load capacitance is not from a capacitor you've added
intentionally; most often it's an unwanted parasitic, such as the capacitance of a length of coaxial cable. However,
situations do arise where it's desirable to decouple a dc voltage at the output of an op amp-for example,when an op
amp is used to invert a reference voltage and drive a dynamic load. In this case, you might want to place bypass
capacitors directly on the output of an op amp. Either way, a capacitive load affects the op amp's performance.
Q. How does capacitive loading affect op amp performance?
A. To put it simply, it can turn your amplifier into an oscillator. Here's how:
Op amps have an inherent output resistance, Ro, which, in conjunction with a capacitive load, forms an additional
pole in the amplifier's transfer function. As the Bode plot shows, at each pole the amplitude slope becomes more
negative by 20 dB/ decade. Notice how each pole adds as much as -90 of phase shift. We can view instability from
either of two perspectives. Looking at amplitude response on the log plot,circuit instability occurs when the sum of
open-loop gain and feedback attenuation is greater than unity. Similarly, looking at phase response, an op amp will
tend to oscillate at a frequency where loop phase shift exceeds -180, if this frequency is below the closed-loop
bandwidth. The closed-loop bandwidth of a voltage-feedback op amp circuit is equal to the op amp's bandwidth
product (GBP, or unity-gain frequency), divided by the circuit's closed loop gain (A CL).
Phase margin of an op amp circuit can be thought of as the amount of additional phase shift at the closed loop
bandwidth required to make the circuit unstable (i.e., phase shift + phase margin = -180). As phase margin
approaches zero, the loop phase shift approaches -180 and the op amp circuit approaches instability. Typically,
values of phase margin much less than 45 can cause problems such as "peaking" in frequency response, and
overshoot or "ringing" in step response. In order to maintain conservative phase margin, the pole generated by
capacitive loading should be at least a decade above the circuit's closed loop bandwidth.When it is not, consider the
possibility of instability.
Q. So how do I deal with a capacitive load?
A. First of all you should determine whether the op amp can safely drive the load on its own. M any op amp data
sheets specify a "capacitive load drive capability". Others provide typical data on "small-signal overshoot vs.
capacitive load". In looking at these figures, you'll see that the overshoot increases exponentially with added load
capacitance. As it approaches 100%, the op amp approaches instability. If possible, keep it well away from this
limit. Also notice that this graph is for a specified gain. For a voltage feedback op amp, capacitive load drive
capability increases proportionally with gain. So aVF op amp that can safely drive a 100-pF capacitance at unity
gain should be able to drive a 1000-pF capacitance at a gain of 10.
A few op amp data sheets specify the open loop output resistance (Ro), from which you can calculate the frequency
of gain-the added pole as described above.The circuit will be stable if the frequency of the added pole (f P ) is more
than a decade above the circuit's bandwidth.
If the op amp's data sheet doesn't specify capacitive load drive or open loop output resistance, and has no graph of
overshoot versus capacitive load, then to assure stability you must assume that any load capacitance will require
some sort of compensa-tion technique.There are many approaches to stabilizing standard op amp circuits to drive
capacitive loads. Here are a few:
Noise-gain manipulation: A powerful way to maintain stability in low-frequency applications-often overlooked
by designers-involves increasing the circuit's closed-loop gain (a/k/a "noise gain") without changing signal gain,thus
reducing the frequency at which the product of open-loop gain and feedback attenuation goes to unity. Some circuits
to achieve this, by connecting RD between the op amp inputs, are shown below. The "noise gain" of these circuits
can be arrived at by the given equation.

Since stability is governed by noise gain rather than by signal gain, the above circuits allow increased stability
without affecting signal gain. Simply keep the "noise bandwidth" (GBP/A NOISE) at least a decade below the load
generated pole to guarantee stability.

One disadvantage of this method of stabilization is the additional output noise and offset voltage caused by increased
amplification of input-referred voltage noise and input offset voltage. The added dc offset can be eliminated by
including CD in series with RD, but the added noise is inherent with this technique. The effective noise gain of these
circuits with and without CD are shown in the figure.
CD, when used, should be as large as feasible; its minimum value should be 10 A NOISE/(2 pRDGBP) to keep the
"noise pole" at least a decade below the "noise bandwidth".
Out-of-loop compensation: Another way to stabilize an op amp for capacitive load drive is by adding a resistor,
RX, between the op amp's output terminal and the load capacitance, as shown below.Though apparently outside the
feedback loop, it acts with the load capacitor to introduce a zero into the transfer function of the feedback network,
thereby reducing the loop phase shift at high frequencies.
To ensure stability, the value of RX should be such that the added zero (fZ) is at least a decade below the closed loop
bandwidth of the op amp circuit.With the addition of RX,circuit performance will not suffer the increased output
noise of the first method, but the output impedance as seen by the load will increase.This can decrease signal gain,
due to the resistor divider formed by RX and RL. If RL is known and reasonably constant, the results of gain loss can
be offset by increasing the gain of the op amp circuit.
This method is very effective in driving transmission lines.The values of RL and RX must equal the characteristic
impedance of the cable (often 50ohms or 75ohms) in order to avoid standing waves. So RX is pre-determined, and all
that remains is to double the gain of the amplifier in order to offset the signal loss from the resistor divider. Problem
solved.
In-loop compensation: If RL is either unknown or dynamic, the effective output resistance of the gain stage must be
kept low. In this circumstance, it may be useful to connect RX inside the overall feedback loop, as shown below.
With this configuration, dc and low-frequency feedback comes from the load itself, allowing the signal gain from
input to load to remain unaffected by the voltage divider, RX and RL.
The added capacitor, CF , in this circuit allows cancellation of the pole and zero contributed by CL.To put it simply,
the zero from CF is coincident with the pole from CL, and the pole from CF with the zero from CL.Therefore, the
overall transfer function and phase response are exactly as if there were no capacitance at all. In order to assure
cancellation of both pole/ zero combinations, the above equations must be solved accurately. Also note the
conditions; they are easily met if the load resistance is relatively large.
Calculation is difficult when RO is unknown. In this case, the design procedure turns into a guessing game-and a
prototyping nightmare.A word of caution about SPICE:SPICE models of op amps don't accurately model open-loop
output resistance (RO); so they cannot fully replace empirical design of the compensation network.
It is also important to note that CL must be of a known (and constant) value in order for this technique to be
applicable. In many applications, the amplifier is driving a load "outside the box," and C L can vary significantly from
one load to the next. It is best to use the above circuit only when CL is part of a closed system.
One such application involves the buffering or inverting of a reference voltage, driving a large decoupling capacitor.
Here, CL is a fixed value, allowing accurate cancellation of pole/zero combinations. The low dc output impedance and
low noise of this method (compared to the previous two) can be very beneficial. Furthermore, the large amount of
capacitance likely to decouple a reference voltage (often many microfarads) is impractical to compensate by any
other method.
All three of the above compensation techniques have advantages and disadvantages. You should know enough by
now to decide which is best for your application. All three are intended to be applied to "standard", unity gain
stable, voltage feedback op amps. Read on to find out about some techniques using special purpose amplifiers.
Q. My op amp has a "compensation" pin. Can I overcompensate the op amp so that it will remain stable when
driving a capacitive load?
A. Yes. This is the easiest way of all to compensate for load capacitance. M ost op amps today are internally
compensated for unity-gain stability and therefore do not offer the option to "overcompensate". But many devices
still exist with inherent stability only at very high noise gains. These op amps have a pin to which an external
capacitor can be connected in order to reduce the frequency of the dominant pole. To operate stably at lower gains,
increased capacitance must be tied to this pin to reduce the gain-bandwidth product. When a capacitive load must be
driven, a further increase (overcompensation) can increase stabilitybut at the expense of bandwidth.
Q. So far you've only discussed voltage feedback op amps exclusively, right? Do current feedback (CF) op amps
behave similarly with capacitive loading? Can I use any of the compensation techniques discussed here?
A. Some characteristics of current feedback architectures require special attention when driving capacitive loads, but
the overall effect on the circuit is the same. The added pole, in conjunction with op-amp output resistance, increases
phase shift and reduces phase margin, potentially causing peaking, ringing, or even oscillation. However, since a CF
op amp can't be said to have a "gain-bandwidth product" (bandwidth is much less dependent on gain), stability can't
be substantially increased simply by increasing the noise gain. This makes the first method impractical. Also, a
capacitor (CF ) should NEVER be put in the feedback loop of a CF op amp, nullifying the third method. The most
direct way to compensate a current feedback op amp to drive a capacitive load is the addition of an "out of loop"
series resistor at the amplifier output as in method 2.
vn
nV/ in
fA/
Part
BW SR
Number Ch MHz V/ms Hz
VOS
Hz mV
Ib
nA
Supply
Voltage
Range IQ
[V]
mA
Cap
Load
RO
Drive
ohms [pF]
Notes
AD817
50
350
15
1500
0.5
3000
5-36
unlim
AD826
50
350
15
1500
0.5
3000
5-36
6.8
unlim
AD827
50
300
15
1500
0.5
3000
9-36
5.25
15
unlim
AD847
50
300
15
1500
0.5
3000
9-36
4.8
15
unlim
AD848
35
200
1500
0.5
3000
9-36
5.1
15
unlim
GMIN=5
AD849
29
200
1500
0.3
3000
9-36
5.1
15
unlim
GMIN=25
AD704
0.8
0.15
15
50
0.03
0.1
4-36
0.375
10000
AD705
0.8
0.15
15
50
0.03
0.06
4-36
0.38
10000
AD706
0.8
0.15
15
50
0.03
0.05
4-36
0.375
10000
OP97
0.9
0.2
14
20
0.03
0.03
4-40
0.38
10000
OP279
22
1000
300
4.5-12
OP400
0.5
0.15
11
600
0.08
0.75
6-40
0.6
10000
AD549
35
0.22
0.5
0.00015 10-36
0.6
4000
OP200
0.5
0.15
11
400
0.08
0.1
6-40
0.57
2000
OP467
28
170
8000
0.2
150
9-36
1600
AD744
13
75
16
10
0.3
0.03
9-36
3.5
1000
comp.term
AD8013 3
140
1000 3.5
12000
3000
4.5-13
3.4
1000
current fb
AD8532 2
30
50
25
0.005
3-6
1.4
1000
AD8534 4
30
50
25
0.005
3-6
1.4
1000
OP27
2.8
3.2
1700
0.03
15
8-44
6.7
70
1000
OP37
12
17
3.2
1700
0.03
15
8-44
6.7
70
1000
OP270
2.4
3.2
1100
0.05
15
9-36
1000
OP470
3.2
1700
0.4
25
9-36
2.25
1000
OP275
22
1500
100
9-44
1000
OP184
4.25
3.9
400
0.18
80
4-36
1000
OP284
4.25
3.9
400
0.18
80
4-36
1000
OP484
4.25
3.9
400
0.25
80
4-36
1000
OP193
0.04
15
65
50
0.15
20
3-36
0.03
1000
OP293
0.04
15
65
50
0.25
20
3-36
0.03
1000
22
10000
GMIN=5
Q. This has been informative, but I'd rather not deal with any of these equations. Besides, my board is already laid
out, and I don't want to scrap this production run. Are there any op amps that are inherently stable when driving
capacitive loads?
A. Yes. Analog Devices makes a handful of op amps that drive "unlimited" load capacitance while retaining excellent
phase margin. They are listed in the table, along with some other op amps that can drive capacitive loads up to
specified values. About the "unlimited" cap load drive devices: don't expect to get the same slew rate when driving 10
F as you do when driving purely resistive loads. Read the data sheets for details.
REFERENCES
Practical Analog Design Techniques, Analog Devices 1995 seminar notes. Cap load drive information can be found in
section 2, "High-speed op amps" (Walt Jung and Walt Kester).
Application Note AN-257: "Careful design tames high-speed op amps," by Joe Buxton, in ADI's Applications
Reference Manual (1993). A detailed examination of the "in-loop compensation" method. Free.
"Current-feedback amplifiers," Part 1 and Part 2", by Erik Barnes, Analog Dialogue 30-3 and 30-4 (1996), now
consolidated in Ask The Applications Engineer (1997). Available on our Web site.
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by M ary M cCarthy & Anthony Collins
S WITCHES AND MULTIPLEXERS
Q. Analog Devices doesnt specify the bandwidth of its ADG series switches and multiplexers. Is there a reason?
A. The ADG series switches and multiplexers have very high input bandwidths, in the hundreds of megahertz.
However, the bandwidth specification by itself is not very meaningful, because at these high frequencies, the
off-isolation and crosstalk will be significantly degraded. For example, at 1 M Hz, a switch typically has off-isolation
of 70 dB and crosstalk of 85 dB. Both off-isolation and crosstalk degrade by 20 dB per decade. This means that at
10 M Hz, the off-isolation is reduced to 50 dB and the crosstalk increases to 65 dB. At 100 M Hz, the off-isolation
will be down to 30 dB while the crosstalk will have increased to 45 dB. So it is not sufficient to consider bandwidth
alonethe off-isolation and crosstalk must be considered to determine if the application can tolerate the degradation
of these specifications at the required high frequency.
Q. Which switches and multiplexers can be operated with power supplies less than those specified in the data sheet?
A. All of the ADG series switches and multiplexers operate with power supplies down to +5 V or 5 V. The
specifications affected by power-supply voltage are timing, on resistance, supply current and leakage current.
Lowering power supply voltage reduces power supply current and leakage current. For example, the ADG411s
IS(OFF) and ID(OFF) are 20 nA, and ID(ON) is 40 nA, at +125C with a 15-V power supply.When the supply
voltage is reduced to 5 V, IS(OFF) and ID(OFF) drop to 2.5 nA, while ID(ON) is reduced to 5 nA at +125C.The
supply currents, IDD, ISS and IL, are 5 mA maximum at +125C with a 15-V power supply.When a 5-V power
supply is used, the supply currents are reduced to 1 A maximum. The on-resistance and timing increase as the
power supply is reduced. The Figures below show how the timing and on-resistance of the ADG408 vary as a
function of power supply voltage.
Q. Some of the ADG series switches are fabricated on the DI process. What is it?
A. DI is short for dielectric isolation. On the DI process, an insulation layer (trench) is placed between the NM OS
and PM OS transistors of each CM OS switch. Parasitic junctions, which occur between the transistors in standard
switches, are eliminated, resulting in a completely latchup-proof switch. In junction isolation (no trench used), the N
and P wells of the PM OS and NM OS transistors form a diode which is reverse-Collins biased in normal operation.
However, during overvoltage or power-off conditions,when the analog input exceeds the power supplies, the diode is
forward biased, forming a silicon controlled rectifier (SCR)-like circuit with the two transistors, causing the current to
be amplified significantly, leading eventually to latch up.This diode doesnt exist in dielectrically isolated switches,
making the part latchup proof.
Q. How do the fault-protected multiplexers and channel protectors work?

A. A channel of a fault-protected multiplexer or channel protector consists of two NM OS and two PM OS
transistors. One of the PM OS transistors does not lie in the direct signal path but, is used to connect the source of
the second PM OS to its backgate. This has the effect of lowering the threshold voltage, which increases the input
signal range for normal operation. The source and backgate of the NM OS devices are connected for the same reason.
During normal operation, the fault-protected parts operate as a standard multiplexer.When a fault condition occurs
on the input to a channel, this means that the input has exceeded some threshold voltage which is set by the supply
rail voltages. The threshold voltages are related to the supply rails as follows: for a positive overvoltage, the
threshold voltage is given by VDD VTN where VTN is the threshold voltage of the NM OS transistor (typically 1.5
V).For a negative overvoltage, the threshold voltage is given by VSS VTP , where VTP is the threshold voltage of the
PM OS device (typically 2 V). When the input voltage exceeds these threshold voltages, with no load on the channel,
the output of the channel is clamped at the threshold voltage.
Q. How do the parts operate when an overvoltage exists?
A. The next two figures show the operating conditions of the signal path transistors during overvoltage conditions.
This one demonstrates how the series N, P and N transistors operate when a positive overvoltage is applied to the
channel.The first NM OS transistor goes into saturation mode as the voltage on its drain exceeds (VDD VTN). The
potential at the source of the NM OS device is equal to (VDD VTN). The other M OS devices are in a non-saturated
mode of operation.
When a negative overvoltage is applied to a channel,the PM OS transistor enters a saturated mode of operation as the
drain voltage exceeds (VSS VTP).As with a positive overvoltage, the other M OS devices are non-saturated.
Q. How does loading affect the clamping voltage?

A. When the channel is loaded, the channel output will clamp at a value of voltage between the thresholds. For
example, with a load of 1 kW,VDD = 15 V, and a positive overvoltage, the output will clamp at VDDVTN
DV,where DV is due to the IR voltage drop across the channels of the non-saturated M OS devices. In the example
shown below the voltage at the output of the clamped NM OS is 13.5 V. The on-resistance of the two remaining
M OS devices is typically 100 W. Therefore, the current is 13.5 V/(1 kW + 100 W) = 12.27 mA.This produces a
voltage drop of 1.2 V across the NM OS and PM OS resulting in a clamp voltage of 12.3 V. The current during a fault
condition is determined by the load on the output, i.e., VCLAMP /RL.
Q.Do the fault-protected multiplexers and channel protectors function when the power supply is absent.
A. Yes.These devices remain functional when the supply rails are down or momentarily disconnected.When VDD
and VSS equal 0 V, all the transistors are off, as shown, and the current is limited to sub nanoampere levels.
Q. What is "charge injection"?

A. Charge injection in analog switches and multiplexers is a level change caused by stray capacitance associated with
the NM OS and PM OS transistors that make up the analog switch. The Figure below models the structure of an
analog switch and the stray capacitance associated with such an implementation.The structure basically consists of
an NM OS and PM OS device in parallel. This arrangement produces the familiar "bathtub" resistance profile for
bipolar input signals.The equivalent circuit shows the main parasitic capacitances that contribute to the charge
injection effect, CGDN (NM OS gate to drain) and CGDP (PM OS gate to drain).The gate-drain capacitance associated
with the PM OS device is about twice that of the NM OS device, because for both devices to have the same
on-resistance, the PM OS device has about twice the area of the NM OS. Hence the associated stray capacitance is
approximately twice that of the NM OS device for typical switches found in the marketplace.
When the switch is turned on, a positive voltage is applied to the gate of the NM OS and a negative voltage is applied
to the gate of the PM OS. Because the stray gate-to-drain capacitances are mismatched, unequal amounts of positive
and negative charge are injected onto the drain.The result is a removal of charge from the output of the switch,
manifested as a negative- going voltage spike. Because the analog switch is now turned on this negative charge is
quickly discharged through the on resistance of the switch (100 W). This can be seen in the simulation plot at 5
ms.Then when the switch is turned off, a negative voltage is applied to the gate of the NM OS and a positive voltage
is applied to the gate of the PM OS.The result is charge added to the output of the switch. Because the analog switch
is now off, the discharge path for this injected positive charge is a high impedance (100 M W). The result is that the
load capacitance stores this charge until the switch is turned on again.The simulation plot clearly shows this with the
voltage on CL (as a result of charge injection) remaining constant at 170 mV until the switch is again turned on at 25
ms. At this point an equivalent amount of negative charge is injected onto the output, reducing the voltage on C L to 0
V. At 35 ms the switch is turned on again and the process continues in this cyclic fashion.
At lower switching frequencies and load resistance, the switch output would contain both positive and negative
glitches as the injected charge leaks away before the next switch transition.
Q. What can be done to improve the charge injection performance of an analog switch?
A. As noted above, the charge injection effect is caused by a mismatch in the parasitic gate-to-drain capacitance of
the NM OS and PM OS devices. So if these parasitics can be matched there will be little if any charge injection
effect.This is precisely what is done in Analog Devices CM OS switches and multiplexers.The matching is
accomplished by introducing a dummy capacitor between the gate and drain of the NM OS device.
Unfortunately the matching is only accomplished under a specific set of conditions, i.e., when the voltage on the
Source of both devices is 0 V.The reason for this is that the parasitic capacitances, C GDN and CGDP , are not constant;
they vary with the Source voltage. When the Source voltage of the NM OS and PM OS is varied, their channel depths
vary, and with them, CGDN and CGDP . As a consequence of this matching at VSOURCE= 0 V the charge injection
effect will be noticeable for other values of VSOURCE.
NOTE: Charge injection is usually specified on the data sheet under these matched conditions, i.e., VSOURCE = 0 V.
Under these conditions,the charge injection of most switches is usually quite good in the order of 2 to 3 pC max.
However the charge injection will increase for other values ofVSOURCE, to an extent depending on the individual
switch. M any data sheets will show a graph of charge injection as a function of Source voltage.
Q. How do I minimize these effects in my application?
A. The effect of charge injection is a voltage glitch on the output of the switch due to the injection of a fixed amount
of charge. The glitch amplitude is a function of the load capacitance on the switch output and also the turn on and
turn off times of the switch.The larger the load capacitance, the smaller will be the voltage glitch on the output, i.e.,
Q=CxV, or V=Q/C, and Q is fixed. Naturally, it may not always be possible to increase the load capacitance, because
it would reduce the bandwidth of the channel. However, for audio applications, increasing the load capacitance is an
effective means of reducing those unwanted "pops" and "clicks".
Choosing a switch with a slow turn on and turn off time is also an effective means of reducing the glitch amplitude on
the switch output. The same fixed amount of charge is injected over a longer time period and hence has a longer time
period in which to leak away. The result is a wider glitch but much reduced in amplitude.This technique is used quite
effectively in some of the audio switch products, such as the SSM -2402/ SSM -2412, where the turn on time is
designed to be of the order of 10 ms.
Another point worth mentioning is that the charge injection performance is directly related to the on-resistance of the
switch. In general the lower the RON, the poorer the charge injection performance.The reason for this is purely due to
the associated geometry, because RON is decreased by increasing the area of the NM OS and PM OS devices, thus
increasing CGDN and CGDP . So trading off RON for reduced charge injection may also be an option in many
applications.
Q. How can I evaluate the charge injection performance of an analog switch or multiplexer?
A. The most efficient way to evaluate a switchs charge injection performance is to use a setup similar to the one
shown below. By turning the switch on and off at a relatively high frequency (<10 kHz) and observing the switch
output on an oscilloscope (using a high impedance probe), a trace similar to that shown in Figure 11 will be
observed.The amount of charge injected into the load is given by DVOUT xCL.Where DVOUT is the output pulse
amplitude.
Ask the Applications Engineer27

By Bill Englemann
SIGNAL CORRUPTION IN INDUSTRIAL MEASUREMENT
Q. What problems am I most likely to run into when instrumenting an
industrial system?
A. The five kinds of problems most frequently reported by
customers of our I/O Subsystems (IOS) Division are:
1. GROUND LOOPS
Ground loops are the bane of instrumentation engineers and
technicians. They cause many lost hours troubleshooting
obscure and hard-to-diagnose measurement problems. Do
these symptoms sound familiar?
Readings slowly drift even though you know the sensor is
not changing.
Readings shift when another piece of equipment is turned on.
Measurements differ when a calibration device is connected
at the end of an instrument cable instead of directly at the input.
A 60-Hz sine wave is superimposed upon your dc
measurement input.
There are unexplained measurement equipment failures.
Any of these problems can be caused by ground loops
inadvertent flows of current through ground, common and
reference paths connected to points at nominally the same
potential. And all of these problems can be eliminated by
isolation, the key signal-conditioning attribute we offer in all
our signal conditioning series.
Sometimes separate grounding of two pieces of equipment
introduces a potential difference and causes current to flow
through signal lines. Why would this happen if they were both
grounded? Because the earth and metal structures are actually
relatively poor conductors of electricity when compared with
the copper wires that carry power and signals. This inherent
resistance to current flow varies with the weather and time of
year and causes current to flow through any wires that are
connecting the two devices. Many factory and plant buildings
experience potentials of several tens or hundreds of volts.
Appropriate signal conditioning eliminates the possibility of
ground loops by electrically isolating the equipment. Signal
conditioning will also protect equipment, rejecting potentially
damaging voltage levels before entering the sensitive
measurement system.
Isolation provides a completely floating input and output port,
where there is no electrical path from field input to output and
to power. Hence, there is no path for current to flow, and no
possibility of ground loops.
Q. How is this possible? How can we provide a path for the signal from
input to output, without any path for current to flow?
A. Its done by magnetic isolation. A representation of the signal
is passed through a transformer, which creates a magnetic
not a galvanicconnection. We have perfected the use of
transformers for accurate, reliable low-level signal isolation.
This approach employs a modulator and demodulator to
transmit the signal across the transformer barrier, and can
achieve isolation levels of 2500 volts ac.
One of the most frequently encountered application problems

involves measuring a low-level sensor such as a thermocouple
in the presence of as much as hundreds of volts of ground
potential. This potential is known as common-mode voltage. The
ability of a high-quality signal conditioner to reject errors
caused by common-mode voltage, while still accurately
amplifying low-level signals is known as common mode rejection
(CMR). Our 5B, 6B and 7B Series signal conditioning
subsystems provide sufficient common-mode rejection to
reduce the impact of these errors by a factor of 100 million to 1!
2. MISWIRING AND OVERVOLTAGE
You know what happens when a cable from a sensitive data
acquisition board is routed into another cabinet, or another
part of the buildingthe input and output wiring terminals
are grouped among hundreds of other terminals carrying
diverse signals and levels: dc signals, ac signals, milli-voltage,
thermocouples, dc power, ac power, proximity switches, relay
circuits, etc. Its not difficult to imagine even a well trained
technician or electrician connecting a wire to the wrong
terminal. Wiring diagrams are often updated in real time with
a red pen, as system needs change. Equipment gets replaced
with equivalents. Sometimes power supplies fail and excess
voltages are applied inadvertently. What can you do to protect
your measurement system?
The answer lies in using rugged signal conditioning on
every analog signal lead. This inexpensive insurance policy
provides protection against miswiring and overvoltage on each
input and output signal line. For example, the use of a
5B Series signal conditioner will provide 240 -V ac of protection,
even on input lines used to measure sensitive thermocouple
signals, with levels in the millivolt range. You can literally
connect a 240-V ac line across the same input lines used
to measure the thermocouple, without any damage. The use
of signal conditioning to interface with field I/O will protect
all measurement and data acquisition equipment on the
system side.
3. LOSS OF RESOLUTION
Resolution is the smallest change in the measurement that the
analog-digital converter (ADC) system can detect and respond
to. For example, if a temperature reading steps from 100.00
to 100.29 to 100.58, as the actual temperature gradually
increases through this range, the resolution (least-significantbit value) is 0.29. This would occur if you had a signal
conditioner measuring a thermocouple with a range of 0 to
+1200 and a 12-bit ADC. There are two ways to improve this
(make the resolution smaller) and detect smaller changes - use
a higher resolution ADC or use a smaller measurement range.
For example, a 15-bit plus sign ADC of the type used in our
6B Series would offer resolution of 0.037 on the 0 to 1200
range example, 8 times smaller! On the other hand, if you knew
that most of the time the temperature would be in the vicinity
of 100, you could order from Analog Devices a thermocouple
signal conditioner with a custom range, calibrated for the exact
thermocouple type and temperature measurement range. For
example, a custom-ranged signal conditioner with a span of
+50 to +150 would offer resolution of 0.024 with a 12-bit
ADC, a big improvement over the 0 to 1200 range.
4. MULTIPLE SIGNALS DONT ALL HAVE THE

SAME PROPERTIES
This can pose quite a challenge to traditional industrial
measurement approaches where 4, 8 or even 16 channels are
dedicated to interfacing to the same signal type. For example,
lets say you need to measure two J thermocouples, one 0 to
+10 V signal, four 4-20 mA signals and two platinum RTDs
(resistance temperature detector).You can either buy individual
transmitters for each channel and then wire them all into a
common 4-20 mA input board, or use a signal conditioning
solution from Analog Devices that is configured channel-bychannel, but is also integrated into a simple backplane
subsystem.
These subsystems incorporate all connections for input, output
and field wiring, as well as simple connections for a dc power
supply. They offer a choice of output options: 0 to +5 V, 0 to
+10 V, 4-20 mA and RS-232/485, and more! Input and output
modules are mix-and-match compatible on a per-channel basis
and hot-swappable for the ultimate flexibility.
5. ELECTRICAL INTERFERENCE
Todays industrial factories and plants contain all kinds of
interference sources: engines and motors, fluorescent lights,
two-way radios, generators, etc. Each of these can radiate
electro-magnetic noise that can be picked up by wiring, circuit
boards and measurement modules. Even with the best shielding
and grounding practices, this interference can show up as noise
on the signal measurement. How can this be eliminated? By
providing high noise rejection in the signal conditioning
subsystem.
Lower-frequency noise can be eliminated by choosing signalconditioning subsystems with excellent common mode and
normal mode rejection. Common mode noise present on both
the plus and minus inputs can be seen when measuring either
the plus or minus input with respect to a common point like
ground. Normal-mode noise is measured in the difference
between the plus and minus inputs. A typical common mode
rejection specification on our signal conditioning subsystems
is 160 dB. This log scale measurement means that the effect of
any common mode voltage noise is reduced relative to signal

by a factor of 108, or 100 million to 1!
Very high frequency noise in the radio frequency bands can
cause dc offsets due to rectification. It requires other
approaches, including careful circuit layout and the use of RFI
filters such as ferrite beads. The performance measures are
indicated by our compliance with the EN certifications for
electromagnetic susceptibility popularized by the CE mark
requirements of the European community. A typical application
where this is important would be where a two-way radio is
used within a few feet of the input wiring and signal
conditioning subsystem. It is necessary to reject measurement
errors whenever the radios are transmitting. Good panel layout
practice and the use of signal conditioning will ensure the best
accuracy in these noisy environments.
CONCLUSION
Q. What are some good installation and wiring practices
A. Here are a few suggestions.You may also want to take a look at
Design Tools and the Analog Devices book, Practical Analog
Design Techniques, available for sale in hard copy and free on
the Web.
Avoid installing sensitive measuring equipment, or wire
carrying low level signals, near sources of electrical and
magnetic noise, such as breakers, transformers, motors, SCR
drives, welders, fluorescent lamp controllers, or relays.
Use twisted pair wiring to reduce magnetic noise pickup.
Look for 10 to 12 twists per foot.
Use shielded cable with the shield connected to circuit
common at the input end only.
Never run signal-carrying wires in the same conduit that
carries power lines, relay contact leads or other high-level
voltages or currents.
In extremely high interference environments, mount signal
conditioning and measurement equipment inside grounded
and closed metal cabinets.

By Eamon Nash
LOGARITHMIC AMPLIFIERS EXPLAINED
Q. Ive just been reading data sheets of some recently released Analog
Devices log amps and Im still a little confused about what exactly a
log amp does.
A. Youre not alone. Over the years, I have had to deal with lots of
inquiries about the changing emphasis on functions that log
amps perform and radically different design concepts. Let me
start by asking you, what do you expect to see at the output of
a log amp?
Q. Well, I suppose that I would expect to see an output proportional to
the logarithm of the input voltage or current, as you describe in the
Nonlinear Circuits Handbook| <http://www.analog.com/
publications/magazines/Dialogue/Anniversary/books.html> and the
Linear Design Seminar Notes| <http://www.analog.com/
publications/press/misc/press_123094.html>.
A. Well, thats a good start but we need to be more specific. The
term log amp, as it is generally understood in communications
technology, refers to a device which calculates the log of an
input signals envelope. What does that mean in practice? Take
a look a the scope photo below. This shows a 10-MHz sine
wave modulated by a 100-kHz triangular wave and the gross
logarithmic response of the AD8307, a 500-MHz 90-dB log
amp. Note that the input signal on the scope photo consists of
many cycles of the 10-MHz signal, compressed together, using
the time/div knob of the oscilloscope. We do this to show the
envelope of the signal, with its much slower repetition frequency
of 100 kHz. As the envelope of the signal increases linearly, we
can see the characteristic log (x) form in the output response
of the log amp. In contrast, if our measurement device were a
linear envelope detector (a filtered rectified output), the output
would simply be a tri-wave.
adjustments to the amplitude. A device that calculates the

instantaneous log of the input signal is quite different, especially
for bipolar signals.
On that point, lets digress for a moment to consider such a
device.Think about what would happen when an ac input signal
crosses zero and goes negative. Remember, the mathematical
function, log x, is undefined for x real and less than or equal to
zero, or x greater than or equal to zero (see figure).
Y
SINH1 (X)
LOG (2X)
X
LOG (2X)
However, as the figure shows, the inverse hyperbolic sine,

sinh1 x, which passes symmetrically through zero, is a good
approximation to the combination of log 2x and minus log
(2x), especially for large values of |x|. And yes, it is possible
to build such a log amp; in fact, Analog Devices many years
ago manufactured and sold Model 752 N & P temperaturecompensated log diode modules, whichin complementary
feedback pairsperformed that function. Such devices, which
calculate the instantaneous log of the input signal are called
baseband log amps (the term true log amp is also used). The
focus of this discussion, however, is on envelope-detecting
log amps, also referred to as demodulating log amps, which
have interesting applications in RF and IF circuitry for
communications.
Q. But, from what you have just said, I would imagine that a log amp
is generally not used to demodulate signals?
VOLTAGE
INPUT
A. Yes, that is correct. The term demodulating came to be applied

to this type of device because a log amp recovers the log of the
envelope of a signal in a process somewhat like that of
demodulating AM signals.
Q. So I dont see the log of the instantaneous signal?
In general, the principal application of log amps is to measure

signal strength, as opposed to detecting signal content. The log
amps output signal, which can represent a many-decade
dynamic range of high-frequency input signal amplitudes by a
relatively narrow range, is typically used to regulate gain. The
classic example of this is using a log amp in an automatic gain
control loop, to regulate the gain of a variable-gain amplifier.
The receiver of a cellular base station, for example, might use
the signal from a log amp to regulate the receiver gain. In
transmitters, log amps are also used to measure and regulate
transmitted power.
A. Thats correct, and its the source of much of the confusion.

The log amp gives an indication of the instant-by-instant lowfrequency changes in the envelope, or amplitude, of the signal
in the log domain in the same way that a digital voltmeter, set
to ac volts, gives a steady (linear) reading when the input is
connected to a constant amplitude sine wave and follows any
However, there are some applications where a log amp is used

to demodulate a signal. The figure shows a received signal that
has been modulated using amplitude shift keying (ASK). This
simple modulation scheme, similar to early transmissions of
radar pulses, conveys digital information by transmitting a series
of RF bursts (logic 1 = burst, logic 0 = no burst). When this
OUTPUT
TIME
signal is applied to a log amp, the output is a pulse train which

can be applied to a comparator to give a digital output. Notice
that the actual amplitude of the burst is of little importance;
we only want to detect its presence or absence. Indeed, it is
the log amps ability to convert a signal which varies over a
large dynamic range (10 mV to 1 V in this case) into one that
varies over a much smaller range (1 V to 3 V) that makes the
use of a log amp so appealing in this application.
1V
3V
2V
1V
100mV
10mV
LOG
AMP
So the output is changing by 1 V for each factor-of-10 (20-dB)

amplitude change at the input. We can describe the log amp
then as having a slope of 50 mV/dB.
Q. Can you explain briefly how a log amp works?

A. The figure shows a simplified block diagram of a log amp. The
core of the device is a cascaded chain of amplifiers. These
amplifiers have linear gain, usually somewhere between 10 dB
and 20 dB. For simplicity of explanation, in this example, we
have chosen a chain of 5 amplifiers, each with a gain of 20 dB,
or 10. Now imagine a small sine wave being fed into the first
amplifier in the chain. The first amplifier will amplify the signal
by a factor of 10 before it is applied to the second amplifier. So
as the signal passes through each subsequent stage, it is
amplified by an additional 20 dB.
Now, as the signal progresses down the gain chain, it will at
some stage get so big that it will begin to clip (the term limit is
also used) as shown. In the simplified example, this clipping
level (a desired effect) has been set at 1 V peak. The amplifiers
in the gain chain would be designed to limit at this same precise
level.
4V
S
1V
DET
VIN
20dB
1V
DET
20dB
1V
DET
20dB
1V
1V
DET
20dB
1V
1V
Q. O.K. I understand the logarithmic transformation. Now can you

explain what the Intercept is?
A. The slope and intercept are the two specifications that define
the transfer function of the log amp, that is, the relationship
between output voltage and input signal level. The figure shows
the transfer function at 900 MHz, and over temperature, of
the AD8313, a 100-MHz-to-2.5-GHz 65-dB log amp. You can
see that the output voltage changes by about 180 mV for a 10
dB change at the input. From this we can deduce that the
slope of the transfer function is 18 mV/dB.
As the input signal drops down below about 65 dBm, the
response begins to flatten out at the bottom of the devices
range (at around 0.5 V, in this case). However, if the linear
part of the transfer function is extrapolated until it crosses the
horizontal axis (0 V theoretical output), it passes through a
point called the intercept (at about 93 dBm in this case). Once
the slope and intercept of a particular device are known (these
will always be given in the data sheet), we can predict the
nominal output voltage of the log amp for any input level within
the linear range of the device (about 65 dBm to 0 dBm in this
case) using the simple equation:
VOUT = Slope (PIN Intercept)
LOW
PASS
FILTER
DET
20dB
To understand how this signal transformation yields the log of

the input signals envelope, consider what happens if the input
signal is reduced by 20 dB. As it stands in the figure, the
unfiltered output of the summer is about 4 V peak (from 3
stages that are limiting and a fourth that is just about to limit).
If the input signal is reduced by a factor of 10, the output of
one stage at the input end of the chain will become negligible,
and there will be one less stage in limiting. Because of the
voltage lost from this stage, the summed output will drop to
approximately 3 V. If the input signal is reduced by a further
20 dB, the summed output will drop to about 2 V.
For example, if the input signal is 40 dBm the output voltage

will be equal to
LIMITER
OUTPUT
1V
VLOG
18 mV/dB (40 dBm (93 dBm))

= 0.95 V
2.0
VS = +5V
1.8
1.6
1.4
INTERCEPT
ERROR CURVES
1.2
408C
1.0
+258C
0.8
+858C
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
INPUT AMPLITUDE dBm
5
10
ERROR dB
The signal at the output of each amplifier is also fed into a full
wave rectifier. The outputs of these rectifiers are summed
together as shown and applied to a low-pass filter, which
removes the ripple of the full-wave rectified signal. Note that
the contributions of the earliest stages are so small as to be
negligible.This yields an output (often referred to as the video
output), which will be a steady-state quasi-logarithmic dc
output for a steady-state ac input signal. The actual devices
contain innovations in circuit design that shape the gain and
limiting functions to produce smooth and accurate logarithmic
behavior between the decade breaks, with the limiter output
sum comparable to the characteristic, and the contribution of
the less-than-limited terms to the mantissa.
It is worth noting that an increase in the intercepts value

decreases the output voltage.
VOUT Volts
After the signal has gone into limiting in one of the stages (this
happens at the output of the third stage in the figure), the
limited signal continues down the signal chain, clipping at each
stage and maintaining its 1 V peak amplitude as it goes.
The figure also shows plots of deviations from the ideal, i.e.,
log conformance, at 40C, +25C, and +85C. For example, at
+25C, the log conformance is to within at least 1 dB for an
input in the range 2 dBm to 67 dBm (over a smaller range,
the log conformance is even better). For this reason, we call
the AD8313 a 65-dB log amp. We could just as easily say that
the AD8313 has a dynamic range of 73 dB for log conformance
within 3 dB.
Q. In doing some measurements, Ive found that the output level at
which the output voltage flattens out is higher than specified in the
data sheet.This is costing me dynamic range at the low end.What is
causing this?
A. I come across this quite a bit. This is usually caused by the
input picking up and measuring an external noise. Remember
that our log amps can have an input bandwidth of as much as
2.5 GHz! The log amp does not know the difference between
the wanted signal and the noise. This happens quite a lot in
laboratory environments, where multiple signal sources may
be present. Remember, in the case of a wide-range log amp, a
60-dBm noise signal, coming from your colleague who is
testing his new cellular phone at the next lab bench, can wipe
out the bottom 20-dB of your dynamic range.
A good test is to ground both differential inputs of the log
amp. Because log amps are generally ac-coupled, you should
do this by connecting the inputs to ground through coupling
capacitors.
Solving the problem of noise pickup generally requires some
kind of filtering. This is also achieved indirectly by using a
matching network at the input. A narrow-band matching
200mV/DIV
network will have a filter characteristic and will also provide

some gain for the wanted signal. Matching networks are
discussed in more detail in data sheets for the AD8307,
AD8309, and AD8313.
Q. What corner frequency is typically chosen for the output stages lowpass filter?
A. There is a design trade-off here. The corner frequency of the
on-chip low-pass filter must be set low enough to adequately
remove the ripple of the full-wave rectified signal at the output
of the summer. This ripple will be at a frequency 2 times the
input signal frequency. However the RC time constant of the
low-pass filter determines the maximum rise time of the output.
Setting the corner frequency too low will result in the log amp
having a sluggish response to a fast-changing input envelope.
The ability of a log amp to respond to fast changing signals is
critical in applications where short RF bursts are being
detected. In addition to the ASK example discussed earlier,
another good example of this is RADAR. The figure on the left
shows the response of the AD8313 to a short 100 MHz burst.
In general, the log-amps response time is characterized by the
metric 10% to 90% rise time. The table below compares the
rise times and other important specifications of different Analog
Devices log amps.
Now take a look at the figure on the right. This shows you
what will happen if the frequency of the input signal is lower
than the corner frequency of the output filter. As might be
expected, the full wave rectified signal appears unfiltered at
the output. However this situation can easily be improved by
adding additional low-pass filtering at the output.
AVERAGE: 50 SAMPLES
OUTPUT
VS = +2.7V
INPUT
GND
PULSED RF
100MHz, 45dBm
OUTPUT
INPUT
HORIZONTAL: 50ns/DIV
TIME
TIME
Part Number
Input Bandwidth
10%90% Rise Time
Dynamic Range
Log Conformance
Limiter Output
AD606
50 MHz
360 ns
80 dB
1.5 dB
Yes
AD640
120 MHz
6 ns
50 dB
1 dB
Yes
AD641
250 MHz
6 ns
44 dB
2 dB
Yes
AD8306
500 MHz
67 ns
95 dB
0.4 dB
Yes
AD8307
500 MHz
500 ns
92 dB
1 dB
No
AD8309
500 MHz
67 ns
100 dB
1 dB
Yes
AD8313
2500 MHz
45 ns
65 dB
1 dB
No
A. That is an interesting effect that results from the nature of the

log transformation that is taking place. Looking again at transfer
function plot (i.e. voltage out vs. input level), we can see that
at low input levels, small changes in the input signal have a
significant effect on the output voltage. For example a change
in the input level from 7 mV to 700 V (or about 30 dBm to
50 dBm) has the same effect as a change in input level from
70 mV to 7 mV. That is what is expected from a logarithmic
amplifier. However, looking at the input signal (i.e., the RF
burst) with the naked eye, we do not see small changes in the
mV range. Whats happening in the figure is that the burst
does not turn off instantly but drops to some level and then
decays exponentially to zero. And the log of a decaying
exponential signal is a straight line similar to the tail in the
plot.
Q. Is there a way to speed up the rise time of the log amps output?
A. This is not possible if the internal low-pass filter is buffered,
which is the case in most devices. However the figure shows
one exception: the un-buffered output stage of the AD8307 is
here represented by a current source of 2 A/dB, which is
looking at an internal load of 12.5 k. The current source and
the resistance combine to give a nominal slope of 25 mV/dB.
The 5-pF capacitance in parallel with the 12.5-k resistance
combines to yield a low-pass corner frequency of 2.5 MHz.
The associated 10%-90% rise time is about 500 ns.
In the figure, an external 1.37-k shunt resistor has been added.
Now, the overall load resistance is reduced to around 1.25 k.
This will decrease the rise time ten-fold. However the overall
logarithmic slope has also decreased ten-fold. As a result,
external gain is required to get back to a slope of 25 mV/dB.
You may also want to take a look at the Application Note AN405. This shows how to improve the response time of the
AD606.
AD8307
2mA/dB
5pF
12.5kV
1.37kV
AD8031
The degree to which the phase of the output signal changes as

the input level changes is called phase skew. Remember, the
phase between input and output is generally not important. It
is more important to know that the phase from input to output
stays constant as the input signal is swept over its dynamic
range. The figure shows the phase skew of the AD8309s limiter
output, measured at 100 MHz. As you can see, the phase varies
by about 6 over the devices dynamic range and over
temperature.
10
NORMALIZED PHASE SHIFT Degrees
Q. I notice that there is an unusual tail on the output signal at the

right.What is causing that?
8
6
TA = +858C
4
TA = 408C
2
0
2
4
TA = +258C
6
8
10
60
50
40
30
20
10
INPUT LEVEL dBm Re 50V
10
Q. I noticed that something strange happens when I drive the log amp
with a square wave.
A. Log amps are generally specified for a sine wave input. The
effect of differing signal waveforms is to shift the effective value
of the log amps intercept upwards or downwards. Graphically,
this looks like a vertical shift in the log amps transfer function
(see figure), without affecting the logarithmic slope. The figure
shows the transfer function of the AD8307 when alternately
fed by an unmodulated sine wave and by a CDMA channel (9
channels on) of the same rms power. The output voltage will
differ by the equivalent of 3.55 dB (88.7 mV) over the complete
dynamic range of the device.
VOUT
3
23.7kV
Q. Returning to the architecture of a typical log amp, is the heavily

clipped signal at the end of the gain chain in any way useful?
A. The signal at the end of the linear gain chain has the property
that its amplitude is constant for all signal levels within the
dynamic range of the log amp. This type of signal is very useful
in phase- or frequency demodulation applications. Remember
that in a phase-modulation scheme (e.g. QPSK or broadcast
FM), there is no useful information contained in the signals
amplitude; all the information is contained in the phase. Indeed,
amplitude variations in the signal can make the demodulation
process quite a bit more difficult. So the signal at the output of
the linear gain chain is often made available to give a limiter
output. This signal can then be applied to a phase or frequency
demodulator.
SINEWAVE
2.5
OUTPUT VOLTAGE Volts
2.67kV
2
3.55dB (88.7mV)
CDMA
1.5
0.5
0
80
70
60
50 40 30 20 10
INPUT POWER dBm
10
20
The table shows the correction factors that should be applied

to measure the rms signal strength of various signal types with
a logarithmic amplifier which has been characterized using a
sine wave input. So, to measure the rms power of a squarewave,
for example, the mV equivalent of the dB value given in the
table (3.01 dB, which corresponds to 75.25 mV in the case of
the AD8307) should be subtracted from the output voltage of
the log amp.
Correction Factor
(Add to Output Reading)
Signal Type
Sine Wave
Log amps, however fundamentally respond to voltage, not to

power. The input to a log amp is usually terminated with an
external 50- resistor to give an overall input impedance of
approximately 50 , as shown in the figure (the log amp has a
relatively high input impedance, typically in the 300 to
1000 range). If the log amp is driven with a 200- signal
and the input is terminated in 200 , the output voltage of the
log amp will be higher compared to the same amount of power
from a 50- input signal. As a result, it is more useful to work
with the voltage at the log amps input. An appropriate unit,
therefore, would be dBV, defined as the voltage level in dB
relative to 1 V, i.e.,
0 dB
Square Wave or DC
3.01 dB
Triangular Wave
+0.9 dB
GSM Channel
(All Time Slots On)
+0.55 dB
CDMA Forward Link

(Nine Channels On)
+3.55 dB
Reverse CDMA Channel
0.5 dB
PDC Channel
(All Time Slots On)
+0.58 dB
Gaussian Noise
+2.51 dB
Q. In your data sheets you sometimes give input levels in dBm and
sometimes in dBV. Can you explain why?
A. Signal levels in communications applications are usually
specified in dBm. The dBm unit is defined as the power in dB
relative to 1 mW i.e.,
Power (dBm) = 10 log10 (Power/1 mW)
Since power in watts is equal to the rms voltage squared, divided
by the load impedance, we can also write this as
Power (dBm) = 10
log10 ((Vrms2/R)/1
Voltage (dBV) = 20 log10 (Vrms /1 V)

However, there is disagreement in the industry as to whether
the 1-V reference is 1 V peak (i.e., amplitude) or 1 V rms.
Most lab instruments (e.g., signal generators, spectrum
analyzers) use 1 V rms as their reference. Based upon this,
dBV readings are converted to dBm by adding 13 dB. So
13 dBV is equal to 0 dBm.
As a practical matter, the industry will continue to talk about
input levels to log amps in terms of dBm power levels, with the
implicit assumption that it is based on a 50 impedance, even
if it is not completely correct to do so. As a result it is prudent
to provide specifications in both dBm and dBV in data sheets.
The figure shows how mV, dBV, dBm and mW relate to each
other for a load impedance of 50 . If the load impedance
were 20 , for example, the V (rms), V (p-p) and dBV scales
will be shifted downward relative to the dBm and mW scales.
Also, the V (p-p) scale will shift relative to the V (rms) scale if
the peak to rms ratio (also called crest factor) is something
other than 2 (the peak to rms ratio of a sine wave).
b
V (p-p)
V (rms)
10
mW)
It follows that 0 dBm occurs at 1 mW, 10 dBm corresponds to

10 mW, +30 dBm corresponds to to 1 W, etc. Because
impedance is a component of this equation, it is always
necessary to specify load impedance when talking about dBm
levels.
dBV
+20
+10
+30
1000
+20
100
+10
10
10
0.1
20
0.01
30
0.001
40
0.0001
50
0.00001
+1
0.1
50V
mW
+10
10
RIN
(HIGH)
dBm
20
0.1
30
0.01
40
0.01
50
0.001
60
AccelerometersFantasy & Reality

By Harvey Weinberg [harvey.weinberg@analog.com]
As applications engineers supporting ADIs compact, low-cost, gravity-sensitive iMEMs
accelerometers, we get to hear lots of creative ideas about how to employ accelerometers in
useful ways, but sometimes the suggestions violate physical laws! Weve rated some of these
ideas on an informal scale, from real to dream land:
Real A real application that actually works today and is currently in production.
Fantasy An application that could be possible if we had much better technology.
Dream Land Any practical implementation we can think of would violate physical laws.
Washing machine load balancing. Unbalanced loads during the high-speed spin-cycle cause
washing machines to shake and, if unrestrained, they can even walk across the floor. An
accelerometer senses acceleration during the spin cycle. If an imbalance is present, the washing
machine redistributes the load by jogging the drum back and forth until the load is balanced.
Real. With better load balance, faster spin rates can be used to wring more water out of clothing,
making the drying process more energy efficienta good thing these days! As an added benefit,
fewer mechanical components are required for damping the drum motion, making the overall
system lighter and less expensive. Correctly implemented, transmission and bearing service life
is extended because of lower peak loads present on the motor. This application is in production.
Machine Health Monitors. Many industries change or overhaul mechanical equipment using a
calendar-based preventive maintenance schedule. This is especially true in applications where
one cannot tolerate unscheduled down-time. So, machinery with plenty of service life left is
often prematurely rebuilt at a cost of millions of dollars across many industries. By embedding
accelerometers in bearings or other rotating equipment, service life can be extended without
risking sudden failure. The accelerometer senses the vibration of bearings or other rotating
equipment to determine their condition.
Real. Using the vibration signature of bearings to determine their condition is a well proven
and industry-accepted method of equipment maintenance, but wide measurement bandwidth is
needed for accurate results. Before the release of the ADXL001, the cost of accelerometers and
associated signal conditioning equipment had been too high. Now, its wide bandwidth (22 kHz)
and internal signal conditioning make the ADXL001 ideal for low-cost bearing maintenance.
Automatic Leveling. Accelerometers measure the absolute inclination of an object, such as a
large machine or a mobile home. A microcontroller uses the tilt information to automatically
level the object.
Real to Fantasy (depending on the application). Self-leveling is a very demanding application,
as absolute precision is required. Surface micromachined accelerometers have impressive
resolution, but absolute tilt measurement with high accuracy (better than 1 of inclination)
requires temperature stability and hysteresis performance that todays surface-micromachined
accelerometers cannot achieve. In applications where the temperature range is modest, high
stability accelerometers like the ADXL203 are up to the task. Applications needing absolute
accuracy to within 5 over a wide temperature range can be handled as well. However more
precise leveling over a wide temperature range requires external temperature compensation.
Even with external temperature compensation absolute accuracy of better than 0.5 of
inclination is difficult to achieve. Some applications are currently in production.
Human Interface for Mobile Phones. The accelerometer allows the microcontroller to
recognize user gestures, enabling one-handed control of mobile devices.
Real. Mobile phone screens eat up most of the available real estate for controls. Using an
accelerometer for user interface functions allows mobile phone makers to add buttonless
features such as Tap/Double Tap (emulating a mouse click/double click), screen rotation, tilt
controlled scrolling, and ringer control based on orientationto name just a few. In addition,
mobile phone makers can use the accelerometer to improve accuracy and usability of navigation
functions, and for other new applications. This application is currently in production.
Car Alarm. The accelerometer senses if a car is being jacked up or being picked up by a tow
truck, and sets off the alarm.
Real. One of the most popular methods of auto theft is to steal the car by simply towing it away.
Conventional car alarms do not protect against this. Shock sensors cannot measure changes in
inclination, and ignition-disabling systems are ineffectual. This application takes advantage of
the high-resolution capabilities of the ADXL213. If the accelerometer measures an inclination
change of more than 0.5 per minute, the alarm is soundedhopefully scaring off the would-be
thief. Good temperature stability is needed as no one wants their car alarm to go off because of
changes in the weather, making the highly stable ADXL213 an ideal choice. This application is
currently in production in OEM and after-market automotive anti-theft systems.
Ski Bindings. The accelerometer measures the total shock energy and signature to determine if
the binding should release.
Fantasy. Mechanical ski bindings are highly evolved, but limited in performance. Measuring the
actual shock experienced by the skier would accurately determine if a binding should release.
Intelligent systems could take each individuals capability and physiology into account. This is a
practical accelerometer application, but current battery technology makes it impractical. Small,
lightweight batteries that perform well at low temperature will eventually enable this application.
Personal Navigation. In this application, position is determined by dead reckoning (double
integration of acceleration over time to determine actual position).
Dream Land. Long term integration results in a large error due to the accumulation of small
errors in measured acceleration. Double integration compounds the errors (t2). Without some
way of resetting the actual position from time to time, huge errors result. This is analogous to
building an integrator by simply putting a capacitor across an op amp. Even if an accelerometers
accuracy could be improved by ten or one hundred times over what is currently available, huge
errors would still eventually result. They would just take longer to happen.
Accelerometers can be used with a GPS navigation system when the GPS signals are briefly
unavailable. Short integration periods (a minute or so) can give satisfactory results, and clever
algorithms can offer good accuracy using alternative approaches. When walking, for example,
the body moves up and down with each step. Accelerometers can be used to make very accurate
pedometers that can measure walking distance to within 1%.
Subwoofer Servo Control. An accelerometer mounted on the cone of the subwoofer provides
positional feedback to servo out distortion.
Real. Several active subwoofers with servo control are on the market today. Servo control can
greatly reduce harmonic distortion and power compression. Servo control can also electronically
lower the Q of the speaker/enclosure system, enabling the use of smaller enclosures, as described
in Loudspeaker Distortion Reduction, by Richard A. Greiner and Travis M. Sims, Jr., JAES Vol.
32, No. 12. The ADXL193 is small and light; its mass, added to that of the loudspeaker cone,
does not change the overall acoustic characteristics significantly.
Neuromuscular Stimulator. This application helps people who have lost control of their lower
leg muscles to walk by stimulating muscles at the appropriate time.
Real. When walking, the forefoot is normally raised when moving the leg forward, and then
lowered when pushing the leg backward. The accelerometer is worn somewhere on the lower leg
or foot, where it senses the position of the leg. The appropriate muscles are then electronically
stimulated to flex the foot as required.
This is a classic example of how micromachined accelerometers have made a product feasible.
Earlier models used a liquid tilt sensor or a moving ball bearing (acting as a switch) to determine
the leg position. Liquid tilt sensors had problems because of sloshing of the liquid, so only slow
walking was possible. Ball-bearing switches were easily confused when walking on hills. An
accelerometer measures the differential between leg back and leg forward, so hills do not fool the
system and no liquid slosh problem exists. The low power consumption of the accelerometer
allows the system to work with a small lithium battery, making the overall package unobtrusive.
This application is in production.
Car-Noise Cancellation. The accelerometer senses low-frequency vibration in the passenger
compartment; the noise-cancellation system nulls it out using the speakers in the stereo system.
Dream Land. While the accelerometer has no trouble picking up the vibration in the passenger
compartment, noise cancellation is highly phase dependent. While we can cancel the noise at one
location (around the head of the driver, for example), it will probably increase at other locations.
Conclusion
Because of their high sensitivity, small size, low cost, rugged packaging, and ability to measure
both static and dynamic acceleration forces, surface micromachined accelerometers have made
numerous new applications possible. Many of them were not anticipated because they were not
thought of as classic accelerometer applications. The imagination of designers now seems to be
the limiting factor in the scope of potential applicationsbut sometimes designers can become
too imaginative! While performance improvements continue to enable more applications, its
wise to try to stay away from solutions that violate the laws of physics.

by Adrian Fox [adrian.fox@analog.com]
PLL SYNTHESIZERS
Q. What is a PLL Synthesizer?

A. A frequency synthesizer allows the designer to generate a variety of
output frequencies as multiples of a single reference frequency.
The main application is in generating local oscillator (LO)
signals for the up- and down-conversion of RF signals.
The synthesizer works in a phase-locked loop (PLL), where
a phase/frequency detector (PFD) compares a fed back
frequency with a divided-down version of the reference
frequency (Figure 1). The PFDs output current pulses are
filtered and integrated to generate a voltage. This voltage drives
an external voltage-controlled oscillator (VCO) to increase or
decrease the output frequency so as to drive the PFDs average
output towards zero.
Figure 1. Block diagram of a PLL.
Frequency is scaled by the use of counters. In the example

shown, an ADF4xxx synthesizer is used with an external filter
and VCO. An input reference (R) counter reduces the reference
input frequency (13 MHz in this example) to PFD frequency
(FPFD = FREF/R); and a feedback (N) counter reduces the
output frequency for comparison with the scaled reference
frequency at the PFD. At equilibrium, the two frequencies
are equal, and the output frequency is N F PFD. The
feedback counter is a dual-modulus prescaler type, with A and B
counters (N = BP + A, where P is the prescale value).
to the power found in a 1-Hz bandwidth at a defined frequency

offset (usually 1 kHz for a synthesizer). Expressed in dBc/Hz,
the in-band (or close-in) phase noise is dominated by the
synthesizer; the VCO noise contribution is high-pass filtered
in the closed loop.
Reference Spurs: These are artifacts at discrete offset
frequencies generated by the internal counters and charge
pump operation at the PFD frequency. These spurs will
be increased by mismatched up and down currents from
the charge pump, charge-pump leakage, and inadequate
decoupling of supplies. The spurious tones will get mixed down
on top of the wanted signal and decrease receiver sensitivity.
Figure 2 shows a typical application in a superheterodyne

receiver. Base station and handset LOs are the most common
application, but synthesizers are also found in low frequency
clock generators (ADF4001), wireless LANs (5.8 GHz), radar
systems, and collision-avoidance systems (ADF4106).
Lock Time: The lock time of a PLL is the time it takes to jump
from one specified frequency to another specified frequency
within a given frequency tolerance. The jump size is normally
determined by the maximum jump the PLL will have to
accomplish when operating in its allocated frequency band.
The step-size for GSM-900 is 45 MHz and for GSM-1800
is 95 MHz. The required frequency tolerances are 90 Hz and
180 Hz, respectively. The PLL must complete the required
frequency step in less than 1.5 time slots, where each time
slot is 577 s.
Q. What are the key performance parameters to be considered in selecting

a PLL synthesizer?
A. The major ones are: phase noise, reference spurs, and
lock time.
Phase Noise: For a carrier frequency at a given power level,
the phase noise of a synthesizer is the ratio of the carrier power
Figure 2. Dual PLL used to mix down from GSM RF to baseband.

All trademarks and registered trademarks are the property of their respective holders.
Q. Ive selected my synthesizer based on the output frequency required.

What about choosing the other elements in the PLL?
A. Frequency Reference: A good, high quality, low-phase-noise
reference is crucial to a stable low-phase-noise RF output. A
square wave or clipped sine wave available from a TCXO crystal
offers excellent performance, because the sharper clocking
edge results in less phase jitter at the R-counter output. The
ADF4206 family features on-board oscillator circuitry allowing
low cost AT-cut crystals to be used as the reference. While
predictable AT crystals cost one third as much as TCXOs, their
temperature stability is poor unless a compensation scheme
with a varactor is implemented.
VCO: The VCO will convert the applied tuning voltage to
an output frequency. The sensitivity can vary drastically
over the full frequency range of the VCO. This may make the
loop unstable (see loop filter). In general, the lower the tuning
sensitivity (Kv) of the VCO, the better the VCO phase noise
will be. The synthesizer phase noise will dominate at smaller
offsets from the carrier. Farther away from the carrier, the
high-pass-filtered noise of the VCO will begin to dominate.
The GSM specification for out-of-band phase noise is
130 dBc/Hz at a 1-MHz offset.
Loop Filter: There are many different types of loop filter. The
most common is the third-order integrator shown in Figure 3.
In general, the loop filter bandwidth should be 1/10 of the PFD
frequency (channel spacing). Increasing the loop bandwidth
will reduce the lock time, but the filter bandwidth should never
be more than PFD/5, to avoid significantly increasing the risk
of instability.
Figure 3. A third-order loop filter. The R2C3 pole provides

extra attenuation for spurious products.
A loop filters bandwidth can be doubled by doubling either the
PFD frequency or the charge-pump current. If the actual Kv
of the VCO is significantly higher than the nominal Kv used to
design the loop filter, the loop bandwidth will be significantly
wider than expected. The variation of loop bandwidth with Kv
presents a major design challenge in wideband PLL designs,
where the Kv can vary by more than 300%. Increasing or
decreasing the programmable charge-pump current is the
easiest way to compensate for changes in the loop bandwidth
caused by the variation in Kv.
Use the lowest Rset resistor specified for operation: Reducing the
Rset increases the charge-pump current, which reduces phase
noise.
Table 1. The integrated phase jitter depends heavily on the
in-band phase noise of the synthesizer. System parameters:
[900-MHz RF, 200-kHz PFD, 20-kHz loop filter]
Synthesizer
Model
In-Band
Phase Noise
(dB)
Integration
Range
(Hz)
Integrated
Phase Error
Degrees rms
ADF4111
86
100 to 1 M
0.86
ADF4112
89
100 to 1 M
0.62
ADF4113
91
100 to 1 M
0.56
ADF4106
92.5
100 to 1 M
0.45
Q. Why is phase noise important?

A. Phase noise is probably the most crucial specification in PLL
selection. In a transmit chain, the linear power amplifier (PA)
is the most difficult block to design. A low-phase-noise LO
will give the designer greater margin for non-linearity in the
PA by reducing the phase error in the up-conversion of the
baseband signal.
The system maximum phase error specification for GSM
receivers/transmitters (Rx/Tx) is 5 rms. As one can see in
Table 1, the allowable PA phase-error contribution can be
significantly greater when the phase noise contributed by the
PLL is reduced.
On the receive side, low phase noise is crucial to obtaining
good receiver selectivity (the ability of the receiver to
demodulate signals in the presence of interferers). In the
example of Figure 4, on the left the desired low level signal
is swamped by a nearby undesired signal mixing with the
LO noise (enclosed dashed area). In this case the filters will
be unable to block these unwanted interferers. In order to
demodulate the desired RF signal, either the transmit side
will require higher output power, or the LO phase noise will
need to be improved.
Q. How do I optimize PLL design for phase noise?

A. Use low N-value: Since phase noise is multiplied up from the
PFD (reference frequency) at a rate of 20 logN, reducing N
by a factor of 2 will improve system phase noise by 3 dB (i.e.,
doubling the PFD frequency reduces phase noise by 10 log2).
Therefore the highest feasible PFD frequency should always
be used.
Choose a higher frequency synthesizer than is required: Operating
under the same conditions at 900 MHz, the ADF4106 will give
6-dB better phase noise than the ADF4111 (see Table 1).
Figure 4. A large unwanted signal mixing with LO noise

swamps the wanted signal. Increased phase noise will
reduce the sensitivity of the receiver, since the demodulator
will not be able to resolve the signal from the noise.
Q. Why are spur levels important?
A. Most communication standards will have stringent maximum
specifications on the level of spurious frequency components
(spurs) that the LO can generate. In transmit mode, the spur
levels must be limited to ensure that they do not interfere with
users in the same or a nearby system. In a receiver, the LO spurs
can significantly reduce the ability to demodulate the mixeddown signal. Figure 4 shows the effect of reciprocal mixing
where the desired signal is swamped with noise due to a large
undesired signal mixing with noise on the oscillator. The same
effect will occur for spurious noise components.
A high level of spurs can indirectly affect lock time by
forcing the designer to narrow the loop bandwidthslowing
responsein order to provide sufficient attenuation of these
unwanted components. The key synthesizer specifications to
ensure low reference spurs are low charge-pump leakage and
matching of the charge pump currents.
Q. Why is lock time important?
A. Many systems use frequency hopping as a means to protect data
security, avoid muti-path fading, and avoid interference. The
time spent by the PLL in achieving frequency lock is valuable
time that cannot be used for transmitting or receiving data; this
reduces the effective data rate achievable. Currently there is no
PLL available than can frequency-hop quickly enough to meet
the timing requirements of the GSM protocol. In base-station
applications, two separate PLL devices are used in parallel to
reduce the number of wasted slots. While the first is generating
the LO for the transmitter, the second PLL is moving to the
next allocated channel. In this case a super-fast (<10-s) settling
PLL would significantly reduce the bill of materials (BOM)
and layout complexity.
Q. How do I minimize lock time?
A. By increasing the PFD frequency. The PFD frequency

determines the rate at which a comparison is made between the
VCO/N and the reference signal. Increasing the PFD frequency
increases the update of the charge pump and reduces lock time.
It also allows the loop bandwidth to be widened.
Figure 5. Loop bandwidth has a significant effect on the lock

time. The wider the loop bandwidth, the faster the lock time,
but also the greater the level of spurious components. Lock
time to 1 kHz is 142 s with a 35-kHz LBWand 248 s
with a 10-kHz LBW.
Loop Bandwidth. The wider the loop bandwidth, the faster
the lock time. The trade-off is that a wider loop bandwidth
will reduce attenuation of spurious products and increase
the integrated phase noise. Increasing the loop bandwidth
significantly (>PFD/5) may cause the loop to become unstable
and permanently lose lock. A phase margin of 45 degrees
produces the optimum settling transient.
Avoid tuning voltages nearing ground or Vp. When the tuning
voltage is within a volt of the rails of the charge pump supply
(Vp), the charge pump begins to operate in a saturation region.
Operation in this region will degrade settling time significantly;

it may also result in mismatch between jumping-up in frequency
and jumping down. Operation in this saturation region can be
avoided by using the maximum Vp available or using an active
loop filter. Using a VCO with a higher Kv will allow Vtune
to remain closer to Vp/2 while still tuning over the required
frequency range.
Choose plastic capacitors. Some capacitors exhibit a dielectric
memory effect, which can impede lock time. For fast phase
locking applications plastic-film Panasonic ECHU capacitors
are recommended.
Q. What factors deter mine the maximum PFD frequency
I can use?
A. In order to obtain contiguous output frequencies in steps of
the PFD frequency
FPFD <
VCO Output Frequency

(P 2 P)
where P is the prescaler value.

The ADF4xxx offers prescaler selections as low as 8/9. This
permits a higher PFD frequency than many competitive parts,
without violating the above ruleenabling lower phase noise
PLL design. Even if this condition is not met, the PLL will lock
if B > A and B > 2 in the programming registers.
Q. Fractional-N has been around since 1970.What are its advantages
to PLL designers?
A. The resolution at the output of an integer-N PLL is limited to
steps of the PFD frequency. Fractional-N allows the resolution
at the PLL output to be reduced to small fractions of the
PFD frequency. It is possible to generate output frequencies
with resolutions of 100s of Hz, while maintaining a high PFD
frequency. As a result the N-value is significantly less than for
integer-N. Since noise at the charge pump is multiplied up
to the output at a rate of 20 logN, significant improvements
in phase noise are possible. For a GSM900 system, the
fractional-N ADF4252 offers phase noise performance of
103 dBc/Hz, compared with 93 dBc/Hz for the ADF4106
integer-N PLL.
Also offering a significant advantage is the lock-time
improvement made possible by fractional-N. The PFD
frequency set to 20 MHz and loop bandwidth of 150 kHz will
allow the synthesizer jump 30 MHz in <30 s. Current base
stations require 2 PLL blocks to ensure that LOs can meet the
timing requirements for transmissions. With the super-fast lock
times of fractional-N, future synthesizers will have lock time
specs that allow the 2 ping-pong PLLs to be replaced with
a single fractional-N PLL block.
Q. If fractional-N offers all these advantages, why are integer-N PLLs
still so popular?
A. Spurious levels! A fractional-N divide by 19.1 consists of
the N-divider dividing by nineteen 90% of the time, and
by twenty 10% of the time. The average division is correct,
but the instantaneous division is incorrect. Because of this,
the PFD and charge pump are constantly trying to correct
for instantaneous phase errors. The heavy digital activity of
the sigma-delta modulator, which provides the averaging
function, creates spurious components at the output. The
digital noise, combined with inaccuracies in matching the

hard-working charge pump, results in spurious levels greater
than those allowable by most communications standards.
Only recently have fractional-N parts, such as the ADF4252,
made the necessary improvements in spurious performance to
allow designers to consider their use in traditional integer-N
markets.
Q. What PLL devices have you released recently, how do they differ,
and where would I use them?
A. ADF4001 is a <200-MHz PLL, pin-compatible with the
popular ADF4110 series, but with the prescaler removed.
Applications are stable reference clock generators, in cases
where all clocks must be synchronized with a single reference
source. They are generally used with VCXOs (voltagecontrolled crystal oscillators), which have lower gain (Kv) and
better phase noise than VCOs.
ADF4252 is a dual fractional-N device with <70 dBc spurious.
It offers <20-s lock times vs. 250 s for integer-N, with
<100 dBc/Hz phase noise due to the high PFD frequencya
ground-breaking product with a software-programmable
trade-off between phase noise and spurs.
ADF4217L/ADF4218L/ADF4219L are low-phase-noise
upgrades for the LMX2331L/LMX2330L/LMX2370. They
consume only 7.1 mA, with a 4-dB improvement in phase noise
over competitive devices. Great news for handset designers!
ADF4106 is a 6-GHz PLL synthesizer. Ideal for WLAN
equipment in the 5.4-to-5.8-GHz frequency band, it is the
lowest-noise integer-N PLL on the market.
Q. What tools are available to simulate loop behavior?
A. ADIsimPLL is a simulation tool developed with Applied Radio
Labs. It consists of extensive models for the ADI synthesizers
as well as popular VCOs and TCXOs. It allows the user to
design passive and active loop filters in many configurations,
simulate VCO, PLL, and reference noise, and model spurious
and settling behavior. Once a design is completed, a custom
evaluation board may be ordered based on the design using an
internal weblink to Avnet.
(a)
(b)
Figure 6. Lock time and phase noise are just two parameters that can be modeled by ADIsimPLL. While phase noise
is reduced by >8 dB, the wider loop bandwidths and high
PFD frequency allowed by fractional-N reduce the lock time
to <30 s for 30-MHz jumps (as shown).
A. Phase noise is the critical specification for many system

designers. Phase-noise performance in the ADF4113 family
is typically 6 dB better than the National equivalent and
>10 dB better than Fujitsu or Philips equivalents.The extended
choice of prescaler settings protects the designer from being
compromised in selecting a higher PFD frequency by the
P2 P rule. Another major advantage is the choice of
eight programmable charge-pump currents; in wideband
designs where the gain of the VCO changes dramatically, the
programmable currents can be adjusted to ensure loop stability
and bandwidth consistency across the entire band.
Q. What is the future direction of the PLL industry?
A. While chipset solutions are prominent in the headlines,
particularly for GSM, the new generation of cellular phone
and base stations are still likely to initially favor discrete
solutions. Discrete PLL and VCO modules offer improved
noise performance and isolation, and are already in high
volume production at the start of the design cycle.
The demand for reduced size and current consumption in
handsets has driven the development of the ADI L-series of
dual synthesizers on 0.35-m Bi-CMOS in miniature CSP
packages. Integrated VCO and PLL modules will be a major
growth in newer system designs, where board area and cost
reduction of an initial design is crucial.
However the most exciting developments are likely to be
in fractional-N technology. Recent improvements in spur
performance have allowed the release of the ADF4252 and
created unprecedented interest. The phase-noise improvement,
super-fast lock times, and versatility inherent in the architecture
are likely to dominate LO blocks of future multi-standard highdata-rate wireless systems.
Acknowledgements
The author would like to thank Mike Curtin, Brendan Daly, and
Ian Collins for their valuable contributions.
(1) Fractional-N Synthesizers, (Design Feature), Microwaves and

RF, August 1999.
Q. Do ADI proprietary parts have specific advantages over comparable

competitive parts?
REFERENCES
The tool is free and may be downloaded from www.analog.com/

pll. Also widely used are the commercially available Eagleware
and MATLAB tools.
(2) Microwave and RF Wireless Systems, by David M. Pozar.

Wiley (2000).
(3) Phase locked loops for high frequency receivers and
transmitters, by Mike Curtin and Paul OBrien. Analog
Dialogue Volume 33, 1999.
(4) Phase-locked Loops, by Roland E. Best. McGraw-Hill (1993).
(5) Phase Noise Reference (Application Note), Applied
Radio Labs.
b

By Reza Moghimi [reza.moghimi@analog.com]
AMPLIFIERS AS COMPARATORS?
Q. What is a comparator? How does it differ from an op amp?
A. The basic function of a high-gain comparator is to determine
whether an input voltage is higher or lower than a reference
voltageand to present that decision as one of two voltage
levels, established by the outputs limiting values. Comparators
have a variety of uses, including: polarity identification,
1-bit analog-to-digital conversion, switch driving, square/
triangular-wave generation, and pulse-edge generation.
In principle, any high-gain amplifier can be used to perform
this simple decision. But the devil is in the details. So there
are some basic differences between devices designed as op
amps and devices designed to be comparators. For example,
for use with digital circuitry, many comparators have latched
outputs, and all are designed to have output levels compatible
with digital voltage -level specifications. There are some
more differences of importance to designersthey will be
discussed here.
In these pages, we will describe the parametric differences

between these two branches of IC amplifier technology and
provide useful hints for using an amplifier as a comparator.
Q. So how do amplifiers and comparators differ?
A. Overall, the operational amplifier (op amp) is optimized to
provide accuracy and stability (both dc and dynamic) for a
specified linear range of output values in precision closed-loop
(feedback) circuits. However, when an open-loop amplifier is
used as a comparator, with its outputs swinging between their
limits, its internal compensation capacitanceused to provide
dynamic stabilitycauses the output to be slow to come out
of saturation and slew through its output range. Comparators,
on the other hand, are generally designed to operate open
loop, with outputs slewing between specified upper and lower
voltage limits in response to the sign of the net difference
between the two inputs. Since they do not require the op amps
compensation capacitors, they can be quite fast.
If the input voltage to a comparator is more positive than the
reference voltage plus the offsetVOS (with zero reference,
its just the offset) plus the required overdrive (due to limited
gain and output nonlinearity), a voltage corresponding to
logic 1 appears at the output. The output will be at logic 0
when the input is less than VOS and the required overdrive. In
effect, a comparator can be thought of as a one-bit analogto-digital converter.
Q. What are some circumstances where one can go either way?

A. Amplifiers should be considered for use as comparators in
applications where low offset and drift, and low bias current,
are neededcombined with low cost. On the other hand, there
are many designs where an amplifier could not be considered as
a comparator because of its lengthy recovery time from output
saturation, its long propagation delay, and the inconvenience of
making its output compatible with digital logic. Additionally,
dynamic stability is a concern.
However, there are cost and performance benefits in using
amplifiers as comparatorsif their similarities and differences
are clearly understood, and the application can tolerate the
generally slower speed of amplifiers. No one can claim that an
amplifier will serve as a drop-in replacement for a comparator
in all casesbut for slow-speed situations requiring highly
precise comparison, the performance of some newer amplifiers
cannot be matched by that of comparators having greater noise
and offset. In some applications with slowly changing inputs,
noise will cause comparator outputs to slew rapidly back and
forth (see Curing comparator instability with hysteresis,
Analog Dialogue, Volume 34, 2000). In addition, there can be
savings in cost or valuable printed-circuit-board (PCB) area
in applications where a dual op amp could be used instead of
an op amp and a comparatoror in a design where three of
the four amplifiers in a quad package are already committed,
and two dc or slowly varying signals must be compared.
Q. Can that fourth amplifier be used as a comparator?
A. This is a question that many system designers are asking us
these days. It would pointless to buy a quad op amp, use only
three channels, and then buy a separate comparatorif indeed
that amplifier could be used in a simple way for the comparison
function. Be clear, though, that an amplifier cant be used
as a comparator interchangeably in all cases. For example,
if the application requires comparison of signals in less than
a microsecond, adding a comparator is probably the only
way to go. But if you understand the internal architectural
differences between an amplifier and a comparator, and
how these differences affect the performance of these ICs in
applications, you may be able to obtain the inherent efficiency
of using a single chip.
Analog Dialogue 37-April (2003)
There are different ways of specifying a comparator and an

amplifier. As an example, in an amplifier, the offset voltage
is the voltage that must be applied to the input to drive the
output to a specified mid-range value corresponding to ideal
zero input. In a comparator this definition is modified to center
in the specified voltage range between 1 and 0 at the output.
The comparators low output value (logic 0) is specified at
less than 0.4 V max in comparators with TTL -compatible
outputs, while for a low-voltage amplifier, the low output value
is very close to its negative rail (e.g., 0 V in a single-supply
system). Figure 1 compares the low output values of typical
amplifier and comparator models, with a 1-mV differential
input applied to each.
V+
V38
1V
+
U18
AMPLIFIER
V39
1.001V
VCC
VCC
VCC
62.82pV
R11
10k
V41
1V
V40
1.001V
4 +
7 U20A
V+
OUT
R12
10k
1
284.12mV
V
2 COMPARATOR
Figure 1. Responses of single-supply amplifier (63 pV)

and comparator (280 mV) models to a 1-mV inputvoltage difference.
Built to compare two levels as quickly as possible, comparators
do not have the internal compensation capacitor (Miller
capacitor) usually found in op amps, and their output circuit
is capable of more flexible excitation than that of op amps.
This absence of compensation circuitry gives comparators
very wide bandwidth. At the output, ordinary op amps use
push-pull output circuitry for essentially symmetrical swings
between the specified power supply voltages, while comparators
usually have an open- collector output with grounded
emitter. This means that the output of a comparator can be
returned through a low-value collector load resistor (pullup
resistor) to a voltage different from the main positive supply.
This feature allows the comparator to interface with a variety
of logic families. Using a low value of pull-up resistance yields

improved switching speed and noise immunitybut at the
expense of increased power dissipation.
Because comparators are rarely configured with negative
feedback, their (differential) input impedance is not multiplied
by loop gain, as is characteristic of op amp circuits. As a result,
the input signal sees a changing load and changing (small)
input current as the comparator switches. Therefore, under
certain conditions, the driving-point impedance must be
considered. While negative feedback keeps amplifiers within
their linear output region, thus maintaining little variation of
most internal operating points, positive feedback is often used
to force comparators into saturation (and provide hysteresis
to reduce noise sensitivity). A comparators input usually
accommodates large signal swings, while its output has a
limited range due to interfacing requirements, so a lot of
rapid level shifting is required within the comparator.
Each of the above differences between an amplifier and
a comparator is there for a reason, with the major goal of
comparing rapidly varying signals as quickly as possible. But,
for comparing slow-speed signalsespecially where sub-mV
resolution is requiredsome new rail-to-rail amplifiers from
Analog Devices could be better buys than comparators.
Q. OK. I can see that there are overall differences. How do
they look to the designer who wants to use an op amp to
replace a comparator?
But, for many rail-to-rail-input amplifiers, input offset voltage

(VOS ) and input bias current (IB ) are non-linear over the input
common-mode voltage range. With these amplifiers, the user
needs to take this variation into account in the design. If the
threshold is set at zero common-mode, but the part is used
at some other common-mode level, then the logic level that
results may not be as anticipated. For example, a part with
offset of 2 mV at zero common mode, and 5-to-6 mV over the
entire common mode range may give an erroneous output when
comparing a difference of 3 mV at some levels in that range.
2. Watch out for input protection diodes
Many amplifiers have protection circuitry at their inputs.

When the two inputs experience a differential voltage greater
than a nominal diode drop (say, 0.7 V), the protection diodes
start conducting and the input breaks down. Therefore, it is
critical to look at the input structure of an amplifier and make
sure that it can accommodate the expected range of input
signals. Some amplifiers, such as the OP777/OP727/OP747,
do not have protection diodes; their inputs can accommodate
differential signals up to the supply voltage levels. Figure 3
shows the response to a large differential signal at the input
of an OP777. Many amplifiers inputs break down under this
condition, while the OP777 responds correctly. CMOS-input
amplifiers do not have protection diodes at their input, and their
input differential voltage can swing rail-to-rail. But remember
that, in some cases, applying a large differential signal at the
input causes significant shifts of amplifier parameters.
A. Here are six major points:
VCC2
V
1. Consider VOS and IB non-linearity vs. input common-mode voltage
VIN
V+
AD8605
R1
100k
V6
3V
Figure 3. Response of an OP777 amplifier to a 2-V, 1-kHz

signal, biased by +2V, and compared with a +0.5-V dc level.
Note that there is no phase inversion for this large swing.
However, the gain is quite low at a common-mode level of
+0.5 V from the negative rail, as can be seen by the approximately 0.3-V overdrive that is needed.
TIME (s)
AD8605 WITH 3V
COMMON MODE
VOLTS
TIME (s)
Figure 2. Response of open-loop AD8605 to a 100-mV

differential step with 3-V common-mode voltage. Note the
essentially linear slewing between the 0- and 5-V rails, and
the clean saturation.
VOUT
R27
100k
VIN
VOUT
0.5V
V
1
V
1
U37
OP777
VOLTS
VCC
V+
When using voltage comparators, it is common practice to

ground one input terminal and use a single ended input. The
primary reason has been the poor common-mode rejection
of the input stage. In contrast, many amplifiers have very
high common mode rejection and are capable of detecting
microvolt-level differences in the presence of large commonmode signals. Figure 2 shows the response of an AD8605 op
amp to a 100-mV differential step riding on a 3-V commonmode voltage.
3. Watch out for input voltage range specs and phase-reversal

tendencies
Unlike operational amplifiers that usually operate with the

input voltages at the same level, comparators typically see
large differential voltage swings at their inputs. But some
comparators without rail-to-rail inputs are specified to have
a limited common-mode input voltage range. If the inputs
exceed a devices specified common-mode range (even though

within the specified signal range), the comparator may respond
erroneously. This may also be true for some of the older types
of amplifiers designed with junction-FET (JFET) and bipolar
technologies. As the input common-mode voltage exceeds a
certain limit (IVR), the output goes through phase inversion.
This phenomenon can be detrimental (see in Chapter 6 of Ask
the Applications Engineer,* the figure that follows the table).
Therefore, it is absolutely critical to pick an amplifier that
does not exhibit phase reversal when overdriven. This is one
type of problem that can be overcome by using amplifiers with
rail-to-rail-inputs.
4. Consider saturation recovery
Typical op amps are not designed to be used as fast comparators,

so individual gain stages will go into saturation when the
amplifier output is driven to one of its extremes, charging
the compensation capacitor and parasitic capacitances. A
design difference between amplifiers and comparators is the
addition of clamp circuitry in comparators to prevent internal
saturation. When an amplifier is pushed into saturation, it
takes time for it to recover and then slew to its new final
output valuedepending on the output structure and the
compensation circuitry. Because of the time it takes to
come out of saturation, an amplifier is slower when used as
comparator than when it is used under control in a closedloop configuration. One can find saturation - recovery
information in many amplifier data sheets. Figure 4 shows
saturation recovery plots for two popular amplifiers (AD8061
and AD8605). The output structures of these amplifiers are
standard push-pull rail-to-rail common-emitter.
5. Pay attention to factors affecting transition time
Speed is one of the distinguishing differences between amplifier

and comparator families. Propagation delay is the time it takes
for a comparator to compare two signals at its input, and for
its output to reach the midpoint between the two output
logic levels. Propagation delay is usually specified with an
overdrive, which is the voltage difference between the applied
input voltage and the reference that is required for switching
within a given time. In the following graphs, the responses
of several rail-to-rail CMOS amplifiers are compared with a
popular comparator. All amplifiers are configured as shown
in Figure 5(a-e) with applied voltage, V IN , = 0.2 V, centered
around 0 V. In the case of the comparator, a 10-k pullup is
used instead of a load to ground. The amplifier speeds differ
widely, but because of saturation and their lower slew rate, all
are much slower than the comparator.
VCC
+ V11
U12
R6
100k
Figure 5a. Amplifier circuit.

8
LM139
AD8061. OUTPUT OVERLOAD RECOVERY,

INPUT STEP = 0V TO 1V
AD8601 AD8515
SLEWING
VOLTS
VS = 2.5V
G=5
RL = 1k
VOUT
2.5V
V+
AD8541
VIN
SATURATION
REGION
VIN
1.0V
10
0V
20
40
20
25
30
25
30
Figure 5b. Positive step.
500mV/DIV
0
15
TIME (s)
60
80
100 120
TIME (ns)
140
160
180
200
AD8605. NEGATIVE OVERLOAD RECOVERY

VS = 2.5V
RL = 10k
AV = 100
VIN = 50mV
+2.5V
LM139
VOLTS
AD8601
0V
50mV
0V
AD8541
AD8515
0
VIN
2
TIME (400ns/DIV)
Figure 4. Recovery of two popular amplifiers in

closed-loop configuration.
10
15
TIME (s)
20
Figure 5c. Negative step.
*www.analog.com/library/analogDialogue/Anniversary/6.html
VCC
LM139
V+
+
V1
V
1
AD8605
2
VOLTS
AD8601
AD8541
AD8515
VIN
OVERDRIVE = 100mV
VOLTS
OVERDRIVE = 10mV
10
20
VOUT
R1
100k
30
40
OVERDRIVE = 1mV
50
TIME (s)
Figure 5d. Positive step.

6
LM139
VOLTS
AD8601
AD8515
2
VIN
10
20
30
40
50
TIME (s)
Figure 5e. Negative step.

Figure 5. Responses of comparator and three open-loop
amplifier models compared, 0.2-V drive. a. Amplifier circuit
configuration. b. Positive step. c. Negative step. Then, with
50-mV signal applied and overdrive of 20 mV. Period = 10 s.
d. Positive step. e. Negative step.
Part
Number
AD8515
AD8601
AD8541
AD8061
LM139
Supply
Current (A)
350
1,000
55
8,000
3,200
Offset
Voltage (mV)
5.00
0.05
6.00
6.00
6.00
Supply
Range (V)
1.85.0
2.75.0
2.75.0
2.78.0
5.03.6
Slew
Rate (V/s)
5
4
3
300
---
While most comparators are specified with 2 -mV to 5 -mV

overdrive, most high precision, low input offset amplifiers can
reliably operate with as little as 0.05-mV overdrive. The amount
of overdrive applied at the input has a significant effect on
propagation delay. Figure 6 shows the response of the AD8605
to several values of overdrive voltage.
50
100
150
200
TIME (s)
250
300
350
Figure 6. Response of the AD8605 as a comparator to

step inputs with overdrive of 1, 10, and 100 mV.
AD8541
As amplifiers are allowed to consume more power, their speed

improves substantially, so that they can compete with comparators
in terms of rise and fall times. Figure 7 includes an example of
thisfor an AD8061, with a 300 V/s slew rate, in an open loop
configuration responding to a sinusoidal zero crossing input,
the output recovery time is 19 ns. However, one of the biggest
drawbacks to using an amplifier as a comparator is often its power
consumption, since one can generally find comparators that draw
less supply current (ISY ), but still function well. Of course, for
instruments using line power, power consumption is usually not
a big driving factor. Besides, many amplifiers have a shutdown
pina feature rarely available in comparators; it can be used to
conserve power.
6
4
AD8061
OUTPUT
VOLTS
2
VIN
100
200
300
TIME (ns)
400
500
PROBE CURSOR
A1 = 201.409n, 45.511m
A2 = 220.423n, 4.7376
DIF = 19.014n, 4.6921
Figure 7. Response of AD8061 as a zero-crossing comparator.
In Figure 8, the AD8061s step response is compared with that

of the popular LM139, and two other open-loop amplifiers,
connected in the same circuit configuration as in Figure 6.
As can be seen, the AD8061 responds within 300 ns, which is
faster than LM139. This is achieved at the expense of higher
current consumption.
output, so that it will not go below 0.7 V, as can be seen from

waveform V(D2,2). The value of VCC of Q2 can be selected
(5 V was selected for this analysis) such that a correct logic
level results, as shown by waveform VOUT.
VCC
VCC2
R21
10k
V+
LM139
V47
U36
OP1177
V
R20
1 10k
D2
1N4148
Q2
2N3716
AD8061
4
VEE2
VOLTS
AD8601
AD8515
Figure 9. OP1177 connected for comparator operation,

with translation and protective circuitry for TTL output.
6
VIN
4
0
10
TIME (ns)
15
20
Figure 8. Step response of three amplifiers and

a popular comparator. Note the especially fast
response of the AD8061.
6. Consider the way to interface with different logic families
Many of todays rail-to-rail-output amplifiers operate with single

supply of 5 V to 15 V, which can easily provide TTL- or CMOScompatible output without the need for additional interfacing
circuitry. If the logic circuit and op amp share the same supply,
then a rail-to-rail op amp will drive CMOS and TTL logic
families quite successfully, but if the op amp and logic circuitry
need different supply levels, additional interface circuitry will be
required. For example, consider an op amp with 5 V supplies
that must drive logic with +5 V supply: Since the logic is liable
to be damaged if 5 V is applied to it, careful attention must be
paid to the design of interface circuitry.
Figure 9 shows an OP1177 (dual-supply amplifier), interfaced
to logic circuitry, and Figure 10 shows its response to 100 mV
of overdrive. With 5-V supplies, quiescent power dissipation
is lowered and thermal feedbackdue to output stage
dissipationis minimized, compared to 15-V operation.
The lower supply voltage also reduces the OP1177 rise and fall
times as the output slews over a reduced voltage rangewhich
in turn reduces the output response time.
Without the protective circuitry on the output of OP1177, the
output would swing to +VCC2 and V EE2 ; these levels might
be detrimental to downstream logic circuitry. Adding Q2 and
D2 prevents the output from going negative and translates
the limits to TTL -compatible output levels. D2 clamps the
VOUT
VOLTS
VIN
VDIODE
0
10
20
30
40
50
TIME (s)
Figure 10. Response waveforms for the OP1177

comparator circuit.
To conserve power, an N-channel MOSFET may be used instead
of the NPN transistor shown in Figure 9.
Q. So the bottom line is...
A. An amplifier can be used as a comparator with excellent
precision at low frequencies. In fact, for comparing signals
with microvolt-level resolution, precision amplifiers are the
only practical choice. They can also be an economical choice
for multiple-channel op amp users when employment of free
amplifier channels to satisfy comparator requirements is
feasible. Savvy designers can save money while optimizing their
designs if they take the trouble to: understand the similarities
and differences between amplifiers and comparators; read the
amplifiers data sheet for the right features; understand about
trade-offs in recovery time, speed, and power consumption;
and are willing to verify designs with amplifiers configured
as comparators.
b
Ask The Application Engineer32

Practical Techniques to Avoid
Instability Due to Capacitive Loading
By Soufiane Bendaoud [soufiane.bendaoud@analog.com]
Giampaolo Marino [giampaolo.marino@analog.com]
The 20 dB/decade slope and 90 lag contributed by the pole,

added to the 20 dB slope and 90 contributed by the amplifier
(plus any other existing lags), results in an increase in the rate of
closure (ROC) to a value of at least 40 dB per decade, which, in
turn, causes instability.
This note discusses typical questions about the effects of capacitive
loads on the performance of some amplifier circuits, and suggests
techniques to solve the instability problems they raise.
Q : ADI has published a lot of information on dealing with capacitive

loading and other stability issues in books, such as the amplifier
seminar series, in earlier issues of Analog Dialogue, and in some
design tools. But, I need a refresherNOW.
R1
R2
ROUT
A : OK. Here goes!
Capacitive loads often give rise to problems, in part because

they can reduce the output bandwidth and slew rate, but mainly
because the phase lag they produce in the op amps feedback
loop can cause instability. Although some capacitive loading is
inevitable, amplifiers are often subjected to sufficient capacitive
loading to cause overshoots, ringing, and even oscillation. The
problem is especially severe when large capacitive loads, such
as LCD panels or poorly terminated coaxial cables, must be
drivenbut unpleasant surprises in precision low-frequency
and dc applications can result as well.
As will be seen, the op amp is most prone to instability when it
is configured as a unity-gain follower, either because (a) there is
no attenuation in the loop, or (b) large common-mode swings,
though not substantially affecting accuracy of the signal gain, can
modulate the loop gain into unstable regions.
The ability of an op amp to drive capacitive loads is affected by
several factors:
1. the amplif iers internal architecture (for example,
output impedance, gain and phase margin, internal
compensation circuitry)
2. the nature of the load impedance
3. attenuation and phase shift of the feedback circuit,
including the effects of output loads, input impedances,
and stray capacitances.
Among the parameters cited above, the amplifier output
impedance, represented by the output resistance, RO , is the one
factor that most affects performance with capacitive loads. Ideally,
an otherwise stable op amp with RO = 0 will drive any capacitive
load without phase degradation.
To avoid sacrificing performance with light loads, most amplifiers
are not heavily compensated internally for substantial capacitive
loads, so external compensation techniques must be used to
optimize those applications in which a large capacitive load at
the output of the op amp must be handled. Typical applications
include sample-and-hold amplifiers, peak detectors, and driving
unterminated coaxial cables.
Capacitive loading, as shown in Figures 1 and 2, affects the openloop gain in the same way, regardless of whether the active input is
at the noninverting or the inverting terminal: the load capacitance,
CL , forms a pole with the open-loop output resistance, RO. The
loaded gain can be expressed as follows:
Aloaded
Figure 1. A simple op amp circuit with capacitive load.

dB
AO
|A|
Analog Dialogue 38-06, June (2004)
|ALOADED|
1 + R2/R1
f (LOG SCALE)
fP
fT
Figure 2. Bod plot for the circuit of Figure 1.

Q : So, different circuits call for different techniques?
A : Yes, absolutely! Youll choose the compensation technique
that best suits your design. Some examples are detailed
below. For example, heres a compensation technique that
has the added benefit of filtering the op amps noise via an
RC feedback circuit.
VIN
RX
ROUT
+
VA
VOUT
CL
RL
CF
B
RIN
RF
Figure 3. In-the-loop compensation circuit.

Figure 3 shows a commonly used compensation technique, often
dubbed in-the-loop compensation. A small series resistor, R x ,
is used to decouple the amplifier output from CL ; and a small
capacitor, Cf, inserted in the feedback loop, provides a high
frequency bypass around CL .
To better understand this technique, consider the redrawn
feedback portion of the circuit shown in Figure 4. VB is connected
to the amplifiers minus input.
VA
ROUT
1
1
= A
, where f p =
f
R
2
OCL
1 + j
fp
RX
CL
and A is the unloaded open-loop gain of the amplifier.
CL
CF
RF
VB
RIN
Figure 4. Feedback portion of the circuit.
http://www.analog.com/analogdialogue
Think of the capacitors, Cf and CL , as open circuits at dc, and

shorts at high frequencies. With this in mind, and referring to
the circuit in Figure 4, lets apply this principle to one capacitor
at a time.
Case 1 (Figure 5a):
With Cf shorted, R x <<Rf , and Ro <<Rin , the pole and zero are
functions of CL , Ro , and Rx.
VA
ROUT
VB
RX
CL
Although this method helps prevents oscillation when heavy

capacitive loads are used, it reduces the closed-loop circuit
bandwidth drastically. The bandwidth is no longer determined
by the op amp, but rather by the external components, Cf and Rf,
producing a closed-loop bandwidth of: f3 dB = 1/(2Cf Rf ).
A good, practical example of this compensation technique can
be seen with the AD8510, an amplifier that can safely drive up
to 200 pF while still preserving a 45 phase margin at unity-gain
crossover. With the AD8510 in the circuit of Figure 3, configured
for a gain of 10, with a 1-nF load capacitance at the output and
a typical output impedance of 15 ohms, the values of Rx and Cf,
computed using the above formulas, are 2 ohms and 2 pF. The
square wave responses of Figures 6 and 7 show the fast response
with uncompensated ringing, and the slower, but monotonic
corrected response.
Figure 5a. Cf short-circuited.
RL = 10k
CL = 1nF
Thus,
Pole Frequency =
1
2 ( RO + RX )CL
and
Zero Frequency =
1
2RX CL
Case 2. (Figure 5b)
With CL open, the pole and zero are a function of Cf.

VA
ROUT
CF
CH2 1.00V
M 10.0s
Figure 6. AD8510 output response without compensation.
RX
RF
CL
RL = 10k
CL = 1nF
VB
RIN
Figure 5b. CL open-circuited.

Thus,
Pole Frequency =
Zero Frequency =
[(
2 RX + R f || ( RO + Rin ) C f
1
2 RX + R f C f
By equating the pole in Case 1 to the zero in Case 2, and the

pole in Case 2 to the zero in Case 1, we derive the following
two equations:
RX =
RO Rin
and
Rf
1 R f + Rin
CL RO
C f = 1 +
Acl R f 2
The formula for Cf includes the term, Acl (amplifier closed-loop

gain, 1+Rf/Rin). By experimenting, it was found that the 1/Acl term
needed to be included in the formula for Cf. For the above circuit,
these two equations alone will allow compensation for any op amp
with any applied capacitive load.
CH2 1.00V
M 10.0s
Figure 7. AD8510 output response with compensation.

In Figure 7, note that, because Rx is inside the feedback loop, its
presence does not degrade the dc accuracy. However, Rx should
always be kept suitably small to avoid excessive output swing
reduction and slew-rate degradation.
Caution: The behaviors discussed here are typically experienced
with the commonly used voltage-feedback amplifiers. Amplifiers
that use current feedback require different treatmentbeyond
the scope of this discussion. If these techniques are used with
a current feedback amplifier, the integration inherent in Cf will
cause instability.
Out-of-the-Loop Compensation
Q : Is there a simpler compensation scheme that uses fewer components?

A : Yes, the easiest way is to use a single external resistor in series
with the output. This method is effective but costly in terms
of performance (Figure 8).
3
+
VIN
4
V+
Snubber Network
Q : If Im using a rail-to-rail amplifier, can you suggest a stabilizing method

that will preserve my output swing and maintain gain accuracy?
VCC
2
The output signal will be attenuated by the ratio of the series

resistance to the total resistance. This will require a wider amplifier
output swing to attain full-scale load voltage. Nonlinear or variable
loads will affect the shape and amplitude of the output signal.
RSERIES
RL
11
VOUT
CL
A : Yes, with an R-C series circuit from output to ground, the

snubber method is recommended for lower voltage applications,
where the full output swing is needed (Figure 11).
VEE
VCC
Figure 8. External Rseries isolates the amplifiers feedback

loop from the capacitive load.
Here a resistor, R series, is placed between the output and the
load. The primary function of this resistor is to isolate the opamp output and feedback network from the capacitive load.
Functionally, it introduces a zero in the transfer function of the
feedback network, which reduces the loop phase shift at higher
frequencies. To ensure a good level of stability, the value of R series
should be such that the zero added is at least a decade below the
unity-gain crossover bandwidth of the amplifier circuit. The
required amount of series resistance depends primarily on the
output impedance of the amplifier used; values ranging from
5 ohms to 50 ohms are usually sufficient to prevent instability.
Figure 9 shows the output response of the OP1177 with a 2-nF
load and a 200-mV peak-peak signal at its positive input. Figure
10 shows the output response under the same conditions, but with
a 50-ohm resistor in the signal path.
RL = 10k
CL = 2nF
CH1 200mV
M 10.0s
Figure 9. Output response of follower-connected OP1177

with capacitive load. Note high frequency ringing.
V+
V
RL
VIN
VEE
Figure 11. The RS-CS load forms a snubber circuit to

reduce the phase shift caused by CL.
Depending on the capacitive load, application engineers usually
adopt empirical methods to determine the correct values for Rs
and Cs. The principle here is to resistively load down the output
of the amplifier for frequencies in the vicinity at which peaking
occursthus snubbing down the amplifiers gain, then use
series capacitance to decrease the loading at lower frequencies.
So, the procedure is to: check the amplifiers frequency response
to determine the peaking frequency; then, experimentally apply
values of resistive loading (Rs) to reduce peaking to a satisfactory
value; then, compute the value of Cs for a break frequency at
about 1/3 the peak frequency. Thus, Cs = 3/(2fpRs), where fp is
the frequency at which peaking occurs.
These values can also be determined by trial and error while
looking at the transient response (with capacitive loading) on an
oscilloscope. The ideal values for Rs and Cs will yield minimum
overshoot and undershoot. Figure 12 shows the output response
of the AD8698 with a 68-nF load in response to a 400-mV signal
at its positive input. The overshoot here is less than 25% without
any external compensation. A simple snubber network reduces the
overshoot to less than 10%, as seen in Figure 13. In this case, Rs
and Cs are 30 ohms and 5 nF, respectively.
CL = 60nF
A = +1
RL = 10k
CL = 2nF
CH1 200mV
CL
CS
VOUT
RS
M 10.0s
Figure 10. OP1177 output response with 50-ohm series

resistance. Note reduced ringing.
CH1 100mV
M 10.0s
Figure 12. AD8698 output response without compensation.
To cure the instability induced by C1, a capacitor, C f, can be

connected in parallel with R 2 , providing a zero which can be
matched with the pole, fp , to lower the rate of closure, and
thus increase the phase margin. For a phase margin of 90,
pick C f =(R1/R 2 ) C1.
CL = 60nF
A = +1
Figure 15 shows the frequency response of the AD8605 in the

configuration of Figure 14.
30
1/ WITHOUT CF
20
1/ WITH CF
M 10.0s
CH1 100mV
Figure 13. AD8698 output response with snubber network.
GAIN (dB)
10
10
Q : OK. I understand these examples about dealing with capacitive

loading on the amplifier output. Now, is capacitance at the input
terminals also of concern?
CLOSED LOOP GAIN

WITH CF
20
CLOSED LOOP GAIN
WITHOUT CF
A : Yes, capacitive loading at the inputs of an op amp can cause

stability problems. Well go through a few examples.
A very common and typical application is in current-to-voltage
conversion when the op amp is used as a buffer/amplifier for a
current-output DAC. The total capacitance at the input consists
of the DAC output capacitance, the op amp input capacitance,
and the stray wiring capacitance.
Another popular application in which significant capacitance
may appear at the inputs of the op amp is in filter design. Some
engineers may put a large capacitor across the inputs (often in
series with a resistor) to prevent RF noise from propagating
through the amplifieroverlooking the fact that this method
can lead to severe ringing or even oscillation.
To better understand what is going on in a representative case,
we analyze the circuit of Figure 14, unfolding the equivalent of
its feedback circuit (input, Vin , grounded) to derive the feedback
transfer function:
VB
R1
(= ) =
VA
( RO + R2 ) (1 + sR1 C1 ) + R1
R1 + R2 + RO
2 R1 C1 ( R2 + RO )
CF
VIN
R1
10k VB
C1
12pF
ROUT
ROUT
VA
VOUT
R2
10k
VB
R1
10k
C1
12pF
Figure 14. Capacitive loading at the

inputinverting configuration.
This function indicates that the noise gain (1/) curve rises at
20 dB/decade above the break frequency, fp. If fp is well below the
open-loop unity-gain frequency, the system becomes unstable.
This corresponds to a rate of closure of about 40 dB/decade.
The rate of closure is defined as the magnitude of the difference
between slopes of the open-loop gain (dB) plot (20 dB/decade at
most frequencies of interest) and that of 1/, in the neighborhood
of the frequency at which they cross (loop gain = 0 dB).
30kHz
100kHz
300kHz
1MHz
FREQUENCY
3MHz
10MHz
Figure 15. Frequency response of Figure 14.

Q : Can I predict what the phase margin would be, or how much peaking
I should expect?
A : Yes, heres how:
You can determine the amount of uncompensated peaking using
the following equation:
Q=
fu
1
, where fz =
fz
2 R1 R2 C1
where fu is the unity gain bandwidth, fz is the breakpoint of the 1/

curve, and C1 is the total capacitanceinternal and external
including any parasitic capacitance.
The phase margin (m) can be determined with the following
equation:
The AD8605 has a total input capacitance of approximately

7 pF. Assuming the parasitic capacitance is about 5 pF, the
closed-loop gain will have a severe peaking of 5.5 dB, using
the above equation. In the same manner, the phase margin is
about 29 , a severe degradation from the op amps natural phase
response of 64 .
VA
R2
10k
30
10kHz
1
1
m = cos1 1 +
4
4Q
2Q2
which gives a pole located at

fp =
Q : How can I make sure the op amp circuit is stable if I want to use an
RC filter directly at the input?
A : You can use a similar technique to that described above. Heres
an example:
It is often desirable to use capacitance to ground from an
amplifiers active input terminals to reduce high-frequency
interference, RFI and EMI. This filter capacitor has a similar
effect on op amp dynamics as increased stray capacitance. Since
not all op amps behave in the same way, some will tolerate less
capacitance at the input than others. So, it is useful in any event,
to introduce a feedback capacitor, Cf, as compensation. For further
RFI reduction, a small series resistor at the amplifier terminal
will combine with the amplifiers input capacitance for filtering at
radio frequencies. Figure 16 shows an approach (at left), that will
have difficulty maintaining stability, compared with a considerably
improved circuit (at right). Figure 17 shows their superimposed

square wave responses.
CF
12pF
VCC
R1
10k
VIN
C1
12pF
B
R5
5k
V
U17
R2
10k
AD8605
R2
5k 2
VIN
V+
V
U18
R3
5k
C1
24pF
AD8605
V+
A
VEE
Figure 16. Input filter without (at left), and with (at right)
compensation and lower impedance levels.
120
In Figure 18, R B and R A provide enough closed-loop gain at high

frequencies to stabilize the amplifier, and C1 brings it back to unity
at low frequencies and dc. Calculating the values of R B and R A is
fairly straightforward, based on the amplifiers minimum stable
gain. In the case of the OP37, the amplifier needs a closed-loop
gain of at least 5 to be stable, so R B = 4R A for = 1/5. For high
frequencies, where C1 behaves like a direct connection, the op
amp thinks its operating at a closed-loop gain of 5, and is therefore
stable. At dc and low frequencies, where C1 behaves like an open
circuit, there is no attenuation of negative feedback, and the circuit
behaves like a unity-gain follower.
The next step is to calculate the value of capacitance, C1. A good
value for C1 should be picked such that it will provide a break
frequency at least a decade below the circuits corner frequency
(f3 dB).
C1 =
80
(mV)
40
Figure 19 shows the output of the OP37 in response to a 2-V p-p

input step. The values of the compensation components are chosen
using the equations above, with fc = 16 MHz
40
RB = 10 k
RA = RB 4 = 2. k
80
120
1
f
2 RA c
10
C1 = 1 (2 2.5E3 16 E 6 10) = 39 pF
5
10
15
TIME (s)
20
25
30
Figure 17. Comparison of output responses of the

circuits in Figure 16. The circuit at left resulted in the
oscillatory response.
Q : You mentioned earlier that stray capacitance is added to the total
input capacitance. How important is stray capacitance?
A : Unsuspected stray capacitance can have a detrimental impact
on the stability of the op amp. It is very important to anticipate
and minimize it.
The board layout can be a major source of stray input capacitance.
This capacitance occurs at the input traces to the summing junction
of the op amp. For example, one square centimeter of a PC board,
with a ground plane surrounding it, will produce about 2.8 pF of
capacitance (depending on the thickness of the board).
To reduce this capacitance: Always keep the input traces as short as
possible. Place the feedback resistor and the input source as close
as possible to the op amp input. Keep the ground plane away from
the op amp, especially the inputs, except where it is needed for
the circuit and the noninverting pin is grounded. When ground
is really needed, use a wide trace to ensure a low resistance path
to ground.
Q : Can op amps that arent unity-gain stable be used at unity-gain?
The OP37 is a great amplifier, but it must be used in a gain of at
least 5 to be stable.
A : You can use such op amps for lower gains by tricking them.
Figure 18 shows a useful approach.
RB
C1
VIN
RA
OP37
VOUT
Figure 18. Unity-gain follower using an input series R-C

to stabilize an amplifier that is not stable at unity-gain.
VIN
1
UNCOMPENSATED
R2
COMPENSATED
R3
CH1 5.00V
CH2 5.00V
M 20.0s
A CH1
100mV
Figure 19. Unity-gain response of the OP37 with and without

compensation.
Q : Can this approach also be used for the inverting configuration? Can
I still use the same equations?
A : For the inverting configuration, the analysis is similar, but
the equations for the closed-loop gain are slightly different.
Remember that the input resistor to the inverting terminal of
the op amp is now in parallel with R A at high frequencies. This
parallel combination is used to calculate the value of R A for
minimum stable gain. The capacitance value, C1, is calculated
in the same way as for the noninverting case.
Q : Are there drawbacks to using this technique?
A : Indeed, there are. Increasing the noise gain will increase
the output noise level at higher frequencies, which may
not be tolerable in some applications. Care should be used
in wiring, especially with high source impedance, in the
follower configuration. The reason is that positive feedback via
capacitance to the amplifiers noninverting input at frequencies
where the gain is greater than unity, can invite instability, as
well as increased noise.
b

All About Direct Digital Synthesis
By Eva Murphy [eva.murphy@analog.com]
Colm Slattery [colm.slattery@analog.com]
What is Direct Digital Synthesis?
Direct digital synthesis (DDS) is a method of producing an analog

waveformusually a sine waveby generating a time-varying
signal in digital form and then performing a digital-to-analog
conversion. Because operations within a DDS device are primarily
digital, it can offer fast switching between output frequencies,
fine frequency resolution, and operation over a broad spectrum
of frequencies. With advances in design and process technology,
todays DDS devices are very compact and draw little power.
Why would one use a direct digital synthesizer (DDS)? Arent

there other methods for easily generating frequencies?
The ability to accurately produce and control waveforms of various

frequencies and profiles has become a key requirement common to
a number of industries. Whether providing agile sources of lowphase-noise variable-frequencies with good spurious performance
for communications, or simply generating a frequency stimulus in
industrial or biomedical test equipment applications, convenience,
compactness, and low cost are important design considerations.
Many possibilities for frequency generation are open to a designer,
ranging from phase-locked-loop (PLL)-based techniques for very
high-frequency synthesis, to dynamic programming of digital-toanalog converter (DAC) outputs to generate arbitrary waveforms
at lower frequencies. But the DDS technique is rapidly gaining
acceptance for solving frequency- (or waveform) generation
requirements in both communications and industrial applications
because single-chip IC devices can generate programmable analog
output waveforms simply and with high resolution and accuracy.
Furthermore, the continual improvements in both process
technolog y and design have resulted in cost and power
consumption levels that were previously unthinkably low. For
example, the AD9833, a DDS-based programmable waveform
generator (Figure 1), operating at 5.5 V with a 25-MHz clock,
consumes a maximum power of 30 milliwatts.
VDD
How does a DDS device create a sine wave?
Heres a breakdown of the internal circuitry of a DDS device:

its main components are a phase accumulator, a means of phaseto-amplitude conversion (often a sine look-up table), and a DAC.
These blocks are represented in Figure 3.
TUNING
WORD M
PHASE
ACCUMULATOR
10
VOUT
COMP 2
AGND
FSYNC
SCLK
SDATA
DGND 4
5
AD9833
10 PIN
SOIC
PHASE-TOAMPLITUDE
CONVERTER
D/A
CONVERTER
fOUT
PHASE
REGISTER
Figure 3. Components of a direct digital synthesizer.

SPI
INTERFACE
Figure 1. The AD9833a one-chip waveform generator.
What are the main benefits of using a DDS?
DDS devices like the AD9833 are programmed through a high

speed serial peripheral-interface (SPI), and need only an external
clock to generate simple sine waves. DDS devices are now available
that can generate frequencies from less than 1 Hz up to 400 MHz
(based on a 1-GHz clock). The benefits of their low power, low
cost, and single small package, combined with their inherent
excellent performance and the ability to digitally program (and reprogram) the output waveform, make DDS devices an extremely
attractive solutionpreferable to less-flexible solutions comprising
aggregations of discrete elements.
What kind of outputs can I generate with a typical DDS device?
DDS devices are not limited to purely sinusoidal outputs.

Figure 2 shows the square-, triangular-, and sinusoidal outputs
available from an AD9833.
Analog Dialogue 38-08, August (2004)
14 TO
16 BITS
24 TO
48 BITS
SYSTEM
CLOCK
CAP/2.5V 3
MCLK
Figure 2. Square-, triangular-, and sinusoidal

outputs from a DDS.
A DDS produces a sine wave at a given frequency. The

frequency depends on two variables, the reference-clock
frequency and the binar y number programmed into the
frequency register (tuning word).
The binary number in the frequency register provides the
main input to the phase accumulator. If a sine look-up table
is used, the phase accumulator computes a phase (angle)
address for the look-up table, which outputs the digital
value of amplitudecorresponding to the sine of that phase
angleto the DAC. The DAC, in turn, converts that number
to a corresponding value of analog voltage or current. To
generate a fixed-frequency sine wave, a constant value (the
phase incrementwhich is determined by the binary number)
is added to the phase accumulator with each clock cycle. If
the phase increment is large, the phase accumulator will step
quickly through the sine look-up table and thus generate a
high frequency sine wave. If the phase increment is small, the
phase accumulator will take many more steps, accordingly
generating a slower waveform.
What do you mean by a complete DDS?
where:
The integration of a D/A converter and a DDS onto a single chip is

commonly known as a complete DDS solution, a property common
to all DDS devices from ADI.
fOUT = output frequency of the DDS

M = binary tuning word
fC = internal reference clock frequency (system clock)
Lets talk some more about the phase accumulator. How does it work?
Continuous-time sinusoidal signals have a repetitive angular phase

range of 0 to 2. The digital implementation is no different. The
counters carry function allows the phase accumulator to act as a
phase wheel in the DDS implementation.
To understand this basic function, visualize the sine-wave oscillation
as a vector rotating around a phase circle (see Figure 4). Each
designated point on the phase wheel corresponds to the equivalent
point on a cycle of a sine wave. As the vector rotates around the
wheel, visualize that the sine of the angle generates a corresponding
output sine wave. One revolution of the vector around the phase
wheel, at a constant speed, results in one complete cycle of the
output sine wave. The phase accumulator provides the equally
spaced angular values accompanying the vectors linear rotation
around the phase wheel. The contents of the phase accumulator
correspond to the points on the cycle of the output sine wave.
n = length of the phase accumulator, in bits

Changes to the value of M result in immediate and phase-continuous
changes in the output frequency. No loop settling time is incurred
as in the case of a phase-locked loop.
As the output frequency is increased, the number of samples per
cycle decreases. Since sampling theory dictates that at least two
samples per cycle are required to reconstruct the output waveform,
the maximum fundamental output frequency of a DDS is fC /2.
However, for practical applications, the output frequency is
limited to somewhat less than that, improving the quality of the
reconstructed waveform and permitting filtering on the output.
When generating a constant frequency, the output of the phase
accumulator increases linearly, so the analog waveform it generates
is inherently a ramp.
Then how is that linear output translated into a sine wave?
JUMP SIZE
fO =
M fC
2N
0000...0
1111...1
A phase -to - amplitude lookup table is used to convert the

phase-accumulators instantaneous output value (28 bits for
AD9833)with unneeded less-significant bits eliminated by
truncationinto the sine-wave amplitude information that is
presented to the (10 -bit) D/A converter. The DDS architecture
exploits the symmetrical nature of a sine wave and utilizes mapping
logic to synthesize a complete sine wave from one-quarter-cycle of
data from the phase accumulator. The phase-toamplitude lookup
table generates the remaining data by reading forward then back
through the lookup table. This is shown pictorially in Figure 5.
REF
CLOCK
DDS CIRCUITRY
NUMBER OF POINTS
8
12
16
20
24
28
32
48
256
4096
65535
1048576
16777216
268435456
4294967296
281474976710656
Figure 4. Digital phase wheel.

The phase accumulator is actually a modulo- M counter that
increments its stored number each time it receives a clock pulse.
The magnitude of the increment is determined by the binarycoded input word (M). This word forms the phase step size
between reference-clock updates; it effectively sets how many
points to skip around the phase wheel. The larger the jump size,
the faster the phase accumulator overflows and completes its
equivalent of a sine-wave cycle. The number of discrete phase
points contained in the wheel is determined by the resolution of the
phase accumulator (n), which determines the tuning resolution
of the DDS. For an n = 28-bit phase accumulator, an M value of
0000...0001 would result in the phase accumulator overflowing
after 228 reference-clock cycles (increments). If the M value is
changed to 0111...1111, the phase accumulator will overflow
after only 2 reference-clock cycles (the minimum required by
Nyquist). This relationship is found in the basic tuning equation
for DDS architecture:
fOUT =
2
M fC
2n
PHASE
ACCUMULATOR
TUNING WORD
SPECIFIES OUTPUT
FREQUENCY AS A
FRACTION OF REF
CLOCK FREQUENCY
AMPLITUDE/SINE
CONV. ALGORITHM
IN DIGITAL
DOMAIN
D/A
CONVERTER
SIN (x)/x
Figure 5. Signal flow through the DDS architecture.
What are popular uses for DDS?
Applications currently using DDS-based waveform generation

fall into two principal categories: Designers of communications
systems requiring agile (i.e., immediately responding) frequency
sources with excellent phase noise and low spurious performance
often choose DDS for its combination of spectral performance and
frequency-tuning resolution. Such applications include using a
DDS for modulation, as a reference for a PLL to enhance overall
frequency tunability, as a local oscillator (LO), or even for direct
RF transmission.
Alternatively, many industrial and biomedical applications use a
DDS as a programmable waveform generator. Because a DDS is
digitally programmable, the phase and frequency of a waveform
can be easily adjusted without the need to change the external
components that would normally need to be changed when using
traditional analog-programmed waveform generators. DDS
permits simple adjustments of frequency in real time to locate
resonant frequencies or compensate for temperature drift. Such
What do you consider to be the key advantages of DDS to designers of real-world equipment and systems?
Todays cost- competitive, high - performance, functionally

integrated DDS ICs are becoming common in both communication
systems and sensor applications. The advantages that make them
attractive to design engineers include:
digitally controlled micro-hertz frequency-tuning and subdegree phase-tuning capability,
extremely fast hopping speed in tuning output frequency
(or phase); phase - continuous frequency hops with no

overshoot/undershoot or analog-related loop settling-time
anomalies,
the digital architecture of DDS eliminates the need for the

manual tuning and tweaking related to component aging and
temperature drift in analog synthesizer solutions, and
the digital control interface of the DDS architecture facilitates
an environment where systems can be remotely controlled and

optimized with high resolution under processor control.
How would I use a DDS device for FSK encoding?
Binary frequency-shift keying (usually referred to simply as FSK) is

one of the simplest forms of data encoding. The data is transmitted
by shifting the frequency of a continuous carrier to one of two
discrete frequencies (hence binary). One frequency, f 1, (perhaps
the higher) is designated as the mark frequency (binary one) and
the other, f 0, as the space frequency (binary zero). Figure 6 shows
an example of the relationship between the mark-space data and
the transmitted signal.
DATA
TIME
SIGNAL AMPLITUDE
t
f0
MARK
f1
SPACE
Figure 6. FSK modulation.

This encoding scheme is easily implemented using a DDS. The
DDS frequency tuning word, representing the output frequencies,
is set to the appropriate values to generate f 0 and f 1 as they occur
in the pattern of 0s and 1s to be transmitted. The user programs
the two required tuning words into the device before transmission.
In the case of the AD9834, two frequency registers are available
to facilitate convenient FSK encoding. A dedicated pin on the
device (FSELECT) accepts the modulating signal and selects
the appropriate tuning word (or frequency register). The block
diagram in Figure 7 demonstrates a simple implementation of
FSK encoding.
DATA
1
0
TUNING
WORD #1
TUNING
WORD #2
MUX
applications include using a DDS in adjustable frequency sources to

measure impedance (for example in an impedance-based sensor),
to generate pulse-wave modulated signals for micro-actuation, or
to examine attenuation in LANs or telephone cables.
DDS
DAC
FSK
CLOCK
Figure 7. A DDS-based FSK encoder.
And how about PSK coding?
Phase-shift keying (PSK) is another simple form of data encoding.

In PSK, the frequency of the carrier remains constant and the phase
of the transmitted signal is varied to convey the information.
Of the schemes to accomplish PSK, the simplest-known as binary
PSK (BPSK)uses just two signal phases, 0 degrees and 180 degrees.
BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift
for a logic 0 input. The state of each bit is determined according
to the state of the preceding bit. If the phase of the wave does not
change, the signal state stays the same (low or high). If the phase
of the wave reverses (changes by 180 degrees), then the signal state
changes (from low to high, or from high to low).
PSK encoding is easily implemented with DDS ICs. Most of the
devices have a separate input register (a phase register) that can
be loaded with a phase value. This value is directly added to the
phase of the carrier without changing its frequency. Changing
the contents of this register modulates the phase of the carrier,
thus generating a PSK output signal. For applications that
require high speed modulation, the AD9834 allows the preloaded
phase registers to be selected using a dedicated toggling input
pin (PSELECT), which alternates between the registers and
modulates the carrier as required.
More sophisticated forms of PSK employ four- or eight- wave
phases. This allows binary data to be transmitted at a faster rate
per phase change than is possible with BPSK modulation. In fourphase modulation (quadrature PSK or QPSK), the possible phase
angles are 0, +90, 90, and 180 degrees; each phase shift can
represent two signal elements. The AD9830, AD9831, AD9832,
and AD9835 provide four phase registers to allow complex phase
modulation schemes to be implemented by continuously updating
different phase offsets to the registers.
Can multiple DDS devices be synchronized for, say, I-Q capability?
It is possible to use two single DDS devices that operate on the

same master clock to output two signals whose phase relationship
can then be directly controlled. In Figure 8, two AD9834s are
programmed using one reference clock, with the same reset pin
being used to update both parts. Using this setup, it is possible
to do I-Q modulation.
MCLK
AD9834
RESET
AD9834
PHASE
SHIFT
Figure 8. Multiple DDS ICs in synchronous mode.
A reset must be asserted after power-up and prior to transferring

any data to the DDS. This sets the DDS output to a known
phase, which serves as the common reference point that allows
synchronization of multiple DDS devices. When new data is
sent simultaneously to multiple DDS units, a coherent phase
relationship can be maintained, and their relative phase offset
can be predictably shifted by means of the phase-offset register.
The AD9833 and AD9834 have 12 bits of phase resolution, with
an effective resolution of 0.1 degree. [For further details on
synchronizing multiple DDS units please see Application Note
AN-605.]
What are the key performance specs of a DDS based system?

Phase noise, jitter, and spurious-free dynamic range (SFDR).
Phase noise is a measure (dBc/Hz) of the short-term frequency

instability of the oscillator. It is measured as the single-sideband
noise resulting from changes in frequency (in decibels below the
amplitude at the operating frequency of the oscillator using a
1-Hz bandwidth) at two or more frequency displacements from
the operating frequency of the oscillator. This measurement
has particular application to performance in the analog
communications industry.
Do DDS devices have good phase noise?
Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal
in a DDS system; and phase truncation may introduce an error level
into the system, depending on the code word chosen. For a ratio
that can be exactly expressed by a truncated binary-coded word,
there is no truncation error. For ratios requiring more bits than
are available, the resulting phase noise truncation error results
in spurs in a spectral plot. Their magnitudes and distribution
depends on the code word chosen. The DAC also contributes
to noise in the system. DAC quantization or linearity errors will
result in both noise and harmonics. Figure 9 shows a phase noise
plot for a typical DDS devicein this case an AD9834.
100
AVDD = DVDD = 3V
TA = 25C
110
dBc/Hz
120
130
140
150
160
100
1k
10k
FREQUENCY (Hz)
100k 200k
Figure 9. Typical output phase noise plot for the AD9834.

Output frequency is 2 MHz and M clock is 50 MHz.
What about jitter?
Jitter is the dynamic displacement of digital signal edges from

their long-term average positions, measured in degrees rms. A
perfect oscillator would have rising and falling edges occurring
at precisely regular moments in time and would never vary.
This, of course, is impossible, as even the best oscillators are
constructed from real components with sources of noise and other
imperfections. A high-quality, low-phase-noise crystal oscillator
will have jitter of less than 35 picoseconds (ps) of period jitter,
accumulated over many millions of clock edges
Jitter in oscillators is caused by thermal noise, instabilities in
the oscillator electronics, external interference through the
power rails, ground, and even the output connections. Other
influences include external magnetic or electric fields, such as
RF interference from nearby transmitters, which can contribute
jitter affecting the oscillators output. Even a simple amplifier,
inverter, or buffer will contribute jitter to a signal.
Thus the output of a DDS device will add a certain amount of
jitter. Since every clock will already have an intrinsic level of jitter,
choosing an oscillator with low jitter is critical to begin with.
Dividing down the frequency of a high-frequency clock is one
way to reduce jitter. With frequency division, the same amount
of jitter occurs within a longer period, reducing its percentage
of system time.
In general, to reduce essential sources of jitter and avoid
introducing additional sources, one should use a stable reference
clock, avoid using signals and circuits that slew slowly, and use
the highest feasible reference frequency to allow increased
oversampling.
Spurious - Free Dynamic Range (SFDR) refers to the
ratio (measured in decibels) between the highest level of the
fundamental signal and the highest level of any spurious,
signalincluding aliases and harmonically related frequency
componentsin the spectrum. For the very best SFDR, it is
essential to begin with a high-quality oscillator.
SFDR is an important specification in an application where the
frequency spectrum is being shared with other communication
channels and applications. If a transmitters output sends
spurious signals into other frequency bands, they can corrupt,
or interrupt neighboring signals.
Typical output plots taken from an AD9834 (10 -bit DDS) with
a 50 -MHz master clock are shown in Figure 10. In (a), the
output frequency is exactly 1/3 of the master clock frequency
(MCLK). Because of the judicious choice of frequencies, there
are no harmonic frequencies in the 25-MHz window, aliases
are minimized, and the spurious behavior appears excellent,
with all spurs at least 80 dB below the signal (SFDR = 80 dB).
The lower frequency setting in (b) has more points to shape the
waveform (but not enough for a really clean waveform), and gives
a more realistic picture; the largest spur, at the second-harmonic
frequency, is about 50 dB below the signal (SFDR = 50 dB).
10
10
20
20
30
30
40
40
dB
dB
50
50
60
60
70
70
80
80
90
90
160
0
RWB 1K
VWB 300
FREQUENCY (Hz)
25M
ST200 SEC
(a)
160
0
RWB 1K
VWB 300
FREQUENCY (Hz)
25M
ST200 SEC
(b)
Figure 10. Output of an AD9834 with a 50-MHz master clock and (a) fOUT = 16.667 MHz (i.e., MCLK/3); (b) fOUT = 4.8 MHz.
Do you have tools that make it easier to program and predict the
performance of the DDS?
The on-line interactive design tool is an assistant for selecting tuning

words, given a reference clock and desired output frequencies
and/or phases. The required frequency is chosen, and idealized
output harmonics are shown after an external reconstruction filter
has been applied. An example is shown in Figure 11. Tabular data
is also provided for the major images and harmonics.
Figure 12. Typical display of programming sequence.
How can I evaluate your DDS devices?
All DDS devices have an evaluation board available for

purchase. They come with dedicated software, allowing the user
to test/evaluate the part easily within minutes of receiving the
board. A technical note accompanying each evaluation board
contains schematic information and shows best recommended
board- design and layout practice.
Where can I find more information on DDS devices?
The main DDS homepage is located at www.analog.com/dds

Figure 11. Screen presentation provided by an
interactive design tool. A sinx/x presentation of
a typical device output.
How will these tools help me program the DDS?
All thats needed is the required frequency output and the

systems reference clock frequency. The design tool will output
the full programming sequence required to program the part. In
the example in Figure 12, the MCLK is set to 25 MHz and the
desired output frequency is set to 10 MHz. Once the update button
is pressed, the full programming sequence to program the part is
contained in the Init Sequence register.
Links to design tools are provided at http://www.analog.com/

Analog_Root/static/techSupport/interactiveTools/#dds
A n in - depth tutorial on DDS technolog y can be found
at ht t p : / / w w w. a n a l o g .c o m / Up l o a d e d F i l e s / Tu to r i a l s /
450968421DDS_Tutorial_rev12 -2 - 99.pdf
A N - 6 05 c a n b e fou nd at ht t p : / / w w w. a n a log.c om /
UploadedFiles/Application_Notes/371092853519044414816
8447035AN605_0.pdf
The latest DDS selection guide can be found at http://
www.analog.com/IST/SelectionTable/?selection_table_id=27 b
Wideband CMOS Switches

By Theresa Corrigan [theresa.corrigan@analog.com]
Q: You mention Off Isolation and Insertion Loss. Could you explain
what these are?
A: Yes, the two most important parameters that describe the
performance of an RF switch are the insertion loss in the closed
state and the isolation in the open state.
Q: What is a CMOS wideband switch?
Off isolation is defined as the attenuation between input and

output ports of the switch when the switch is off. Crosstalk is a
measure of the isolation from channel to channel.
A: CMOS wideband switches are designed primarily to meet the

requirements of devices transmitting at ISM (industrial, scientific,
and medical) band frequencies (900 MHz and up). The low
insertion loss, high isolation between ports, low distortion, and
low current consumption of these devices make them an excellent
solution for many high frequency applications that require low
power consumption and the ability to handle transmitted power
up to 16 dBm. Examples of applications mentioned later in this
article, include car radios, antenna switching, wireless metering,
high speed filtering and data routing, home networking, power
amplifiers, and PLL switching.
A: To improve their bandwidth, wideband switches use only

N- channel MOSFETs in the signal path. An NMOS-only
switch has a typical 3-dB bandwidth of 400 MHzalmost
twice the bandwidth performance of a standard switch with
NMOS and PMOS FETs in parallel. This is a result of the
smaller switch size and greatly reduced parasitic capacitance
due to removal of the P- channel MOSFET. N- channel
MOSFETs act essentially as voltage- controlled resistors.
The switches operate as follows:
0
VDD = 1.65V TO 2.75V
TA = 25C
10
20
30
ISOLATION (dB)
Q: How do these switches come to be so much faster than typical analog

CMOS switches?
For example, the ADG919 SPDT switch provides about

37 dB of isolation at 1 GHz, as shown in Figure 2. The
same device, using the chip-scale package (CSP)offered
for space-constrained wireless applications, such as antenna
switchingoffers a 6-dB improvement (43 dB at 1 GHz).
40
50
S12
60
70
80
S21
90
100
10k
Vgs > Vt Switch ON
100k
As the signal frequency increases to greater than several

hundred megahertz, parasitic capacitances tend to dominate.
Therefore, achieving high isolation in the switches off -state
and low insertion loss in the on state for wideband applications is
quite a challenge for switch designers. The channel resistance
of a switch must be limited to less than about 6 ohms to achieve
a low-frequency insertion loss of less than 0.5 dB on a line
with 50-ohm matched impedances at the source and load.
As a departure from the familiar switch topology, inserting
a shunt path to ground for the off -throwand its associated
stray signalallows the design of switches with increased offisolation at high frequencies. The FETs have an interlocking
finger layout that reduces the parasitic capacitance between
the input (RFx) and the output (RFC), thereby increasing
isolation at high frequencies and enhancing crosstalk rejection.
For example, when MN1 is on to form the conducting path
for RF1, MN2 is off and MN4 is on, shunting the parasitics at
RF2 to ground, as shown in Figure 1.
RF COMMON
MN3
R1
R3
100M
1G
10G
MN2
RF2
Insertion loss is the attenuation between input and output ports of

the switch when the switch is on. The switch is generally one of
the first components encountered in a receivers signal path, so a
low insertion loss is required to ensure minimum signal loss. Low
switch insertion loss is also important for systems that require a
low overall noise figure.
To obtain the best insertion-loss performance from the ADG9xx
family of switches, one should operate the part at the maximum
allowable supply voltage of 2.75 V. The reason can be seen in
Figure 3, which shows plots of insertion loss versus frequency for
the ADG919 at three different values of supply voltage.
0.30
0.35
0.40
0.45
0.50
0.55
VDD = 2.25V
0.60
0.65
0.75
MN4
0.80
10k
TA = 25C
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
IN
Figure 1. A typical transistor based Tx/Rx switch.
Analog Dialogue 38-10, October (2004)
VDD = 2.75V
VDD = 2.5V
0.70
R2
R4
Figure 2. Off isolation vs. frequency.
INSERTION (dB)
Where Vgs is the gate-to-source voltage and Vt is defined as the

threshold voltageabove which a conducting channel is formed
between the source and drain terminals.
RF1
10M
FREQUENCY (Hz)
Vgs < Vt Switch OFF
MN1
1M
Figure 3. Insertion loss vs. frequency.
Q: How does insertion loss relate to the On-resistance spec of a standard

analog switch?
A: Signal loss is essentially determined by the attenuation
introduced by switch resistance in the on condition, Ron , in
series with the source-plus-load resistancemeasured at
the lower frequencies of operation. Figure 4 shows a typical
profile of on -resistance as a function of source voltage for an
N-channel MOSFET device.
28
24
RON ()
Q: How about the ESD (electrostatic discharge) performance as

compared to GaAs?
A: The ADG9xx family of parts passes the 1-kV ESD HBM
(human body model) requirement. ESD protection circuitry is
easily integrated on these CMOS devices to protect the RF and
digital pins. This makes the switches ideal for any applications
that are ESD sensitive, and they offer a reliable alternative to
GaAs devices having ESD ratings as low as 200 V.
Q: What are the other important specifications of these switches?
20
A: Video Feedthrough (Figure 5) is the spurious dc transient

present at the RF ports of the switch when the control voltage
is switched from high- to- low-, or low- to- high, without an
RF signal present. This is analogous to charge injection of a
typical analog switch. It is measured in a 50-ohm test setup,
with 1-ns (rise-time) pulses and a 500-MHz bandwidth.
16
12
low insertion loss (0.5 dB) all the way down to dc. In addition to
providing a smaller, more efficient design solution, the ADG9xx
family is less power-demanding, consuming less than 1 A over
all voltage and temperature conditions.
0.4
0.8
1.2
1.6
2.0
2.4
VS (V)
Figure 4. On resistance vs. source voltage.

Q: What technologies have been commonly used in the design of highfrequency switches?
CTRL
A: Traditionally, only a few processes were available for developing

good wideband/RF switches. Gallium arsenide (GaAs) FETs,
PIN diodes, and electromechanical relays have dominated the
market, but standard CMOS is now a strong entry.
PIN diodes are highly linear devices with good distortion
characteristics, but they have many drawbacks given todays
high performance demands. They have very slow switching
times (microseconds, compared to nanoseconds for CMOS
switches); they are power-hungry, making them unsuitable for
many battery-operated devices; andunlike CMOS switches
with their response from RF to dcthere is a practical lower
frequency limit to the use of PIN diodes as linear switches.
GaAs has been popular because of its low on resistance, low
off capacitance, and high linearity at high frequencies. As
CMOS process geometries continue to shrink, however, the
performance of CMOS switches has increased to the extent
that they can achieve 3-dB frequencies of up to 4 GHz and
are able to compete with GaAs switches. Designed to maximize
bandwidth while maintaining high linearity and low power
consumption, CMOS switches now offer a practical alternative
to GaAs switches in many low-power applications.
RFC
2
CH2 p-p
2.002mV
CH1 500mV
Q: What does this mean?

A: It means that if the insertion loss at 1 GHz was 0.8 dB with a
low-level input, it would be 1.8 dB with a 17-dBm input signal
[Note: dBm is the dB (logarithmic) measure of the ratio of
power to 1 mW, or voltage to 224 mV in 50 ohms. 17 dBm
corresponds to 50 mW, or 1.6 V rms or 4.5 V p-p].
20
18
16
14
P1dB (dBm)
GaAs switches, as such, need dc-blocking capacitors in series with

the RF ports, effectively floating the die relative to dc ground, so
that the switches can be controlled with positive control voltages.
Wideband switches, such as the ADG9xx family, do not have
this requirement, eliminating concerns of reduced bandwidth,
the impact of the capacitors on overall system performance, and
the extra space and cost of GaAs solutions. Eliminating the
blocking capacitors allows the ADG9xx parts to maintain their
M10.0ns
P1dB (1-dB compression point) is the RF input power level at

which the switch insertion loss increases by 1 dB over its low-level
value. It is a measure of the RF power-handling capability of the
switch. As shown in Figure 6, the ADG918 has a P1dB of 17 dBm
at 1 GHz, with V DD = 2.5 V.
Q: So what are the main benefits of CMOS wideband switch solutions

over gallium arsenide?
A: Switches, such as the ADG9xx family of parts, have an
integrated TTL driver that allows easy interfacing with other
CMOS devices, since CMOS is compatible with LVTTL logic
levels. The small size of devices with integrated drivers is a
solution for many space-constrained applications.
CH2 1mV
Figure 5. Video feedthrough.
12
10
8
6
4
VDD = 2.5V
TA = 25C
2
0
250
500
750
1000
1250
1500
FREQUENCY (MHz)
Figure 6. 1-dB compression point vs. frequency.
Q: Power-handling capability seems to decrease substantially at the

lowest frequencies in Figure 6. Why?
A: In normal operation, the switches can handle a 7-dBm (5-mW)
input signal. For a 50-ohm load, this corresponds to a
0.5-V rms signal, or 1.4 V peak-to-peak for sine waves.
[V p-p = V rms 2 2].
The power handling capability is reduced at lower frequencies
for two reasons:
50
VG
VS
N+
VD
Both of the above mechanisms can be overcome by applying a small

dc bias (about 0.5 V) to the RF input signal when the switch is
being used at low frequencies (<30 MHz) and high powergreater
than 7 dBm (or 5 mW, 1.4 V p-p in 50 ohms). This will raise the
minimum level of the sine-wave input signal and thus ensure
that the parasitic diodes are continually reverse-biased and that
the shunt transistor, never seeing Vgs > Vt, remains in the off state
for the whole period of the input signal. Figure 9 again shows a
plot of input- and output signals at 100 MHz and 10 dBm input
power (about 2 V p-p in 50 ohms), but this time with a 0.5-V dc
bias. It is clearly visible that clipping or compression no longer
occurs at 100 MHz.
50
N+
P TYPE
SUBSTRATE
Figure 7. Physical NMOS structure.
As shown in Figure 7, the inherent NMOS structure consists of two

regions of N-type material in a P-type substrate. Parasitic diodes
are thus formed between the N and P regions. When an ac signal,
biased at 0 V dc, is applied to the source of the transistor, and Vgs
is large enough to turn the transistor on (Vgs > Vt), the parasitic
diodes can be forward-biased for some portion of the negative halfcycle of the input waveform. This happens if the input sine wave
goes below approximately 0.6 V, and the diode begins to turn
on, thereby causing the input signal to be clipped (compressed),
as shown in Figure 8. The plot shows a 100-MHz, 10-dBm input
signal and the corresponding 100-MHz output signal. It is readily
seen that the output signal has been truncated.
REF1 FREQ
99.98MHz
REF1 AMPL
1.85V
REF1 FREQ
99.98MHz
REF1 AMPL
1.85V
C1 FREQ
100.05MHz
C1 AMPL
1.51V
C1 FREQ
100.00MHz
C1 AMPL
1.75V
CH1 500mV
M2.00ns
CH1
0V
Figure 9. 100-MHz, 10-dBm input/output signals

with 0.5-V dc bias.
Q: How do I apply a dc bias to RF inputs?
A: To minimize any current drain through the termination
resistance on the input side, it is best to add the bias on the
output (RFC) side. This is the best practice, especially for
low-power portable applications, but it may be necessary to
apply dc-blocking capacitors on the RF outputs if downstream
circuitry cannot handle the dc bias.
Q: Can these switches operate with a negative supply?
A: They can operate with a negative signal on the GND (ground)
pin as long as it adheres to the 0.5 V to +4 V Absolute
Maximum Rating for V DD to GND. Note that operating the
part in this manner places the internal terminations at this new
GND potentialan undesirable effect in some applications.
Q: What about the distortion performance of these switches?
CH1 500mV
M2.00ns
CH1
0V
Figure 8. 100-MHz, 10-dBm input/output signals

with 0-V dc bias.
At low frequencies, the input signal is below the 0.6 V level for
longer periods of time, and this has a greater impact on the 1-dB
compression point (P1dB).
The second reason why parts can handle less power at lower
frequencies is the partial turn-on of the shunt NMOS device
when it is supposed to be off. This is very similar to the mechanism
described above where there was partial turn-on of the parasitic
diode. In this case, the NMOS transistor is in the off state, with
Vgs < Vt. With an ac signal on the source of the shunt device,
there will be a time in the negative half-cycle of the waveform
where Vgs > Vt, thereby partially turning on the shunt device.
This will compress the input waveform by shunting some of its
energy to ground.
A: When tones at closely spaced frequencies are passed through

a switch, the nonlinearity of the switch causes false tones to be
generated, causing undesired outputs at other frequencies. In
communications systems, where channels are becoming more
tightly spaced, it is essential to minimize this intermodulation
distortion (IMD) to ensure minimum interference. Applying
two closely spaced equal-power signals with a set frequency
spacing (e.g., 900 MHz and 901 MHz) to the input of a device
under test (DUT), results in the output spectrum shown in
Figure 10. The 3rd -order harmonic, usually expressed in dBc,
is the log of the ratio of the power in the 3rd order harmonic
to the power of the fundamental. The larger the (negative)
value, the lower the distortion. Sending these tones through
the ADG918, using a combiner with an input power of 4 dBm,
resulted in an IP3 of 35 dBm as shown in Figure 11. [Note: an
excellent discussion of various types of distortion can be found
in Ask The Applications Engineer13]1
Q: What is a reflective switch?
INTERMODULATION DISTORTION (dB)
A: The ADG902 (SPST), ADG919 (SPDT), ADG936R (dual

SPDT), and the ADG904R (SP4T) parts are described as
reflective switches because they have 0-ohm shunts to ground.
FUNDAMENTAL
10
15
Q: Where would I use an absorptive switch over a reflective switch?
20
IMD
PRODUCT
25
A: An absorptive switch has a good impedance-match, or voltage

standing-wave ratio (VSWR), on each port, regardless of the
switch mode. It should be used when there is a need for proper
back-termination in the off channel, to maintain a good VSWR.
An absorptive switch is therefore ideal for applications that
require minimum reflections back to the RF source. It also
ensures that the maximum power is transferred to the load in
a 50-ohm system.
30
35
40
45
50
2f1 f2
f1
f2
2f2 f1
A reflective switch is suitable for applications where high off -port

VSWR does not matter and the switch has some other desired
performance feature. Reflective switches are commonly used
in applications where the matching is provided elsewhere in
the system. In most cases, an absorptive switch can be used
instead of a reflective switch, but not vice versa.
FREQUENCY
Figure 10. Output spectrum of two-tone IMD test.

40
35
Q: How can I determine the VSWR of these switches?
30
A: VSWRvoltage standing-wave ratiothe ratio of the sum

of forward and reflected voltages to the difference of forward
and reflected voltagesindicates the degree of impedance
match present at the switch RF port. When it comes to
measurement, it is easier to describe the impedance match in
terms of return loss, the amount of reflected power relative to
the incident power at a port.2
IP3 (dBm)
25
20
15
10
5
0
250
VDD = 2.5V
TA = 25C
350
450
550
650
750
850
FREQUENCY (MHz)
Figure 11. IP3 vs. frequency.

IP3Third-order intercept point. The IMD is measured, and
from this the IP3 value is calculated. IP3 is a figure of meritin dBm
for the device. IP3, specified in the data sheet, is a measure of the
distortion caused by the switch due to the power in these false tones.
The larger the IP3 value the smaller the tones in the adjacent channels,
indicating that the switch has good harmonic performance.
Simply by measuring both incident and reflected power, the

return loss can be determined, and from this the VSWR can
be calculated by using readily available VSWR/return-loss
conversion charts. Figure 13 shows a typical return-loss
curve for the ADG918 in the on - and off conditions. Note
that the ADG918, an absorptive switch, has good return-loss
performance for the off, as well as the on, switch. The ADG919
version, which does not include termination resistors, would
not have good return-loss performance in the off condition.
0
5
Q: What configurations are available in the ADG9xx family?
Q: What is an absorptive switch?
RF1
RFC
RF2
RF2
CTRL
CTRL
50
Figure 12. ADG918, an absorptive switch, and ADG919,

a reflective switch.
20
OFF SWITCH (ADG918)
25
ON SWITCH
35
40
10k
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
Figure 13. Return loss vs. frequency for the ADG918 switch.
ADG919
RF1
50
15
30
A: The ADG901 (SPST), ADG918 (SPDT), ADG936 (dual

SPDT), and the ADG904 (SP4T) parts are described as
absorptive (matched) switches, because they have on-chip
50-ohm-terminated shunt legs.
RFC
RETURN LOSS (dB)
10
A: The ADG9xx family comprises SPST (single- pole, singlethrow), SPDT (single-pole, double-throw), and dual -SPDT
switchesand 4:1 single-pole multiplexers (SP4T). These are
offered in both absorptive and reflective versions, in order to
suit all application needs.
ADG918
TA = 25C
VDD = 2.5V
Q: Now that youve explained how these parts perform, tell me where
and how they are used.
A: Due to their low insertion loss at up to 1-GHz and wide 3-dB
bandwidth (up to 4 GHz), switches in this family are ideal for
many automotive entertainment systems.
They have found homes in tuner modules and set-top
boxes to switch between the cable-TV input and the off-air
antenna input. Another area where these parts are suitable
is in car-radio antenna switching. Because these are
generally 50 -ohm-impedance systems, the 50-ohm internal

terminations offered by the absorptive version of these
switchesthe ADG901, ADG918, and ADG904ensure
excellent impedance-matching and minimum reflections.
The variety of topologies available makes these parts very
easy to design into antenna-diversity-switch applications,
allowing the user to switch between several antennas and a
single tuner in multiband radios.
Q: What is PLL Switching, and why use the ADG918?

A: Switching between two phase-locked loops (PLLs)commonly
described as the ping-pong techniqueallows a designer to
achieve faster system settling times. The low power-consumption
and simple single-pin control of the ADG918 make it an easy
solution to integrate.
In switching between two oscillators, the desired isolation
performance can be achieved by cascadingi.e., connecting
a number of switches in cascade. This is a very simple way to
provide a high-isolation specification for a system, preventing
any interference at the higher frequencies. Cascading five
ADG918s provides 130-dB isolation at 1 GHz, with an insertion
loss of 3 dB. In this application, such an increase in insertion
loss is not material, since the principal concern is about the
signal levels relative to one another.
These parts are also suitable for wireless metering systems,

providing the required isolation between transmit and receive
signals (Figure 14).
LNA
ANTENNA
ADG918
Tx/Rx SWITCH
A nice feature of the ADG918 in this application is that it acts

as an integrated low-pass filter, eliminating the unwanted
harmonics created by the two PLLs. Achieved by the natural
increase in insertion loss at high frequencies, it easily prevents
the unwanted harmonics from propagating through the
switches, as shown in Figures 15 and 16.
PA
Figure 14. Tx/Rx Switching.

These parts are perfect for high-speed filter selection
and data routing: the ADG904 can be used as a 4:1
demultiplexer to switch high -frequency signals between
different filtersand also to multiplex the signal to the
output. For differential filter selection and data routing,
the ADG936 dual SPDT (single - pole, double -throw) switch
is an ideal solution. Data switching in modem cards for
point-to -point wireless systems, such as microwave
radio links for military and avionic applications, requires
the high-frequency performance offered by the ADG9xx
family of parts.
PLL 1
SWITCH
PLL 2
Figure 15. PLL switching application.

GaAs SWITCH
They are also suitable for home-networking applications

systems allowing the wireless remote control of many different
functions, such as opening and closing roller blinds, control
of lighting (on, off or dimming)in which the information is
transmitted through a wireless link. The excellent isolation
performance at high frequency and low power-consumption
preserve a systems current budgetthus constituting an
ideal application.
Due to their high frequency rangeup to 4 GHzthis family
of parts are also suitable for many Bluetooth technologies
enabling wireless communication in the 2.5 - GHz ISM
frequency band.
Wideband switches can be used in the design of power
amplif iers (PAs) with 800 -, 900 -, 1900 -, 2100 -MHz
frequenciesfor cellular CDMA and GSM applications.
The switch is used in the feed forward correction loop
around the main amplif ier, allowing the active - and
passive feedback- and feed -forward paths to be switched
out, permitting the amplif iers distortion levels to be
tested. The switch allows for gain - and phase correction
in the system. The high isolation, low insertion loss, and
the low distortion at 900 MHz make the ADG9xx family
ideal for PA design in this frequency range.
The ADG918 can be used to implement PLL switching for
frequency-hopping in GSM applications.
O/P
ADG9xx
2f
3f
Figure 16. ADG918 switch cascade acting as integrated

low-pass filter, compared with naked GaAs switching.
Q: So...to summarize?
A: In summary, CMOS wideband switches, especially those in
the ADG9xx family, are excellent choices for all applications
in the ISM band that require high isolation and low insertionloss for battery- operated devices with space constraints.
Evaluation kits are available from Analog Devices to make
the design-in of these parts fast and hassle freeevery
designers dream!
b
NOTES
1
http://www.analog.com/library/analogDialogue/Anniversary/13.html
https://ewhdbks.mugu.navy.mil/VSWR.htm
In general, there are three parts to the capacitance-sensing

solution, all of which can be supplied by Analog Devices.
Capacitance Sensors for Human Interfaces

to Electronic Equipment
T he
By Susan Pratt [susan.pratt@analog.com]
The sensora PCB with a pattern of traces, such as buttons,
driver IC, which provides the excitation, the

capacitance-to-digital converter, and compensation
circuitry to ensure accurate results in all environments.
scroll bars, scroll wheels, or some combination. The traces
can be copper, carbon, or silver, while the PCB can be FR4,
flex, PET, or ITO.
Q: What is a capacitance sensor?

A: Capacitance sensors detect a change in capacitance when
something or someone approaches or touches the sensor. The
technique has been used in industrial applications for many years
to measure liquid levels, humidity, and material composition.
A newer application, coming into widespread use, is in humanto-machine interfaces. Mechanical buttons, switches, and jog
wheels have long been used as the interface between the user
and the machine. Because of their many drawbacks, however,
interface designers have been increasingly looking for more
reliable solutions. Capacitive sensors can be used in the same
manner as buttons, but they also can function with greater
versatility, for example, when implementing a 128-position
scroll bar.

Software on the host microcontroller to implement the serial
interface and the device setup, as well as the interrupt service

routine. For high-resolution sensors such as scroll bars and
wheels, the host runs a software algorithm to achieve high
resolution output. No software is required for buttons.
CIRCUIT BOARD
CIN
Integrated circuits specifically designed to implement

capacitance sensing in human-machine interface applications
are now available from Analog Devices. The AD71421 and the
AD7143, for example, can stimulate and respond to up to 14 and
eight capacitance sensors, respectively. They provide excitation
to the capacitance sensor, sense the changes in capacitance
caused by the users proximity, and provide a digital output.
AD7142/
AD7143
INTERRUPT
14 OR 8
HOST
MP
SENSORS
EXCITATION SOURCE
HOST SOFTWARE:
- SERIAL INTERFACE
- CODE TO SUPPORT
POSITIONING
Q: How does capacitance sensing work?

A: A basic sensor includes a receiver and a transmitter, each of
which consists of metal traces formed on layers of a printedcircuit board (PCB). As shown in Figure 1, the AD714x has an
on-chip excitation source, which is connected to the transmitter
trace of the sensor. Between the receiver and the transmitter
trace, an electric field is formed. Most of the field is concentrated
between the two layers of the sensor PCB. However, a fringe
electric field extends from the transmitter, out of the PCB, and
terminates back at the receiver. The field strength at the receiver
is measured by the on-chip sigma-delta capacitance-to-digital
converter. The electrical environment changes when a human
hand invades the fringe field, with a portion of the electric
field being shunted to ground instead of terminating at the
receiver. The resultant decrease in capacitanceon the order
of femtofarads as compared to picofarads for the bulk of the
electric fieldis detected by the converter.
SERIAL INTERFACE
4-WIRE SPI (AD7142 ONLY)
2-WIRE I2C (AD7142 AND AD7143)
Figure 2. Three-part capacitance-sensing solution.

Q: What are the advantages of capacitive sensing?
A: Capacitance sensors are more reliable than mechanical
sensorsfor a number of reasons. There are no moving parts,
so there is no wear and tear on the sensor, which is protected
by covering material, for example, the plastic cover of an MP3
player. Humans are never in direct contact with the sensor,
so it can be sealed away from dirt or spillages. This makes
capacitance sensors especially suitable for devices that need
to be cleaned regularlyas the sensor will not be damaged by
harsh abrasive cleaning agentsand for hand-held devices,
where the likelihood of accidental spillages (e.g., coffee) is
not negligible.
Q: Tell me more about how the AD714x ICs work.
USER INTERFERES
WITH FRINGE FIELD
PLASTIC COVER
Tx
BULK OF FIELD
CONFINED
BETWEEN
Tx AND Rx
Rx
3-$
ADC
A: These capacitance-to-digital converters are designed

specifically for capacitance sensing in human-interface
applications. The core of the devices is a 16-bit sigma-delta
capacitance-to-digital converter (CDC), which converts
the capacitive input signals (routed by a switch matrix)
into digital values. The result of the conversion is stored
in on-chip registers. The on-chip excitation source is a
250-kHz square wave.

16-BIT
DATA
EXCITATION
SIGNAL
250kHz
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 1. Sensing capacitance.
The host reads the results over the serial interface. The AD7142,
available with either SPI- or I2C-compatible interfaces, has
14 capacitance-input pins. The AD7143, with its I2C interface,
has eight capacitance-input pins. The serial interface, along with
an interrupt output, allows the devices to connect easily to the
host microcontroller in any system.
VREF VREF+
29
31
CIN2
32
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
10
CIN13
11
CSHIELD
12
SRC
15
SRC
16
VDRIVE
20
27
65536
POWER-ON
RESET
LOGIC
16-BIT
3-$
CDC
CALIBRATION
ENGINE
THRESHOLD
13
AVCC
14
AGND
THRESHOLD
CALIBRATION
RAM
CONTROL
AND DATA
REGISTERS
250kHz
EXCITATION
SOURCE
SERIAL INTERFACE
AND CONTROL LOGIC
21
SDO/
SDA
22
23
INTERRUPT
AND GPIO
LOGIC
24
SDI/ SCLK CS/

ADD0
ADD1
17
DVCC
18
DGND1
19
DGND2
26
GPIO
SENSOR
TOUCH
Figure 4. Sensor activation.

25
INT
Figure 3. AD7142 block diagram.

These devices interface with up to 14 external capacitance

sensors, arranged as buttons, bars, wheels, or a combination
of sensor types. The external sensors consist of electrodes on
a 2- or 4-layer PCB that interfaces directly with the IC.
The devices can be set up to interface with any set of

input sensors by programming the on-chip registers. The
registers can also be programmed to control features such
as averaging and offset adjustment for each of the external
sensors. An on-chip sequencer controls how each of the
capacitance inputs is polled.
SENSOR 1 INT
ASSERTED
The AD714x also include on-chip digital logic and 528 words
of RAM that are used for environmental compensation.
Humidity, temperature, and other environmental factors
can af fect t he operation of capacitance sensors ; so,
transparently to the user, the devices perform continuous
calibration to compensate for these effects, giving error-free
results at all times.
One of the key features of the AD714x is sensitivity control,
which imparts a different sensitivity setting to each sensor,
controlling how soft or hard the users touch must be to
activate the sensor. These independent settings for activation
thresholds, which determine when a sensor is active, are vital
when considering the operation of different-size sensors. Take,
for example, an application that has a large, 10-mm-diameter
button, and a small, 5-mm-diameter button. The user expects
both to activate with same touch pressure, but capacitance is
related to sensor area, so a smaller sensor needs a harder touch
to activate it. The end user should not have to press one button
harder than another for the same effect, so having independent
sensitivity settings for each sensor solves this problem.
Figure 4 shows an ideal situation, where the ambient

capacitance value does not change. In reality, the ambient
capacitance changes constantly and unpredictably due
to changes in temperature and humidity. If the ambient
capacitance value changes sufficiently, it can affect the
sensor activation. In Figure 5, the ambient capacitance value
increases; Sensor 1 activates correctly, but when the user
tries to activate Sensor 2, an error occurs. The ambient value
has increased, so the change in capacitance measured from
Sensor 2 is not large enough to bring the value below the lower
threshold. Sensor 2 cannot now be activated, no matter what
the user does, as its capacitance cannot decrease below the
lower threshold in these circumstances. A worse possibility
is that the ambient capacitance level continues to increase
until it is above the upper threshold. In this case, Sensor 1
will become active, even though the user has not activated it,
and it will remain activethe sensor will be stuck onuntil
the ambient capacitance falls.
CDC OUTPUT CODES
AMBIENT CAPACITANCE VALUE
CDC OUTPUT CODE
30
CIN1
SWITCH
MATRIX
CIN0
SENSOR
TOUCH
TEST
28
CHANGING ENVIRONMENTAL CONDITIONS
Figure 5. Sensor activation with changing ambient capacitance.

On-chip logic circuits deal with the effects of changing ambient

capacitance levels. As Figure 6 shows, the threshold levels are
not constant; they track any changes in the ambient capacitance
level, maintaining a fixed distance away from the ambient level
to ensure that the change in capacitance due to user activation
is always sufficient to exceed the threshold levels. The threshold
levels are adapted automatically by the on-chip logic and are
stored in the on-chip RAM. No input from the user or host
processor is required.
Q: How is the environment taken into account?
1
CDC OUTPUT CODES
A: The AD714x measures the capacitance level from the sensor

continuously. When the sensor is not active, the capacitance
value measured is stored as the ambient value. When a user
comes close to or touches the capacitance sensor, the measured
capacitance decreases or increases. Threshold capacitance levels
are stored in on-chip registers. When the measured capacitance
value exceeds either upper or lower threshold limits, the sensor
is considered to be activeas shown in Figure 4and an
interrupt output is asserted.
SENSOR 2 INT
NOT ASSERTED
SENSOR 1 INT
ASSERTED
2
6
5
4
SENSOR 2 INT
NOT ASSERTED
CHANGING ENVIRONMENTAL CONDITIONS
Figure 6. Sensor activation with auto-adapting thresholds.
Q: How is capacitance sensing applied?

A: As noted earlier, the sensor traces can be any number of
different shapes and sizes. Buttons, wheels, scroll-bar,
joypad, and touchpad shapes can be laid out as traces on
the sensor PCB. Figure 7 shows a selection of capacitance
sensor layouts.
Button
Sensor
SRC
CIN
The number of sensors that can be implemented using a single

device depends on the type of sensors required. The AD7142
has 14 capacitance input pins and 12 conversion channels. The
AD7143 has eight capacitance inputs and eight conversion
channels. The table below shows the number of input pins and
conversion stages required for each sensor type. Any number of
sensors can be combined, up to the limit established by the number
of available inputs and channels.
CIN
SRC
8-Way Switch
CIN
CIN
CIN
CIN
Slider
SRC
Sensor Type
Number of CIN
inputs required
Number of conversion
channels required
Button
1 (0.5 for differential

operation)
8-Way
Switch
4top, bottom,
left, and right
Slider
81 per segment
81 per segment
Wheel
81 per segment
81 per segment
Keypad
Touchpad
1 per row, 1 per

column
1 per row, 1 per

column
Measurements are taken on all connected sensors sequentially

in a round-robin fashion. All sensors can be measured within
36 ms, though, allowing essentially simultaneous detection of
each sensors statusas it would take a very fast user to activate
or deactivate a sensor within 40 ms.
Q: What design help can you offer first-time users?
As part of the design resources available for capacitance

sensing, a Mentor Graphics PADs layout library is available
online. Many different types and sizes of sensors are available
in this library as components, which can be dragged and
dropped directly into a PCB layout. The library is available
as an interactive part of the Touch Controller System Block
Diagram.2 Also available is AN-854,3 an application note
that provides details, tips, and tricks on how to use the sensor
library to lay out the desired sensors quickly.
When designing the PCB, place the AD7142 or AD7143 on the

same board as the sensors to minimize the chances of system
errors due to moving connectors and changing capacitance.
Other components, LEDs, connectors, and other ICs, for
example, can go on the same PCB as the capacitance sensors, but
the sensor PCB must be glued or taped to the covering material
to prevent air gaps above the sensors, so the placement of any
other components on the PCB must take this into account.
For applications where RF noise is a concern, then an RC filter

can be used to minimize any interference with the sensors.
Using a ground plane around the sensors will also minimize
any interference.
The PCB can have either two- or four layers. A 4-layer design
must be used when there is no room, outside of the sensor
active areas, to route between the IC and the sensors, but a
2-layer design can be used if there is enough routing room.
Touchpad
Keypad
Wheel
A: Analog Devices has a number of resources available to

designers of capacitance sensors. The first step in the design
process is to decide what types of sensors are needed in the
application. Will the user need to scan quickly through long
lists, such as contacts on a handset or songs on an MP3 player?
If so, then consider using a scroll bar or scroll wheel to allow
the user to scan through those lists quickly and efficiently. Will
the user need to control a cursor moving around a screen? An
X-Y joypad would be a good fit for this application. Once the
type, number, and dimensions of the required sensors have
been fixed, the sensor PCB design can begin.
Figure 7. Selection of capacitance sensors.

Many options for implementing the user interface are available to
the designer, ranging from simply replacing mechanical buttons
with capacitive button sensors to eliminating buttons by using a
joypad with eight output positions, or a scroll wheel that gives
128 output positions.
The maximum distance allowed between the sensor traces

and capacitance input pin is 10 cm, but one sensor can be
10 cm from the pins in one direction, while another can
be 10 cm from the pins in the opposite direction, allowing
20 cm between sensors.
Q: My sensor PCB is ready, now what?
A: Capacitance is notoriously difficult to simulate, so the sensor
response in each application must be characterized to ensure
that the AD7142/AD7143 is set up optimally for the application.
This characterization process need only take place once per
application, with the same setup values then being used for each
individual product.

The sensors are characterized in the application. This means

that any covering material must be in place on top of the sensor,
and any other PCBs or components that may have an effect on
the sensors performance must be in place around the sensor.
Q: You mentioned software?

A: The interaction between the host processor and the AD7142/
AD7143 is interrupt-driven. The host implements the
serial interface, either SPI or I2C. The AD7142/AD7143
will interrupt the host when a sensor is touched. The host
can then read back data from the on-chip registers. If the
sensors are buttons, or other simple on/off type sensors, the
host simply reads back from the on-chip status registers; an
active button causes a bit to be set in the status register.
However, if the sensors have a high-resolution output, a
software algorithm must run in the host interrupt routine
to process the AD7142/AD7143 data.

The code is provided free of charge or royalties to customers

who sign a license agreement with Analog Devices. For a
scroll bar, the code typically occupies 500 bytes of data
memory and 8k bytes of code memory. For a scroll wheel,
the code typically occupies 600 bytes of data memory and
10k bytes of code memory.
Analog Devices provides sample drivers,4 written in C-code,

for basic configuration, button sensors, and 8-way switches
using SPI- and I2C-compatible interfaces. Sample drivers
for scroll wheels and scroll bars are available after signing a
software license.
For each conversion channel, we need to configure:
Internal connection from the devices CIN input pin to the

converter. This ensures that each sensor is connected to the
converter using one conversion channel.
Sensor offset value, to offset for CBULK. This is the capacitance

associated with the electric field that is confined within the
PCB, between the transmitter and receiver electrodes.
This value does not change when the sensor is active, but
instead provides a constant offset for the measurement fringe
capacitance value.
Initial values for upper and lower offset registers. These
values are used by the on-chip logic to determine the

activation threshold for each sensor.
The easiest way to perform the characterization is to connect

the sensor PCB to the AD7142/AD7143 evaluation board
available from Analog Devices. The microcontroller and
software that are included on the evaluation board can be used
to characterize the sensor response and save the setup values.
Q: What kind of response can I expect?

A: The practical response from the sensor is defined by the
converters output change when the sensor goes from inactive
to active. This change will depend on the area of the sensor
the larger the sensor area, the greater the change when the
sensor is active. The sensor response will also depend on the
thickness of the covering materialif it is very thick (4 mm
or more), the sensor response will be minimal. The reason
is that the electric field will not penetrate through very thick
covering material, so the user will not be able to shunt enough
of the field to ground to generate a large response. Figure 8
is a typical sensor response from a button sensor. It shows a
change of about 250 LSBs between the sensor active and sensor
inactive in this case.
35100
UPPER
ACTIVATION
THRESHOLD
SENSOR NOT ACTIVE

35000
34900
34800
MEASURED RESPONSE
FROM SENSOR
SENSOR ACTIVE
LOWER
ACTIVATION
THRESHOLD
34700
Figure 8. Typical response from a button sensor.
Q: Ideas on assembling my finished product?

A: No air gap is allowed between the sensor PCB and the covering
material or product case because having one would cause less of
the electric field to extend above plastic, decreasing the sensor
response. Also, the plastic or other covering material might bend
on contact, causing the user to interact with a variable electric
field, and resulting in a nonlinear sensor response. Thus, the
sensor PCB should be glued to the covering material to prevent
any air gaps from forming.

Also, there can be no floating metal around the sensors. A

Keep Out distance of 5 cm is required. Metal closer to the
sensors than 5 cm should be grounded, but there can be no
metal closer to the sensors than 0.2 mm.
Finally, the plastic covering the sensors active areas should

be about 2 mm thick. Larger sensor areas should be used
with thicker plastic; and plastic thickness of up to 4 mm can
be supported.
CONCLUSION
Capacitance sensors are an emerging technology for human-machine

interfaces and are rapidly becoming the preferred technology over a
range of different products and devices. Capacitance sensors enable
innovative yet easy-to-use interfaces for a wide range of portable
and consumer products. Easy to design, they use standard PCB
manufacturing techniques and are more reliable than mechanical
switches. They give the industrial designer freedom to focus on
styling, knowing that capacitance sensors can be relied upon to give
a high-performance interface that will fit the design. The designer
can benefit from the Analog Devices portfolio of IC technology and
products, plus the expertise and the hardware and software tools
available to make it as easy and as quick as possible to design-in
b
capacitance sensors.
REFERENCESVALID AS OF OCTOBER 2006

1
ADI website: www.analog.com (Search) AD7142 (Go)

ADI website: www.analog.com (Search) Touch Controller System
Block Diagram (Go)
3
ADI website: www.analog.com (Search) AN-854 (Go)
4
http://www.analog.com/en/content/0,2886,760_1077_
F107310,00.html#software
2

Amplifier- or Transformer Drive for the ADC?
By Rob Reeder [rob.reeder@analog.com]
Jim Caserta [jim.caserta@analog.com]
Design of the input configuration, or front end, ahead of a
high-performance analog-to-digital converter (ADC) is critical
to achieving desired system performance. Optimizing the
overall design depends on many factors, including the nature of
the application, system partition, and ADC architecture. The
following questions and answers highlight the important practical
considerations affecting the design of an ADC front end using
amplifier- and transformer circuitry.
Q. What is the fundamental difference between amplifiers and
transformers?
20
40
A. A typical amplifier that might be considered, the ADA4937,

for example, when configured for G = 1, has an output
noise spectral density of 6 nV/Hz at high frequencies,
compared to the 10-nV/Hz input noise spectral density of
the 80-MSPS AD9446-802 ADC. The problem here is that
the amplifier has a noise bandwidth equivalent to the full
bandwidth of the ADC, around 500 MHz, while the ADC
noise is folded to one Nyquist zone (40 MHz). Without a
filter, the integrated noise then becomes 155 mV rms for the
amplifier and 90 mV rms for the ADC. Theoretically, this
degrades the overall system SNR (signal-to-noise ratio) by
6 dB. To confirm this experimentally, the measured SNR,
with the ADA4937 driving the AD9446-80, is 76 dBFS, and
the noise floor is 118 dB (Figure 1). With a transformer
drive, the SNR is 82 dBFS. The driver amplifier has thus
degraded the SNR by 6 dB.
50
60
70
80
90
+
100
SNR: 74.81dBc
SNRFS: 75.8dBFS
THD: 81.17dBc
SINAD: 73.9dBc
SFDR: 82.64dBc
WO SPUR: 98.31dBc
NOISE FLOOR: 117.9dB
FUND LEAD: 100
HARM LEAK: 3
DC LEAK: 6
110
120
130
140
150
0
12
16
20
24
28
32
36
40
FREQUENCY (MHz)
Figure 1. ADA4937 amplifier driving an AD9446-80

ADC at 80 MSPS without a noise filter.

To make better use of the ADCs SNR, a filter is inserted

between the amplifier and ADC. With a 100-MHz 2-pole filter,
the amplifiers integrated noise becomes 71 mV rms, degrading
the ADCs SNR by only 3 dB. Use of the 2-pole filter improves
the SNR performance of the Figure 1 circuit to 79 dBFS, with
a noise floor of 121 dB, as shown in Figure 2a. The 2-pole
filter is built with 24-V resistors and 30nH inductors in series
with each of the amplifiers outputs, and a 47pF differentially
connected capacitor (Figure 2b).
Q. Why would you use an amplifier?
Q. How much noise does an amplifier typically add, and what can I
do to reduce this?
FUND: 0.997dBFS
2ND: 86.5dBc
3RD: 83.03dBc
4TH: 103.38dBc
5TH: 100.03dBc
6TH: 95.59dBc
30
A. An amplifier is an active element, while a transformer is passive.

Amplifiers, like all active elements, consume power and add
noise; transformers consume no power and add negligible
noise. Both have dynamic effects to be dealt with.
ENCODE: 80MHz
SAMPLES: 32768
ANALOG: 19.0991MHz
10
20
FUND: 1.036dBFS
2ND: 82.97dBc
3RD: 82.94dBc
4TH: 102.95dBc
5TH: 98.1dBc
6TH: 96.3dBc
30
40
AMPLITUDE (dBFS)
A. Amplifier performance has fewer limitations than those of

transformers. If dc levels must be preserved, an amplifier
must be used, because transformers are inherently ac-coupled
devices. On the other hand, transformers provide galvanic
isolation if needed. Amplifiers provide gain more easily
because their output impedance is essentially independent of
gain. On the other hand, a transformers output impedance
increases with the square of the voltage gainwhich depends
on the turns ratio. Amplifiers provide flatter response in the
pass band, free of the ripple due to the parasitic interactions
in transformers.
ENCODE: 80MHz
SAMPLES: 32768
ANALOG: 19.0991MHz
10
AMPLITUDE (dBFS)
Wideband A/D Converter Front-End Design

Considerations II:
50
60
70
80
90
5
100
SNR: 78.11dBc
SNRFS: 79.14dBFS
THD: 79.76dBc
SINAD: 75.85dBc
SFDR: 82.56dBc
WO SPUR: 100.61dBc
NOISE FLOOR: 121.3dB
FUND LEAD: 100
HARM LEAK: 3
DC LEAK: 6
110
120
130
140
150
0
12
16
20
24
28
32
36
40
FREQUENCY (MHz)
Figure 2a. Driving an AD9446-80 with a 100-MHz noise filter.

2006
AVDD
2006
10k6
506
0.1MF
VOCM
18k6
246
ADA4937
AV = UNITY
2286
SIGNAL
GENERATOR
246
30nH
47pF
30nH
AD9446
2k6
3pF
ADC INPUT
IMPEDANCE
2006
Figure 2b. Schematic diagram of ADA4937 amplifier driving

an AD9446-80 ADC at 80 MSPS with a 2-pole noise filter.
Analog Dialogue 41-02, February (2007)
A. This depends on the amplifier and ADC used. Two typical

amplifiers, with similar power consumption, are the AD8352,3
which draws 37 mA @ 5 V (185 mW), and the ADA4937, which
draws 40 mA @ 5 V (200 mW). Overall power consumption
can be reduced by about one-third, with slightly degraded
performance, by using a 3.3-V supply. ADCs feature more
diversity in power consumption, depending on resolution
and speed. The 16-bit, 80-MSPS AD944680 draws 2.4 W,
the 14-bit, 125-MSPS AD9246-1254 draws 415 mW, and the
12-bit, 20-MSPS AD9235-205 draws only 95 mW.
Q. When do you need to use a transformer?
Q. What are some considerations in this analysis?

A. One must start by understanding the level of difficulty in
designing a front end for a given ADC. First, is the ADC
internally buffered, or is it unbuffered (for example, a
switched-capacitor type)? Naturally, the level of difficulty
increases as the frequency increases in either case. But
switched-capacitor types are more difficult for the designer
to deal with.

If gain is needed to make full use of the ADCs input range, an

application that might otherwise favor a transformer becomes
more difficult as the required gain (turns ratio) increases.
Of course, the difficulty increases with frequency. Design of

an IF system below 100 MHz with a buffered ADC would be
relatively simple compared to a high-IF design with low signal
levels using an unbuffered ADC, as Figure 3 illustrates. With
so many parameters pulling in different directions, trade-offs
are sometimes difficult and often puzzling to keep track of
as components are changed and evaluated.
A. Transformers offer the biggest performance advantage

compared to amplifiers at very high signal frequencies and
when significant additional noise cannot be tolerated at the
ADC input.
Q. How do transformers and amplifiers differ when providing gain?
When a low-output-impedance amplifiersuch as the

ADA4937is used, the result is a very low source impedance,
usually less than 5 V. 25-V transient-limiting resistors can
be used in series with each ADC input; in the case of the
AD9246, the ADCs full 650-MHz analog input bandwidth
would be usable.
So far the discussion has been about 3-dB bandwidths. When
tighter flatness is needed, say 0.5 dB in a 1-pole system, the
3-dB bandwidth needs to be about 33 wider. For 0.1-dB
flatness with one pole, the ratio increases to 6.53. If 0.5dB
flatness is required at up to 150 MHz, a 3-dB bandwidth
greater than 450 MHz is required, which is difficult to
attain with a G = 2 transformer but is straightforward with
a low-output-impedance amplifier.
Q. What are the factors to consider in choosing a transformer or an

amplifier to drive an ADC?
A. They can be boiled down to a half-dozen parametersoutlined
in this table:

RELATIVE DIFFICULTY
For example, when a G = 2 transformer is used from a

50-V source impedance, the impedance seen at the secondary
side of the transformer is 200 V. The AD9246 ADC has a
differential input capacitance of 4 pF which, coupled with
the 200-V transformer impedance, reduces the ADCs 3-dB
bandwidth from 650 MHz to 200 MHz. Extra series resistance
and differential capacitance are often needed to improve
performance and reduce kickback from the converter, which
can limit 3-dB bandwidth further, possibly to 100 MHz.
Parameter
Bandwidth
Gain
Pass band flatness
Power requirement
Noise
DC vs. ac coupling

Usual preference
Transformer
Amplifier
Amplifier
Transformer
Transformer
Amplifier (dc level preservation)
Transformer (dc isolation)
Applications in which key parameters are in conflict require

additional analysis and trade-offs.
EASY
VERY
DIFFICULT
A. The main difference is in the impedance they present to

the ADC input, which directly affects system bandwidth. A
transformers input- and output impedance are related by the
square of the turns ratio, while an amplifiers input and output
impedance are essentially independent of gain.
DIFFICULT
Q. How do high-speed amplifiers and ADCs compare in power

consumption?
WITH
GAIN
UNBUFFERED
ADCs
WITH
GAIN
BUFFERED
ADCs
BASEBAND
IF
VERY HIGH IF
FREQUENCY
Figure 3. Frequency vs. relative difficulty.

It may be useful to employ a spreadsheet or table to keep all of

the parameters straight as the design moves forward. There is
no optimum design to satisfy all cases; it will be subject to the
available components and the application specifications.
Q. OK, design can be difficult. Now how about some details regarding
system parameters ?
A. First, it is paramount that everything be taken into account
when designing an ADC front end! Each component should
be viewed as part of the load on the previous stage; and
maximum power transfer occurs when Z SOURCE = conjugate
Z LOAD (Figure 4).
SIGNAL
SOURCE
MAX POWER TRANSFER
OCCURS WHEN ZSOURCE = ZLOAD (CONJUGATE)
ZSOURCE
ZLOAD
SIGNAL
SOURCE
Z = R jX
XFMR
VIN+
ZSOURCE
R
ZLOAD
Z = 506
Z = R + jX
C
R
R
VIN
C
ADC
INTERNAL
INPUT Z
Figure 4. Maximum power transfer.
Now to the design parameters:
Q. What is important to know about transformers?
Input impedance is the characteristic impedance of the design.

In most cases it is 50 V, but different values may be called for.
The transformer makes a good transimpedance device. It allows
the user to couple between different characteristic impedances
when needed and fully balance the overall load of the system. In
an amplifier circuit, the impedance is specified as an input- and
output characteristic that can be designed to not change over
frequency as a transformer might.
A. Transformers have many different characteristicssuch as

voltage gain and impedance ratio, bandwidth and insertion
loss, magnitude- and phase imbalance, and return loss. Other
requirements may include power rating, type of configuration
(such as balun or transformer), and center-tap options.
Designing with transformers is not always straightforward.
For example, transformer characteristics change over
frequency, thus complicating the model. An example
of a starting point for modeling a transformer for ADC
applications can be seen in Figure 6. Each of the parameters
will depend on the transformer chosen. It is suggested that
you contact the transformer manufacturer to obtain a model
if available.
Bandwidths are ranges of frequencies used in the system. They

can be narrow or wide, at baseband, or covering multiple Nyquist
zones. Their frequency limits are typically the 3-dB points.
Input drive level is determined by the system gain needed for

the particular application. It is closely related to the bandwidth
specification and depends on the front-end components chosen,
such as the filter and amplifier/transformer; their characteristics
can cause the drive level requirement to be one of the most difficult
parameters to maintain.
0
3dB BANDWIDTH =
325MHz
3
4
5
6
7
8
9
100
150
RCORE
C1
PRIMARY
2
L1
1:1
Z RATIO
L3
R2
L2
R3
C6
SECONDARY
R4
L4
C4
C5
Figure 6. Transformer model.
Turns ratio is the ratio of the secondary- to the primary voltage.

Impedance ratio is the square of the turns ratio.
Signal gain is ideally equal to the turns ratio. Although voltage
gains are inherently noise-free, there are other considerationsto
be discussed below.
11
50
R1
Current ratio is inversely related to the turns ratio.
10
0
Among the characteristics of a transformer:
PASS-BAND
FLATNESS
INPUT DRIVE LEVEL (dBm)
FULL-SCALE AMPLITUDE (dBFS)
C3
LPRIMARY
Pass-band flatness (also gain flatness) specifies the amount of

(positive and negative) variation of response with frequency within
a specified bandwidth. It may be a ripple or simply a monotonic
rolloff, like a Butterworth filter characteristic. Whatever the
case, pass-band flatness is usually required to be less than or
equal to 1 dB and is critical for setting the overall system gain.
C2
LSECONDARY
Voltage standing-wave ratio (VSWR) is a dimensionless

parameter that can be used to understand how much power is
being reflected into the load over the bandwidth of interest. An
important measure, it determines the input drive level required
to achieve the ADCs full-scale input.
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 5. Bandwidth, pass-band flatness, and

input drive level defined.
Signal-to-noise ratio (SNR) is the log-ratio of the rms
value of the full-scale signal to the root-sum-square of all
noise components within a given bandwidth, but not including
distortion components. In terms of the front end, SNR degrades
with increased bandwidth, jitter, and gain (at high gains, amplifier
noise components that may have been negligible at low gain can
become significant).
Spurious-free dynamic range (SFDR) is the ratio of the rms
full-scale value to the rms value of the largest spurious spectral
component. Two major contributors of spurs at the front end
are the nonlinearity of the amplifier (or the transformers lack
of perfect balance), which produces mostly second-harmonic
distortionand the input mismatch and its amplification
by the gain (at higher gain, matching is more difficult and
parasitic nonlinearities are amplified), generally seen as a
third-harmonic distortion.
A transformer can be viewed simplistically as a pass-band filter

with nominal gain. Insertion loss, the filters loss over the
specified frequency range, is the most common measurement
specification found in a data sheet, but there are additional
considerations.
Return loss is a measure of the mismatch of the effective
impedance of the secondarys termination as seen by the
primary of a transformer. For example, if the square of the ratio
of secondary to primary turns is 2:1, one would expect a 50-V
impedance to be reflected onto the primary when the secondary
is terminated with 100 V. However, this relationship is not exact;
for example, the reflected impedance on the primary changes
with frequency. In general, as the impedance ratio goes up, so
does the variability of the return loss.
Amplitude- and phase imbalance are critical performance
characteristics when considering a transformer. These two
specifications give the designer a perspective on how much
nonlinearity to expect when a design calls for very high (above
100MHz) IF frequencies. As the frequency increases, the
nonlinearities of the transformer also increase, usually dominated
by phase imbalance, which translates to even-order distortions
(mainly 2nd-harmonic).
The AD8139 is commonly used for baseband designs, i.e.,

where input frequencies of interest are less than 50 MHz.
For higher-IF designs the AD8352 is commonly used. This
amplifier shows good noise- and spur rejection over a much
wider band of frequencies, up to the 200-MHz region. The
ADA4937 can be used for frequencies up to 150 MHz; its main
advantage is in dc-coupled applications with ADCs, because it
can handle a wide range of common-mode output voltages.
Figure 7 shows typical phase imbalance as a function of frequency

for single- and double-transformer configurations.
DOUBLE XFMR
CONFIGURATION
SINGLE XFMR
CONFIGURATION
12
Q. What are important characteristics of the ADCs that I might use?
0
0.1
PERFORMANCE
DIFFERENCE AT 100MHz
10
100
1000
10000
FREQUENCY (MHz)
Figure 7. Transformer phase imbalance for single- and

double-transformer configurations.

Remember, not all transformers are specified the same way by

all manufacturers, and transformers with apparently similar
specs may perform differently in the same situation. The best
way to select a transformer for your design is to collect and
understand the specs of all transformers being considered, and
request any key data items not stated on manufacturers data
sheets. Alternatively, or in addition, it may be useful to measure
their performance yourself using a network analyzer.
A. The popular CMOS switched-capacitor ADC does not have

an internal input buffer, so it has much lower power dissipation
than buffered types. The external source connects directly
to the ADCs internal switched-capacitor sample-and-hold
(SHA) circuit (Figure 8). This presents two problems. First,
the input impedance varies with time and as the mode is
switched between sample and hold. Second, the charge injected
into the sampling capacitors reflects back onto the signal
source; this may cause settling delays for passive filters in the
drive circuit.
AVCC
Drive capability is another advantage of amplifiers. Transformers

are not made for driving long traces on PC boards. They are
intended for direct connection to the ADC. If the system
requirements dictate that the driver/coupler needs to be
located far away from the ADC, or on a different board, an
amplifier is strongly recommended.
DC coupling can also be a reason for using an amplifier, since
transformers are inherently ac-coupled. Some high-frequency
amplifiers can couple at frequencies all the way down
to dc, if that part of the spectrum is important in the
application. Typical amplifiers to consider include the
AD8138 and ADA4937.
Amplifiers can also provide dynamic isolation, roughly 30 dB
to 40 dB of reverse isolation, to squelch kickback glitches from
current transients in an unbuffered ADCs input.
If the design calls for wideband gain, an amplifier provides a
better match than a transformer to the ADCs analog inputs.
Another trade-off is bandwidth vs. noise. For designs involving
frequencies greater than 150MHz, transformers will do a
better job of maintaining SNR and SFDR. However, within
the first or second Nyquist zone, either a transformer or an
amplifier can be used.
Q. What are the preferred ADI amplifiers for driving high-performance

ADCs?
A. A handful of amplifiers are best for high-speed ADC front
ends. These include the AD81386 and AD8139;7 the AD8350,8
AD8351,9 and AD8352;10 and the ADA4937 and ADA4938.
SHA
SAMPLING
CAP
VCMIN
INTERNAL
INPUT CLOCK
FLIP-AROUND
SWITCH
Figure 8. Block diagram of switched-capacitor

ADC input stage.

It is important to match the external network to the ADC trackmode impedance, displayed in Figure 9. As you can see, the real
(resistive) part of the input impedance (blue line) is very high
(in the several kilohm range) at lower frequencies (baseband)
and rolls off to less than 2 kV above 100 MHz.
The imaginary, or capacitive, part of the input impedance, the

red line, starts out as a fairly high capacitive load and tapers off
to about 3 pF (right-hand scale) at high frequencies.
To match to this input structure is a pretty challenging design

problem, especially at frequencies greater than 100 MHz.
10
RPAR (k6) TRACK MODE
9
PARALLEL RESISTANCE (k6)
INPUT
SWITCH
AVCC
SAMPLING
SWITCHES
INTERNAL
SAMPLE
CLOCK
GND
ESD
VIN
VCMIN
INPUT
SWITCH SAMPLING
CAP
ESD
VIN+
Q. Which parameters are important in choosing an amplifier?

A. The principal reason for using an amplifier instead of
a transformer is to get better pass-band flatness. If this
specification is critical to your design, an amplifier should
produce less variability, typically 60.1 dB over the frequency
range. Transformers have lumpy response and require fine
tuning when they must be used and flatness is an issue.
FLIP-AROUND
SWITCH
INTERNAL
INPUT CLOCK
CPAR (pF) TRACK MODE
0
0.5
1.0
VIN+
R
6
5
VIN
ADC INTERNAL
INPUT Z
R || jX
jX
PARALLEL
CONFIGURATION
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0
50
100
150
200
250
300
350
400
450
PARALLEL CAPACITANCE (pF)
PHASE IMBALANCE (Degrees)
16
5.0
500
FREQUENCY (MHz)
Figure 9. Typical input impedance graph of a

switched-capacitor ADC in track mode.
The waveforms in Figures 10 and 11 illustrate the advantage

of differential signaling. At first glance, the individual singleended ADC input waveforms in Figure 10 look pretty bad.
However, Figure 11 demonstrates that the corruption of the
single-ended traces is almost purely a common-mode effect.
CH1 200mV
CH3 2.00V
CH2 200mV
M50.0ns
CH2
A. Figure 12 shows four examples of ADC input configurations

using a transformer.

In baseband applications (a), the input impedance is much

higher so the match is more straightforward than, and not
as critical as, the match at higher frequencies. Usually,
small-value series resistors will suffice to damp out the
charge injection with a differentially connected capacitor.
This simple filter attenuates the broadband noise, achieving
optimal performance.
In order to get a well-matched input in broadband applications

(b), try to make the inputs real (resistive) component
predominate. Minimize the capacitive terms with inductors
or ferrite beads in shunt or series with the analog front end.
This can yield good bandwidth, improve gain flatness, and
provide better performance (SFDR) as seen using the AD92xx
switched-capacitor ADC family.
For buffered high-IF applications (c), a double-balun

configuration is shown, with a filter similar to the baseband
configuration. This allows inputs of up to 300 MHz and
provides good balancing to minimize even-order distortions.
For narrow-band (resonant) applications (d), the topology is

similar to broadband. However, the match is in shunt instead of
series, to narrow the bandwidth to the frequency specified.
1.69V
Figure 10. Single-ended measurement of a switchedcapacitor ADC input relative to the clock edges.
BASEBAND APPLICATIONS (a)

AVDD
10nH*
ANALOG
INPUT
INPUT
Z = 506
XFMR
1:1 Z
1k6 336
VIN+
2pF TO
20pF
626
0.1MF
BUFFERED OR
UNBUFFERED
ADC
C
ADC
INTERNAL
INPUT Z
BUFFERED OR
UNBUFFERED
ADC
C
ADC
INTERNAL
INPUT Z
VIN
336
1k6
BUFFERED OR
UNBUFFERED
ADC
C
ADC
INTERNAL
INPUT Z
*OPTIONAL
IF APPLICATIONSBROADBAND (b)
AVDD
3
ANALOG
INPUT
M50.0ns
CH3 2.00V
CH4
160mV
1k6
Looking at the ADC inputs differentially (Figure 11), one

can see that the input signal is much cleaner. The corrupt
clock-related glitches are gone. The common-mode rejection
inherent in differential signaling cancels out common-mode
noise, whether from the supply, digital sources, or charge
injection.
Buffered-input ADCs are easier to understand and use.
The input source is terminated in a fixed impedance. This
is buffered by a transistor stage that drives the conversion
process at low impedance, so charge-injection spikes and
switching transients are significantly reduced. Unlike
switched-capacitor ADCs, the input termination has little
variation over the ADCs analog input frequency range, so
selection of the proper drive circuit is much easier. The buffer
is specifically designed to be very linear and have low noise;
its only downside is that its power consumption causes the
ADC to dissipate more power overall.
Q. Can you show me some examples of transformer and amplifier

drive circuits?
336
VIN+
FB* 106
INPUT
Z = 506
4996
626
2pF TO
5pF
1k6
FB* 106
CH4 500mV
Figure 11. Differential measurement of a switchedcapacitor ADC input relative to the clock edges.

FB*
106 XFMR
1:1 Z
VIN
336
0.1MF
1k6
*FERRITE BEAD
IF APPLICATIONSBROADBAND (c)
ANALOG
INPUT
INPUT
Z = 506
0.1MF
10nH*
BALUN
1:1 Z
336
366
0.1MF
366
0.1MF
VIN+
C*
R*
336
VIN
336
VIN+
BALUN
1:1 Z
*OPTIONAL
IF APPLICATIONSNARROW BAND (d)

ANALOG
INPUT
INPUT
Z = 506
XFMR OR BALUN
1:1 TO 1:4 Z
0.1MF
R*
0.1MF*
0.1MF 0.1MF
0.1MF*
*OPTIONAL
**DEPENDS ON THE TRANSFORMER
***DEPENDS ON THE IF MATCH
R**
L***
R**
336
VIN
BUFFERED OR
UNBUFFERED
ADC
C
ADC
INTERNAL
INPUT Z
CML
Figure 12. ADC front-end designs with transformer drive.
When using an amplifier with a buffered or unbuffered ADC

in baseband applications, the design is fairly straightforward
(Figure 13). Just make sure that the common-mode voltage
of the amplifier is shared with the ADC, and use a simple
low-pass filter to get rid of the unwanted broadband noise
(a). For IF applications (b and c), the matching network
is essentially similar to that in baseband, but usually has
shallower roll-off. Inductors or ferrite beads can be used on
the outputs of the amplifier to help extend the bandwidth if

needed. This is not always necessary, however, because the
amplifiers characteristics are less prone to changing over the
band of interest than those of transformers. For narrow-band
or resonant applications (d), the filter is matched to the output
impedance of the amplifier to cancel the input capacitance
of the ADC. Usually a multipole filter is used to get rid of
broadband noise outside the frequency region of interest.
BASEBAND APPLICATIONS (a)

4996
AVDD
4996
10k6
506
336
AD8138
VOCM
SIGNAL
GENERATOR
10pF TO
20pF
AV = UNITY
18k6/10k6
0.1MF
5236
BUFFERED OR
UNBUFFERED
ADC
C
ADC INPUT
IMPEDANCE
336
4996
IF APPLICATIONSBROADBAND (b)
2006
AVDD
INDUCTOR OR
FERRITE
BEAD
2006
506
10k6
656
0.1MF
ADA4937
VOCM
C*
AV = UNITY
18k6/10k6
SIGNAL
GENERATOR
336
R
336
2886
ADC INPUT
IMPEDANCE
INDUCTOR OR
FERRITE
BEAD
2006
BUFFERED OR
UNBUFFERED
ADC
C
*OPTIONAL
IF APPLICATIONSBROADBAND (c)
XFMR
1:1 Z
0.1MF
0.1MF
RGP
256
506
CD*
SIGNAL
GENERATOR
RD*
1006
CML
1006
AD8352
RG*
RGN
256
0.1MF
336
ADC INPUT
IMPEDANCE
336
0.1MF
BUFFERED OR
UNBUFFERED
ADC
C
*AV = DEPENDS ON THE VALUE

OF CD, RD, AND RG.
IF APPLICATIONSNARROW BAND (RESONANT) (d)

0.1MF
506
1nF
SIGNAL
GENERATOR
256
0.1MF
CD
RD
RG
336
L*
RGP
656
AD8352
C*
AV = 10dB
RGN
1nF
L*
L*
C* CML
06 1006
1006
L*
C*
L*
336
BUFFERED OR
UNBUFFERED
ADC
C
ADC INPUT
IMPEDANCE
RN = 2006
CD = 0.3pF
RD = 4.3k6
RG = 1206
*DEPENDS ON IF MATCH
Figure 13. ADC front-end designs with amplifier drive.
Q. Would you summarize the important points?
Q. How about some references for further reading?
A. When facing a new design, remember to:

Understand the level of design difficulty.
Rank the important parameters in your design.
Include the ADC input impedance and the external
components in the input circuit when determining the
total load on the transformer or amplifier.
A. Application Notes
AN-742, Frequency-Domain Response of Switched-Capacitor
ADCs.
When choosing a transformer, always remember:

Not all transformers are created equal.
Understand transformer specifications.
Ask the manufacturer for parameters that are not given,
and/or do modeling.
High-IF designs are sensitive to transformer phase
imbalance.
Two transformers or baluns may be needed for very
high-IF designs to suppress the even-order distortions.
When choosing an amplifier, always remember:
Note the noise specification.
Understand amplifier specifications.
For low-IF or baseband frequencies, use the AD8138/
AD8139.
For mid-IF, use the ADA4937.
For high-IF designs, use the AD8352.
Amplifiers are less sensitive to imbalance and
automatically suppress even-order distortions.
Some amplifiers can dc-couple to the ADCs input, e.g.,
the AD8138/AD8139 and ADA4937/ADA4938.
Amplifiers inherently isolate the input source from output
loading effects and can therefore be more useful than
a transformer for dealing with sensitive input sources.
Amplifiers can drive long distances and are especially
useful when system partition dictates two or more
boards in a design.
Amplifiers may require another supply domain and will
always add to system power requirements.
When choosing an ADC, always remember:
Is the ADC internally buffered?
Switched-capacitor ADCs have a time-varying input
impedance and are more difficult to design with at
high-IFs.
If using an unbuffered ADC, always input-match in the
track mode.
Buffered ADCs are easier to design with, even at high IFs.
Buffered ADCs tend to burn more power.
Finally:
Baseband designs are the easiest with either ADC type.
Use ferrite beads or low-Q inductors to tune out the
input capacitance on switched-capacitor ADCs. This
maximizes input bandwidth, creates a better input
match, and maintains SFDR.
Two transformers may be needed to deal with high IFs.
AN-827, A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs.
B. Papers
Reeder, Rob. Transformer-Coupled Front-End for Wideband
A/D Converters. Analog Dialogue 39-2. 2005. pp. 3-6.

Reeder, Rob, Mark Looney, and Jim Hand. Pushing the State
of the Art with Multichannel A/D Converters. Analog Dialogue
39-2. 2005. pp. 7-10.
Kester, Walt. Which ADC Architecture Is Right for Your

Application? Analog Dialogue 39-2. 2005. pp. 11-18.
Reeder, Rob and Ramya Ramachandran. Wideband A/D

Converter Front-End Design ConsiderationsWhen to Use
a Double Transformer Configuration. Analog Dialogue 40-3.
2006. pp. 19-22.
C. Technical Data
AD9246, 80-/105-/125-MSPS 14-Bit, 1.8-V, SwitchedCapacitor ADC

AD9445 105-/125-MSPS 14-Bit, 5-/3.3-V, Buffered ADC
AD9446 16-Bit, 80-/100-MSPS Buffered ADC
AD8138 Low-Distortion Differential ADC Driver
AD8139 Ultralow Noise Fully Differential ADC Driver
AD8350 1.0-GHz Differential Amplifier
AD8351 Low-Distortion Fully Differential RF/IF Amplifier
AD8352 2-GHz Ultralow Distortion Differential RF/IF

Amplifier
ADA4937 Ultralow Distortion Differential ADC Driver
ADA4938 Ultralow Distortion Differential ADC Driver
ADC Switched-Capacitor Input Impedance Data (Sparameters)

for AD9215, AD9226, AD9235, AD9236, AD9237, AD9244,
AD9245. Go to their web pages, click on Evaluation Boards,
upload Microsoft Excel spreadsheet.
REFERENCESVALID AS OF FEBRUARY 2007

1
ADI website: www.analog.com (Search) ADA4937 (Go)

ADI website: www.analog.com (Search) AD9446-80 (Go)
3
4
5
6
7
8
9
10
2
Q: How are regulators distinguished by dropout voltage?
Low-Dropout Regulators
A: We can suggest three classes: standard regulators, quasi-LDOs,

and low-dropout regulators (LDOs).
By Jerome Patoux [jerome.patoux@analog.com]
Standard regulators, which typically employ NPN pass

transistors, usually drop out at about 2 V.
Quasi-LDO regulators usually use a Darlington structure

(Figure 2) to implement a pass device made up of an NPN
transistor and a PNP. The dropout voltage, VSAT (PNP) + V BE
(NPN), is typically about 1 Vmore than an LDO but less
than a standard regulator.
This article introduces the basic topologies and suggests good

practical usage for ensuring stable operation of low-dropout voltage
regulators (LDOs). We will also discuss design characteristics of
Analog Devices families of LDOs, which offer a flexible approach
to maintaining dynamic- and dc stability.
Q: What are LDOs and how are they used?
VIN
A: Voltage regulators are used to provide a stable power supply

voltage independent of load impedance, input-voltage
variations, temperature, and time. Low-dropout regulators
are distinguished by their ability to maintain regulation with
small differences between supply voltage and load voltage.
For example, as a lithium-ion battery drops from 4.2 V (fully
charged) to 2.7 V (almost discharged), an LDO can maintain
a constant 2.5 V at the load.

The increasing number of portable applications has thus

led designers to consider LDOs to maintain the required
system voltage independently of the state of battery charge.
But portable systems are not the only kind of application that
might benefit from LDOs. Any equipment that needs constant
and stable voltage, while minimizing the upstream supply
(or working with wide fluctuations in upstream supply), is a
candidate for LDOs. Typical examples include circuitry with
digital and RF loads.
A linear series voltage regulator (Figure 1) typically consists
of a reference voltage, a means of scaling the output voltage
and comparing it to the reference, a feedback amplifier, and
a series pass transistor (bipolar or FET), whose voltage drop
is controlled by the amplifier to maintain the output at the
required value. If, for example, the load current decreases,
causing the output to rise incrementally, the error voltage will
increase, the amplifier output will rise, the voltage across the
pass transistor will increase, and the output will return to its
original value.
VIN
VOUT
R1
ERROR
AMPLIFIER
VERR
R2
RL
R1
ERROR
AMPLIFIER
R2
RL
Figure 2. Quasi-LDO circuit.

LDO regulators are usually the optimal choice based on dropout

voltage, typically 100 mV to 200 mV. The disadvantage,
however, is that the ground-pin current of a LDO is usually
higher than that of a quasi-LDO or a standard regulator.
Standard regulators have a higher dropout voltage and

dissipation, and lower efficiency, than the other types. They
can be replaced by LDO regulators much of the time, but the
maximum input voltage specificationwhich can be lower
than that for standard regulatorsshould be considered.
In addition, some LDOs will need specially chosen external
capacitors to maintain stability. The three types differ somewhat
in both bandwidth and dynamic stability considerations.
Q: How can I select the best regulator for my application?

A: To choose the right regulator for a specific application, the
type and range of input voltage (e.g., the output voltage of
the dc-to-dc converter or switching power supply ahead of the
regulator), needs to be considered. Also important are: the
required output voltage, maximum load current, minimum
dropout voltage, quiescent current, and power dissipation.
Often, additional features may be useful, such as a shutdown
pin or an error flag to indicate loss of regulation.

The source of the input voltage needs to be considered in order

to choose a suitable category of LDO. In battery-powered
applications, LDOs must maintain the required system voltage
as the battery discharges. If the dc input voltage is provided
from a rectified ac source, the dropout voltage may not be
critical, so a standard regulatorwhich may be cheaper and
can provide more load currentcould be a better choice. But
an LDO could be the right choice if lower power dissipation
or a more precise output voltage is necessary.
The regulator should, of course, be able to provide enough

current to the load with specified accuracy under worst-case
conditions.
Figure 1. Basic enhancement-mode PMOS LDO.
The dropout voltage is the difference between the output voltage

and the input voltage at which the circuit quits regulation with
further reductions in input voltage. It is usually considered to be
reached when the output voltage has dropped to 100 mV below
the nominal value. This key factor, which characterizes the
regulator, depends on load current and junction temperature of
the pass transistor.
VERR
VREF
VREF
In Figure 1, the error amplifier and PMOS transistor form a

voltage-controlled current source. The output voltage, VOUT, is
scaled down by the voltage divider (R1, R2 ) and compared to the
reference voltage (V REF ). The error amplifier's output controls an
enhancement-mode PMOS transistor.
VOUT
LDO Topologies
In Figure 1, the pass device is a PMOS transistor. However, a

variety of pass devices are available, and LDOs can be classified
depending on which type of pass device is used. Their differing
structures and characteristics offer various advantages and
drawbacks.
Analog Dialogue 41-05, May (2007)
VOUT
SINGLE NPN
VIN
Q1
VOUT
VIN
VOUT
DARLINGTON NPN
VIN
VOUT
Q2
SINGLE PNP
PMOS
Figure 3. Examples of pass devices.

For a given supply voltage, the bipolar pass devices can deliver the
highest output current. A PNP is preferred to an NPN, because
the base of the PNP can be pulled to ground, fully saturating the
transistor if necessary. The base of the NPN can only be pulled
as high as the supply voltage, limiting the minimum voltage drop
to one V BE. Therefore, NPN and Darlington pass devices cant
provide dropout voltages below 1 V. They can be valuable, however,
where wide bandwidth and immunity to capacitive loading are
necessary (thanks to their characteristically low ZOUT ).
PMOS and PNP transistors can be effectively saturated, minimizing
the voltage loss and the power dissipated by the pass device, thus
allowing low dropout, high-efficiency voltage regulators. PMOS
pass devices can provide the lowest possible dropout voltage
drop, approximately R DS(ON) 3 IL . They also allow the quiescent
current flow to be minimized. The main drawback is that the
MOS transistor is often an external componentespecially for
controlling high currentsthus making the IC a controller, rather
than a complete self-contained regulator.
The power loss in a complete regulator is
PD = (VIN VOUT) IL + VINIGND

The first part of this relationship is the dissipation of the pass
device; the second part is the power consumption of the controller
portion of the circuit. The ground current in some regulators,
especially those using saturable bipolar transistors as pass devices,
can peak during power-up.
Q: How can LDO dynamic stability be ensured?
A: Classical LDO circuit designs for general-purpose applications
have problems with stability. The difficulties stem from the
nature of their feedback circuits, the wide range of possible
loads, the variability of elements within the loop, and the
difficulty of obtaining precision compensation devices with
consistent parameters. These considerations will be discussed
below, followed by a description of the anyCAP circuit
topology, which has improved stability.

LDOs generally use a feedback loop to provide a constant

voltage, independent of load, at the output. As is true for any
high-gain feedback loop, the location of the poles and zeros in
the loop-gain transfer function will determine the stability.
NPN-based regulators, with their low-impedance emitterloaded output, tend to be relatively insensitive to output
capacitive loading. PNP and PMOS regulators, however, have
higher output impedance (collector loaded in the case of the
PNP). In addition, the loops gain and phase characteristics
The transfer function of PNP- and PMOS-based LDOs has

several poles that impact stability:
The dominant pole (P0 in Figure 4) is set by the error
amplifier; it is controlled and fixed, in conjunction with

the gm of the amplifier, through an internal compensation
capacitance CCOMP. This pole is common to all of the LDO
topologies described above.
The second pole (P1) is set by the output elements (the
combination of the output capacitance and the load

capacitance and resistance). This makes the application
problem more difficult to handle, as these elements affect
both the loop gain and bandwidth.
A third pole (P2) is due to parasitic capacitance around the
pass elements. PNP power transistors have a unity-gain

frequency ( f T) much lower than that of comparable NPN
transistors, under the same conditions.
P0
GAIN (dB)
VIN
strongly depend on the load impedance, thus requiring special

consideration for stability.
P1
ZESR
P2
Figure 4. LDO frequency amplitude response.

As Figure 4 shows, each pole contributes 20 dB/decade of rolloff in gain, with up to 908 of phase shift. As the LDOs discussed
here have multiple poles, the linear regulator will be unstable if
the phase shift at the unity-gain frequency approaches 1808.
Figure 4 also shows the effect of loading the regulator with
a capacitor, whose effective series resistance (ESR) will add a
zero (ZESR ) into the transfer function. This zero will help to
compensate for one of the poles and can help to stabilize the
loop if it occurs below the unity-gain frequency and keeps the
phase shift well below 1808 at that frequency.
ESR can be critical for stability, especially for LDOs with verticalPNP pass devices. As a parasitic property of a capacitor, however,
the ESR is not always well-controlled. A circuit may require the
ESR to fall within a certain window to ensure that the LDO
operates in the stable region for all output currents (Figure 5).
UNSTABLE
CAPACITOR ESR (6)
Examples of four types of pass devices are shown in Figure 3,

including NPN and PNP bipolar transistors, Darlington circuits,
and PMOS transistors.
STABLE
UNSTABLE
IOUT (mA)
Figure 5. Stability as a function of output current and

load-capacitor ESR.
Even in principle, choosing the right capacitor with the right ESR
(high enough to reduce the slope before the frequency response
crosses through 0 dB, yet low enough to bring the gain below
0 dB before the associated pole, P2) can be challenging. Yet
the practical considerations add further challenges: ESR varies,
depending on the brand; and the minimum capacitance value
to use in production will require bench tests, including extreme
cases with minimum ambient temperature and maximum load.
The choice of the type of capacitor is also important. Perhaps the
most suitable are tantalum capacitors, despite their large size in the
higher-capacitance ranges. Aluminum electrolytics are compact,
but their ESR tends to deteriorate at low temperatures, and they
don't work well below 308C. Multilayer ceramic types do not
have sufficient capacitance for conventional LDOs (but they are
suitable for anyCAP designs, read on).
consumption, efficiency, price, ease of use, and the various

specifications and packages available.

The popular ADP33xx anyCAP family of ADI LDOs has been

on the market for several years. Based on a BiCMOS process
and a PNP pass transistor, it allows good regulation and many
of the advantages mentioned above, but tends to be somewhat
more expensive than CMOS parts.
Some recent designs, such as the ADP17xx family, are entirely

CMOS-based, with a PMOS pass transistor, which allows the
fabrication of LDOs at lower cost, but with a trade-off on
line-regulation performance. Devices in this family can handle
a large range of output capacitance, but they still require at
least 1 mF and 500-mV ESR. For example, the 150-mA
ADP17103 and ADP17114 are optimized for stable operation
with small 1-mF ceramic output capacitors, allowing for good
transient performance while occupying minimal board space,
and the 300-mA ADP1712,5 ADP1713,6 and ADP17147 can
use 2.2-mF capacitors.
Both of these families have 16 fixed-output-voltage options,

from 0.75 V to 3.3 V, as well as an adjustable-output option in
the 0.8-V to 5-V range. Accuracy is to within 62% over line,
load, and temperature. The ADP1711 and ADP1713 fixedvoltage versions allow for a reference-bypass capacitor to be
connected; this reduces output voltage noise and improves
power-supply rejection. The ADP1714 includes a tracking
feature, which allows the output to follow an external voltage
rail or reference. Dropout voltages at rated load are 150 mV
for the ADP1710 and ADP1711; and 170 mV for the ADP1712,
ADP1713, and ADP1714. Power-supply rejection (PSR) is high
(69 dB and 72 dB at 1 kHz), and power consumption is low,
with ground current of 40 mA and 75 mA with 100-mA load.
Typical transient responses of the ADP1710 and ADP1711 are

compared in Figure 7 for a nearly full-load step, with 1-mF
and 22-mF input- and output capacitors.
Analog Devices anyCAP family of LDOs
LDO implementation is considerably easier now, thanks to

improvements in both dc and ac performance associated with
regulators employing the Analog Devices anyCAP LDO
architecture. As the term implies, regulators embodying it are
relatively insensitive to both the size of the capacitor and its ESR,
thus allowing for a wider possible range of output capacitance.
The approach has spread and is now more widely available in
the marketplace, but it may be helpful to understand how this
architecture (Figure 6) simplifies the stability issue.
VOUT
VIN
CCOMP
NONINVERTING
WIDEBAND
DRIVER
gM
PTAT
VOS
R4
R3 D1
R1
CL
IPTAT
R2
RL
Figure 6. Simplified schematic of anyCAP LDO.

VOUT RESPONSE TO LOAD STEP
FROM 7.5mA TO 142.5mA
10mV/DIV
T he a ny C A P fa m i ly of L DOs, i nclud i ng t he 10 0 -m A
ADP33071 and the 200-mA low-quiescent-current ADP3331, 2
can remain stable with output capacitance as low as 0.47 mF,
using good-quality capacitors of any type, including compact
multilayer ceramic. ESR is essentially a nonissue.
The simplified schematic of Figure 6 shows how a single loop
provides both regulation and reference functions. The output
is sensed by the external R1-R2 voltage divider, and fed back
to the input of a high-gain amplifier through diode D1 and the
R3-R4 divider. At equilibrium, the amplifier produces a large,
repeatable, well-controlled offset voltage that is proportional to
absolute temperature (PTAT). This voltage combines with the
complementary temperature-sensitive diode voltage drop to
form the implicit reference, a temperature-independent virtual
band-gap voltage.
The amplifier output connects to an unusual noninverting
driver that controls the pass transistor, allowing the frequency
compensation to include the load capacitor in a pole-splitting
arrangement based on Miller compensation. This provides
reduced sensitivity to value, type, and ESR of the load capacitor.
Additional advantages of the pole-splitting scheme include superior
line-noise rejection and very high regulator gain, thereby providing
exceptional accuracy and excellent line and load regulation.
Q: Would you discuss the Analog Devices families of LDOs?
A: The choice of LDO depends, of course, on the supply voltage
range, load voltage, and required maximum dropout voltage.
The main differences between devices focus on power
ADP1710
CIN = 1MF
COUT = 1MF
ADP1711
CIN = 22MF
COUT = 22MF
VIN = 5V
VOUT = 3.3V
TIME (4Ms/DIV)
Figure 7. Transient response of ADP1710/ADP1711.

The operating junction temperature range is 408C to +1258C.
Both families are available in tiny 5-lead TSOT packages, a
b
small-footprint solution to the variety of power needs.
REFERENCESVALID AS OF MAY 2007

1
ADI website: www.analog.com (Search) ADP3307 (Go)

3
4
5
6
7
2
and test equipment. The resolution of the oscilloscope also became

a factor: at low input amplitudes, noise dominated the system and
made triggering difficult. I also observed intermittent rogue samples
of data (see Figure 3). Upon investigating, I found that these
erroneous samples occurred before the test equipment had finished
updating its settingsin effect a system settling-time issue. In the
end, each test consumed an incredible 35 minutes. Analyzing the
time usage for the test, I found that, for each sample, most of the time
was spent in communication between the host and the test equipment,
rather than actually performing the measurement.
Better, Faster Open-Loop Gain Measurement

By David Hunter [david.hunter@analog.com]
In systems that utilize feedback, the feedback network is a circuit

configured for a particular gain and phase relationshipfor
example, an adjustable proportional-integral-differential (PID)
controller to manipulate the loop gain and/or phase to ensure
stability (see Figure 1). It is often desirable to measure the
performance of this feedback network in a particular configuration
so as to model the open-loop behavior. But this type of measurement
is often challenging. For example, the low-frequency gain of an
integrator can be very high, generally exceeding the measurement
range of conventional test and measurement equipment. The goal
of such measurements is to characterize the frequency response of
the network rapidly and with minimal effort, using available tools
and a small amount of special circuitry.
INPUT V(s)
ERROR
+ AMPLIFIER
PLANT
H(s)
70
60
GAIN (dB)
50
40
30
20
OUTPUT Y(s)
10
FEEDBACK
NETWORK
G(s)
0
100
1k
Figure 1. A basic system implementing feedback.

Q. That makes sense. I have an example of a project that I would
welcome suggestions for.
A. Tell me about it.
Q. To qualify a recent design, I had been working on a programmable
feedback network and needed to collect hard data to verify the
expected behavior. To collect the data, I evaluated the available
test equipment and pieced together a crude open-loop measurement
system using a general-purpose interface-bus (GPIB) IEEE-488
interfacing card, a simple digital oscilloscope, and an arbitrary
function generator (see Figure 2).
HOST PC
USB
GPIB
SIGNAL
SOURCE
DEVICE
UNDER TEST
DIGITAL
OSCILLOSCOPE
Figure 2. Functional model of the test system.

Using the available developer libraries for the GPIB interface, I wrote
software to perform data-point collection for Bode plots. In much
the same way that we learned in engineering school to draw a Bode
plot by hand, the function generator was set to output a sine wave
at a set of frequencies, point by point, as the systems input. The
oscilloscope then measured both the system input and system output
to calculate the gain at a given frequency.
A. How did that turn out?

Q. After performing numerous iterations with the devices-under-test,
the faults of performing open-loop measurements on a budget, using
standard lab equipment, became apparent. High precision required
many data points, and each data point consumed significant
amounts of time simply to exchange messages between the software
10k
FREQUENCY (Hz)
100k
1M
Figure 3. Samples collected in three different tests of

the same configuration.
A. Execution time would improve if you were to implement

hardware functions to replace software routines. For example,
utilizing the available I2C serial bus on your programmable
device, less time would be spent sending ASCII characters to
form text-based command messages. By making this change,
youre removing several layers of abstraction and interpretation
from your test loop, resulting in precise and direct control of
the systems operation.
Q. W hat hardware devices would it take to implement such
a scheme?
A. Use a wideband direct digital synthesizer (DDS) IC, such as
the AD5932,1 to replace the function generator. This DDS
provides your design with excellent frequency range and a
high-quality sinusoidal output. Gain measurement becomes
a simple task with the application of a pair of logarithmic
amplifier ICs, such as the AD8307, 2 and a difference
amplifier. And the final critical piece of the acquisition system
is an analog-to-digital converter IC to replace the digital
oscilloscope. Using a multi-input ADC, such as the AD79923
or AD7994,4 will lower the total cost of the system by using
two available channels to capture the logarithmic amplifiers
result and perform the difference operation in software. The
revised arrangement will look like Figure 4.
PC
USB
SIGNAL
SOURCE
I2C
DEVICE
UNDER TEST
I2C
ADC
LOG-AMP
STAGE
Figure 4. Block diagram of new test system.
Analog Dialogue Volume 41 Number 4
Q. How does gain measurement with a log amp work?

A. In response to ac inputs, the AD8307 low-cost, easy-to-use
logarithmic amplifier produces a dc outputequivalent
to 25mV/dB of input power (0.5 V per decade of voltage)
into a 50- load. With a wide dynamic range of 92dB, the
device allows the user to measure even the small input signals
experienced in high-gain, open-loop circuits. While you
will not actually be driving 50- loads, this standard allows
calculating gain (in dB) as the difference of two AD8307 device
outputs, which measure the signal input and output.
Thus, for 0 dBm, or 1 mW, the input voltage amplitude is

316.2mV (or 223.6 mV rms). If that is the input level, and the
output amplitude of the device under test is 3.162 V (a gain of
10 with an rms amplitude of 2.236 V), then from Equation 6
the output power is +20 dBm, the same as one would obtain
from the voltage gain expressed by the ratio in Equation 5. The
values are consistent so long as the references are consistent.
We can therefore find the system gain easily.
Combining Equation 8 and Equation 6,
Q. Can you explain this in more detail?

A. We start with a brief review of logarithm rules:
(2)
(3)
(4)
(5)

In high-impedance voltage-amplifier circuits the focus

is on signal gain, rather than power gain. So dB is a
logarithmic expression of the ratio of output amplitude to
input amplitude.
At zero dB, the voltage ratio is unity. To express a given
power level measurement in dB, it must be referred to a
reference power level. In standard practice, if the measured
power is equal to 1 mW, the absolute power level is 0 dBm
(or dB above a milliwatt). For a 50- load,
Using a low-distortion sine wave, V rms and average powerfor

a 50- systemis calculated using Equations 7 and 8:
(7)
(8)

Apply the log amplifiers conversion gain of 25mV/dB:
(10)
Applying Equation 1, using two AD8307 log amplifiers to

measure output and input, their difference results in an easy
measurement of gain.
(6)
For unity impedance-ratios, log 1 = 0. Thus, for equalresistance loads,
Electrical power gain or attenuation is typically expressed as

a log ratio: Since the world of dB deals with ac voltages, VA
and V B are rms voltages, and, consequently, PA and PB are
average power levels.
(9)
(1)
(11)

The AD8307s inherent output at 0 dB is about 2.0 V.

However, the constants (when calibrated) drop out of the
equation when the output is calculated as the difference of
the log amp outputs.
Q. How do you find the difference?

A. There are many options to obtain the difference, ranging
from an easy-to-apply instrumentation amplifier, such as the
AD6225 or AD627,6 to a discrete multi-op-amp solution, or
even in software after conversion to digital, perhaps using a
multichannel ADC like the AD7994. For best accuracy, the
designer must, of course, calibrate to eliminate gain- and offset
errors between devices. Data sheets available on the Analog
Devices website provide this informationas well as excellent
tips on frequency-specific issues.
Q. You mentioned the AD5932 direct digital synthesizer. What
is that?
A. The AD5932 DDS is a simple, programmable, digitally
controlled waveform generator. Using a few simple instructions,
the user can configure sine waves, for example, with a complete
frequency and phase profile. While this device does not possess
an I2C interface, a GPIO device on the I2C bus can perform
bit-banging operations to imitate the expected interface. After
configuration is completed, a single write to the GPIO device
can increment the output frequency.

The output of the AD5932 is 580 mV peak-to-peak, a value

that is, in most cases, too large an input for open-loop gain
www.analog.com/analogdialogue
measurement. The attenuation needed depends on the input

level appropriate for gain measurement of the device under
test at its specified output level. If the input signal is too large,
the output will be distorted, or even clipped, giving false
measurements. If the signal is too small, offset errors and noise
will dominate the waveforms output and cause problems. A
typical signal starts at 10 mV in amplitude, then increases to
produce the specified device output valueor the largest value
possible without clipping or distortion, as distortion will cause
measurement errors.
80
60
GAIN (dB)
50
40
30
Q. Can you give me an example of how it works?
20
A. After assembling the circuit building blocks as shown in

Figure4, you can verify (or calibrate) the performance using,
first, a unity-gain amplifier, then a gain-of-10 amplifier in place
of the device under test.
10
0
100
Figure 5 is an example of measurements showing unity gain

and a gain of 10, actually about 1 dB high, with variation held
to well within 1 dB.
GAIN (dB)
10
100k
1M
Figure 6. Bode-plot data combining both new (blue)

and old (green) data. Note the sampling noise of
the traditional system.
A. Each test run was completed in under 35 seconds.

Q. Wow! Thats an improvement of about 6000%.
10
100
10k
FREQUENCY (Hz)
Q. The correlation looks good, and there seem to be none of the outliers
plotted in the earlier method. How long did it take to scan through
this set of measurements?
1k
Equipment:
1. National Instruments Cardbus GPIB adapter
2. Tektronix TDS3032B with GPIB
3. Tektronix AFG320 with GPIB
30
20
LOG AMP SYSTEM

TRADITIONAL SYSTEM
70
1k
10k
FREQUENCY (Hz)
100k
A. Yes, and, in addition, the simplicity of the design lends itself

easily to use in embedded systems, as the majority of the math
operations are managed by the log amplifiers. A clever designer
could also integrate a phase-measurement device and turn this
system into a true Bode plotter. And you could obtain an allin-one solution, with high-frequency applications, using the
single-chip AD83027 gain- and phase-measuring log amp.
1M
Figure 5. Example of calibration gain data to qualify

performance. Note the uncalibrated excess gain of
+1 dB for the 20-dB setting.
REFERENCESVALID AS OF NOVEMBER 2007
As another example, once confidence in the technique is gained,

a sample device with a known behavior can then be tested.
Figure 6 shows a typical result, superimposed on the previously
collected data to verify the accuracy of this method vs. that
of the method you described. The result of the test revealed
an error of about 0.5 dB, indicating that the new system
measurement had the same measurement characteristics, but
with far lower noise and faster settling times.

3
4
5
6
7
2
DVDD
AD8307
7.5mA
VPS 7
INP 8
INM 1
INP
ENB
INT
NINE DETECTOR CELLS

SPACED 14.3dB
COM 2
INPUT-OFFSET
COMPENSATION LOOP
INTERRUPT
MCLK
CTRL
2A
/dB
OUT
12.5k
STANDBY
AD5932
VCC
2.5V
24-BIT
PIPELINED
DDS CORE
INCR
FREQUENCY
CONTROLLER
AGND
AVDD
BUFFER
SYNCOUT
BUFFER
MSBOUT
SYNC
INCREMENT
CONTROLLER
DATA
MIRROR
1.1k
DGND
REGULATOR
BAND GAP REFERENCE

AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
+INP
CAP/2.5V
24
10-BIT
DAC
VOUT
FULL-SCALE
CONTROL
COMP
DATA AND CONTROL
COM
3
OFS
SERIAL INTERFACE
CONTROL
REGISTER
ON-BOARD
REFERENCE
FSYNC SCLK SDATA
This article is available in HTML and PDF at http://www.analog.com/analogdialogue. Click on archives, then select volume, number, and title.
10

Zero-Drift Operational Amplifiers
By Reza Moghimi
What Are Zero-Drift Amplifiers?
Zero-drift amplifiers dynamically correct their offset voltage and

reshape their noise density. Two commonly used typesautozero amplifiers and choppersachieve nanovolt-level offsets and
extremely low offset drifts due to time and temperature. The
amplifiers 1/f noise is also seen as a dc error, so it is removed as
well. Zero-drift amplifiers provide many benefits to designers, as
temperature drift and 1/f noise, always nuisances in the system,
are otherwise very difficult to eliminate. In addition, zero-drift
amplifiers have higher open-loop gain, power-supply rejection, and
common-mode rejection as compared to standard amplifiers; and
their overall output error is less than that obtained by a standard
precision amplifier in the same configuration.
of two consecutive noise samples results in true cancellation. At

higher frequencies this correlation diminishes, with subtraction
errors causing wideband components to fold back into the baseband.
Thus, auto-zero amplifiers have more in-band noise than standard
op amps. To reduce low-frequency noise, the sampling frequency
has to be increased, but this introduces additional charge injection.
The signal path includes only the main amplifier, so relatively large
unity-gain bandwidth can be obtained.
How Does a Chopper Work?
VOS1
How Does Auto-Zeroing Work?
Auto-zero amplifiers, such as the AD8538, AD8638, AD8551,

and AD8571 families, usually correct for input offset in two clock
phases. During Clock Phase A, switches labeled A are closed,
while switches labeled B are open, as shown in Figure 1. The
offset voltage of the nulling amplifier is measured and stored on
capacitor CM1.
MAIN
A
VIN
B
VOA
VOS
+
VOUT
B
VNB
CHOP3
VNULL
NULLING
CM1
VNA
Figure 1. Phase A of auto-zero amplifier: nulling phase.

During Clock Phase B, switches labeled B are closed, while
switches labeled A are open, as shown in Figure 2. The offset
voltage of the main amplifier is measured and stored on capacitor
CM2, while the stored voltage on capacitor CM1 adjusts for the offset
of the nulling amplifier. The overall offset is then applied to the
main amplifier while processing the input signal.
VOSB
+
VIN+
B
A
This is exactly what is done in a new series of amplifiers from

Analog Devices. The AD8628 zero-drift amplifier, shown in
Figure 4, uses both auto-zeroing and chopping to reduce the energy
at the chopping frequency, while keeping the noise very low at lower
frequencies. This combined technique allows wider bandwidth
than was possible with conventional zero-drift amplifiers.
1
INPL
INML
2, 3
1
A1
OUT
CC
A3
C1
C2
C3
C4
VN
A5
3
3
CM
VCMR
2
2
2
VN
Figure 2. Phase B of auto-zero amplifier: auto-zero phase.

The sample-and-hold function turns auto-zero amplifiers into
sampled-data systems, making them prone to aliasing and fold-back
effects. At low frequencies, noise changes slowly, so the subtraction
Analog Dialogue 44-03 Back Burner, March (2010)
A0
4, 1
NULLING
VOS3
Figure 3 shows the block diagram design of the ADA4051 chopper

amplifier, which uses a local autocorrection feedback (ACFB) loop.
The main signal path includes input chopping network CHOP1,
transconductance amplifier Gm1, output chopping network
CHOP2, and transconductance amplifier Gm2. CHOP1 and
CHOP2 modulate the initial offset and 1/f noise from Gm1 up to
the chopping frequency. Transconductance amplifier Gm3 senses
the modulated ripple at the output of CHOP2. Chopping network
CHOP3 demodulates the ripple back to dc. All three chopping
networks switch at 40 kHz. Finally, transconductance amplifier
Gm4 nulls the dc component at the output of Gm1which would
otherwise appear as ripple in the overall output. The switched
capacitor notch filter (SCNF) selectively suppresses the undesired
offset-related ripple without disturbing the desired input signal
from the overall output. It is synchronized with the chopping clock
to perfectly filter out the modulated components.
C5
CM
Gm3
Figure 3. Chopping scheme used in the ADA4051.
VOUT
B
VO
VOSA
+
SC NF
2, 3
MAIN
A
VIN
VOS4
Can the Two Techniques Be Combined?
CM2
Gm2
VOS2
Gm4
Zero-drift amplifiers are used in systems with an expected design

life of greater than 10 years and in signal chains that use high
closed-loop gains (>100) with low-frequency (<100 Hz), lowamplitude level signals. Examples can be found in precision weigh
scales, medical instrumentation, precision metrology equipment,
and infrared-, bridge-, and thermopile sensor interfaces.
VOS
+
Gm1
AUTOCORRECTION FEEDBACK
What Are Good Applications for Zero-Drift Amplifiers?
VIN
AUTOCORRECTION FEEDBACK LOOP CANCELS THE

INITIAL OFFSET OF Gm1s OUTPUT; LESS RIPPLE
CHOP2
CHOP1
4, 1
C6
4
A2
3
A4
3
1
2
Figure 4. The AD8628 combines auto-zeroing with chopping

to achieve wider bandwidth.
Table 1.
What Applications Issues Are Encountered When Using

Zero-Drift Amplifiers?
Zero-drift amplifiers are composite amplifiers that use digital

circuitry to dynamically correct for analog offset errors.
The charge injection, clock feedthrough, intermodulation
distortion, and increased overload recovery time that result
from the digital switching action can cause problems within
poorly designed analog circuits. The magnitude of the clock
feedthrough increases with an increase in closed-loop gain or
source resistance; adding a filter at the output or using a lower
resistance on the noninverting input will reduce the effect. Also,
the output ripple of a zero-drift amplifier increases as the input
frequency gets closer to the chopping frequency.
What Happens to Signals at Frequencies Higher Than That of the

Internal Clock?
Signals with frequencies greater than the auto-zero frequency

can be amplified. The speed of an auto-zeroed amplifier depends
on the gain-bandwidth product, which is dependent on the main
amplifier, not the nulling amplifier; the auto-zero frequency gives
an indication of when switching artifacts will start to occur.
What Are Some Differences Between Auto-Zeroing and Chopping?
NOISE DENSITY (nV/ Hz)
Auto-zeroing uses sampling to correct offset, while chopping uses

modulation and demodulation. Sampling causes noise to fold back
into baseband, so auto-zero amplifiers have more in-band noise.
To suppress noise, more current is used, so the devices typically
dissipate more power. Choppers have low-frequency noise
consistent with their flat-band noise but produce a large amount
of energy at the chopping frequency and its harmonics. Output
filtering may be required, so these amplifiers are most suitable
in low-frequency applications. Typical noise characteristics of
auto-zero and chopping techniques are shown in Figure 5.
STD OP AMP
AUTO-ZERO
CHOPPER
STABILIZED
+
AUTO-ZERO
CHOPPER
STABILIZED
Auto-Zero
Chopper
Stabilized
Chopper
Stabilized +
Auto-Zero
Very low offset,

TCVOS
Very low offset,

TCVOS
Very low offset,

TCVOS
Sample-and-hold
Modulation/
demodulation
Sample-andhold, modulation/
demodulation
Higher lowfrequency noise

due to aliasing
Similar noise
to flat band (no
aliasing)
Combined noise
shaped over
frequency
Higher power
consumption
Lower power
consumption
Higher power
consumption
Wide bandwidth
Narrow bandwidth Widest bandwidth
Lowest ripple
Higher ripple
Lower ripple level

than chopping
Little energy
at auto-zero
frequency
Lots of energy
at chopping
frequency
Little energy
at auto-zero
frequency
What Are Some of ADIs Popular Zero-Drift Amplifiers?
Table 2 shows a sample of zero-drift amplifiers offered by ADI.
References
1. Bridge-Type Sensor Measurements Are Enhanced by AutoZeroed Instrumentation Amplifiers. www.analog.com/

library/analogdialogue/cd/vol38n2.pdf#page=6.
2. Demystifying Auto-Zero AmplifiersPart 1. www.analog.
com/library/analogdialogue/cd/vol34n1.pdf#page=27.
3. Demystifying Auto-Zero AmplifiersPart 2. www.analog.
com/library/analogdialogue/cd/vol34n1.pdf#page=30.
4. MT-055 Tutorial, Chopper Stabilized (Auto-Zero) Precision
Op Amps. www.analog.com/static/imported-files/tutorials/
MT-055.pdf.
Author
FREQUENCY (kHz)
Figure 5. Typical noise of various amplifier topologies

vs. frequency.
When Should I Use Auto-Zero Amplifiers? When Should I Use Choppers?
Choppers are a good choice for low-power, low-frequency

applications (<100 Hz), while auto-zero amplifiers are better for
wideband applications. The AD8628, which combines auto-zero
and chopping techniques, is ideal for applications that require low
noise, no switching glitch, and wide bandwidth. Table 1 shows
some of the design trade-offs.
Reza Moghimi [reza.moghimi@analog.com] is

an applications engineer in San Jose, CA. He
received a BSEE from San Jose State University
in 1984 and an MBA in 1990and has also
received a number of on-the-job certificates.
He has worked for Raytheon Corporation,
Siliconix, Inc., and Precision Monolithics, Inc.
(PMI)which was integrated with Analog
Devices in 1990. At ADI, he has served in test-, product-, and
project-engineering assignments. He has written many articles
and design ideasand has given presentations at technical
seminars. His hobbies include travel, music, and soccer.
Table 2.
Part Number
Supply
Voltage
BW
@ ACL
Min
Quad
Min Max In Out (MHz)
2.5
AD8630 2.7 5.5
Single
AD8628
Dual
AD8629
AD8538
AD8539
AD8638
AD8639
4.5
16
AD8551
AD8552
AD8554
2.7
5.5
AD8571
AD8572
AD8574
2.7
5.5
1.8
5.5
ADA4051-1 ADA4051-2
Railto-Rail
2.7
5.5
Slew
Rate
(V/s)
1
VOS
Max
(V)
5
TCVOS
Typ
(V/C)
0.002
0.43
0.4
13
0.03
1.35
2.5
0.01
1.5
0.4
0.005
IS/
CMRR PSRR AVOL
Noise
Amp
Min
Min
Min @ 1 kHz Max
(dB)
(dB) (dB) (nV/Hz) (mA) Topology
120
115
125
22
1.1
AZ, C
115
105
115
50
0.18
AZ
118
127
120
60
1.3
AZ
120
120
125
42
0.975
AZ
1.5
0.4
0.005
120
120
125
51
0.975
AZ
0.115
0.04
15
0.02
105
110
106
95
0.017
Analog Dialogue 44-03 Back Burner, March (2010)
Switch and Multiplexer Design

Considerations for Hostile Environments
By Michael Manning
Introduction
Hostile environments found in automotive, military, and avionic

applications push integrated circuits to their technological
limits, requiring them to withstand high voltage and current,
extreme temperature and humidity, vibration, radiation, and a
variety of other stresses. Systems engineers are rapidly adopting
high-performance electronics to provide features and functions
in application areas such as safety, entertainment, telematics,
control, and human-machine interfaces. The increased use
of precision electronics comes at the price of higher system
complexity and greater vulnerability to electrical disturbances
including overvoltages, latch-up conditions, and electrostatic
discharge (ESD) events. Because electronic circuits used in these
applications require high reliability and high tolerance to system
faults, designers must consider both the environment and the
limitations of the components that they choose.
In addition, manufacturers specify absolute maximum ratings for
every integrated circuit; these ratings must be observed in order
to maintain reliable operation and meet published specifications.
When absolute maximum ratings are exceeded, operational
parameters cannot be guaranteed; and even internal protections
against ESD, overvoltage, or latch-up can fail, resulting in device
(and potentially further) damage or failure.
This article describes challenges engineers face when designing
analog switches and multiplexers into modules used in hostile
environments and provides suggestions for general solutions
that circuit designers can use to protect vulnerable parts. It also
introduces some new integrated switches and multiplexers that
provide increased overvoltage protection, latch-up immunity, and
fault protection to deal with common stress conditions.
Standard Analog Switch Architecture
To fully understand the effects of fault conditions on an analog switch,

we must first look at its internal structure and operational limits.
A standard CMOS switch (Figure 1) uses both N- and P-channel
MOSFETs for the switch element, digital control logic, and driver
circuitry. Connecting N- and P-channel MOSFETs in parallel
permits bidirectional operation, allowing the analog input voltage
to extend to the supply rails, while maintaining fairly constant on
resistance over the signal range.
INVERTER
VDD
VDD
PMOS
SOURCE
DRAIN I/O
NMOS
VSS
VDD
VSS
INPUT
BUFFER
DIGITAL
INPUT
DRIVER
GND
Figure 1. Standard analog switch circuitry.
The source, drain, and logic terminals include clamping

d iodes to t he suppl ies to prov ide E SD protec t ion, as
illustrated in Figure 1. Reverse-biased in normal operation,
the diodes do not pass current unless the signal exceeds the
supply voltage. The diodes vary in size, depending on the
process, but they are generally kept small to minimize leakage
current in normal operation.
The analog switch is controlled as follows: the N-channel device
is on for positive gate-to-source voltages and off for negative
gate-to-source voltages; the P-channel device is switched by
the complementary signal, so it is on at the same time as the
N-channel device. The switch is turned on and off by driving
the gates to opposite supply rails.
With a fixed voltage on the gate, the effective drive voltage
for either transistor varies in proportion to the polarity and
magnitude of the analog signal passing through the switch.
The dashed lines in Figure 2 show that when the input signal
approaches the supplies, the channel of one device or the other
will begin to saturate, causing the on resistance of that device
to increase sharply. The parallel devices compensate for one
another in the vicinity of the rail voltages, however, so the result
is a fully rail-to-rail switch, with relatively constant on resistance
over the signal range.
P-CHANNEL RON
RON ( )
N-CHANNEL RON
COMBINED
RESISTANCE
OF PMOS AND
NMOS FETs.
VSOURCE (V)
Figure 2. Standard analog switch RON graph.
Absolute Maximum Ratings
Switch power requirements, specif ied in the device data

sheet, should be followed in order to guarantee optimal
performance, operation, and lifetime. Unfortunately, power
supply failures, voltage transients in harsh environments,
and system or user faults that occur in the course of realworld operation may make it impossible to meet data sheet
recommendations consistently.
Whenever an analog switch input voltage exceeds the supplies, the
internal ESD protection diodes become forward-biased, allowing
large currents to flow, even if the supplies are turned off, causing
ratings to be exceeded. When forward-biased, the diodes are not
rated to pass currents greater than a few tens of milliamperes; they
can be damaged if this current is not limited. Furthermore, the
damage caused by a fault is not limited to the switch but can also
affect downstream circuitry.
The Absolute Maximum Ratings section of a data sheet (Figure 3)
describes the maximum stress conditions a device can tolerate; it
is important to note that these are stress ratings only. Exposure to
absolute maximum ratings conditions for extended periods may
affect device reliability. The designer should always follow good
engineering practice by building margin into the design. The
example here is from a standard switch/multiplexer data sheet.
Common Fault Conditions, System Stresses, and Protection Methods
Fault conditions can occur for many different reasons; some of

the most common system stresses and their real-world sources
are shown in Table 1:
Table 1.
Figure 3. Absolute Maximum Ratings section of a data sheet.

In this example, the V DD to VSS parameter is rated at 18 V.
The rating is determined by the switchs manufacturing
process and design architecture. Any voltage higher than 18 V
must be completely isolated from the switch, or the intrinsic
breakdown voltages of elements associated with the process
will be exceeded, which may damage the device and lead to
unreliable operation.
Voltage limitations that apply to the analog switch inputswith
and without power suppliesare often due to the ESD protection
circuitry, which may fail as a result of fault conditions.
VDD
VDD
SOURCE I/O
DRAIN I/O
VSS
VSS
Figure 4. Analog switchESD protection diodes.

Analog and digital input voltage specifications are limited to
0.3 V beyond V DD and V SS , while digital input voltages are
limited to 0.3 V beyond V DD and ground. When the analog
inputs exceed the supplies, the internal ESD protection diodes
become forward-biased and begin to conduct. As stated in the
Absolute Maximum Ratings section, overvoltages at IN, S, or
D are clamped by internal diodes. While currents exceeding
30 mA can be passed through the internal diodes without any
obvious effects, device reliability and lifetime may be reduced,
and the effects of electromigration, the gradual displacement
of metal atoms in a conductor, may be seen over time. As heavy
current f lows through a metal path, the moving electrons
interact with metal ions in the conductor, forcing atoms to
move with the f low of electrons. Over time this can lead to
open- or short circuits.
When designing a switch into a system, it is important to consider
potential faults that may occur in the system due to component
failure, user error, or environmental effects. The next section will
discuss how fault conditions that exceed the absolute maximum
ratings of a standard analog switch can damage the switch or cause
it to malfunction.
Fault Type
Fault Causes
Overvoltage:
Loss of power
System malfunction
Hot-swap connects and disconnects
Power-supply sequencing issues
Miswiring
User error
Latch-Up:
Overvoltage conditions (as listed above)

Exceeding process ratings
SEU (single-event upsets)
ESD
Storage/assembly
PCB assembly
User operation
Some stress may not be preventable. Regardless of the source of

the stress, the more important issue is how to deal with its effects.
The questions and answers below cover these fault conditions:
overvoltages, latch-up, and ESD eventsand some common
methods of protection.
OVERVOLTAGE
What Is an Overvoltage Condition?
Overvoltage conditions occur when analog or digital input

conditions exceed the absolute maximum ratings. The following
three examples highlight some common issues designers need to
consider when using analog switches.
1. Loss of power with signals present on analog inputs (Figure 5).
In some applications, the power supply to a module is lost, while
input signals from remote locations may still be present. When
power is lost, the power supply rails may go to groundor one
or more may float. If the supplies go to ground, the input signals
can forward-bias the internal diode, and current from the switch
input will flow to grounddamaging the diode if the current is
not limited.
VDD
VS > VDD
FORWARD
CURRENT
FLOWS
LOAD
CURRENT
FORWARD
CURRENT
S
RS
RL
VS
GND
VSS
Figure 5. Fault paths.

If loss of power causes the supplies to float, the input signals
can power the part through the internal diodes. As a result, the
switchand possibly any other components running from its V DD
supplymay be powered up.
2. Overvoltage conditions on analog inputs.
VDD
When analog signals exceed the power supplies (V DD and VSS),

the supplies can be pulled to within a diode drop of the fault
signal. Internal diodes become forward-biased and currents flow
from the input signal to the supplies. The overvoltage signal can
also pass through the switch and damage parts downstream. The
explanation for this can be seen by considering the P-channel
FET (Figure 6).
RL
GND
0V
0V
VSS
GND
Figure 8. Resistor-diode protection network.
0V
Figure 6. FET switch.

A P-channel FET requires a negative gate-to-source voltage to
turn it on. With the switch gate equal to V DD, the gate-to-source
voltage is positive, so the switch is off. In an unpowered circuit,
with the switch gate at 0 V or where the input signal exceeds V DD,
the signal will pass through the switchas there is now a negative
gate-to-source voltage.
3. Bipolar signals applied to a switch powered from a single supply.
This situation is similar to the previously described overvoltage
condition. The fault occurs when the input signal goes below
ground, causing the diode from the analog input to ground to
forward-bias and current to flow. When an ac signal, biased at
0 V dc, is applied to the switch input, the parasitic diodes can be
forward-biased for some portion of the negative half-cycle of the
input waveform. This happens if the input sine wave goes below
approximately 0.6 V, turning the diode on and clipping the input
signal, as shown in Figure 7.
Schottky diodes connected from the analog inputs to the supplies

provide protection, but at the expense of leakage and capacitance.
The diodes work by preventing the input signal from exceeding the
supply voltage by more than 0.3 V to 0.4 V, ensuring that the internal
diodes do not forward bias and current does not flow. Diverting the
current through the Schottky diodes protects the device, but care
must be taken not to overstress the external components.
A third method of protection involves placing blocking diodes
in series with the supplies (Figure 9), blocking current flow
through the internal diodes. Faults on the inputs cause the
supplies to float, and the most positive and negative input signals
become the supplies. As long as the supplies do not exceed the
absolute maximum ratings of the process, the device should
tolerate the fault. The downside to this method is the reduced
analog signal range due to the diodes on the supplies. Also,
signals applied to the inputs may pass through the device and
affect downstream circuitry.
VDD
VDD = 0V
SWITCH
SIGNAL
RANGE
CLIPPING
1
GND = 0V
5V INPUT
SOURCE INPUT:
5V SINE WAVE
VS
RL
DRAIN OUTPUT:
CLIPPED SIGNAL
GND
VSS
Figure 9. Blocking diodes in series with supplies.

CH1 2.00V
CH2 100mV
M200s
T
36.0s
A CH1
3.00V
Figure 7. Clipping.
Whats the Best Way to Deal with Overvoltage Conditions?
The three examples above are the results of analog inputs

exceeding a supplyV DD, V SS , or GND. Simple protection
methods to counter these conditions include the addition of
external resistors, Schottky diodes to the supplies, and blocking
diodes on the supplies.
Resistors, to limit current, are placed in series with any
switch channel that is exposed to external sources (Figure 8).
The resistance must be high enough to limit the current to
approximately 30 mA (or as specified by the absolute maximum
ratings). The obvious downside is the increase in RON, RON,
per channel, and ultimately the overall system error. Also, for
applications using multiplexers, faults on the source of an off
channel can appear at the drain, creating errors on other channels.
While these protection methods have advantages and disadvantages,

they all require external components, extra board area, and
additional cost. This can be especially significant in applications
with high channel count. To eliminate the need for external
protection circuitry, designers should look for integrated protection
solutions that can tolerate these faults. Analog Devices offers a
number of switch/mux families with integrated protection against
power off, overvoltage, and negative signals.
What Prepackaged Solutions Are Available?
The ADG4612 and ADG4613 from Analog Devices offer low on

resistance and distortion, making them ideal for data acquisition
systems requiring high accuracy. The on resistance profile is very
flat over the full analog input range, ensuring excellent linearity
and low distortion.
The ADG4612 family offers power-off protection, overvoltage
protection, and negative-signal handling, all conditions a standard
CMOS switch cannot handle.
When no power supplies are present, the switch remains in the off
condition. The switch inputs present a high impedance, limiting
current flow that could damage the switch or downstream circuitry.
This is very useful in applications where analog signals may be
present at the switch inputs before the power is turned on, or
where the user has no control over the power supply sequence. In
the off condition, signal levels up to 16 V are blocked. Also, the
switch turns off if the analog input signal level exceeds V DD by V T.
SX
DX
OV
MONITOR
SX
DX
DIGITAL
INPUT
PS
MONITOR
INX
VDD
The ADG465 single- and ADG467 octal channel protectors

have the same protective architecture as these fault-protected
multiplexers, without the switch function. When powered, the
channel is always in the on condition, but in the event of a fault,
the output is clamped to within the supply voltages.
LATCH-UP
What Is a Latch-Up Condition?
Latch-up may be defined as the creation of a low-impedance

path between power supply rails as a result of triggering a
parasitic device. Latch-up occurs in CMOS devices: intrinsic
parasitic devices form a PNPN SCR structure when one of the
two parasitic base-emitter junctions is momentarily forwardbiased (Figure 12). The SCR turns on, causing a continuing
short between the supplies. Triggering a latch-up condition is
serious: in the best case, it leads to device malfunction, with
power cycling required to restore the device to normal operation;
in the worst case, the device (and possibly power supply) can be
destroyed if current flow is not limited.
Figure 10. ADG4612/ADG4613 switch architecture.

Figure 10 shows a block diagram of the familys power-off
protection architecture. Switch source- and drain inputs are
constantly monitored and compared to the supply voltages, V DD
and VSS. In normal operation the switch behaves as a standard
CMOS switch with full rail-to-rail operation. However, during a
fault condition where the source or drain input exceeds a supply by
a threshold voltage, internal fault circuitry senses the overvoltage
condition and puts the switch in isolation mode.
Analog Devices also offers multiplexers and channel protectors
that can tolerate overvoltage conditions of +40 V/25 V beyond the
supplies with power (15 V) applied to the device, and +55 V/40 V
unpowered. These devices are specifically designed to handle faults
caused by power-off conditions.
PMOS
NMOS
NMOS
PMOS
VSS
VDD
Figure 11. High-voltage fault-protected switch architecture.

These devices comprise N-channel, P-channel, and N-channel
MOSFETs in series, as illustrated in Figure 11. When one of the
analog inputs or outputs exceeds the power supplies, one of the
MOSFETs switches off, the multiplexer input (or output) appears
as an open circuit, and the output is clamped to within the supply
rail, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. This protects the multiplexer,
the circuitry it drives, and the sensors or signal sources that drive
the multiplexer. When the power supplies are lost (through, for
example, battery disconnection or power failure) or momentarily
disconnected (rack system, for example), all transistors are off and
the current is limited to subnanoampere levels. The ADG508F,
A DG509F, and A DG528F include 8:1 and dif ferential
4:1 multiplexers with such functionality.
I/O
I/O
I/O
I/O
VSS/GND
N+
P+
P+
N+
N+
P+
RW
Q1
Q2
N-WELL
RS
P SUBSTRATE
I/O
VDD
RW
Q1
(b)
Q2
RS
VSS/GND
I/O
Figure 12. Parasitic SCR structure: a) device

b) equivalent circuit.
VSS
VDD
(a)
VDD
The fault and overvoltage conditions described earlier are among

the common causes of triggering a latch-up condition. If signals
on the analog or digital inputs exceed the supplies, a parasitic
transistor is turned on. The collector current of this transistor
causes a voltage drop across the base emitter of a second parasitic
transistor, which turns the transistor on, and results in a selfsustaining path between the supplies. Figure 12(b) clearly shows
the SCR circuit structure formed between Q1 and Q2.
Events need not last long to trigger latch-up. Short-lived transients,
spikes, or ESD events may be enough to cause a device to enter
a latch-up state.
Latch-up can also occur when the supply voltages are stressed
beyond the absolute maximum ratings of the device, causing
internal junctions to break down and the SCR to trigger.
The second triggering mechanism occurs if a supply voltage
is raised enough to break down an internal junction, injecting
current into the SCR.
Whats the Best Way to Deal with Latch-Up Conditions?
Protection methods against latch-up include the same protection

methods recommended to address overvoltage conditions.
Adding current-limiting resistors in the signal path, Schottky
diodes to the supplies, and diodes in series with the suppliesas

illustrated in Figure 8 and Figure 9all help to prevent current
from flowing in the parasitic transistors, thereby preventing the
SCR from triggering.
Switches with multiple supplies may have additional power-supply
sequencing issues that may violate the absolute maximum ratings.
Improper supply sequencing can lead to internal diodes turning
on and triggering latch-up. External Schottky diodes, connected
between supplies, will adequately prevent SCR conduction by
ensuring that when multiple supplies are applied to the switch,
V DD is always within a diode drop (0.3 V for Schottky) of these
supplies, thereby preventing violation of the maximum ratings.
As an alternative to using external protection, some ICs are

manufactured using a process with an epitaxial layer, which
increases the substrate- and N-well resistances in the SCR
structure. The higher resistance means that a harsher stress is
required to trigger the SCR, resulting in a device that is less
susceptible to latch-up. An example is the Analog Devices iCMOS
process, which made possible the ADG121x, ADG141x, and
ADG161x switch/mux families.
For applications requiring a latch-up proof solution, new
trench-isolated switches and multiplexers guarantee latch-up
prevention in high-voltage industrial applications operating at up
to 20 V. The ADG541x and ADG521x families are designed
for instrumentation, automotive, avionics, and other harsh
environments that are likely to foster latch-up. The process uses
an insulating oxide layer (trench) placed between the N-channel
and the P-channel transistors of each CMOS switch. The oxide
layers, both horizontal and vertical, produce complete isolation
between devices. Parasitic junctions between transistors in
junction-isolated switches are eliminated, resulting in a completely
latch-up proof switch.
I/O
T
R
E
N
C
H
P+
VG
I/O
P-CHANNEL
P+
VG
I/O
T
R
E
N
C
H
N+
N-CHANNEL
I/O
N+
T
R
E
N
C
H
SUBSTRATE (BACKGATE)
Figure 13. Trench isolation in latch-up prevention.

The industry practice is to classify the susceptibility of inputs
and outputs to latch-up in terms of the amount of excess current
an I/O pin can source or sink in the overvoltage condition before
the internal parasitic resistances develop enough voltage drop to
sustain the latch-up condition.
A value of 100 mA is generally considered adequate. Devices in the
ADG5412 latch-up proof family were stressed to 500 mA with
a 1-ms pulse without failure. Latch-up testing at Analog Devices
is performed according to EIA/JEDEC-78 (IC Latch-Up Test).
Typically the most common type of voltage transient that

a device is exposed to, ESD, can be def ined as a single,
ICs can be damaged by the high voltages and high peak currents
generated by an ESD event. The effects of an ESD event on
an analog switch can include reduced reliability over time, the
degradation of switch performance, increased channel leakage,
or complete device failure.
ESD events can occur at any stage of the life of an IC, from
manufacturing through testing, handling, OEM user, and enduser operation. In order to evaluate an ICs robustness to various
ESD events, electrical pulse circuits modeling the following
simulated stress environments were identified: human body model
(HBM), field-induced charged device model (FICDM), and machine
model (MM).
Whats the Best Way to Deal with ESD Events?
ESD prevention methods, such as maintaining a static-safe work

area, are used to avoid any build up during production, assembly,
and storage. These environments, and the individuals working in
them, can generally be carefully controlled, but the environments
in which the device later finds itself may be anything but controlled.
Analog switch ESD protection is generally in the form of diodes
from the analog and digital inputs to the supplies, as well as power
supply protection in the form of diodes between the suppliesas
illustrated in Figure 14.
ANALOG INPUT
PROTECTION
DIGITAL INPUT
PROTECTION
VDD
BURIED OXIDE LAYER
ESDELECTROSTATIC DISCHARGE
What Is an Electrostatic Discharge Event?
fast, high-current transfer of electrostatic charge between two objects

at different electrostatic potentials. We frequently experience this
after walking across an insulating surface, such as a rug, storing
a charge, and then touching an earthed piece of equipment
resulting in a discharge through the equipment, with high currents
flowing in a short space of time.
VL
VSS
POWER SUPPLY
PROTECTION
VDD
VDD
VSS
VSS
GND
IN
GND
Figure 14. Analog switch ESD protection.

The protection diodes clamp voltage transients and divert current
to the supplies. The downside of these protection devices is that
they add capacitance and leakage to the signal path in normal
operation, which may be undesirable in some applications.
For applications that require greater protection against ESD
events, discrete components such as Zener diodes, metal-oxide
varistors (MOVs), transient voltage suppressors (TVS), and diodes
are commonly used. However, they can lead to signal integrity
issues due to the extra capacitance and leakage on the signal line;
this means design engineers need to carefully consider the tradeoff between performance and reliability.
While the vast majority of ADI switch/mux products meet HBM

levels of at least 2 kV, others go beyond this in robustness,
achieving HBM ratings of up to 8 kV. ADG541x family members
have achieved a 8-kV HBM rating, a 1.5-kV FICDM rating,
and a 400-V MM rating, making them industry leaders,
combining high-voltage performance and robustness.
Conclusion
When switch or multiplexer inputs come from remotely located

sources, there is an increased likelihood that faults can occur.
Overvoltage conditions may occur due to systems with poorly
designed power-supply sequencing or where hot-plug insertion is
a requirement. In harsh electrical environments, transient voltages
due to poor connections or inductive coupling may damage
components if not protected. Faults can also occur due to powersupply failures where power connections are lost while switch
inputs remain exposed to analog signals. Significant damage may
result from these fault conditions, possibly causing damage and
requiring expensive repairs. While a number of protective design
techniques are used to deal with faults, they add extra cost and
board area and often require a trade-off in switch performance; and
even with external protection implemented, downstream circuitry
is not always protected. Since analog switches and multiplexers are
often a modules most likely electronic components to be subjected
to a fault, it is important to understand how they behave when
exposed to conditions that exceed the absolute maximum ratings.
Switch/mux products, like devices mentioned here, are available

with integrated protection, allowing designers to eliminate external
protection circuitry, reducing the number and cost of components
in board designs. Savings are even more significant in applications
with high channel count.
Ultimately, using switches with fault protection, overvoltage
protection, immunity to latch-up, and a high ESD rating yields
a robust product that meets industry regulations and enhances
customer and end-user satisfaction.
Author
Michael Manning [michael.manning@analog.com]

graduated from National University of Ireland,
Galway, w it h a BSc i n applied physics a nd
electronics. In 2006, he joined Analog Devices as
an applications engineer in the switch/multiplexer
group in Limerick, Ireland. Previously, Michael
spent five years as a design and applications engineer in the
automotive division at ALPS Electric in Japan and Sweden.
APPENDIX
Analog Devices Switch/Multiplexer Protection Products:
High-Voltage Latch-Up Proof Switches
Part
Number
Max
On
Number
Analog Charge Leakage
of Switch RON Signal Injection @ 85C
Configuration Functions () Range
(pC)
(nA)
Supply Voltages
Packages
Price @ 1k
($U.S.)
ADG5212
SPST/NO
160
VSS to
V DD
0.07
0.25
Dual (15 V), Dual (20 V),

Single (+12 V), Single (+36 V)
CSP, SOP
2.18
ADG5213
SPST/
NO-NC
160
VSS to
V DD
0.07
0.25

CSP, SOP
2.18
ADG5236
SPST/
NO-NC
160
VSS to
V DD
0.6
0.4

CSP, SOP
2.26
ADG5412
SPST/NO
VSS to
V DD
240

CSP, SOP
2.18
ADG5413
SPST/NO-NC
VSS to
V DD
240

CSP, SOP
2.18
ADG5433
SPST/NO-NC
12.5
VSS to
V DD
130

CSP, SOP
2.15
ADG5434
SPST/NO-NC
12.5
VSS to
V DD
130

SOP
3.04
ADG5436
SPST/NO-NC
VSS to
V DD
0.6

CSP, SOP
2.26
High-Voltage Latch-Up Proof Multiplexers

Part
Number
RON
Configuration ()
Max
Analog
Signal
Range
On
Charge
On
Leakage
Injection Capacitance @ 85C
(pC)
(pF)
(nA)
Supply Voltages
Packages
Price @
1000 to
4999
($U.S.)
ADG5204
(4:1) 2
160
VSS to
V DD
0.6
30
0.5
Dual (15 V), Dual (20 V), CSP, SOP

2.26
ADG5408
(8:1) 1
14.5
VSS to
V DD
115
133

2.41
ADG5409
(4:1) 2
12.5
VSS to
V DD
115
81

2.41
ADG5404
(4:1) 1
VSS to
V DD
220
132

2.26
Low-Voltage Fault-Protected Multiplexers

Part
Number
Configuration
Number
of Switch
Functions
ADG4612
SPST/NO
ADG4613
SPT/NO-NC
Max
Analog
Signal
Range
5.5 V to
V DD
5.5 V to
V DD
Fault
Response
Time (ns)
Fault
Recovery
Time (s)
3 dB
Bandwidth
(MHz)
Packages
Price @ 1k
($U.S.)
295
1.2
293
SOP
1.84
295
1.2
294
CSP, SOP
1.84
High-Voltage Fault-Protected Multiplexers

Switch/
Mux
Function
x#
RON
()
ADG438F (8:1) 1
400
ADG439F
(4:1) 2
400
ADG508F (8:1) 1
300
ADG509F
(4:1) 2
ADG528F
(8:1) 1
Part
Number
tTRANSITION
(ns)
Supply
Voltages (V)
Power Dissipation (mW)
Packages
Price @
1000 to
4999
($U.S.)
170
Dual (15 V)
2.6
DIP, SOIC
3.68
170
Dual (15 V)
2.6
DIP, SOIC
3.68
VSS + 3 V to
V DD 1.5 V
200
Dual (12 V),

Dual (15 V)
DIP, SOIC
3.31
300
VSS + 3 V to
V DD 1.5 V
200
Dual (12 V),

Dual (15 V)
DIP, SOIC
3.31
300
VSS + 3 V to
V DD 1.5 V
200
Dual (12 V),

Dual (15 V)
DIP, LCC
3.91
Max Analog
Signal Range
VSS + 1.2 V to
V DD 0.8 V
VSS + 1.2 V to
V DD 0.8 V
High-Voltage Channel Protectors

Part Number
ADG465
ADG467
Configuration
Channel Protector
Channel Protector
Number
of Switch
Functions
1
8
RON
()
80
62
Max Positive
Supply (V)
20
20
Max Negative
Supply (V)
20
20
Packages
SOIC, SOT
SOIC, SOP
Price @ 1k
($U.S.)
0.84
2.40

LDO Operational Corners: Low Headroom
and Minimum Load
LDO Headroom and Its Effects on Output Noise and PSRR
By Glenn Morita
The latest multigigahertz analog circuits, built on deep submicron processes, require ever-lower power supply voltages, in
some cases less than 1 V. These high-frequency circuits often
require a considerable amount of supply current, so thermal
management can become difficult. A design goal is to reduce
power dissipation to that which is absolutely necessary for
circuit performance.
Switch-mode dc-to-dc converters make the most efficient
power supplies, with some devices exceeding 95% efficiency,
but this high efficiency comes at the cost of increased powersupply noise, often over a wide bandwidth. Low-dropout
linear regulators (LDOs) are frequently used to clean up noisy
supply rails, but they also present trade-offs, dissipating power
and increasing the systems thermal load. To minimize these
problems, LDOs can be operated with a smaller difference
(headroom voltage) between input and output voltages. This
article discusses the impact of low-headroom voltage operation on power-supply rejection and total output noise.
LDO Power-Supply Rejection vs. Headroom

LDO power-supply rejection ratio (PSRR) is strongly dependent on headroom voltagethe difference between the input
and output voltages. For a fixed headroom voltage, PSRR
decreases as the load current increases; this is especially true with
large load currents and small headroom voltages. Figure 1 shows
the PSRR for the ADM7160 ultralow-noise, 2.5-V linear regulator
with 200-mA load current and 200-mV, 300-mV, 500-mV and
1-V headroom voltages. As the headroom voltage decreases,
the PSRR decreases, and the difference can be dramatic. For
example, at 100 kHz, changing the headroom voltage from
1 V to 500 mV results in a 5-dB decrease in PSRR. However, a
smaller change in headroom voltage, from 500 mV to 300 mV,
causes the PSRR to drop more than 18 dB.
Figure 2 shows a block diagram of the LDO. As the load current increases, the gain of the PMOS pass element decreases
as it leaves saturation and enters the triode region. This causes
the overall loop gain to decrease, resulting in lower PSRR. The
smaller the headroom voltage, the more dramatic the reduction in gain. As the headroom voltage continues to decrease, it
reaches a point at which the gain of the control loop drops to 1,
and the PSRR falls to 0 dB.
Another factor that reduces the loop gain is the resistance
of the pass element, which includes the FETs on resistance,
the on-chip interconnect resistance, and the wire bonds. An
estimate of this resistance can be derived from the dropout
voltage. For example, the ADM7160 in the WLCSP package
has a maximum dropout voltage of 200 mV at 200 mA. Using
Ohms law, the resistance of the pass element is about 1 .
The pass element can be approximated as a fixed resistor
plus a variable resistance.
Voltage drops due to the load current flowing through this
resistance subtract from the drain-to-source operating voltage
of the FET. For example, with a 1- FET, a load current of
200 mA reduces the drain-to-source voltage by 200 mV. When
estimating the PSRR of LDOs operating with 500-mV or 1-V
headroom, the voltage drop across the pass element must be
taken into account, as the pass FET is effectively operating
with only 300 mV or 800 mV.
VIN
VARIABLE
RDSON RESISTANCE
REFERENCE
ADM7160 PSRR VS HEADROOM VOLTAGE 2.5V/200mA
NOTES
1. ERROR AMP CONTROLS VALUE OF VARIABLE
RESISTOR TO REGULATE OUTPUT VOLTAGE.
2. AT LOW HEADROOM VOLTAGE, THE VARIABLE
RESISTOR IS NEARLY 0.
0
10
PSRR (dBm)
20
VOUT
GND
1V
500mV
300mV
200mV
VIN
30
VOUT
40
R1
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECTION
GND
50
60
70
10
EN
100
1k
10k
100k
1M
10M
SHUTDOWN
REN
REFERENCE
R2
FREQUENCY (Hz)
Figure 1. ADM7160 PSRR vs. headroom.
Analog Dialogue 48-09, September 2014
Figure 2. Block diagram of a low-dropout regulator.
analog.com/analogdialogue
Effect of Tolerances on LDO Headroom

Customers often ask applications engineers to help them select
an LDO to generate low-noise voltage X from input voltage Y
at load current Z, but one factor frequently ignored when setting these parameters is the tolerance of the input and output
voltages. As headroom voltage falls to lower and lower values,
the tolerance of the input and output voltages can dramatically affect the operating conditions. The worst-case tolerance
of the input and output voltages always results in a lower
headroom voltage. For example, the worst-case output voltage
can be 1.5% high and the input voltage can be 3% low. When
a 3.3-V regulator is powered by a 3.8-V source, the worst-case
headroom voltage is 336.5 mV, far lower than the expected
500 mV. With the worst-case load current of 200 mA, the
drain-to-source voltage of the pass FET is only 136.5 mV. The
PSRR of the ADM7160 in this case can be expected to fall far
short of the published 55 dB at 10 mA.
Figure 4 shows the output noise of a 2.5-V ADM7160 with

500-mV headroom and 100-mA load compared to the baseline
noise of an E3631A bench supply, which specifies less than
350-V-rms noise from 20 Hz to 20 MHz. The many spurs
below 1 kHz are harmonics related to rectification of the
60-Hz line frequency. The broad spur above 10 kHz is from
the dc-to-dc converter that generates the final output voltage.
The spurs above 1 MHz are due to RF sources in the environment unrelated to the power-supply noise. The measured
noise of the supply used for these tests is 56 V rms from
10 Hz to 100 kHz and 104 V rms including the spurs. The
LDO rejects all of the noise on the power supply, and has
about 9-V-rms output noise.
ADP7151 2.5V/100mA 500mV HEADROOM NOISE SPECTRAL DENSITY
100k
NSD
E3631A N + S
10k
PSRR of an LDO Operating in Dropout
Maintaining Performance when Operating with

Low Headroom
It is imperative to consider the effect of headroom voltage
on PSRR when operating at low headroom, as failure to do
so will result in a noisier output voltage than expected. PSRR
vs. headroom voltage plots, such as that shown in Figure 3,
are usually found in the data sheet and can be used to determine the amount of noise rejection possible for a given set
of conditions.
PSRR VS HEADROOM, VARIOUS FREQUENCIES AT 100mA LOAD
0
1kHz
10kHz
100kHz
500kHz
1MHz
10
PSRR (dB)
20
1k
nV/Hz
Customers frequently ask applications engineers about

an LDOs PSRR in dropout. Initially this may seem like a
reasonable question, but a glance at the simplified block
diagram will show it to be meaningless. When the LDO is in
dropout, the variable resistance portion of the pass FET is zero,
and the output voltage is equal to the input voltage minus the
voltage drop due to the load current through the RDSON of
the pass FET. The LDO is not regulating and has no gain to
reject noise on the input; it is simply operating as a resistor.
The RDSON of the FET forms an RC filter with the output
capacitor, providing a small amount of residual PSRR, but
a simple resistor or ferrite bead could perform the same job
much more cost effectively.
100
10
10
100
1k
10k
100k
10M
Figure 4. ADM7160 noise spectral density

with 500 mV headroom.
As the headroom voltage drops to 200 mV, the noise spurs

above 100 kHz begin to poke though the noise floor as the
high-frequency PSRR approaches 0 dB. The noise rises slightly
to 10.8 V rms. As the headroom falls to 150 mV, rectification harmonics start to affect the output noise, which rises to 12 V rms.
A moderate peak appears at about 250 kHz, so sensitive circuitry may be adversely affected even though the increase in
total noise is modest. As the headroom voltage drops further,
performance becomes compromised, and spurs related to
rectification become visible in the noise spectrum. Figure 5
shows the output with 100-mV headroom. The noise has risen
to 12.5 V rms. The harmonics contain very little energy, so
the noise with spurs is only slightly higher at 12.7 V rms.
ADP151 2.5V/100mA 100mV HEADROOM NOISE SPECTRAL DENSITY
100k
NSD
E3631A N + S
30
10k
40
50
nV/Hz
1k
60
70
80
0.2
1M
FREQUENCY (Hz)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
HEADROOM VOLTAGE (V)
10
Figure 3. PSRR vs. headroom voltage.
However, its sometimes easier to see how to apply this information by demonstrating how the LDOs PSRR effectively
filters out the noise of the source voltage. The following plots
show the impact on the total output noise of an LDO when
operating at different headroom voltages.
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 5. ADM7160 noise spectral density

with 100 mV headroom.
100k
NSD
E3631A N + S
With 500-mV headroom, rectification harmonics and a peak

at 12 kHz are clearly visible, as shown in Figure 8. The output
voltage noise rises to 3.9 V rms.
ADM7150 NOISE + SPURS VS HEADROOM VOLTAGE 5V/500mA LOAD
100k
1k
100
10
10k
1k
nV/Hz
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100
Figure 8. ADM7150 noise spectral density with 500-mV headroom.
10
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
With 350-mV headroom, the LDO is in dropout. No longer able

to regulate the output voltage, the LDO acts like a resistor, and
the output noise has risen to nearly 76 V rms, as shown in
Figure 9. The input noise is only attenuated by the pole formed
by the RDSON of the FET and the capacitance at the output.
ADM7150 NOISE + SPURS VS HEADROOM VOLTAGE 5V/500mA LOAD
Figure 6. ADM7160 noise spectral density in dropout.
100k
Ultralow-Noise LDOs with High PSRR
Figure 7 shows the noise spectral density of a 5-V ADM7150

with 500-mA load current and 800-mV headroom. The output
noise is 2.2 V rms from 10 Hz to100 kHz. As the headroom
drops to 600 mV, the rectification harmonics start to become
apparent, but the effect on the noise is small as the output
noise rises
to 2.3NOISE
V rms.
ADM7150
+ SPURS VS HEADROOM VOLTAGE 5V/500mA LOAD
100k
PS
800mV
10k
NSD (nV/Hz)
1k
100
10
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 9. ADM7150 noise spectral density in dropout.
Conclusion
Modern LDOs are increasingly being used to clean up dirty
power supply rails, which are often implemented with switching regulators that generate noise over a broad spectrum.
The switching regulators create these voltage rails at high
efficiency, but the dissipative LDOs reduce both noise and
efficiency. Therefore, LDOs should be operated with as little
headroom voltage as possible.
1k
100
10
0.1
PS
350mV
10k
A new class of LDOs such as the ADM7150 ultralow-noise,

high-PSRR regulator essentially cascade two LDOs, so the
resulting PSRR is approximately the sum of that of the
individual stages. These LDOs require somewhat higher
headroom voltages but are able to achieve PSRRs exceeding
60 dB at 1 MHz and well over 100 dB at lower frequencies.
NSD (nV/Hz)
PS
500mV
10k
NSD (nV/Hz)
With 75-mV headroom, the output noise becomes severely

compromised, and rectification harmonics appear throughout
the spectrum. The rms noise rises to 18 V rms and the noise
plus spurs rises to 27 V rms. The noise beyond ~200 kHz
is attenuated because the LDO loop has no gain and acts as
a passive RC filter. With 65-mV headroom, the ADM7160 is
operating in dropout. As shown in Figure 6, the output voltage noise of the ADM7160 is essentially the same as the input
noise. The rms noise is now 53 V rms and the noise plus
spurs is 109 V rms. The noise beyond ~100 kHz is attenuated
because the LDO
is acting as a passive RC filter.
ADP151 2.5V/100mA DROPOUT NOISE SPECTRAL DENSITY
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 7. ADM7150 noise spectral density with 800-mV headroom.
As shown, their PSRR is a function of both load current and

headroom voltage, decreasing as the load current increases or
the headroom voltage decreases due to the reduced loop gain
as the operating point of the pass transistor moves from the
saturation region to the triode region.
Considering the input source noise characteristics, PSRR,

and worst-case tolerances allows designers to optimize both
the power dissipation and output noise to achieve an efficient, low-noise power supply for sensitive analog circuits.
When operating at very low headroom voltages, the
worst-case tolerance of the input and output voltages
can affect the PSRR. Designing for worst-case tolerances
will ensure a robust design; failure to do so will yield a
power solution with lower PSRR resulting in higher than
expected total noise.
References
Linear Regulators
Morita, Glenn. Noise-Reduction Network for AdjustableOutput Low-Dropout Regulators. Analog Dialogue,
Volume 48, Number 1, 2014.
Morita, Glenn. Low-Dropout RegulatorsWhy the Choice
of Bypass Capacitor Matters. Analog Dialogue, Volume 45,
Number 1, 2011.
Morita, Glenn. AN-1120 Application Note. Noise Sources in
Low-Dropout (LDO) Regulators. Analog Devices, Inc., 2011.
Minimum Load Current OperationZero-Load Operation

By Luca Vassalli
As an applications engineer, I am frequently asked about operating regulators with no load. Most modern LDOs and switching regulators are stable with no load, so why do people repeatedly ask? Some older power devices require a minimum load
to guarantee stability, as one of the poles that must be compensated is affected by the effective load resistance, as discussed
in Low-Dropout Regulators (Ask the Applications Engineer37). For example, Figure A shows that the LM1117 requires a
1.7-mA minimum load current (up to 5 mA).
LM1117-N ELECTRICAL CHARACTERISTICS (continued)

Typicals and limits appearing in normal type apply for TJ = 25C. Limits appearing in Boldface type apply over the entire
junction temperature range for operation, 0C to 125C.
Symbol
ILIMIT
Parameter
Conditions
Current Limit
VIN VOUT = 5V, TJ = 25C
Minimum Load
Current (5)
LM1117-N-ADJ
VIN = 15V
Min (1)
Typ (2)
Max (1)
Units
800
1200
1500
mA
1.7
mA
Figure A. LM1117 minimum load current specifications.
Most newer devices are designed to operate with no load, and exceptions to this rule are very limited. The same design techniques that allow LDOs to be stable with any output capacitor, especially low ESR caps, are used to guarantee stability at no
load. For those few modern devices that require a load, the limitation is usually a result of leakage current through the pass
element, not the stability. So, how can you tell? Read the data sheet. If the device requires a minimum load, the data sheet
would surely say something.
The ADP1740 and other low-voltage, high-current LDOs fall into this category. The worst-case leakage current from the
integrated power switch is about 100 A at 85C and 500 A at 125C. Without a load, the leakage current would charge the
output capacitor until the switch VDS was low enough to reduce the leakage current to a negligible level, raising the no-load
output voltage. The data sheet says that a 500 A minimum load is required, so a dummy load is advisable if the device will
operate at high temperature. This load is small compared to the devices 2-A rating. Figure B shows the minimum load current
specification from the ADP1740 data sheet.
ADP1740/ADP1741
Data Sheet
Parameter
SENSE INPUT BIAS CURRENT
(ADP1740)
OUTPUT NOISE
Symbol
SNSI-BIAS
Test Conditions/Comments
1.6 V VIN 3.6 V
OUTNOISE
POWER SUPPLY REJECTION RATIO
PSRR
10 Hz to 100 kHz, VOUT = 0.75 V

10 Hz to 100 kHz, VOUT = 2.5 V
VIN = VOUT + 1 V, IOUT = 10 mA
1 kHz, VOUT = 0.75 V
1 kHz, VOUT = 2.5 V
10 kHz, VOUT = 0.75 V
10 kHz, VOUT = 2.5 V
100 kHz, VOUT = 0.75 V
100 kHz, VOUT = 2.5 V
Min
Typ
10
Max
Unit
A
23
65
V rms
V rms
65
56
65
56
54
51
dB
dB
dB
dB
dB
dB
Minimum output load current is

Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of the resistors used.
3
Based on an endpoint calculation using 10-mA and 2-A loads. See Figure 6 for typical load regulation performance.
4
Dropout voltage is de ed as the input to output voltage di erential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.6 V.
5
Start-up time is de ned as the time between the rising edge of EN to VOUT being at 95% of its nominal value.
6
Current-limit threshold is de ed as the current at which the output voltage drops to 90% of the speci ed typical value. For example, the current limit for a 1.0 -V
output voltage is de ned as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
1
2
Figure B. ADP1740 minimum load current specification.
What if the data sheet doesnt explicitly specify a

minimum load? In most cases, a minimum load is not
required. It may not sound very convincing, but if a minimum load was required, the data sheet would certainly
say so. The confusion often comes into play because data
sheets will often include graphs showing the specifications over some operating range. Most of these graphs
are logarithmic, allowing them to show multiple decades
of load ranges, but a log scale cannot go to zero. Figure C
shows the ADM7160 output voltage and ground current
vs. load current over the 10-A to 200-mA range. Other
graphs, such as ground current vs. input voltage, show
measurements at multiple load currents, but dont show
data at zero current. In addition, parameters such as
PSRR, line regulation, load regulation, and noise specify
a certain load current range that does not include zero, as
shown in Figure D. None of this means that a minimum
load is required, though.
As shown in Figure E, the ADP2370 high-voltage, low-quiescent-current buck regulator produces increased ripple
due to PSM operation when the load switches between
800 mA and 1 mA. The fact that the test was done at 1 mA
does not indicate that 1 mA is the minimum load.
LOAD CURRENT
1
VOUT
INDUCTOR CURRENT
2.55
VOUT (V)
M40.0s A CH1
T
320mA
72.00%
Figure E. ADP2370 load transient in power-saving mode.
2.53
Figure F shows the ripple voltage changing with load

current. In this case the graph goes all the way to zero,
indicating both that the load can be zero and that the
noise at no load may not be any worse than the noise
at 1 mA or 10 mA.
2.51
2.49
0.05
2.47
0.1
10
100
RIPPLE VOLTAGE (V p-p)
0.04
2.45
0.01
1k
ILOAD (mA)
1k
IGND (A)
CH1 500mA BW CH2 200mV

CH3 500mA BW
0.03
3.2V
5.0V
9.0V
15V
0.02
0.01
100
100
200
300
400
500
600
700
800
LOAD CURRENT (mA)
Figure F. ADP2370 output ripple vs. load current.
Conclusion
10
0.01
0.1
1
10
ILOAD (mA)
100
1k
Figure C. ADM7160 output voltage and

ground current vs. load current.
LOAD REGULATION
VOUT < 1.8 V
VOUT 1.8 V
VOUT/ILOAD
ILOAD = 100 A to 200 mA
ILOAD = 100 A to 200 mA,
TJ = 40C to +125C
ILOAD = 100 A to 200 mA
ILOAD = 100 A to 200 mA,
TJ = 40C to +125C
0.006
0.012
%/mA
%/mA
0.008
%/mA
%/mA
0.003
Figure D. ADM7160 load regulation.
Users of switching regulators with power-saving mode

(PSM) are often worried about operation at light loads
because PSM reduces the operating frequency, skips
pulses, provides a burst of pulses, or some combination
of these. PSM reduces power consumption and increases
efficiency at light loads. Its disadvantage is a noticeable
increase in output ripple, but the device remains stable
and can easily operate with no load.
Most modern regulators are stable with zero load

current, but when in doubt, consult the data sheet.
Be careful, though. Logarithmic graphs dont go to
zero, and tests arent always done with zero load
current, so you shouldnt infer that the regulator
wont work with no load even though no-load data
isnt shown. With switching regulators, ripple in
power-saving mode is normal, not a sign of instability.
References
Caveat Emptor
Linear Regulators
Switching Regulators
Patoux, Jerome. Low-Dropout Regulators (Ask the
Applications Engineer37), Analog Dialogue, Volume 41,
Number 2, 2007.

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Ask The Applications Engineer1

TROUBLE FROM THE START

Busy signal is always present on power-up the problem is almost

ABOUT LOG COMPENSATION RESISTORS

At turn-on, a typical ADCs logic will be in a random state; for

Analog Dialogue 22-2 (1988)

*Much useful information about logarithmic and other analog function

Ask The Applications Engineer2

of full-scale range). Depending on the architecture used, this

WHEN IT COMES TO TRIMMING . . .

where OP is output, IP is input, and K is a scale factor (Note

OP = (K IP) + [(K OS) + (K IP) + (K OS)]

In this case offset is trimmed at analog zero, after which gain is

Here offset is trimmed at FS negative and gain is trimmed at

Analog Dialogue 23-1 (1989)

Ask The Applications Engineer 2

From (6) it is evident that if the gain is constant we need only

very large value of summing resistance, compared to the

a. CMOS DAC connected for current steering. Input impedance is constant.

a. Voltage applied to non-inverting input.

b. Current summed at inver ting input.

Analog Dialogue 23-1 (1989)

b. The same DAC connected for voltage output.

Ask The Applications Engineer3

Q. What are the advantages and disadvantages of the two types?

Q. How does a VFC work?

A. The same three as in most precision circuitry: offset errors,

Analog Dialogue 23-2 (1989)

Ask The Applications Engineer 3

The phase-locked-loop FVC illustrated differs from any other

The critical capacitors in a precision VFC (the multivibrators

Designing PLL systems is beyond the scope of this discussion,1

If a capacitor is charged, discharged and then open-circuited

Q. What is a synchronous VFC?

For each cycle of the input frequency, a charge, Q, is delivered

Despite these difficulties the improvement in performance

Analog Dialogue 23-2 (1989)

Ask The Applications Engineer5

For example, after a high-to-low transition on the AD790, its

Also the output of an operational amplifier is not readily matched

Figure 1. Applying external hysteresis to a comparator.

It could be the comparators ground connection. Make sure that

Another cause of the oscillation may be a high source impedance

A useful discussion of comparator foibles can be found in Troubleshooting

Analog Dialogue 23-4 (1989)

Ask The Applications Engineer 5

I sometimes see unexpected behavior in my comparator.What could be

Figure 4. Comparator output, buffer output, and comparator

Figure 3. Autozeroed comparator integrates out offsets during calibration cycle.

Analog Dialogue 23-4 (1989)

Ask The Applications Engineer6

Q. So where are the differences?