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Project Work
Problem Statement
2
2.1
Design Approach
Logic and Arithmetic Circuit Design
2.2
Addition
Design 64-bit Carry Lookahead Adder circuit using KGP blocks and Recursive doubling algorithm. Now
use the same module for the design of the addition, addition with carry, subtraction and subtraction with
barrow modules.
2.3
Multiplication
Design the 64-bit Wallace Tree multiplier (or Array multiplier) using carry-save-adders.
2.4
Design Single precision floating addition, subtraction and multiplication circuit, where adder can be designed using carry lookahead adder and multiplier can be either Wallace tree multiplier or Array multiplier.
3
3.1
The design instruction should of 32-bit size. Load and Store Instruction will have the format as shown in
Figure 1. The rest of the logic and arithmetic instructions will have the format as shown in Figure 2.
3.2
Processor Architecture
Usage
ADDRdst , Rsrc2 , Rsrc1
ADCRdst , Rsrc2 , Rsrc1
SU BRdst , Rsrc2 , Rsrc1
SBBRdst , Rsrc2 , Rsrc1
M U LRdst , Rsrc2 , Rsrc1
F ADDRdst , Rsrc2 , Rsrc1
F SU BRdst , Rsrc2 , Rsrc1
F M U LRdst , Rsrc2 , Rsrc1
AN DRdst , Rsrc2 , Rsrc1
ORRdst , Rsrc2 , Rsrc1
XORRdst , Rsrc2 , Rsrc1
N ADDRdst , Rsrc2 , Rsrc1
N ORRdst , Rsrc2 , Rsrc1
XN ORRdst , Rsrc2 , Rsrc1
N OT Rdst , Rsrc1
N EGRdst , Rsrc1
LOADRdst , Address(22 bit)
ST ORERdst , Address(22 bit)