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Pll System :

1.what is pll , differ from wire ?


2.phase Detector basics : xor,Model
3.type1 pll loop operation : lock condition(settles),transient
behavior waveforms.
4.what is loop filter and its trade offs ?
low pass filter average extractor of Phase detector output.
Trades : 1.order of filter Inverse prop. with output ripples.but
the order is limited by stability
2. BW inversely with ripple attenuation but prop.To
settling speed.
5.Vco type and model ? Effect of Ripples at output of filter ?
6.why use laplace model?open loop and closed TF of the type1 ?
7.what is type and order of pll define ?
Type : no of nonlossless integrators.
order : order of lossy LPF.
8. PM of type1 order1 pll ?
9.Issues: 1.Reduce spur level at output of filter :
1.A.first order filter with low cutoff freq. PM<45
Ringing and slow loop.
1.B.second order more PM reduction and may be unstable.
2.cycle slipping : at large change in divider.
When phase accumlation higher than PI . Take long time to
settle and may not lock (lock range).
Type 11 charge pump pll :
1.PFD :pros: 1.comparison Range inc. 2.phase error is asymmetrical around zero
3. PLL will always relock.
Comparing type I and II : H(s) , DC gain of H(s),phase error at PD input , vlpf
range that can span, pfd and cp model .
It suffers from ringing at the output because PM=0 . So we should have a pole
and a zero.
The commonly used PFD+CP :

C2 < C1

and the closed loop response =

validitiy of linear model if time granularities inherient in the waveform


similar respect to time scale :
wc < wref/10 cross over or loop BW.

Max phase margin when wc= geometric mean of (wp,wz) so PM max function in c1/c2

Phase noise: CP:dominant in band, VCO : out of band.SDM:shapes noise and athigh
frequency.
1. PFD+CP+divider noises will be low passed. 2. filter noise is band passed
3. Vco noise will be high passed.
Select a PM of 65 which implies a wn/wc and at their curves intersection with
the PM . And also to have good approx relation of wc and w3db
=0.7, c1/c2=20
settling time : time required to charge the capacitor that stores vco tuning
range.

In our graduation project : ISM band PLL ,Low IF Receiver


Design steps :
1.choose the compliance range : input voltage tuning for vco and then KVCO.
2.choose PM to avoid peaking.
3.wc = 1/settling time 1/wc choose for certain noise and spur attenuation.
4.loop filter values : accord to gain and PM and BW
5.Division Ratio by Fout and Fref relation. And channel spacing for the type
6.SDM order and CP current accord to noise attenuation required.
SDM 3rd order to decrease in band noise and Division Ratio : 69.38 71.38

My work :
1.Divide by two I/Q generator :1.5 mA,250f,1.83G,600 mvpp diff
1.8 degree IQ mismatch and stable across corners.
2.Feedback dividers : MMD
CML as 1 st Divide by 2 /3 circuit and other as CMOS Dividers to
achieve a division ratio from 69 to 71 a CML to Cmos
circuit is interfacing these two stages .we use only one CML as
Max input frequency is 1.83 GHZ after 1 stage max output is about
915 MHz which is less than max operating frequency of CMOs at
our 130 n technology (with reasonable dynamic power).
it consumes about 1.9 mA and noise floor -154 dBc/HZ as noise
floor , it is well tested across corner analysis.