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C2 < C1
Max phase margin when wc= geometric mean of (wp,wz) so PM max function in c1/c2
Phase noise: CP:dominant in band, VCO : out of band.SDM:shapes noise and athigh
frequency.
1. PFD+CP+divider noises will be low passed. 2. filter noise is band passed
3. Vco noise will be high passed.
Select a PM of 65 which implies a wn/wc and at their curves intersection with
the PM . And also to have good approx relation of wc and w3db
=0.7, c1/c2=20
settling time : time required to charge the capacitor that stores vco tuning
range.
My work :
1.Divide by two I/Q generator :1.5 mA,250f,1.83G,600 mvpp diff
1.8 degree IQ mismatch and stable across corners.
2.Feedback dividers : MMD
CML as 1 st Divide by 2 /3 circuit and other as CMOS Dividers to
achieve a division ratio from 69 to 71 a CML to Cmos
circuit is interfacing these two stages .we use only one CML as
Max input frequency is 1.83 GHZ
after 1 stage max output is about
915 MHz which is less than max operating frequency of CMOs at
our 130 n technology (with reasonable dynamic power).
it consumes about 1.9 mA and noise floor -154 dBc/HZ
as noise
floor , it is well tested across corner analysis.