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HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
FEATURES
D, N, OR PW PACKAGE
(TOP VIEW)
1B
2B
3B
4B
5B
6B
7B
E
DESCRIPTION/ORDERING INFORMATION
16
15
14
13
12
6
7
11
10
1C
2C
3C
4C
5C
6C
7C
COM
PACKAGE
PDIP (N)
40C to 105C
SOIC (D)
TSSOP (PW)
Tube of 425
ULN2003AIN
Tube of 40
ULN2003AID
Reel of 2500
ULN2003AIDR
Reel of 2000
ULN2003AIPWR
TOP-SIDE MARKING
ULN2003AIN
ULN2003AI
UN2003AI
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
LOGIC DIAGRAM
9
1B
2B
3B
4B
5B
6B
7B
16
15
14
13
12
11
10
COM
1C
2C
3C
4C
5C
6C
7C
Input
B
Output
C
2.7 k
7.2 k
3 k
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
(1)
50
voltage (2)
30
500
mA
500
mA
40
D package
JA
Package thermal
TJ
Tstg
(2)
(3)
(4)
2.5
105
73
N package
67
PW package
(1)
UNIT
50
Input
IOK
MAX
Collector-emitter voltage
C/W
108
65
150
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Characteristics
TA = 25C
PARAMETER
VI(on)
VCE(sat)
TEST FIGURE
5
TEST CONDITIONS
VCE = 2 V
2.7
IC = 300 mA
II = 350 A,
II = 500 A,
II = 0
VCE = 50 V,
IF = 350 mA
II(off)
VCE = 50 V,
II
Input current
VI = 3.85 V
IR
VR = 50 V
Ci
Input capacitance
VI = 0,
MAX
IC = 250 mA
IC = 100 mA
VF
TYP
2.4
II = 250 A,
ICEX
MIN
IC = 200 mA
0.9
1.1
IC = 200 mA
1.3
IC = 350 mA
1.2
1.6
1.7
IC = 500 A
50
f = 1 MHz
15
50
V
A
65
0.93
UNIT
1.35
mA
50
25
pF
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
Electrical Characteristics
TA = 40C to 105C
PARAMETER
VI(on)
TEST FIGURE
5
TEST CONDITIONS
VCE = 2 V
MIN
TYP
MAX
IC = 200 mA
2.7
IC = 250 mA
2.9
IC = 300 mA
IC = 100 mA
0.9
1.2
II = 350 A,
IC = 200 mA
1.4
1.2
II = 500 A,
IC = 350 mA
ICEX
VCE = 50 V,
II = 0
VF
IF = 350 mA
II(off)
VCE = 50 V,
II
Input current
VI = 3.85 V
IR
VR = 50 V
Ci
Input capacitance
VI = 0,
30
100
2.2
1.35
mA
100
25
pF
65
0.93
f = 1 MHz
1.7
1.7
IC = 500 A
II = 250 A,
VCE(sat)
UNIT
15
Switching Characteristics
TA = 25C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPLH
See Figure 8
0.25
tPHL
See Figure 8
0.25
VOH
VS = 50 V,
VS 20
UNIT
s
s
mV
Switching Characteristics
TA = 40C to 105C
TYP
MAX
tPLH
PARAMETER
See Figure 8
10
tPHL
See Figure 8
10
VOH
VS = 50 V,
TEST CONDITIONS
MIN
VS 50
UNIT
mV
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
VCE
VCE
II(off)
IC
ICEX
Open
Open
IC
II
VCE
II
IC
II(on)
VI
Open
NOTE: II is fixed for measuring VCE(sat), variable for
measuring hFE.
Open
VR
IR
VI(on)
VCE
IC
VF
Open
IF
Open
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
50%
50%
tPHL
tPLH
50%
Output
50%
VOLTAGE WAVEFORMS
VS
Input
2 mH
Open
1N3064
200
Pulse
Generator
(see Note A)
Output
CL = 15 pF
(see Note B)
TEST CIRCUIT
5 ns
10 ns
90%
1.5 V
Input
10%
VIH
(see Note C)
90%
1.5 V
40 s
10%
0V
VOH
Output
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 .
B. CL includes probe and jig capacitance.
C. For testing, VIH = 3 V
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
TYPICAL CHARACTERISTICS
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
TA = 25C
2
II = 250 A
II = 350 A
II = 500 A
1.5
0.5
0
0
100
200
300
400
500
600
2.5
VCE(sat)
VCE(sat) Collector-Emitter Saturation Voltage V
2.5
700
TA = 25C
II = 250 A
2
II = 350 A
1.5
II = 500 A
1
0.5
800
100
IC Collector Current mA
200
300
400
500
600
700
800
Figure 11
Figure 10
COLLECTOR CURRENT
vs
INPUT CURRENT
500
RL = 10
TA = 25C
450
IC
IC Collector Current mA
VCE(sat)
VCE(sat) Collector-Emitter Saturation Voltage V
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
COLLECTOR CURRENT
(ONE DARLINGTON)
400
VS = 10 V
350
VS = 8 V
300
250
200
150
100
50
0
0
25
50
75
100
125
150
175
200
II Input Current A
Figure 12
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
THERMAL INFORMATION
N PACKAGE
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
D PACKAGE
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
600
600
500
500
IIC
C Maximum Collector Current mA
IIC
C Maximum Collector Current mA
N=1
N=1
N=4
400
N=3
300
N=2
N=7
N=6
N=5
200
100
TA = 70C
N = Number of Outputs
Conducting Simultaneously
10
20
30
40
50
60
70
Duty Cycle %
Figure 13
N=3
400
N=4
300
N=7
N=6
N=5
200
100
TA = 85C
N = Number of Outputs
Conducting Simultaneously
0
0
N=2
80
90 100
10
20
30
40
50
60
70
Duty Cycle %
Figure 14
80
90 100
ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY
www.ti.com
APPLICATION INFORMATION
VCC
VCC
16
15
14
13
12
11
10
RP
Lamp
Test
TTL
Output
16
15
14
13
12
11
10
TTL
Output
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Lead/Ball Finish
ULN2003AID
ACTIVE
SOIC
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
ULN2003AIDR
ACTIVE
SOIC
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
ULN2003AIN
ACTIVE
PDIP
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
ULN2003AIPW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
ULN2003AIPWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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