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HNC Electrical and Electronic Engineering

Year One - 2013/14


Module: Digital & Analogue Devices

Operational
Amplifiers

Keith A. Hudson
M1306117
11/03/2014

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Keith A. Hudson
M1306117

Digital & Analogue Devices


05 March, 2014

Contents
1

Assumptions ............................................................................................................................................... 6

Adder / Subtractor Circuit (Task 1a) ........................................................................................................... 7

2.1

Requirements ...................................................................................................................................... 7

2.2

Circuit Simulation Using Proteus ......................................................................................................... 8

2.3

Actual Circuit ..................................................................................................................................... 15

Integration Circuit (Task 1b) ..................................................................................................................... 17


3.1

Requirements .................................................................................................................................... 17

3.2

Circuit Simulation Using Proteus ....................................................................................................... 18

3.3

Actual Circuit ..................................................................................................................................... 21

4-bit Analogue to Digital Convertor Circuit (Task 1c) ............................................................................... 23


4.1

Requirements .................................................................................................................................... 23

4.2

Circuit Simulation Using Proteus ....................................................................................................... 25

4.3

Actual Circuit ..................................................................................................................................... 34

Conclusions ............................................................................................................................................... 36

Bibliography .............................................................................................................................................. 37

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Year One: 2013/14

Keith A. Hudson
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Digital & Analogue Devices


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Figures
Figure 1: Adder / Subtractor circuit ................................................................................................................... 8
Figure 2: Testing i/p A ........................................................................................................................................ 9
Figure 3: Testing i/p B ...................................................................................................................................... 10
Figure 4: Testing i/p C ...................................................................................................................................... 11
Figure 5: A = 5 V, B = 4 V, Output = 1.3 V......................................................................................................... 12
Figure 6: A = 5 V, B = 4 V, C = 2 V, Output = 0.3 V ........................................................................................... 13
Figure 7: A = 5 V, B = 4 V, C = 5 V, Output = -1.2 V .......................................................................................... 14
Figure 8: Adder / subtractor circuit ................................................................................................................. 15
Figure 9: Multi-meters showing the actual output from each Op Amp .......................................................... 16
Figure 10: Op Amp Integrator circuit ............................................................................................................... 17
Figure 11: The simulated Integrator Circuit ..................................................................................................... 18
Figure 12: The input and output wave forms .................................................................................................. 19
Figure 13: Input / Output ranges ..................................................................................................................... 19
Figure 14: Output voltage at 0.4s .................................................................................................................... 20
Figure 15: integrator circuit on breadboard .................................................................................................... 21
Figure 16: Power supply................................................................................................................................... 21
Figure 17: Function generator producing the square wave input for the integrator ..................................... 21
Figure 18: Setting up the PSU and initial oscilloscope output ......................................................................... 22
Figure 19: Oscilloscope output ........................................................................................................................ 22
Figure 20: Input 0000, Output 0 ...................................................................................................................... 25
Figure 21: Input 0001, Output 1 ...................................................................................................................... 26
Figure 22: Input 0010, Output 2 ...................................................................................................................... 26
Figure 23: Input 0011, Output 3 ...................................................................................................................... 27
Figure 24: Input 0100, Output 4 ...................................................................................................................... 27
Figure 25: Input 0101, Output 5 ...................................................................................................................... 28
Figure 26: Input 0110, Output 6 ...................................................................................................................... 28
Figure 27: Input 0111, Output 7 ...................................................................................................................... 29
Figure 28: Input 1000, Output 8 ...................................................................................................................... 29
Figure 29: Input 1001, Output 9 ...................................................................................................................... 30
Figure 30: Input 1010, Output 10 .................................................................................................................... 30
Figure 31: Input 1011, Output 11 .................................................................................................................... 31
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Keith A. Hudson
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Digital & Analogue Devices


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Figure 32: Input 1100, Output 12 .................................................................................................................... 31


Figure 33: Input 1101, Output 13 .................................................................................................................... 32
Figure 34: Input 1110, Output 14 .................................................................................................................... 32
Figure 35: Input 1111, Output 15 .................................................................................................................... 33
Figure 36: 4-bit converter ................................................................................................................................ 34
Figure 37: Duel PSUs ........................................................................................................................................ 34
Figure 38: Oscilloscope showing input and output voltages ........................................................................... 35

HNC Electrical and Electronic Engineering

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Keith A. Hudson
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Digital & Analogue Devices


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Tables
Table 1: Amplification values for each input value............................................................................................ 7
Table 2: Values for A and B and the expected Output .................................................................................... 12
Table 3: Values for A, B and C and the expected Output ................................................................................ 13
Table 4: Same values for A and B and a different C and the expected Output ............................................... 14
Table 5: Values for resistor, R and capacitor, C ............................................................................................... 17
Table 6: Input vs. output voltage ..................................................................................................................... 18
Table 7: Weighting associated with each bit ................................................................................................... 23
Table 8: Input values and expected outputs ................................................................................................... 23
Table 9: Prime factors ...................................................................................................................................... 24
Table 10: Amplification values for each input bit ............................................................................................ 24
Table 11: Ideal vs. real Op Amp ....................................................................................................................... 36

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Year One: 2013/14

Keith A. Hudson
M1306117

Digital & Analogue Devices


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1 Assumptions
The actual value of the resistors used will be slightly different to the manufacturers stated value. This may
be as much as 10% for a resistor with a silver band. Those with a brown tolerance band are more accurate
1%. Resistors with smaller tolerances (i.e. more accurate) are available but they are more expensive. For
these experiments resistors with a tolerance of 1% would be sufficiently accurate.
These experiments assume the use of ideal Op Amps. These have the following characteristics:
1.
2.
3.
4.
5.
6.
7.

Voltage gain is infinite.


Gain is independent of frequency.
Input resistance is infinite.
Output resistance is zero.
Input voltage offset is zero.
Output can swing to the positive or negative supply rails.
Output can swing instantly to the correct value.

The power supply needs to provide an accurate voltage to the Op Amp rails and as input. The model used
is a HY3005D-2. The Data Sheet for this model states accuracy is:

Source:
Load:

constant voltage
constant voltage

0.01%
0.01%

1mV
5mV

These figures are accurate enough for the following circuits.

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Year One: 2013/14

Keith A. Hudson
M1306117

Digital & Analogue Devices


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2 Adder / Subtractor Circuit

(Task 1a)

2.1 Requirements
A circuit is required with the following characteristics:

It should have three input voltages: Input A, Input B and Input C


The value of Input A should be multiplied by 0.1, i.e. divided by 10 (we will call this o/p A)
The value of Input B should be multiplied by 0.2, i.e. divided by 5 (o/p B)
The value of Input C should be multiplied by 0.5, i.e. divided by 2 (o/p C)
There will be one output from the circuit: Output = o/p A + o/p B o/p C

For an ideal op-amp the output voltage is calculated as follows:


what output to input ratio is required we can calculate the ratio of

.Therefore, if we know
to

(ignoring the change of sign):

Table 1: Amplification values for each input value

Input A

Input B

Input C

The ratio is 0.1 or

The ratio is 0.2 or

The ratio is 0.2 or

If we chose an arbitrary value for


, say 1k, then
= 10 k

= 5 k

= 2 k

To add two numbers (i.e. voltages) together we simply connect the wires together and the op-amp will
amplify them according to the resistor ratios used. The output from the op-amp will be negative (i.e.
inverted), so we need to pass the result through a second inverting op-amp to invert it again, thus
correcting the sign.
Our circuit needs to perform the following arithmetic operation:
. If we multiply
both sides by -1 we get
. The output from the first op-amp is
. So if
we add C to that output, and invert the result we are left with the required output result.

HNC Electrical and Electronic Engineering

Year One: 2013/14

Keith A. Hudson
M1306117

Digital & Analogue Devices


05 March, 2014

2.2 Circuit Simulation Using Proteus


The required circuit was created with using two Inverting Op-Amps, with the appropriate resistor ratios as
shown in Figure 1.

Figure 1: Adder / Subtractor circuit

For each input a variable resistor was connected to a five volt source to allow an input value to be selected
in the range 0-5V. Initially all the inputs were set to zero. Input A was then set to 2V to ensure the
amplification was correct. If Input A is 2V, the circuit output should be 0.40V. The result can be seen in
Figure 2. This was the repeated for Input B. This time the Output should be 0.20V, See Figure 3. For Input C
the output should be 1.00V, see Figure 4.

HNC Electrical and Electronic Engineering

Year One: 2013/14

Keith A. Hudson
M1306117

Digital & Analogue Devices


05 March, 2014

Figure 2: Testing i/p A

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Figure 3: Testing i/p B

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Figure 4: Testing i/p C

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The next step is to test that 0.1 * i/p A + 0.2 * i/p B produces the correct results.
Table 2: Values for A and B and the expected Output

Figure 5: A = 5 V, B = 4 V, Output = 1.3 V

As Figure 5 shows, the actual Output matches expected Output.

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Table 3: Values for A, B and C and the expected Output

Figure 6: A = 5 V, B = 4 V, C = 2 V, Output = 0.3 V

As Figure 6Figure 5 shows, the actual Output matches expected Output.

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Keeping A and B unchanged; a larger value of C is be used to ensure a negative result is correctly
calculated.
Table 4: Same values for A and B and a different C and the expected Output

Figure 7: A = 5 V, B = 4 V, C = 5 V, Output = -1.2 V

As Figure 7 shows, the actual Output matches expected Output.

HNC Electrical and Electronic Engineering

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Keith A. Hudson
M1306117

Digital & Analogue Devices


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15

2.3 Actual Circuit


The actual circuit was created using power supplies (PSU), resistors and boards each containing a 741 Op
Amp. Various wires were used to connect everything together. The resultant circuit can be seen in Figure 8.

Figure 8: Adder / subtractor circuit

The equipment is as follows:

Each of the white boards contains a 741 Op Amp.


The PSU on the right, provide power to the rails of the 741 on the right.
The PSU in the middle, provide power to the rails of the 741 on the left.
The PSU on the left provides 5V for inputs A, B and C.
The multi-meters show the output voltage from the respective Op Amps.

The Op Amp on the left- is the adder, with inputs:

The output from the Op Amp on the left will be

(minus because it is an inverting amplifier).

The Op Amp on the right- is the subtractor, with inputs:

The output from the Op Amp on the right will be

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(minus because

).

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Keith A. Hudson
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Digital & Analogue Devices


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Figure 9: Multi-meters showing the actual output from each Op Amp

The output from the adder Op Amp is 1,501 V. The output from the subtractor Op Amp is 1.017 V. The
respective values are not exactly 1.5 and 1.0 for a number of reasons:

The input voltage to the Op Amps was not exactly 5.0 V. (Actually 5.1 V.)
The resistance of the wires may have affected the input ratios slightly.
The calibration of the PSUs and multi-meters may be out.

HNC Electrical and Electronic Engineering

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Keith A. Hudson
M1306117

Digital & Analogue Devices


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17

3 Integration Circuit (Task 1b)


3.1 Requirements
A circuit is required, such that the output voltage,

, where

is the input voltage.

Figure 10: Op Amp Integrator circuit

The above circuit (see Figure 10) is an example of an Op Amp Integrator circuit. The output is calculated as
follows:

(Bird, 2010)

If we look at the required output:

, it is very similar to the output from the above (Figure

10) circuit. If we ignore the (-) sign because we know this is an inverting amplifier, then we need:

Table 5: Values for resistor, R and capacitor, C

If a resistor of 5k is used then what size capacitor


is needed?

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Keith A. Hudson
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Digital & Analogue Devices


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18

3.2 Circuit Simulation Using Proteus


Using the values from Table 5, the resultant circuit can be seen in Figure 11:

Figure 11: The simulated Integrator Circuit

A signal generator was used to produce a square wave (Peak-to-peak: 5V, max +2.5V, min -2.5V) input to
the circuit. The input and output waves were displayed on an oscilloscope. As Figure 12 shows the output
is a triangular wave. The output is the integral of the input.
Figure 13 shows the input and the output values. The output starts at 0V and drops at a constant rate to 247mV. It then increases at a constant rate back to 0V.
Table 6: Input vs. output voltage

Time (s)
i/p (V)
o/p (mV)

0
+2.5
0

<0.5
+2.5
-247

>0.5
-2.5
0

1.0
-2.5
+247

Table 6 shows the input and output voltages during the first oscillation of the input square wave and the
corresponding triangular output wave. When the input is positive the output is negative and when the
input is negative the output is positive.

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Figure 12: The input and output wave forms

Figure 13: Input / Output ranges

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If we take a time between 0 and 0.5 seconds, the input


voltage is constant
So

becomes
At time, t=0.4s, the output voltage will be:

On the simulator we get


value.

, almost the same

Figure 14: Output voltage at 0.4s

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3.3 Actual Circuit

Figure 16: Power supply


Figure 15: integrator circuit on breadboard

Figure 17: Function generator producing the square wave input for the integrator

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Figure 18: Setting up the PSU and initial oscilloscope output

Due to an error in wiring the integrator circuit, the Op Amp was damaged and consequently failed to
produce the desired output (see Figure 19).

Figure 19: Oscilloscope output

Wiring up circuits using breadboard is extremely fiddly and mistakes are easy to make and difficult to
locate. Proteus is relatively easy to use and generates errors if things are incorrectly wired. When using
Proteus all the components are working. Real components are easy to damage and may not be working
when even when they are new.

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23

4 4-bit Analogue to Digital Convertor Circuit

(Task 1c)

4.1 Requirements
This circuit requires four digital inputs. Each input will be on or off. For simplicity an input voltage of 1V will
be used for on, and 0V will be used for off. In practice any set voltage could be used to represent on.
Each of the four input bits will be weighted differently:

Table 7: Weighting associated with each bit

Bit
1
2
3
4

Weight
1
2
4
8

Binary
0001
0010
0100
1000

MSB

Input bits
1000
1001
1010
1011
1100
1101
1110
1111

Output Value
8
9
10
11
12
13
14
15

LSB

LSB: least significant bit, MSB: most significant bit.


Table 8: Input values and expected outputs

Input bits
0000
0001
0010
0011
0100
0101
0110
0111

Output Value
0
1
2
3
4
5
6
7

For the input bits MSB is on the right, LSB on the left
The adder/subtractor circuit Figure 1 can be easily adapted to fulfil the requirements of this circuit:

Remove the input from the subtractor part of the circuit.


Add two more inputs to the adder part of the circuit.
Change the resistor ratios to match the new requirements.
The second op amp (was the subtractor) will now be used to correct the sign so that the final
output is positive.

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24

The lowest common multiple (LCM) of 1, 2, 4 and 8 is 8 (See Table 9).


Table 9: Prime factors

1
2
4
8

The feedback resistor (

2
2*2
2*2*2

To find the lowest common multiple, we need to think


about which list has the most of each factor. In this
case it is list 8, which has 2*2*2. So the lcm is 2*2*2=8.
(BBC, 2014)

) on the adder op amp should be a factor of 8. So an 8k resistor will be used.

Table 10: Amplification values for each input bit

Bit 1

Bit 2

Bit 3

Bit 4

The multiplier is 1

The multiplier is 2

The multiplier is 4

The multiplier is 8

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4.2 Circuit Simulation Using Proteus


The final circuit is shown in Figure 20. Each input is connected to the 1V source via a switch. When a switch
is up the input is off, i.e. 0V. When the switch is down the input is on, i.e. 1V.
Figure 20 to Figure 35 show all possible input combinations and the corresponding outputs.

Figure 20: Input 0000, Output 0

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Figure 21: Input 0001, Output 1

Figure 22: Input 0010, Output 2

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Figure 23: Input 0011, Output 3

Figure 24: Input 0100, Output 4

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Figure 25: Input 0101, Output 5

Figure 26: Input 0110, Output 6

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Figure 27: Input 0111, Output 7

Figure 28: Input 1000, Output 8

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Figure 29: Input 1001, Output 9

Figure 30: Input 1010, Output 10

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Figure 31: Input 1011, Output 11

Figure 32: Input 1100, Output 12

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Figure 33: Input 1101, Output 13

Figure 34: Input 1110, Output 14

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Figure 35: Input 1111, Output 15

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4.3 Actual Circuit


The circuit was created on breadboard (see Figure 36) using:

Four dip-switches (top-right)


Op Amp (centre-left)
Resistors: feedback resistor (centre-left), various resistors (top-right) to weight each of the dipswitches as required.

Figure 36: 4-bit converter

Two PSUs to power the Op Amp. One also provides power to the dip-switches.

Figure 37: Duel PSUs

A selection of wires to connect everything together.

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Figure 38: Oscilloscope showing input and output voltages

The values shown in Figure 38 differ from those in the simulator primarily because different input voltages
were used. Had the voltage been the same, there would probably still show some slight difference:

The supply voltage to the Op Amps was not exactly 12.0 V. (Actually +12.0, -12.1 V.)
The resistance of the wires may have affected the input ratios slightly.
The calibration of the PSUs and oscilloscope may be out.

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5 Conclusions
Although the ideal Op Amp does not exist, many of those available are close enough.
Table 11: Ideal vs. real Op Amp

Characteristic

Ideal Op Amp

Voltage gain

Infinite.

Gain vs. frequency

Gain is independent of frequency.

Input resistance

Infinite.

2M.

Output resistance

Zero.

Typically 75.

Input voltage offset

Zero.

A few mV.

Output voltage

Can swing to the positive or negative


supply rails.

Typically 13V for an amp with rails


of 15V.
Takes a finite time to reach the
output value and additional time to
settle (slew rate).

Output reaction time

Can swing instantly to the correct


value.

Real Op Amp
Very high gain. Open-loop gain in the
order of 200,000.
Gain remains constant up to about
10kHz.

Effect of using a real Op Amp:


1. Voltage gain was not an issue for any of the circuits because at most a gain of *8 was required.
2. Frequency was not a problem, because two of the circuits were DC (i.e. a frequency of 0Hz) and the
integrator circuit used a frequency of 1Hz.
3. The input resistance of the Op Amp was far higher than any of the resistors used in the circuit. So
for the purpose of these experiments it was effectively infinite.
4. The output resistance of the Op Amp was far lower than any of the resistors used in the circuit. So
for the purpose of these experiments it was as good as zero.
5. The output voltage was kept well below the values of the Op Amp supply rails.
6. The time taken for the output to react to the input was small enough to be of no consequence.
We have shown in both simulations and actual circuits that Op Amps can be used to perform arithmetic
operations on one or more input voltages and deliver the results (almost) instantly.

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6 Bibliography
BBC, 2014. BBC - GCSE Bitesize: Highest common factor and lowest common multiple. [Online]
Available at: http://www.bbc.co.uk/schools/gcsebitesize/maths/number/primefactorshirev1.shtml
[Accessed 06 03 2014].
Bird, J., 2010. 19.8 Op amp integrator. In: Electrical and Electronic Principles and Technology. Fourth ed.
Oxford: Newnes, pp. 303-304.
Middlesbrough College, 2013. The Operational Amplifier. Middlesbrough: Middlesbrough College.

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