Академический Документы
Профессиональный Документы
Культура Документы
Silicon on insulator
From Wikipedia, the free encyclopedia
Contents
SIMOX process
1 Industry need
2 SOI transistors
3 Manufacture of SOI wafers
4 Use in the microelectronics industry
5 Use in high-performance Radio-Frequency
(RF) applications
6 Use in photonics
7 See also
8 References
9 External links
Industry need
The implementation of SOI technology is one of several manufacturing strategies employed to allow the
continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law.
Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:[5]
Lower parasitic capacitance due to isolation from the bulk silicon, which improves power
http://en.wikipedia.org/wiki/Silicon_on_insulator
1/6
10/31/2014
SOI transistors
An SOI MOSFET is a semiconductor device
(MOSFET) in which a semiconductor layer such as
silicon or germanium is formed on an insulator layer
which may be a buried oxide (BOX) layer formed in
Smart Cut process
[8][9][10]
a semiconductor substrate.
SOI MOSFET
devices are adapted for use by the computer
industry. The buried oxide layer can be used in SRAM memory designs.[11] There are two type of SOI
devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For a n-type
PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is
large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk
MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in
FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX)
supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in
http://en.wikipedia.org/wiki/Silicon_on_insulator
2/6
10/31/2014
higher switching speeds. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, higher subthreshold slop body effect, etc. are reduced in FDSOI since the source and drain electric fields can't
interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film
is not connected to any of the supplies.
http://en.wikipedia.org/wiki/Silicon_on_insulator
3/6
10/31/2014
In November 2010, several news sources indicated that Intel may switch to SOI for the 22 nm node.[23]
More recently, Intel announced it will not go to SOI at 22 nm due to costs, and instead has used FinFET
technology in Ivy Bridge.
On the foundry side, July 2006 TSMC claimed no customer wanted SOI,[24] but Chartered
Semiconductor devoted a whole fab to SOI.[25]
Use in photonics
SOI wafers are widely used in silicon photonics.[27] The crystalline silicon layer on insulator can be used
to fabricate optical waveguides and other passive optical devices for integrated optics. The crystalline
silicon layer is sandwiched between the buried insulator (Silicon oxide, Sapphire etc.) and top cladding
of air (or Silicon oxide or any other low refractive index material). This enables propagation of
electromagnetic waves in the waveguides on the basis of total internal reflection.
See also
Intel TeraHertz - similar technology from Intel.
Wafer (electronics)
Wafer bonding
Silicon on sapphire
References
1. ^ a b Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator"
(http://www.soitec.com/pdf/Frontiers_SOI.pdf). J Appl Phys 93 (9): 4955. doi:10.1063/1.1558223
(http://dx.doi.org/10.1063%2F1.1558223).
2. ^ Marshall, Andrew; Natarajan, Sreedhar (2002). SOI design: analog, memory and digital techniques. Boston:
Kluwer. ISBN 0792376404.
3. ^ Colinge, Jean-Pierre (1991). Silicon-on-Insulator Technology: Materials to VLSI. Berlin: Springer Verlag.
ISBN 978-0-7923-9150-0.
4. ^ IBM Advances Chip Technology With Breakthrough For Making Faster, More Efficient Semiconductors
(http://www-03.ibm.com/press/us/en/pressrelease/2521.wss)
5. ^ Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications
(http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf) by Horacio Mendez, Executive Director
of the SOI Industry Consortium, April 9, 2009
6. ^ http://www.infotech-enterprises.com/fileadmin/infotech-
http://en.wikipedia.org/wiki/Silicon_on_insulator
4/6
10/31/2014
6. ^ http://www.infotech-enterprises.com/fileadmin/infotechenterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf
7. ^ IBM touts chipmaking technology (http://news.cnet.com/IBM+touts+chipmaking+technology/2100-1001_3254983.html)
8. ^ United States Patent 6,835,633 SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using
30-100 Ang. thin oxide as bonding layer
9. ^ United States Patent 7,002,214 Ultra-thin body super-steep retrograde well (SSRW) FET devices
10. ^ Ultrathin-body SOI MOSFET for deep-sub-tenth micron era; Yang-Kyu Choi; Asano, K.; Lindert, N.;
Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu; Electron Device Letters, IEEE; Volume 21, Issue
5, May 2000 Page(s):254 - 255
11. ^ United States Patent 7138685 " Vertical MOSFET SRAM cell" describes SOI Buried Oxide (BOX)
structures and methods for implementing enhanced SOI BOX structures.
12. ^ U.S. Patent 5,888,297 (https://www.google.com/patents/US5888297) Method of fabricating SOI substrate
Atsushi Ogura, Issue date: Mar 30, 1999
13. ^ U.S. Patent 5,061,642 (https://www.google.com/patents/US5061642) Method of manufacturing
semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991
14. ^ SIMOX-SOI Technology: Ibis Technology (http://www.ibis.com/simox.htm)
15. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gsele, WileyInterscience, 1998, ISBN 978-0-471-57481-1
16. ^ U.S. Patent 4,771,016 (https://www.google.com/patents/US4771016) Using a rapid thermal process for
manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988
17. ^ http://www.sigen.com/
18. ^ ELTRAN - Novel SOI Wafer Technology (http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf),
JSAPI vol.4
19. ^ U.S. Patent 5,417,180 (https://www.google.com/patents/US5417180)
20. ^ Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed (http://chiparchitect.com/news/2000_11_07_process_130_nm.html)
21. ^ Process Technology (http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0121000303#soi)
22. ^ Rong, Haisheng; Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani, Nicolaescu, Remus; Fang,
Alexander; Paniccia, Mario (January 2005). "An all-silicon Raman laser"
(http://www.ece.ucsb.edu/uoeg/publications/papers/Rong05nature.pdf). Nature 433: 292294.
doi:10.1038/nature03723 (http://dx.doi.org/10.1038%2Fnature03723).
23. ^ http://www.eetimes.com/electronics-news/4210354/Analyst--Intel-to-endorse-SOI-at-22-nm-semiconductor
24. ^ TSMC has no customer demand for SOI technology - Fabtech - The online information source for
semiconductor professionals (http://www.fabtech.org/content/view/1698/74/)
25. ^ Chartered expands foundry market access to IBM's 90nm SOI technology
(http://www.charteredsemi.com/media/corp/2006n/20060420_IBM_SOI.asp)
26. ^ Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO"
(http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf). Mobile Experts. Retrieved 2 May 2012.
27. ^ "Silicon photonics: an introduction" by Graham T. Reed, Andrew P. Knights. WIley. Page 111
(http://books.google.be/books?
id=6lsVVvFCBeAC&lpg=PA57&ots=XmqaiUFliA&dq=SOI%20Wafers%20in%20Photonics&hl=en&pg=PA
111#v=onepage&q=SOI%20&f=false)
http://en.wikipedia.org/wiki/Silicon_on_insulator
5/6
10/31/2014
External links
SOI Industry Consortium (http://www.soiconsortium.org/) - a site with extensive information and
education for SOI technology
SOI IP portal (http://www.chipestimate.com/SOI) - A search engine for SOI IP
AMDboard (http://www.amdboard.com/soispecial.html) - a site with extensive information
regarding SOI technology
Advanced Substrate News (http://www.advancedsubstratenews.com/) - a newsletter about the SOI
industry, produced by Soitec.
MIGAS '04 (http://www.migas.inpg.fr/2004/index.htm) - The 7th session of MIGAS International
Summer School on Advanced Microelectronics, devoted to SOI technology and devices.
MIGAS '09 (http://www.migas.inpg.fr/) - 12th session of the International Summer School on
Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"
Retrieved from "http://en.wikipedia.org/w/index.php?title=Silicon_on_insulator&oldid=621449145"
Categories: Semiconductor structures Semiconductor technology Microtechnology
This page was last modified on 16 August 2014 at 05:27.
Text is available under the Creative Commons Attribution-ShareAlike License; additional terms
may apply. By using this site, you agree to the Terms of Use and Privacy Policy. Wikipedia is a
registered trademark of the Wikimedia Foundation, Inc., a non-profit organization.
http://en.wikipedia.org/wiki/Silicon_on_insulator
6/6