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Proceedings of the 2
nd
 International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India
 
119
PWM CONTROL STRATEGIES FOR MULTILEVEL INVERTERS BASED ON CARRIER REDISTRIBUTION TECHNIQUE
S. Nagaraja Rao
1
, D.V. Ashok Kumar
2
, Ch.Sai Babu
3
 
1
Research Scholar, JNTUK,Kakinada (A.P), India
2
Professor, Dept.of EEE, SDIT, Nandyal (A.P), India
3
Professor, Dept.of EEE, JNTUK, Kakinada (A.P), India
ABSTRACT
This paper proposes three Pulse width modulated (PWM) methods based on Carrier Redistribution Techniques that utilize the (CFD) control freedom degree of vertical offsets among carriers. They are named as Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) and Phase Disposition (PD). Ingeneral Pulse width modulated (PWM) techniques of a voltage source inverter need a reference signal and carrier signal to generate the required modulating signals for the desired output. Modifications in Modulating techniques can be considered in two ways, namely Modified reference and Modified carrier. The existing multilevel carrier-based pulse width modulation strategies have no special provisions to offer quality output, besides lower order harmonics are introduced in the spectrum, especially at low switching frequencies. This paper proposes a novel multilevel PWM strategy to corner the advantages of low frequency switching and reduced total harmonic distortion (THD) based on Carrier Redistribution Technique. This paper also presents the most relevant control and modulation methods by a new reference/carrier based PWM scheme for three phase Diode Clamped Multilevel Inverter and comparing the performance of the proposed scheme with that of the existing control schemes. Finally, the simulation results are included to verify the effectiveness of the proposed multilevel inverter configuration using various PWM Techniques and validate the proposed theory.
Keywords:
Diode Clamped MLI, Pulse width modulation, APOD, POD, PD, Total Harmonic Distortion.
I. INTRODUCTION
The voltage source inverters produce an output voltage or current with levels either 0 or ±Vdc. They are known as the two-level inverter. To produce a quality output voltage or a current
 
INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)
ISSN 0976 – 6545(Print)
 
ISSN 0976 – 6553(Online)
 
Volume 5, Issue 8, August (2014), pp. 119-131 © IAEME: www.iaeme.com/IJEET.asp
 
Journal Impact Factor (2014): 6.8310 (Calculated by GISI)
 
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Proceedings of the 2
nd
 International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India
 
120
wave form with less amount of ripple content, they require high switching frequency. In high- power and high-voltage applications these two level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of device ratings. These limitations can be overcome using multilevel inverters. The multilevel inverters have drawn tremendous interest in power industry. It may be easier to produce a high-power, high-voltage inverter with multi level structure because of the way in which the voltage stresses are controlled in the structure. The unique structure of multilevel voltage source inverters allows them to reach high voltages with low harmonics without use of transformers or series connected synchronized-switching devices. As the number of voltage levels increases, the harmonic content of the output voltage wave form decreases significantly. In general multilevel inverter can be viewed as voltage synthesizers, in which the high output voltage is synthesized from many discrete smaller voltage levels. The main advantages of this approach are summarized as follows:
 
They can generate output voltages with extremely low distortion and lower (dv/dt).
 
They can operate with a lower switching frequency.
 
Their efficiency is high (>98%) because of the minimum switching frequency.
 
They are suitable for medium to high power applications. The selection of the best multilevel topology for each application is often not clear and is subject to various engineering tradeoffs. Multilevel inversion is a power conversion strategy in which the output voltage is obtained in steps thus bringing the output closer to a sine wave and reduces the total harmonic distortion (THD). In general MLI’s are three types they are named as diode clamped, flying capacitor and cascaded inverters. In this paper diode clamped MLI is considered based on their own advantages [1]. This paper presents a PWM control strategies for a seven level inverter Diode Clamped inverter based on carrier redistribution technique. Simulation results are included to verify the operating principle of the proposed multilevel inverters.
II.
 
SYSTEM
 
CONFIGURATION
 
Fig .1:
 Multilevel concept for (a) two level (b) three level and (c) n- level Multilevel inverter structures have been developed to overcome shortcomings in solid-state switching device ratings so they can be applied to higher voltage systems. The multilevel voltage source inverters [2] unique structure allows them to reach high voltages with low harmonics without the use of transformers. The general function of the multilevel inverter is to synthesize a desired ac voltage from several levels of dc voltages as shown in Fig.1. Table.1 compares the power component requirement per phase leg among the three multilevel voltage source inverters mentioned above. The table shows that the number of main switches and main diodes needed by the inverters to achieve the number of voltage levels.
 
Proceedings of the 2
nd
 International Conference on Current Trends in Engineering and Management ICCTEM -2014 17 – 19, July 2014, Mysore, Karnataka, India
 
121
Table.1:
Component requirements per phase of m-level multilevel inverters
Devices Diode clamped MLI Flying Capacitor MLI Cascaded H-Bridge MLI
Main switching Devices 2(m-1) 2(m-1) 2(m-1) Main diodes 2(m-1) 0 2(m-1) Clamping diodes (m-1)* (m-2) (m-1)*(m-2) 0 Dc Balancing Capacitors m-1 m-1 (m-1)/2 Balancing Capacitors 0 2(m-1) 0
III. 7-LEVEL DIODE CLAMPED INVERTER
 
Fig. 2:
 Configuration of Three-phase Diode Clamped Seven Level Inverter (DC7LI) Fig. 2 shows a seven-level diode-clamped inverter in which the dc bus consists of six capacitors, C1, C2, C3, C
4,
 C
5
 and C6. For dc-bus voltage V
dc
, the voltage across each capacitor is V
dc
 and each device voltage stress will be limited to one capacitor voltage level through clamping diodes. To explain how the staircase voltage is synthesized, the neutral point
n
is considered as the output phase voltage reference point. There are seven switch combinations to synthesize seven level output as shown in Table2.
Table.2:
 Switching sequence for single phase 7 level diode clamped inverter
Output voltage S1 S2 S3 S4 S5 S6 S1
1
S2
1
S3
1
S4
1
S5
1
S6
1
0
1 1 1 1 1 1 1 0 0 0 0 0
Vdc
0 1 1 1 1 1 1 0 0 0 0 0
2Vdc
0 0 1 1 1 1 1 1 0 0 0 0
3Vdc
0 0 0 1 1 1 1 1 1 0 0 0
-Vdc
0 0 0 0 0 1 1 1 1 1 1 0
-2vdc
0 0 0 0 1 1 1 1 1 1 0 0
-3vdc
0 0 0 1 1 1 1 1 1 0 0 0

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