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Connection Diagram
Truth Tables
Features
Y
Y
Y
Y
Y
HC160/HC161
CLK
CLR
ENP
ENT
Load
Function
X
X
X
X
L
H
H
H
H
H
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
u
u
HC162/HC163
TL/F/5008 1
TL/F/5008
CLK
CLR
ENP
ENT
Load
Function
L
H
H
H
H
H
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
X
X
X
u
u
RRD-B30M115/Printed in U. S. A.
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
January 1992
Operating Conditions
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65 C to a 150 C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260 C
Min
2
Max
6
Units
V
VCC
b 40
b 55
a 85
a 125
C
C
1000
500
400
ns
ns
ns
Parameter
Conditions
TA e 25 C
VCC
74HC
TA eb40 to 85 C
Typ
54HC
TA eb55 to 125 C
Units
Guaranteed Limits
VIH
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
IIN
Maximum Input
Current
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating plastic N package: b 12 mW/ C from 65 C to 85 C; ceramic J package: b 12 mW/ C from 100 C to 125 C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY89.
Guaranteed Limit
Units
fMAX
Symbol
Parameter
Conditions
43
30
MHz
tPHL, tPLH
30
35
ns
tPHL, tPLH
29
34
ns
tPHL, tPLH
18
32
ns
tPHL
27
38
ns
tREM
10
20
ns
tS
30
ns
tH
ns
tW
16
ns
Parameter
Conditions
VCC
TA e 25 C
Typ
74HC
TA eb40 to 85 C
54HC
TA eb55 to 125 C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
40
45
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
tPHL
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
100
32
28
215
43
37
271
54
46
320
64
54
ns
ns
ns
tPLH
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
88
18
15
175
35
30
220
44
37
260
52
44
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
95
30
26
205
41
35
258
52
44
305
61
52
ns
ns
ns
tPLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
51
43
ns
ns
ns
tPHL
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
90
28
24
195
39
33
246
49
42
291
58
49
ns
ns
ns
tPLH
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
80
16
14
160
32
27
202
40
34
238
48
41
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clear to RC
2.0V
4.5V
6.0V
100
32
28
220
44
37
275
55
47
325
66
55
ns
ns
ns
tPHL
Maximum Propagation
Delay, Clear to Q
2.0V
4.5V
6.0V
100
32
28
210
42
36
260
52
45
315
63
54
ns
ns
ns
tREM
2.0V
4.5V
6.0V
125
25
21
158
32
27
186
37
32
ns
ns
ns
tS
Minimum Setup
Time Clear or Data
to Clock
2.0V
4.5V
6.0V
150
30
26
190
38
32
225
45
38
ns
ns
ns
tS
Minimum Setup
Time Load
to Clock
2.0V
4.5V
6.0V
135
27
23
170
34
29
200
41
35
ns
ns
ns
tS
Minimum Setup
Time Enable
to Clock
2.0V
4.5V
6.0V
175
35
30
220
44
37
260
52
44
ns
ns
ns
tH
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
Parameter
Conditions
VCC
TA e 25 C
Typ
74HC
54HC
TA eb40 to 85 C TA eb55 to 125 C Units
Guaranteed Limits
tH
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tW
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
75
15
13
95
19
16
110
22
19
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
2.0V
4.5V
6.0V
tr, tf
2.0V
4.5V
6.0V
CPD
Power Dissipation
Capacitance (Note 5)
CIN
(per package)
40
8
7
90
5
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption,
IS e CPD VCC f a ICC.
Logic Diagrams
MM54HC160/MM74HC160 or MM54HC162/MM74HC162
TL/F/5008 2
MM54HC161/MM74HC161 or MM54HC163/MM74HC163
TL/F/5008 3
Logic Waveforms
160, 162 Synchronous Decade Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to BCD seven
(3) Count to eight, nine, zero, one, two, and three
(4) Inhibit
TL/F/5008 4
161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
TL/F/5008 5
74HC160/MM54/74HC161/MM54/74HC162/MM54/74HC163
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
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National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.