International Journal of Electrical and

Electronics Engineering Research (IJEEER)

ISSN(P): 2250-155X; ISSN (E): 2278-943X
Vol. 4, Issue 4, Aug 2014, 73-78
TJPRC Pvt. Ltd.

DESIGN OF CMOS TERNARY LOGIC GATES

1

V. T. GAIKWAD & P R. DESHMUKH2

1

Associate Professor, Department of Information Technology, SIPNA College of Engineering & Technology,
Amravati, Maharashtra, India
2

Professor, Department of Information Technology, SIPNA College of Engineering & Technology,

Amravati, Maharashtra, India

ABSTRACT
The multi valued logic (MVL) is becoming quite useful in VLSI/ULSI applications as being able to reduce the
number of interconnection lines and increase their information content. It is found useful in various applications, such as
memories, communications, arithmetic circuits, signal processing and supporting chips.
With the development of multi valued algebras, multi valued semiconductor circuits are the principle area
of research. The realistic network synthesis relies upon the availability of a relevant semiconductor circuits.
In this paper, the design of the basic ternary logic gates is proposed. These logic gates can be used to further
implement the ternary logic circuits.

KEYWORDS: Logic Gates, Multi Valued Logic, Ternary Logic System

INTRODUCTION
Among various types of MVL, the ternary logic receives more attention than others because of lower
interconnection cost estimation [1] and a simple electronic circuit implementation method [2] Ternary logic offers several
important advantages over binary logic in the design of digital systems [3], [4] like more information can be transmitted
over a given set of lines [5][6]. The complexity of interconnections can be, reduced & reduction in chip area can be
achieved.
Another advantage of MVL is the use of fewer operations, and potentially fewer gates [5][6]. But the key issue in
MVL systems is development of superior multi valued hardware algorithms and appropriate devices. These circuits in turn
represent the operators used in formal algebra [7].

DESIGN OF TERNARY LOGIC GATES

The most fundamental building blocks in the design of digital systems are the inverter, NOR gate, and NAND
gate. We propose the ternary implementations for the inverter, NOR Gate, and NAND gate, in which the static power
dissipation is low.

MVL-INVERTER
A MVL inverter is a complement function; which in the binary notation is known as an inverter. It is also called
as the MVL-NOT function. There are three basic ternary elements: the STI (Simple Ternary Inverter), the NTI
(Negative Ternary Inverter) and the PTI (Positive Ternary Inverter), whose logic functions are shown in Table 1.
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V. T. Gaikwad & P R. Deshmukh

The rule of ternary inversion for these three types of basic ternary operations are defined by
(1)
C in Eq. (1) takes the values of logic 2 for a PTI, logic 1 for a STI and logic 0 for a NTI which correspond to
higher level (2), middle level (1) and lower level (0), respectively.
Design of STI
A MVL-NOT function is an elementary function in MVL. In order to make a voltage mode multi-valued signal,
high accuracy is necessary, because the voltage levels for each logic level are an equal division of VDD. The table 1 is a
truth table for STI.
Table 1: Truth Table for STI
Input
0
1
2

Output
2
1
0

In most of previous designs the transmission gate or pull up transistors are used at the output of Slandered Ternary
Inverter. We have proposed the design of STI without use of the transmission gate or pull up transistors.
Figure 1 shows the schematic example of typical balance simple ternary inverter (STI) in previous designs where
logic levels are -1V, 0v, + 1V. It is designed by connecting a CMOS transmission gate to the common drain output of a
CMOS inverter. The gates of p- and n- MOSFETs (Q3 and Q4) in the transmission gate are tied to negative and positive
power supplies, respectively. The transmission gate aids in pulling up a control signal, C of 0V to the output when the
inverter is in cut-off.

Figure 1: Balanced Standard Ternary Inverter

Figure 2 shows the Simple ternary inverter (STI) implemented using a PMOS transistor Q1 & NMOS transistor
Q2 with Logic 2 at VDD, Logic 0 at GND (0 V) & logic 1 is a middle voltage between VDD & GND.

Impact Factor (JCC): 5.9638

Index Copernicus Value (ICV): 3.0

75

Design of CMOS Ternary Logic Gates

Figure 2: Standard Ternary Inverter (STI)

The circuit operation is simulated on micro wind. The figure 3 shows the graph of Voltage Vs Time for input and
output.

Figure 3: Simulation Results of STI of Figure 1

From the simulation results, some of the important parameters are for the clock pulse of 0.1 ps are
Table 2: Typical Voltage & Current Parameters of STI
Vdd
1.2 V

Idd Max
2.17 mA

Idd Avg
0.003 mA

The resistance of channels can be change by altering the length-to-width ratio of the PMOS and NMOS channels.
Thus, the resistance of the circuit is directly proportional to its L/W ratio which can be effectively used to change the
resistance of transistors to suit design needs [8][9]. However, there is a lower limit to the value of L and W due to the
limitations imposed by the design rules of the foundry [10]
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76

V. T. Gaikwad & P R. Deshmukh

DESIGN OF TERNARY NAND GATE

A TNAND function gives the inversion of the minimum value of the input signal where input signal belongs to 0,
1 and 2 or -1, 0 & +1 in balance ternary. The NAND o/p can be defined as
= MIN

The truth table for this function is given in Table 2.

Table 3: Truth Table for Ternary NAND Gate

Vin1
0
0
0
1
1
1
2
2
2

Vin2
0
1
2
0
1
2
0
1
2

V Out
2
2
2
2
1
1
2
1
0

The design of proposed TNAND gate for balance ternary is shown in figure 4 where the transistor at the o/p are
used to pull the o/p to logic 1 i.e. at middle level. W/L ratio of the NMOS transistor is selected to generate the o/p voltage
levels accordingly.

Figure 4: TNAND Gate Design

The results of the design are simulated on Micro Wind. Figure 5 Figure 6 shows the result of the Voltage Vs Time
when different the different i/p logic levels.

Impact Factor (JCC): 5.9638

Index Copernicus Value (ICV): 3.0

77

Design of CMOS Ternary Logic Gates

Figure 5: Simulated O/P of TNAND Gate

Figure 6: O/P Voltage vs Time of TNAND

The results for drain & source currents against o/p voltage are also simulated as shown in figure 7

Figure 7: Simulation Results for Transistor Currents & Voltage

The results are simulated for clock pulse of 0.1 ps. The power dissipation for STI and TNAND is observed as
given below
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78

V. T. Gaikwad & P R. Deshmukh

Table 4: Power Dissipation of STI & TNAND

Gate
STI
NAND

Power Dissipation
97.69W
3.752 W

Design of the CMOS ternary Inverter & NAND gates has been described & their results are simulated. The design
of other logic gate can also be proposed with the similar approach.

CONCLUSIONS
These logic gates then may be used to design other ternary circuits. The parameters of these proposed ternary
gates can be analyzed and compared with the other ternary gates found in the literature.
The proposed designs have much lower power dissipation relative to other known ternary circuits reported in the
literature. Furthermore, they lead to significant reductions in the component count. Considering the various advantages of
the multi valued logic, the appropriate design of the MVL logic gates is also important so that it will lead to the further
development and its applications in this area

REFERENCES
1.

S. L. Hurst, Multi Valued logic-Its status and its future, IEEE Trans. Comput. Vol. C-33, pp. 1160-1179, 1984.

2.

H. T. Mouftah and I. B. Jorden, Integrated circuits for temary logic, in IEEE Proc. ISMVL, May 1974,
pp. 285-302.

3.

K. C. Smith, The prospects for multi Valued loglc: A technology and application view, IEEE Tram Corn put,
Vol. C-30, pp. 619-634, Sept. 1981.

4.

D. L Porat, Three valued digital systems, Proc. IEE, Vol. 116, pp. 946-954, June 1969.

5.

Jean-Marc Philippe, Ekue Kinvi-Boh, Sebastien Pillement An Energy-Efficient Ternary Interconnection Link for
Asynchronous Systems, IEEE proc. ISCAS 2006.

6.

Tomaz Felicijan, B. Furber, An Asynchronous Ternary Logic System, IEEE Transactions on Very Large Scale
Integration Systems, Vol. 11, No. 6, December 2003

7.

Michitaka Kameyama, "Toward the Age of' Beyond-Binary Electronics and System IEEE Proceedings of 20th
International Symposium on MVL, May 1990, pp.162-166.

8.

X. Wu, F. Prosser, CMOS ternary logic circuits, Proc. IEE - G, Vol. 137, no. 1, pp. 21-27, Feb. 1990.

9.

H. T. Mouftah and I. B. Jorden, Integrated circuits for ternary logic, in IEEE Proc. ISMVL, May 1994,
pp. 285-302.

10. X. W. Wu, Prof. F. P. Prosser, CMOS ternary logic circuits, IEEE Proceedings, Vol. 137, Pt. G, No I,
February 1990.

Impact Factor (JCC): 5.9638

Index Copernicus Value (ICV): 3.0