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Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/10207 1
TL/F/10207 2
Pin Names
CEP
CET
CP
P0P3
PE
U/D
Q0Q3
TC
TL/F/10207
VCC e Pin 16
GND e Pin 8
Description
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
RRD-B30M105/Printed in U. S. A.
June 1989
(Note)
Note: The Absolute Maximum Ratings are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the Electrical Characteristics
table are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define
the conditions for actual device operation.
54LS168
Parameter
Units
Min
Nom
Max
4.5
5.5
VCC
Supply Voltage
VIH
VIL
IOH
IOL
TA
ts (H)
ts (L)
15
15
ns
th (H)
th (L)
5
5
ns
ts (H)
ts (L)
20
20
ns
th (H)
th (L)
0
0
ns
ts (H)
ts (L)
25
25
ns
th (H)
th (L)
0
0
ns
tw (H)
tw (L)
20
20
ns
b 55
V
V
0.7
b 0.4
mA
mA
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
VOH
VOL
II
IIH
IIL
IOS
ICC
Supply Current
Typ
(Note 1)
Min
Max
Units
b 1.5
2.5
V
0.4
0.1
mA
Inputs
20
CET
40
mA
Data
b 0.5
b 400
b 30
b 400
CET
b 60
b 800
b 20
b 100
mA
34
mA
Switching Characteristics
VCC e a 5.0V, TA e a 25 C (See Section 1 for test waveforms and output load)
54LS168
Symbol
Parameter
CL e 15 pF
Min
Units
Max
fMax
25
tPLH
tPHL
Propagation Delay
CP to Qn
20
20
ns
tPLH
tPHL
Propagation Delay
CP to TC
30
30
ns
tPLH
tPHL
Propagation Delay
CET to TC
15
20
ns
tPLH
tPHL
Propagation Delay
U/D to TC
25
25
ns
MHz
mA
Functional Description
The LS168 uses edge-triggered D-type flip-flops and has
no constraints on changing the control or data input signals
in either state of the Clock. The only requirement is that the
various inputs attain the desired state at least a setup time
before the rising edge of the clock and remain valid for the
recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on
the P0 P3 inputs enters the flip-flops on the next rising
edge of the Clock. In order for counting to occur, both CEP
and CET must be LOW and PE must be HIGH. The U/D
input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW,
provided that CET is LOW, when a counter reaches zero in
the COUNT DOWN mode or reaches 9 in the COUNT UP
mode. The TC output state is not a function of the Count
Enable Parallel (CEP) input level. The TC output of the
LS168 decade counter can also be LOW in the illegal
states 11, 13 and 15, which can occur when power is turned
on or via parallel loading. If an illegal state occurs, the
LS168 will return to the legitimate sequence within two
counts. Since the TC signal is derived by decoding the flipflop states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equation below).
1. Count Enable e CEP # CET # PE
CEP
CET
U/D
L
H
H
H
H
X
L
L
H
X
X
L
L
X
H
X
H
L
X
X
State Diagram
Logic Diagram
TL/F/10207 4
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
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Hong Kong
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Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.