Test Response Compaction Using Arithmetic Functions

Albrecht P. Stroele
University of Karlsruhe, Institute of Computer Design and Fault Tolerance
P. 0. Box 6980, D-76128 Karlsruhe, Germany

Abstract

using fault simulation. So probabilistic models are used

and the portion of aliased faults is estimated by the probability of aliasing. Since BIST methods usually apply a
large number of test patterns, the behavior of the aliasing
probability for long test lengths is most important.
Rajski and Tyszer were the first to analyse response
compaction by accumulators. They studied accumulators
with binary adders and 1's complement adders [7] and also
accumulators where the overflow from the most significant bit position is stored in an extra flip-flop [6]. They
have shown that the limiting value of the aliasing proba2k- 1-Pf
1
1
bility is
, -, and -, respectively, for
2k- 1
2k- 1
these three types of k-bit accumulators (i: number of least
significant bits that are not affected by the fault, pf: probability of an erroneous response).
But their analysis is restricted to "primitive" faults, a
class of combinational faults, which lead to errors with
certain number theoretic properties. Furthermore, they
assume that also with faulty CUTS error-free responses
occur with nonzero probability. And [6] implicitly uses
the assumption that in the error-free case all states of the
accumulator occur with equal probability, which does not
hold in general.
This paper presents a more general analysis of aliasing
in compactors that are based on different types of adders
and subtracters. The analysis includes the complete set of
combinational faults (i.e. all faults that do not introduce
sequential behavior), and the restrictions of previous
studies are removed. Moreover, these compactors are compared to multiple input signature registers (MISRs) that
are based on linear feedback shift registers.
As the investigated configurations are built from basic
blocks of data paths, the hardware overhead is very small
compared to the well-known self-test methods that insert
multi-functional test registers. Moreover, there is almost
no performance degradation. This makes the proposed configurations particularly well-suited to high-performance
circuits where speed is critical.
Throughout the paper, we use the following notation
for a compactor that is based on an adder or subtracter
modulo N:

Configurations of registers and adders, subtracters, or

arithmetic logic units, which are available in many data
paths, can be utilized to generate test patterns and compact
test reponses. This paper analyzes aliasing in these configurations when the test responses of circuits with arbitrary
combinational faults are compacted, and gives the limiting
values that the aliasing probability tends to for increasing
test lengths. Configurations that feed back the overjlow
during addition or the underjlow during subtraction are the
best choices. In some of them the pr,obability of aliasing
tends to a limiting value of 1 / (2k-1), which is almost
the same as in compactors based on linear feedback shift
registers with irreducible Characteristicpolynomials.

2k-i

1 . Introduction
Built-in self-test (BIST) requires that test patterns are
generated on-chip and test responses are compacted onchip. Data paths of processors and in particular circuits for
digital signal processing often contain adders, subtracters,
or arithmetic logic units (ALUs) that together with a register can be configured as shown in figure 1 and serve as
pattern generators [4, 8, 91 and response compactors.

Figure 1: Pattern generator / test response compactor built

from basic blocks of a data path

When this hardware structure is employed for response
compaction, with every clock pulse a test response from
the circuit under test (CUT) is added to or subtracted from
the register contents. At the end of the test application, the
contents of the register (i.e. the computed signature) are
compared to the signature of the fault-free circuit. Due to a
loss of information during compaction, however, even
some erroneous response sequences can lead to the errorfree signature. For large circuits, it is computationally
unfeasible to determine the exact number of aliased faults

380
0-8186-7304-4/96 $05.00 0 1996 IEEE

14'h VLSI Test Symposium - 1996

t.

r(t):
observed test response at time t
ref(t): error-free test response at time t
e(t): error at time t
where r(t), ref(t), and e(t) are the values of the corresponding bit vectors, r(t) = ref(t) + e(t). As we assume that
random patterns are applied and the CUT has combinational faults, successive errors are statistically independent
in time. Let E := {EO, EI, ..., Em- 1 } be the set of error
values that occur with nonzero probability, -(N- 1) I : ~Ii
N-1 for i = O,l, ...,m-1.
6 := gcd{eo, ~ 1...,, ~ ~ -N}1 , denotes the largest
integer that divides every error value and N. Using the
equality gcd{x2-x1, x3-x2} =: gcd(x2-x1, x3-x1}, the
greatest common divisor of N and all the differences
between error values becomes
6' := gcd{Eo-Eo, E ~ - E O,...,
, Em-l-EO, E O - E ~ ,..,,,Em-l-El,
..., EO-Em-1, Em-l-Em..l, N}
= gcd{ El-EO, E ~ - E O ,..., E ~ . . ~ - EN}
o,
The proofs of this paper repeatedly use the fact that every
(modulo N)-sum of values from the set { xo, X I ,..., xz+l}
is a multiple of gcd{xo, x i , ..., xz-l, N}, and conversely
every multiple of gcd{xo, xi,..., xz-l, N} ranging between
0 and N-1 can be represented by such a sum [3]. In
particular, every error e(i) is a multiple of 6, every
difference of errors is a multiple of 6', and 6 divides 6'.
Hence, every error can be represented by e(i) = x.d + y( i).S
..e,

6'
6

where x is the same for all errors, 0 2 x < -, and y(i) can
assume a positive or negative value.
In the following section, the analysis begins with
configurations using adders and subtracters modulo N
where N is an arbitrary positive integer. In section 3,
adders and subtracters are considered that add the overflow
bit or subtract the underflow bit immediately at the least
significant bit position. Section 4 extends the ana1ysi:s to
configurations where the overflow bit or the underflow bit,
respectively, is stored in an extra flip-flop. Section 5
shows some experimental results and compares the
arithmetic compactors to MISRs.

,E
[[ s;lcc(0) + re$)

I[ Sacc(0) + 1=0(reAi) + e(i)) ] mod N

t-1

t-1

] mod N t

1=0

t-1

ze(i) ] mod N

1=0

{ sacc,ef(t) + 1=0
x e ( i ) ] modN
where sacc,,f(t) is the signature of the fault-free circuit.
Aliasing occurs if and only if sacc(t) = sacc,ef(t) holds,
t- 1

that is [I:
e(i>] mod N = 0, and at least one error e(i),
1=0

0 5 i < t, is different from 0. Hence, for the analysis it is

sufficient to consilder only the compaction of the errors.
The following theorem shows that aliasing can occur only
at specific times and the probability of aliasing at these
times tends to a limiting value for increasing test lengths.

Theorem U:
Let an accumulator with (modulo N)-adder compact test
responses that are statistically independent in time and
have errors with values EO, ~ 1...,
, Em-1. Then the probability of aliasing is,
Pal(t)

6'

if t @ I n . - I n e 1%)
6

= 0

else
where

6 = gcd{ EO, ~ 1...,

, ~ ~ -N}
1 ,
6' = gcd{El-Eo, E ~ - E O ,..., E,-~-Eo, N}

Before we prove the theorem, we show a simple

example. A 4-bit accumulator with addition modulo 16
compacts test responses where the errors can only have the
values EO = 6 and ~1 = 10. Figure 2 shows the possible
state transitions when the errors are compacted.

...

...
...
...

d
Figure 2:

i:

time;

State transitions of the 4-bit accumulator

For t 2 3, at odd times only the states 2, 6, 10, 14 and

at even times only the states 0, 4, 8, 12 can occur. As a
consequence, aliasnng can happen only at even times. With
6 = gcd{6,10,16) = 2 and 6' = gcd( 10-6,16} = 4, we

2 . Compaction using addition or

subtraction modulo N
The accumulator considered in this section uses a binary
adder that performs addition modulo N, usually N = 2k.
The overflow from the most significant bit position is
ignored. The accumulator is initialized to a known state
Sacc(0) E {0, 1, ..., N-1}. Initialization is always assumed
to be error-free. Then in every clock cycle, a test respclnse
r(i) is added to the current state Sacc(i). Compaction of the
test responses r(O), r(l), ..., r(t-1) gives the the signature
at time t

1
4

get ~ ~ l ( 2 n -=l )0 and lim pal(2n) = - for n e N.

n-w

Proof:
Starting from a given state s(0), the accumulator compacting the errors can reach all states out of { 0, 1, ..., N- 1 }
that differ from s(0) by a multiple of 6. In general,
however, not all of these N / 6 states are reachable at the
same point of time. Two different error sequences e(O),
e(l), ..., e(t-I) and e'(O), e'(l), ..., e'(t-1) result in states
s(t) and s'(t), which differ by As(t) = [s'(t) - s(t)] modN =

t- 1

sacc(t> = [ ~acc(O)+ i=O

Cr(i>I mod N

381

t- 1

[,x(e'(i) - e(i))] mod N.

1=0

some initial steps, aliasing can occur at every time

Starting with the difference

t2: to, and we get lim pal(t) =

As(0) = 0, all the differences As can be reached that are

equal to a sum of error differences [ ~ i - ~mj o] d N ,
0 5 i j < m, and this sum is always a rnultiple of 6'.
There exist nonnegative integers ELI,..., am.l such that
6' = [al.(&l-&O)+ ... + a,_l.(m-1-~0)] m o d N holds [3].
m-1

a = I.E
ai steps the state [s(O) + a.Eo] mod N
= 1
as well as the state [s(O) + a.&o+ 6'1 mod N can be
reached. In 2a steps, the states [s(O) + ~ C X . E O ]mod N,
Then in

[s(O) + 2a.&0+ 6'1 mod N and [s(O) + 2a.&0+ 26'1

mod N can be reached, and so on. Thus, starting from an
N
arbitrary state s(O), after (7
- l ) , a s,teps,
states can

?6

be reached. There is no point of time where more than

N/6' different states are possible.
We now consider transitions with 'c = 6'/6 steps, which
7- 1

7- 1

are caused by inputs .ze(t+i) = x.6.7

1=0

+ 1=0
,E 6',y(t+i)

7- 1

6'.(x

6
-

N
A prim number N is most favorable for compaction.
For m > l , this gives 6 = 6' = 1 independently of the
1
pcssible errors, and lim pal(t) = t+m
N .
Often, N equals 2k. Let i be the least significant bit
pcsition where an error can have a "1". Then we have
6 :I 2'. If also error-free responses or errors having a "0" at
2i
pcsition i can occur, then 6' = 6 and lim Pal(t) = 3 =
t-+m
2
2-:k-1)follow. Hence, faults that do not affect the less
significant bits of the test responses are aliased with
relatively high probability.
Compactors can also be built with (modulo N)-subtracters. Subtraction of r(i) corresponds to addition of N-r(i),
and gcd{ -EO, - E I , ..., -Em-l, N} = gcd(E0, ~ 1...,, Em-1, N}
holds. So these compactors have the same probability of
aliasing as compactors using (modulo N)-addition.
t+m

+ ,zy(t+i) . If all the N7

states that differ by multi6
1=0

ples of 6' can occur at time t, then at time t+7 just the
same states are possible. The subsets of states that are
reachable at times t, t+l, ..., t+.t-l must be disjoint since

3 . Compaction using addition or

subtraction with immediate feedback
of overflow or underflow

each of them comprises

This configuration is also based on an adder that operates modulo N. But now a simple modification is introduced that avoids the loss of error information contained in
the overflow bit. The overflow from the most significant
bit position is immediately added at the least significant
bit position (in figure 1, CO is connected to ci). This
corresponds to the "end-around carry" when numbers in 1's
complement representation are added. For this accumulator, the next state becomes Sacc(t+l) =
if sacc(t)=O and r(t)=O
:sacc(t)-l+r(t)] mod(N-1) + 1 else
When the accumulator once has reached a state Sacc(t) # 0,
state 0 cannot occur again.
Theorem 2:
Let an accumulator with immediate feedback of overflow compact test responses that are statistically independent in time and have errors with values EO, ~ 1...,, ~ ~ - 1 .
Then the probability of aliasing is
0 I t I to: Pal(t) = 0

'
6'

7.6

states and, altogether,

N I 6 states can be reached. For the example, 7 = 412 = 2

leads to two disjoint subsets, each containing 16/4 = 4
states.
Aliasing occurs if the initial state s(0) = 0 is reached
again. This is possible only at every 7-th point of time.
To analyse the probability of aliasing, we consider the
Markov chain with the set of states (0, 6', 26', ..., N-6')
and the 7-step transitions introduced above. Using a number of 7-step transitions, all these states can be reached,
and then after every additional 7-step transition the same
states can be reached again. So the Markov chain is
irreducible and aperiodic. Its transition matrix is doubly

7- 1

stochastic since for every sum

7- 1

,Ee(tt-i) the successor and

1=0

for every sum . x e ( t - ~ + i the

) predecessor is determined
1=0

uniquely. It follows that the Markov chain has a limiting

distribution where all the N/6' states have the same probability. In particular, the probability of state 0 tends to
Q.E.D.
6'IN.
Theorem 1 also contains the rare case that all the errors
have the same value EO#O. This leads to 6' = gcd (0, N }
= N, and aliasing occurs periodically after N/6 steps,
Pal(t) =

N n e { 1, 2,

1 if t = n . - ,

to c t :

6'
6

lim Pal ( n . - )

where

I O else
If (among other possible responses) the error-free
response can occur (EO = 0, m > 1), we get 6 = 6'. After

382

6'

&}

else
N- 1
6 = gcd{Eo,El, ..., Em-1, N}
6' = gcd{ E I - E O , E ~ - E O ,..., Em-l-Eo, N}
0
if sacc(0)# 0
minimal time t for
which i, j < t exist with
ref(i) # 0 and rG) # 0
else

n+-

...}

6'
6

if t g {n - I n

Pal(t) = 0
~

Proof:

Hence, theorern 2 and corollary 1 also hold for compactors

with subtracters if the condition sacc(0) # 0 is replaced
by SSub(0) f :N- 1.

We begin with the case that the accumulator is initialized to sacc(0) # 0. The observed signature
sacc(t) = [ Sacc(0) - 1 +

t- 1

,z(ref(i) + e(i))] mod (N-1)

i-1

4 . Compaction using addition or

subtractioii with stored overflow or
underfflow bit

1=0

and the signature of the fault-free circuit, sacc,ef(t), differ

by N-2 at most. For the difference, we have
t-

1=0e(i)I mod W-1)

[sacc(t>- sacc,ef(t>Imod V - 1 ) = l.5

(*I

Immediate feedback of overflow can lead to increased

addition times as the overflow from the most significant
bit position must be added at the least significant bit position during tlhe sarne clock cycle. Inserting a flip-flop into
the feedback line solves this problem (see figure 3). The
overflow is temporarily stored in this flip-flop and then
added during the next clock cycle. The state of this accumulator configuration is described by zacc(t) := c(t).N+s(t)
where c(t) and s(t) are the contents of the flip-flop and the
register, respectively. At the end of the test application,
only the contents ID the register are evaluated as a signature.
test response r(t)

t- 1

Hence, aliasing occurs if and only if [.ze(i)]l mod (Pi-1)

1=0

has value 0. This is the same situation as considered in the

proof of theorem 1, and the result is obtained accordingly.
If the accumulator is initialized to Sacc(0) = 0, however,
the difference saCc(t)- sacc,ef(t) can also have the values
N-1 and -(N-1). But these values are possible only if
sa,c,eAO) =...= sacc,ef(t-l) = 0 or ~aCc(0) ...= s,cc(t- l )=~0
holds. In these situations, aliasing cannot occur. After the
first time where in the error-free case and in the presence of
errors a nonzero response occurred, the differeince s&t) sacc,,f(t) is correctly described by (*) and the ablove
QED.
argument applies.
Independent of the chosen initialization, tbe following
corollary shows which values of N are optimum.

Corollary 1:
Let an accumulator with 1's complement adder compact
test responses that are statistically independent in time and
have errors with at least two different values. Let N- 1 be
prime. Then a point of time, to, exists such that for all
t > to aliasing is possible. The limiting value of the
aliasing probability is lim pal(t) = 1/(N- 1).

Figure 3: Accumulator with stored overflow bit

In the following analysis, we first assume that in the

error-free case the sequence of test responses is not constant 0 and not constant N-1 and that the same holds in the
presence of errors. Afterwards we complete the analysis
and consider these special cases.

t+-

If N-1 is not prime, the CUT may have some fa.ults

that lead to 6 ' > 6 and thus at some times cannot cause
aliasing. Then the test length t should be chosen such that
gcd{t, N - l } = 1 holds and hence gcdlt, 8 )= 1 for all 130ssible 6'. For example, t can be chosen to be a power 'of 2
if N is a power of 2. In this way, aliasing is completely
eliminated for these faults.
In the corresponding configuration using subtraction,
the subtracter operates modulo IT and the underflow of the
most significant bit position is immediately subtracted at
the least significant bit position. This results in the next
state ssub(t+l) =

Theorem 3:
Let an accumulator with (modulo N)-adder and stored
overflow bit compact test responses that are statistically
independent in time and have errors with values EO,~ 1...,,
~ ~ -For
1 the
. error-free case and in the presence of errors,
let the sequence of test responses be different from the
constant 0 and the constant N-1 sequence. Then the probability of aliasing is
Pal(t)

if ssub(t) = N- 1 and r(t) = 0

ellse
If the compactor once has rea.ched a state different from
N-1, then state N-1 can never be reached again. The state
transition diagram of this configuration (states sSut))is
isomorphic to the state transition diagram of the corresponding accumulator (states sac,) provided that both
compactors operate on the same inputs. This can easily be
checked using the bijective mapping
g: (0, 1, ..., N-1) + (0, 1,..., N - l } ,
Sacc = g(S,ub) := N - 1 - Ssub.

{ Ei:b(t)

=:

6'
6

if t g {n.- I n e br)

- r(t)] mod (N-1)

where

6 = gc:d{EO,El, ..., Em-l,N}

6' = gC:d{El-Eo, E2-EO, ..., E,_~-Eo, N}

Proof:
If r(O)= ...=r(t-2)=0 and r(O)= ...=r(t-2)=N-l do not
hold, the accumulator cannot assume the states 0 and 2N-1
after time t-2. The accumulator considered here differs from
the accumulalor considered in the previous section by
adding the overflow bit one clock period later. So the state
zacc(t) can be cornputed in the following way. First, the

383

given ref(t-l) can actually occur). These N relevant lines

include the line c = Tef(t- 1) or the line c = Tef(t- 1)- N, but
not both. With error e(t-1) = Tef(t-l), aliasing is not
possible as we get zacc(t) = T(t-1) + ref(t-l) + e(t-1) =
s(t-1) + ref(t-l) + S e f ( t - l ) = T(t-1) + ~ ~ ~ ~ , The
~ f ( t ) .
aliasing condition Zacc(t) mod N = Zacc,ef(t)mod N would
require T(t-1) mod N = 0, and that is impossible because
of 1 I T(t- 1) I N- 1. For the same reason, also the error
s,f(t- 1) - N cannot cause aliasing. Each of the remaining
N-l relevant lines of table 1 lists exactly one of the possible differences of states, T,f(t-l) - 1, ..., TeAt-l) - (N-l),
as a necessary condition for aliasing.

responses r(O), r ( l ) , ..., r(t-2) are compacted using an

accumulator with immediate feedback of overflow which
has been initialized to
s(O)+c(O)
if zacc(0)@{0,2N-1)
:=
N-1
else
Let X(t-1) be the state of the register in figure 3 at time
t- 1 if the produced overflow c(t- 1) has already been added to
the contents of the register, T(t-1) := s(t-1) + c(t-1) =
sacc(t-l). This gives

s(t-1) = [ sacc(0) - 1 +

t-2

,xr(i)] mod(N-1) + 1
t-2

and

1=0

Sef(t-1) = [ sacc(0) - 1 + ,E reAi)] mod(N-1)

1=0

6'

Then in the final step, the last test response r(t-1) is

added to the register contents T(t-1), and the overflow is
stored in the flip-flop. So at time t we have
zacc(t) = s(t-l)+r(t-1) = T(t-l)+!r,f(t-l)+e(t-l) and
Zacc,ef(t) 1 Xef(t-1) +ref(t-l) .
Aliasing occurs if and only if
= s(t)
sedt)
= zacc(t) mod N
zacc,eAt>mod N
[TeAt-l>+r&t-l)] m o d N = [T(t-l)+ref(t-l)+e(t-l)]
mod N
[FeAt-l) - T(t-l)] mod N
= e(t-1) mod N
The probability of aliasing is pal(t) =:
P(e = c) . P ([ Tef(t-1) -F(t-l)] mod N = c mod N) .

If T = - successive errors are added, the sum is a multi-

ple of 6' (see the proof of theorem 1). For the difference of
states AS(i) = TeAi) - T(i) this means:
, :
AT(i) E { n.6' I nE Z }
For i = 0, T , ~ T ...
for i = 1 , ~ + 1..., :
Ai'(i)E {(.t-l).x6+n.6'InZ}
for i = T-1 , 2 ~1,- ... : AS(i) E { x6 + n.6' I nE Z}
If we now compare the errors e(i) = x6 + y(i)4' with the
set of state differences that are possible at different points
of time, then we see that the condition AT(i)modN =
e(i) mod N can be satisfied only for ~ - 1 , 2 2 - 1...
, Hence,
aliasing can occur only at times that are multiples of T.
Apart from an initial phase where a smaller number of
state differences is possible, at these times always the
N-1 .
same 7differences are reachable, and fort+ they have

ctE

P(e = c) denotes the constant probability that the error has

value c.
Table 1 lists all the values that can be assumed by
errors (first column) and all the differences of states,
AT = Sef - S, that together with the error value of this row
lead to aliasing at the following point of time. If two
differences AT are listed in the same row, they differ by N.
Hence, for a given state Tef only one is possible.
error value c I

N-2
N- 1
Table 1:

=
-

differences of states that lead to aliasing

-W1)
-(N-2)

-2
-1
0
1
2

equal probability (see proof of theorem 1). Regarding the

limiting value of the aliasing probability, we get
lim pal(n,T)
n+m

AX = -(N-2),

A T = -(N-2),

AT = -2,
AT = -1
AT= 0
AT= 1
AT = 2,

AX=1
AT = 2

lim

n+m

-"

N-1

6'
I N-1

P(AT(nT-1) mod N = c mod N) . P(e = c)

CEE

lim [I - P(e=Tef(nT-l)-N) - P(e=TeAn.t-l))]

n+-

Q.E.D.

It remains to analyse the special cases with all

responses equal to 0 or all responses equal to N-1. With a
test method that aims at high fault coverage, both situations cannot occur for the error-free responses. Otherwise
all the "stuck-at-1'' or all the "stuck-at-0'' faults at the
outputs of the CUT (and many other faults) could not be
detected. The response sequences of faulty circuits,
however, may be constant 0 or constant N- 1. Then at time
t = 2 at the latest, the accumulator reaches a state zoo and
afterwards does not change any more. Aliasing occurs at
time t if [Tef(t-1) + ref(t-1)] mod N = Z, mod N holds.
The errors are e(i) = -ref(i) or e(i) = N- 1-ref(i), respectively, for all i 2 0. Analysing the aliasing probability
gives almost the same result as in theorem 3. Only the
times where aliasing occurs with nonzero probability are

AT = N-2

AT = N-2
AT = -2,
AT=-1
Conditions for aliasing

Since the observed response r(t-1) must have a value

between 0 and N- 1, only errors c E { -ref(t- 1), -ref(t- 1)+ 1,
..., -ref(t-l)+N-l} can occur together with the error-free
response ref(t-1). Thus, in table 1 just N successive lines
are relevant (i.e. they include the situations that for a

384

D: MISR with primitive characteristic polynomial

x~+x4+.3+x2+1
The compactors were initialized to 0, the same response
sequences were fed to all of them, and compaction was
simulated. The sequences of error-free responses were
produced using a random number generator, and errors were
inserted according to given probabilities. In each experiment, 100000 response sequences were used. During simulation, the aliasing events were counted for each time t
separately. At time t an aliasing event occurs if errors have
appeared and1 the signature is the same as in the error-free
case. The aliasing probability was estimated by
# aliasing events at time t
= T G a t e d test response sequences
In the first experiment, the distortions of the error-free
responses could assume all possible values with equal
probability 1/256. Figure 4 shows the simulation results
for A and D, the results for B and C are almost the same.
The limiting value of 1/256 = 0.00391 (A and D) or
1/255 = 0.00392 (B and C ) is approached fast.

shifted by a constant that depends on the initialization of

the accumulator.
Obviously, those accumulators with stored overflow bit
where N-1 is a prime number are best, and corollary 1
from section 3 is valid here, too.
In the following, we consider the case 6 = 6'= 1 in mlore
detail. Then the limiting value of the aliasing probability
is lim Pal(t) =
t-+-

= lim
t+-

x P(AT(t-1) mod N

=I

ccE

c mod N) . P(e = c)

. lim [ 1 - P(e = Tef(t-l)-N) - P(e = T,f(t-l))] .

N-1
t+If it is additionally assumed that all states I , 2, ...,N- 1
occur with equal probability as tlhe error-free state Sef(t-l),
-

the expectation value of P(e = T,f(t-l)-N) + P(e = X,f(t-l))

N- 1
1
is
[P(e = s-N) + P(e = s)]
N- 1 s=l
1
Pf
- . (1 -P(e=O)) = __
N- 1
M-1 '
where pf is the probability of observing an erroneous response. Thus the limiting value of the aliasing probability
1
Pf
becomes -.
(1 - -)
. This is exactly the result that
N- 1
N- 1
Rajski and Tyszer derived in an other way [6]. The upper
bound 1/(N-l), which theorem 3 gives without restriction
to a uniform distribution, is very precise for large N. For
N > 3 we have
1
Pf
1
- 5 -.(I--)
< -- 1
w- 1
N+l
N-1
N- 1
The additional assumption of a uniform distribution for
sef, however, does not hold in general. For example, consider a circuit that multiplies the value at its inputs by 3
and produces the result at its outlputs. Here all error-free responses are multiples of 3. If the responses are compacted
using an 8-bit accumulator (N-1 = 255 = 17.3.5) initialized
to zacc(0) = 0, then Sef is always a multiple of 3.
A compactor that is based on subtraction with immediate feedback of underflow can also be modified such that
underflow is temporarily stored in a flip-flop. The state
transition diagram of this configuration is isomorphic to
the state transition diagram of the corresponding accumulator. Hence, theorem 3 and corollary 1 also hold for compactors using subtraction.

0.02

1
I

0
Figure4:

test length t

.-

100
Probability of aliasing in accumulator A and
MISR, first experiment

50

If errors occur less frequently and only few error values

are possible, the aliasing probability approaches its limiting value more slowly. The second experiment assumed
that with probability 0.2 a unidirectional "O"+" 1" error
occurred in bit position 23, and also with probability 0.2
a unidirectional " 1"+"0" error occurred in bit position 24.
The remaining responses were error-free. So the set of
error values is E =: {0,8,-16).
For accumulator A, we get 6 = gcd{O,8, -16,256) = 8
and a'= 8. Thus the aliasing probability tends to 8/256 =
0.03125 if the test length tends to infinity (see figure 5).
This limiting value is larger than in the first experiment
since the fault does not affect the three least significant
bits of the test responses. For the MISR, the limiting
value is the same as in the first experiment, it does not
depend on the values of the errors [l, 2, 51.
For accumulators B and C , we have 6 = gcd{O, 8, -16,
255) = 1, 6'=: 1, and
Pal(t) = 1/255. The aliasing probability show:$damped oscillations with a long period (see
figure 6). But already the local maximum at t = 1179 is
significantly less than the limiting value achieved without

5 . Experimental results
Four different compactors for %bit test responses were
investigated experimentally:
A: 8-bit accumulator using addition modulo 256
B: 8-bit accumulator using addition with immediate feedback of overflow
C: 8-bit accumulator using addition with stored overflow
and for comparison also

385

can occur only at times t = 4 5 , 4 8 , 5 1 , ... With respect to

these times the limiting value of the aIiasing probability
is 31255 = 0.012.

feedback of overflow. Many other experiments confirmed

that, generally, in accumulators the probability of aliasing
approaches its limiting value not as fast as in MISRs.

6 . Conclusions
Three different types of accumulators and the corresponding configurations with subtracters have been investigated regarding their compaction performance. In accumulators using addition modulo 2k, the probability of
aliasing is relatively high for all those faults that d o not
affect the low significant bits of the test responses. Accumulators with immediate feedback of overflow and accumulators with stored overflow bit do not suffer from this
problem. Their performance is best if their width k is chosen such that 2k-l is a prime number, e.g. k = 3,7, or 31.

O.l0I\
0.05
0.02

I
L

500
test length t

100

Figure 5: Probability of aliasing in accumulator A and

MISR, second experiment

Then the aliasing probability tends to - (or slightly

2k- 1
lower) for increasing test lengths. This is almost the same
limiting value as for the best compactors based on linear
feedback shift registers and additive cellular automata,
which have a limiting value of 1/2k. Even if 2k-l is not a
prime number, the limiting value of 1/(2k-l) holds for a
large number of faults. For the remaining faults, the
limiting value is a multiple of 1/(2k-1). But for some of
them, aliasing can occur only at specific times. If the test
length is chosen appropriately, e.g. a power of 2, aliasing
is completely eliminated for these faults. The probability
of aliasing in compactors using subtracters is exactly the
same as in the corresponding accumulators.

0.02

4000
test length t

1000

Probability of aliasing in accumulator B and

accumulator C, second experiment
The third experiment demonstrates a situation where
aliasing can occur only at fixed points of time. Here, the
error-free responses were generated with the restriction that
at least one of the three least significant bits should be
"0". With probability 0.1 a "0"+"1" error was inserted at
bit position 22, and with probability 0.2 two "O"+" 1
errors were inserted at bit positions 2 l and Z3, respectively. To the remaining responses, e = 1 was added
(affecting only the three least significant bit positions).
The responses were compacted by accumulator B.
Figure6:

References
[ I ] M. Damiani, P. Olivo, B. Ricc6, "Analysis and Design of

'I

[2]

[3]

r41
0.03

[5]

0.02

[6]

Linear Finite State Machines for Signature Analysis

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W. Daehn, T. W. Williams, K. D. Wagner, "Aliasing
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U. Dudley, "Elementary Number Theory", Freeman, San
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S . Gupta, J. Raiski, J. Tyszer, "Test Pattern Generation
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T. Kameda,' S: Pilarski, A. Ivanov, "Notes on Multiule
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J. Raj&, J. Tyszer, "Test Response Compaction in
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April 1993, pp. 531-539

[7] J. Rajski, J. Tyszer, "Accumulator-Based Compaction of
Test Responses", Trans. on Comp., 1993, pp. 643-650
[8] A. P. Strode, "A Self-Test Approach Using Accumulators
as Test Pattern Generators", Int. Symp. on Circuits and
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Delay Fault Testing", European Design & Test Conf.,
1995, pp. 431-435

0.01

100

200
test length t

Figure 7: Probability of aliasing in accumulator B, third

experiment

With E = { 1,4, lo}, we get 6 = gcd{ 1,4,10,255} = 1

and 6' = gcd{ 3,9,255} = 3. Figure 7 shows that aliasing

386