Manual de Laboratorio Electronica III

IC Applications Lab Manual
ECE, MRCET
MALLA REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY

Maisammaguda, Dhulapally post, via Hakimpet, Secunderabad
LABORATORY MANUAL
(IC APPLICATIONS LAB)
III B. Tech I-SEM
Department of
ELECTRONICS & COMMUNICATION ENGINEERING
ECE, MRCET
CONTENTS
S.No.
Experiment Name
Page No.
INTRODUCTION - STUDY OF IC741 & IC555
ADDER, SUBTRACTOR & COMPARATOR USING IC741 OP-
AMP
3
INTEGRATOR AND DIFFERENTIATOR USING IC741 OP-AMP
13
ACTIVE LOW PASS & HIGH PASS BUTTERWORTH FILTERS
18
(2ND ORDER)
5
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING
26
IC741 OP-AMP
6
IC555 TIMER IN MONOSTABLE OPERATION
32
SCHMITT TRIGGER CIRCUITS USING IC741 & IC555
37
FUNCTION GENERATOR USING IC741
43
D FLIP FLOPS AND MASTER SLAVE JK FLIP FLOPS
49
10
DECADE COUNTER AND UP-DOWN COUNTER
54
11
UNIVERSAL SHIFT REGISTER (74194)
61
12
4-BIT MAGNITUDE COMPARATOR
69
13
3 - 8 DECODER USING IC 74138
73
14
8 - 1 LINE MULTIPLEXER AND 2 - 4 DEMULTIPLEXER
77
15
RAM USING 74189
82
ECE, MRCET
PART - 1
ECE, MRCET
INTRODUCTION
STUDY OF IC741 & IC555
AIM: To study pin details, specifications, applications and features of IC741 (Op-Amp)
and IC555 (Timer).
COMPONENTS: IC741 & IC555
IC741: (Operational Amplifier)
Symbol:
Pin Configuration:
Specifications:
Supply Voltage
18V
Internal Power Dissipation

Differential input voltage
310mw
30V
Input Voltage
15V
Operating temperature range
0C to 70C
Applications:
Non-inverting amplifier
Inverting amplifier
Integrator
Differentiator
Low Pass, High Pass, Band pass and Band Reject Filters
ECE, MRCET
Features:
No External frequency compensation is required
Short circuit Protection
Off Set Null Capability
Large Common mode and differential Voltage ranges
Low Power Dissipation
No-Latch up Problem
741 is available in three packages: 8-pin metal can, 10-pin flat pack and 8 or 14-pin DIP
IC555: (Timer)
Pin Configuration:
Functional block diagram:
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Specifications:
Supply Voltage
Maximum Current rating
5V to 18V
200mA
Minimum Triggering Voltage

Operating temperature range
- (1/3) VCC
0C to 70C
Applications:
1. Astable Multivibrator, Schmitt trigger, Free running ramp Generator, etc.,
2. Monostable Multivibrator, Frequency divider, Pulse structure
Features:
555 timers are reliable, easy to use and low cost. The device is available as an 8 pin circular
style, an 8pin mini DIP or a 14 Pin DIP
QUESTIONS:
1. What is the symbol of op-amp?
2. Draw the pin diagram of op-amp.
3. What is the supply voltage range that an op-amp can with stand?
4. What is the input voltage range that an op-amp can with stand?
5. What are the available package types of IC741?
6. What is a virtual ground? What are the differences between the physical ground and
the virtual ground?
7. What is the current flowing through the input terminals of an Ideal op-amp?
8. Which loop voltage gain is larger, closed or open?
9. What is the normal value of saturation voltage of an op-amp?
10. Mention a few applications of op-amp.
11. Mention some features of op-amp.
12. What is the main purpose of IC555 timer?
13. Draw the pin diagram of op-amp.
14. Draw the functional diagram of IC555 timer.
15. How many comparators are present in IC555 timer?
16. What are the trigger voltages of UC and LC?
17. What is the functionality of power amplifier in the output stage of IC555 timer?
18. Which is the Flip-Flop used in IC555 timer?
19. What is the use of RESET pin in IC555 timer?
20. What are the available package types of IC555 timer?
21. Mention a few applications of IC555 timer.
22. What is the dc level required for the negative going trigger pulse at pin 2 of IC555
timer?
ECE, MRCET
EXPERIMENT NO: 1
DATE:
ADDER, SUBTRACTOR & COMPARATOR USING IC741 OP-AMP
AIM: To study Adder, Subtractor & Comparator circuits using OP-AMP IC741 and verify
their theoretical and practical output.
APPARATUS:
Bread Board
IC741, Resistors
DC Supply
Function Generator
Multi meter
CRO
Probes, Connecting Wires
THEORY:
Adder: Op-amp can be used to design a circuit whose output is the sum of several input
signals. Such a circuit is called a summing amplifier or an adder. Summing amplifier can
be classified as inverting & non-inverting summer depending on the input applied to
inverting & non-inverting terminals respectively. Circuit Diagram shows a non-inverting
adder with n inputs. Here the output will be the linear summation of input voltages. The
circuit can be used either as summing amplifier, scaling amplifier, or as averaging
amplifier.
From the circuit of adder, it can be noted that at pin3
I1+I2+I3+.In=0
+
=0
=0
V a=
Vo
Va
Vo
Vo = (1+
)
)(
ECE, MRCET
= (1+ (n-1)) (
=n (
)
)
Vo= V1+V2+V3++Vn
This means that the output voltage is equal to the sum of all the input voltages.
Subtractor: A subtractor is a circuit that gives the difference of the two inputs, Vo =V2-V1,
Where V1 and V2 are the inputs. By connecting one input voltage V1 to inverting terminal
and another input voltage V2 to the non inverting terminal, we get the resulting circuit as
the Subtractor. This is also called as differential or difference amplifier using op-amps.
Output of a differential amplifier (subtractor) is given as
Vo = (-Rf/R1) (V1-V2)
If all external resistors are equal in value, then the gain of the amplifier is equal to -1. The
output voltage of the differential amplifier with a gain of -1 is
Vo = (V2-V1)
Thus the output voltage Vo is equal to the voltage V2 applied to the non inverting
terminal minus the voltage V1 applied to the inverting terminal. Hence the circuit is called a
Subtractor.
Comparator: A Comparator is a non-linear signal processor. It is an open loop mode
application of Op-amp operated in saturation mode. Comparator compares a signal voltage
at one input with a reference voltage at the other input. Here the Op-amp is operated in
open loop mode and hence the output is Vsat. It is basically classified as inverting and
non-inverting comparator. In a non-inverting comparator Vin is given to +ve terminal and
Vref to ve terminal. When Vin < Vref, the output is Vsat and when Vin > Vref, the output is
+Vsat (see expected waveforms). In an inverting comparator input is given to the inverting
terminal and reference voltage is given to the non inverting terminal. The output of the
inverting comparator is the inverse of the output of non-inverting comparator. The
comparator can be used as a zero crossing detector, window detector, time marker
generator and phase meter.
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CIRCUIT DIAGRAM:
Adder:
Subtractor:
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Comparator:
PROCEDURE:
Adder:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply dc voltages at each input terminal for V1 and V2 from the dc supply and
check the output voltage Vo at the output terminal.
4. Tabulate 3 different sets of readings by repeating the above step.
5. Compare practical Vo with the theoretical output voltage Vo =V1+V2.
Subtractor:
3. Apply dc voltages at each input terminal for V1 and V2 from the dc supply and
check the output voltage Vo at the output terminal.
4. Tabulate 3 different sets of readings by repeating the above step.
5. Compare practical Vo with the theoretical output voltage Vo =V2-V1.
Comparator:
3. Apply 1 KHz sine wave with 5 Vpp at the non-inverting input terminal of IC741
using a function generator.
4. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
5. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
6. Observe the input sinusoidal signal at channel-1 and the corresponding output
square wave at channel-2 of CRO. Note down their amplitude and time period.
7. Overlap both the input and output waves and note down voltages at positions on
sine wave where the output changes its state. These voltages denote the Reference
voltage.
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8. Plot the output square wave corresponding to the sine input with Vref = 1V.
TABLE:
Adder:
S.No. V1
Volts
V2
Volts
Theoretical
Vo=V1+V2
Practical Vo
Volts
Subtractor:
S.No. V1
Volts
V2
Volts
Theoretical
Vo=V2-V1
Practical Vo
Volts
Comparator:
Theoretical Reference voltage (from
circuit)
Practical Reference voltage (from output
waveforms)
EXPECTED WAVEFORMS:
COMPARATOR INPUT & OUTPUT WAVEFORMS
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RESULT:
QUESTIONS:
1. Draw the circuit diagram of 3 input adder.
2. What is the other name for adder?
3. Draw the circuit diagram of a Subtractor.
4. Which amplifier acts as a Subtractor?
5. How many basic input parameters are required for a comparator?
6. Draw the circuit diagram of a non-inverting comparator and inverting comparator.
7. What is the output of a non-inverting comparator and inverting comparator if the
input is sinusoidal?
8. What are the differences between the Inverting and NonInverting comparator?
9. What is the name of the comparator if the reference voltage is 0V?
10. Draw the circuit diagram and the output waveform of a Zero Crossing Detector if
the input is sinusoidal?
11. What is the name of a regenerative comparator?
12. Draw an op- amp circuit whose output Vo is V1+ V2 V3 V4.
12
ECE, MRCET
EXPERIMENT NO: 2
DATE:
INTEGRATOR AND DIFFERENTIATOR USING IC741 OP-AMP
AIM: To study the operation of the Integrator & differentiator using op-amp and trace the
output wave forms for sine and square wave inputs.
APPARATUS:
Bread Board
IC741, Resistors, Capacitors
Function Generator
CRO
Probes
Connecting wires
THEORY:
Integrator:
A circuit in which the output voltage is the integration of the input voltage is called
an integrator.
In the practical integrator to reduce the error voltage at the output, a resistor R F is
connected across the feedback capacitor CF. Thus, RF limits the low-frequency gain and
hence minimizes the variations in the output voltage.
The frequency response of the integrator is shown in the fig. 2.1. fb is the frequency
at which the gain is 0 dB and is given by
fb = 1/2 R1Cf.
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ECE, MRCET
In this fig. there is some relative operating frequency, and for frequencies from f to
fa the gain RF/R1 is constant. However, after fa the gain decreases at a rate of 20 dB/decade.
In other words, between fa and fb the circuit of fig. 2.1 acts as an integrator. The gainlimiting frequency fa is given by
fa = 1/2 RfCf.
Normally fa<fb. From the above equation, we can calculate Rf by assuming fa & Cf.
This is very important frequency. It tells us where the useful integration range starts.
If fin < fa
If fin = fa
If fin = 10fa
- circuit acts like a simple inverting amplifier and no integration results,

- integration takes place with only 50% accuracy results,
- integration takes place with 99% accuracy results.
In the circuit diagram of Integrator, the values are calculated by assuming fa as 50

Hz. Hence the input frequency is to be taken as 500Hz to get 99% accuracy results.
Integrator has wide applications in
1. Analog computers used for solving differential equations in simulation arrangements.
2. A/D Converters
3. Signal wave shaping
4. Function Generators.
Differentiator:
As the name suggests, the circuit performs the mathematical operation of
differentiation, i.e. the output voltage is the derivative of the input voltage.
dVin
Vo = - Rf C1
dt
Both the stability and the high-frequency noise problems can be corrected by the
addition of two components: R1 and Cf, as shown in the circuit diagram. This circuit is a
practical differentiator.
The input signal will be differentiated properly if the time period T of the input
signal is larger than or equal to RfC1. That is, T>= RfC1
Differentiator can be designed by implementing the following steps.
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Then, assuming a value of C1<1 F, calculate the value of Rf
2. Calculate the values of R1and Cf so that R1C1=RfCf.
Differentiator has wide applications in
1. Monostable Multivibrator
2. Signal wave shaping
3. Function Generators.
14
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CIRCUIT DIAGRAM:
Integrator:
Differentiator:
15
ECE, MRCET
PROCEDURE:
Integrator:
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the output
terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase
shifted from the sine wave input) and note down the position, the amplitude and the
time period of Vin & Vo.
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a triangular wave and note
down the position, the amplitude and the time period of Vin & Vo.
8. Plot the output voltages corresponding to sine and square wave inputs.
Differentiator:
3. Apply sine wave at the input terminals of the circuit using function Generator.
4. Connect channel-1 of CRO at the input terminals and channel-2 at the output
terminals.
5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase
shifted from the sine wave input) and note down the position, the amplitude and the
time period of Vin & Vo.
6. Now apply the square wave as input signal.
7. Observe the output of the circuit on the CRO which is a spike wave and note down
the position, the amplitude and the time period of Vin & Vo.
8. Plot the output voltages corresponding to sine and square wave inputs.
EXPECTED WAVEFORMS:
16
ECE, MRCET
Differentiator:
RESULT:
QUESTIONS:
1. What is an Integrator?
2. Draw the circuit of the Integrator using op-amp IC741.
3. Write down the expression for Vo of an Integrator.
4. Draw the frequency response of the Integrator and explain.
5. Draw the output waveform of the Integrator when the input is a Square wave.
6. What is the purpose behind the connection of Rf in the feedback path of Integrator?
7. What are the applications of Integrator?
8. Why Rcomp is used in both Integrator and Differentiator circuits?
9. What is a Differentiator?
10. Draw the circuit of the Differentiator using op-amp IC741.
11. Write down the expression for Vo of a Differentiator.
12. Draw the output waveform of the Differentiator when the input is a Sine wave.
13. Why R1 and Cf are connected in the circuit of the Differentiator?
14. What are the applications of Differentiator?
17
ECE, MRCET
EXPERIMENT NO: 3
DATE:
ACTIVE LOW PASS & HIGH PASS BUTTERWORTH FILTERS (2ND ORDER)
a) 2nd Order LOW PASS FILTER
AIM: To plot the frequency response of Butterworth LPF (Second order) and find the high
cut-off frequency.
APPARATUS:
Bread Board
Function Generator
CRO
Probes
Connecting Wires
741 Op-amp, Resistors, Capacitors
THEORY:
Filters are classified as follows:
Based on components used in the circuit
Active filters Use active elements like transistor or op-amp(provides gain)
in addition to passive elements
Passive filters Use only passive elements like resistors, capacitors and
inductors, hence no gain here.
Based on frequency range
Low pass filter(LPF) Allows low frequencies
High pass filter(HPF) Allows high frequencies
Band pass filter(BPF) Allows band of frequencies
Band reject filter(BRF) Rejects band of frequencies
All pass filter Allows all frequencies but with a phase shift
Active Filter is often a frequency selective circuit that passes a specified band of
frequencies and blocks or attenuates signals of frequencies outside this band.
These Active Filters are most extensively used in the field of communications and
signal processing. They are employed in one form or another in almost all sophisticated
electronic systems such as Radio, Television, Telephone, Radar, Space Satellites, and BioMedical Equipment.
Active Filters employ transistors or Op Amps in addition to that of resistors and
capacitors. Active filters have the following advantages over passive filters. (1) Flexible
gain and frequency adjustment. (2) No loading problem (because of high input impedance
and low output impedance) and (3) Active filters are more economical than passive filters.
A Second Order Low Pass Butterworth filter uses RC networks for filtering.
Note that the op-amp is used in the non-inverting configuration; hence it does not load
down the RC network. Resistors R1 and RF determine the gain of the filter.
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The gain magnitude equation of the Low Pass filter can be obtained by converting
equation into its equivalent polar form, as follows.
| Vo / Vin |
= AF/1+ (f / fH) 4
where
1
fH = -------------------- = high cut-off frequency of the filter.
2 R2R3C2C3
The operation of the low pass filter can be verified from the gain magnitude
equation.
1. At very low frequencies, that is f < fH
| Vo/Vin |
= AF
2. At f = fH, | Vo/Vin |
= AF/2 = 0.707 AF
3. At f > fH
< AF
| Vo/Vin |
Thus the Low Pass filter has a constant gain AF from 0 Hz to the almost high
cut-off frequency, fH, it has the gain 0.707AF at exactly fH, and after fH it decreases at a
constant rate with an increase in frequency. The gain decreases 40 dB (= 20 log 102) each
time the frequency is increased by 10. Hence the rate at which the gain rolls off after fH is
40 dB/decade. The frequency f = fH is called the cut-off frequency because the gain of the
filter at this frequency is down by 3 dB (=20log 0.707) from 0 Hz. Other equivalent terms
for cut-off frequency are -3dB frequency, break frequency, or corner frequency.
DESIGN:
1. Choose a value for the high cut-off frequency, fH(1 KHz)
2. To simplify the design calculations, set R2=R3=R and C2=C3=C. Then choose a
value of C 1F(0.0047 F)
3. Calculate the value of R using the equation

4. Finally, because of the equal resistor (R2=R3) and capacitor (C2=C3) values, the pass
band voltage gain AF = (1+ ) of the second-order low-pass filter has to be equal to
1.586. That is, Rf = 0.586R1. This gain is necessary to generate Butterworth
response. Hence choose a value of R1 100K (33 K) and calculate the value of
Rf.
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CIRCUIT DIAGRAM:
PROCEDURE:
3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output
terminals (Vo).
4. Set Vin = 1V & fin=10Hz using function generator.
5. By varying the input frequency in regular intervals, note down the output voltage.
6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.
7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Yaxis) using Semi log Graph.
8. Find out the high cut-off frequency, fH (at Gain= Constant Gain, Af 3 dB) from
the frequency response plotted.
9. Verify the practical (fH from graph) and the calculated theoretical cut-off frequency
(fH = 1/2RC ).
20
TABLE:
Vin = 1V
S.No. Input Frequency
f(Hz)
ECE, MRCET
Output Voltage
Vo (V)
Gain Magnitude Gain in dB =

| Vo/Vin |
20log| Vo/Vin |
CALCULATIONS:
THEORETICAL Cut-off frequency:
fH = 1 / (2RC) = high cut-off frequency of the Low pass filter.
=
PRACTICAL Cut-off frequency (from Graph) :
fH = high cut-off frequency of the Low pass filter
= 3dB cut-off frequency
=
EXPECTED GRAPH:
RESULT:
21
ECE, MRCET
ACTIVE LOW PASS & HIGH PASS BUTTERWORTH FILTERS (2ND ORDER)
b) 2nd Order HIGH PASS FILTER
AIM: To plot the frequency response of Butterworth HPF (Second order) and find the low
cut-off frequency.
APPARATUS:
Bread Board
Function Generator
CRO
Probes
Connecting Wires
THEORY:
Second Order High Pass Filter consists of RC networks for filtering. Second Order
High Pass filter can be constructed from a Second Order Low Pass filter simply by
interchanging frequency determining components R & C . Op-Amp is used in the non
inverting configuration. Resistor R1 and RF determine the gain of the Filter.
The voltage gain magnitude equation of the second order High-pass filter is
V0
AF
----- = ---------------Vin
[1+(fL/f)4]
where f = Operating (input) frequency.
1
fL = -------------------- = Low cut-off frequency of the filter.
2R2R3C2C3
This is the frequency at which the magnitude of the gain is 0.707 times its pass band
value. Obviously, all frequencies higher than fL are Pass Band frequencies, with the highest
frequency determined by the closed-loop bandwidth of the OP-Amp.
The operation of the highpass filter can be verified from the gain magnitude
equation.
1. At very low frequencies, that is f < fL
| Vo/Vin |
< AF
2. At f = fL, | Vo/Vin |
= AF/2 = 0.707 AF
3. At f > fL,
= AF
| Vo/Vin |
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For example, in the first order High Pass filter the gain rolls off or increases at
the rate of 20dB/decade in stop band, that is for input signal frequency lesser than Low
cut-off frequency (fL ) ; For Second Order High Pass filter the rolloff rate is 40dB /
decade.
High Pass filter has constant gain AF, after the Low cut-off frequency onwards (fL).
DESIGN: Follow the same procedure as given for low-pass filter.
CIRCUIT DIAGRAM:
PROCEDURE:
3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output
terminals (Vo).
4. Set Vin = 1V & fin=10Hz using function generator.
5. By varying the input frequency in regular intervals, note down the output voltage.
6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log(Vo/Vin) at every frequency.
7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Yaxis) using Semi log Graph.
8. Find out the low cut-off frequency, fL (at Gain= Constant Gain, Af 3 dB) from the
frequency response plotted.
9. Verify the practical (fL from graph) and the calculated theoretical cut-off frequency
(fL = 1/2RC).
23
TABLE:
Vin = 1V
S.No. Input Frequency
f(Hz)
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Output Voltage
Vo (V)
Gain Magnitude Gain in dB =

| Vo/Vin |
20log| Vo/Vin |
CALCULATIONS:
THEORETICAL Cut-off frequency:
fL = 1 / (2RC) = Low cut-off frequency of the HPF.
=
PRACTICAL Cut-off frequency:
fL = Low cut-off frequency of the HPF.
= 3dB cut-off frequency
=
EXPECTED GRAPH:
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RESULT:
QUESTIONS:
1. How filters are classified? Give one example for each classification.
2. What is an active filter and why it is called so?
3. How an active filter differs from a passive filter?
4. What are the advantages of active filters over passive filters?
5. Draw the circuit diagrams of active filters LPF and HPF.
6. Draw the frequency response of all filters (LPF, HPF, BPF, BRF and All-pass).
7. What is the gain roll off rate for a 1st order and 2nd order filter?
8. What is the formula for cut-off frequency?
9. What is a 3 dB frequency and why it is called so?
10. What are the other names for 3 dB frequency?
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EXPERIMENT NO: 4
DATE:
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC741 OP-AMP
a) RC Phase Shift Oscillator

AIM: To design an RC Phase Shift Oscillator and compare its theoretical and practical
frequency of oscillation.
APPARATUS:
Bread Board
CRO
Probes
Connecting wires
THEORY:
Oscillator is a circuit which generates output without any input. Oscillator can be
defined as a device that converts dc to ac.
Oscillators can be classified as:
Based on the components used:
RC Oscillators - RC Phase shift, Wien Bridge Oscillator
LC Oscillators - Colpitts, Hartley, Clapp Oscillator
Crystal Oscillators
Based on the type of waveform:
Sinusoidal Oscillators RC Phase shift, Wien Bridge, Colpitts, Hartley.
Non-Sinusoidal Oscillators- UJT relaxation Oscillators
Based on frequency range:
Audio frequency oscillator RC oscillators
Radio frequency oscillator LC oscillators
Barkhausens criterion for oscillations:
1) For sustained oscillations the phase shift around the circuit( amplifier and
feedback circuit) should be 360o or 0o.
2) The magnitude of the loop gain of the oscillator should be greater than or equal
to 1.
A Phase shift oscillator consists of an Op-Amp as the amplifying stage and three
RC cascaded networks as the feedback circuit. The feedback circuit provides feedback
voltage from the output back to the input of the amplifier. The Op-Amp is used in the
inverting mode, therefore any signal that appears at the inverting terminal is shifted by 180o
at the output. An additional 180o phase shift required for oscillation is provided by the 3
RC sections each section providing a Phase shift of 60o. Thus the total phase shift around
the loop is 360o (or 0o). At some specific frequency when the phase shift of the cascaded
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RC sections is exactly 180o and the gain of the amplifier is sufficiently large, the circuit
will oscillate. This frequency is called the frequency of oscillation fo and is given by
fo = 1/2RC6 = 0.065/ RC
At this frequency, the magnitude of gain Av must be at least 29
i.e., Rf/R1 = 29.
Thus the circuit will produce a sinusoidal waveform of frequency fo if the gain is 29 and the
total Phase shift around the circuit is exactly 360o or 0o.
DESIGN:
1. Choose a desired frequency of oscillation, say fo=200 Hz.
2. Choose a value for capacitor C (0.1 F) and then calculate the value of R by using
the equation for fo.
3. Find out the values of Rf & R1 as per the required gain which is at least 29. To
prevent the loading of the amplifier because of RC networks, it is necessary that
R1 >= 10R. Hence choose R1=10R and then calculate the value of Rf from gain
equation. (Note: In practical, the value of Rf may need to be varied to be more than
the calculated value.)
CIRCUIT DIAGRAM:
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PROCEDURE:
3. Connect the output of the circuit to CRO through probes.
4. Adjust the potentiometer to get the accurate sinusoidal waveform on CRO.
5. Calculate the practical frequency of oscillation fo = 1/T by observing the time
period of the output sinusoidal waveform on the CRO and compare it with
theoretical frequency of oscillation fo = 1/2RC6
6. Sketch the output waveform by noting the time period and peak to peak voltage of
the output waveform.
TABLE:
Theoretical frequency
fo= 1/2RC6
Practical frequency
fo = 1/T
EXPECTED WAVEFORM:
RESULT:
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RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC741 OP-AMP
b) Wien Bridge Oscillator

AIM: To design a Wien Bridge Oscillator and compare its theoretical and practical
frequency of oscillation.
Wien
APPARATUS:
Bread Board.
CRO
Probes
Connecting wires
THEORY:
Because of its simplicity and stability, one of the most commonly used audiofrequency oscillators is the Wien Bridge. The circuit diagram shows the Wien Bridge
oscillator in which the Wien Bridge circuit is connected between the amplifier input
terminals and output terminal. The bridge has a series RC network in one arm and a parallel
RC network in the adjoining arm. In the remaining two arms of the bridge, resistors R1 &
Rf are connected.
The feedback signal in this circuit is connected to the non-inverting terminal,
therefore the Op-Amp is working in non-inverting mode. Hence this amplifier doesnt
provide any phase shift. Therefore the feedback network need not provide any phase shift.
The condition of zero Phase shift around the circuit is achieved by balancing the bridge.
When the bridge is balanced, the frequency of oscillation fo is exactly the resonant
frequency which is given by the equation
fo = 1/2RC = 0.159/RC
At this frequency the gain Av required for sustained oscillation is 3(practically it is more).
i.e.
Av = 1+Rf/R1 = 3.
DESIGN:
1. Choose a desired frequency of oscillation, say fo =500 Hz.
the equation for fo.
3. Choose a value for R1 (10 K) and calculate the value of Rf from the gain equation.
(Note: In practical, the value of Rf may need to be varied to be more than the
calculated value.)
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ECE, MRCET
CIRCUIT DIAGRAM:
PROCEDURE:
3. Connect the output of the circuit to CRO through probes.
4. Adjust the potentiometer to get the accurate sinusoidal waveform on CRO.
5. Calculate the practical frequency of oscillation fo = 1/T by observing the time
period of the output sinusoidal waveform on the CRO and compare it with
theoretical frequency of oscillation fo = 1/2RC
6. Sketch the output waveform by noting the time period and peak to peak voltage of
the output waveform.
TABLE:
Theoretical frequency
fo= 1/2RC
Practical frequency
fo = 1/T
EXPECTED WAVEFORMS:
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ECE, MRCET
RESULT:
QUESTIONS:
1. Why is potentiometer used in the circuit of RC Phase Shift Oscillator and Wien
Bridge Oscillator?
2. How oscillators are classified? Give one example for each classification.
3. What is Barkhausens criterion?
4. What is the phase shift provided by RC networks in RC Phase Shift Oscillator?
5. What is the minimum gain required at frequency of oscillations in RC Phase Shift
Oscillator and Wien Bridge Oscillator?
6. What is the formula for frequency of oscillations in RC Phase Shift Oscillator and
Wien Bridge Oscillator?
7. How do you vary the gain of the oscillator?
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EXPERIMENT NO: 5
DATE
IC555 TIMER IN MONOSTABLE OPERATION

AIM: To design a Monostable Multivibrator using IC555 and compare its theoretical and
practical pulse width.
APPARATUS: Bread Board.
CRO
Probes
Connecting wires
555 Timer, Resistors, Capacitors
THEORY:
Monostable multivibrator is also called as oneshot Multivibrator. When the output
is low, the circuit is in stable state, transistor T1 is ON and Capacitor C is shorted to the
ground. However, upon application of a negative trigger pulse to Pin2, transistor T1 is
turned OFF, which releases short circuit across the external capacitor and drives the output
High. The capacitor C now starts charging up toward VCC through R. However when the
voltage across the external capacitor equals 2/3 VCC, upper comparators output switches
from low to high which in turn derives the output to its low state. And the output of the flip
flop turns transistor T1 ON, and hence the capacitor C rapidly discharges through the
transistor. The output of the Monostable remains low until a trigger pulse is again applied.
Then the cycle repeats. The time during which the output remains high is given by
tp = 1.1 R C
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Waveforms for IC555 Monostable Multivibrator
Once triggered, the circuits output will remain in the high state until the set time t p
elapses. The output will not change its state even if an input trigger is applied again during
this time interval tp.
DESIGN:
1. Choose a desired pulse width, say tp =1.1 ms.
the equation for tp.
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CIRCUIT DIAGRAM:
Note: Either one of the above trigger circuits can be used to give trigger to the Pin 2.
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PROCEDURE:
3. Connect function generator at the trigger input.
4. Connect channel-1 of CRO to the trigger input and channel-2 of CRO to the output
(Pin 3).
5. Using Function Generator, apply 1 KHz square wave with amplitude of approx.
equal to 9 Vpp at the trigger input.
6. Observe the output voltage with respect to input and note down the pulse width and
amplitude.
7. Now connect channel-2 of CRO across capacitor and observe the voltage across the
capacitor and note it down.
8. Compare the practical pulse width noted in the step above with its theoretical value
(tp=1.1 RC)
CALCULATIONS:
THEORETICAL Pulse width
R=
C=
tp = 1.1 RC =
PRACTICAL Pulse width
tp =
EXPECTED WAVEFORMS:
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RESULT:
QUESTIONS:
1. What is the other name for monostable multivibrator (MSMV)?
2. When MSMV is in stable state, what is the output level?
3. Why trigger is required in the case of MSMV?
4. Which type of trigger pulse is required for MSMV?
5. What is the formula for the output pulse width of MSMV?
6. How long MSMV stays in unstable state?
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ECE, MRCET
EXPERIMENT NO: 6
DATE
a) SCHMITT TRIGGER CIRCUIT - USING IC741

AIM: To study the Schmitt trigger characteristics by using IC741 and compare theoretical
and practical values of the Upper Threshold voltage, VUT and the Lower Threshold voltage,
VLT.
APPARATUS:
741 Op-Amp
Resistors
Bread board
Function generator
CRO
Probes
Connecting wires
THEORY:
Circuit shows an inverting comparator with positive feedback. This circuit converts
an irregular shaped waveform to square wave or pulse. This circuit is known as Schmitt
trigger or Regenerative comparator or Squaring circuit. The input voltage Vin triggers
(changes the state of ) the output Vo every time it exceeds certain voltage levels called
Upper threshold voltage, VUT and Lower threshold voltage, VLT. The hysteresis width is the
difference between these two threshold voltages i.e. VUT VLT. These threshold voltages
are calculated as follows.
VUT = (R1/R1+R2) Vsat
when Vo= Vsat
VLT = (R1/R1+R2) (-Vsat)
when Vo= -Vsat
The output of Schmitt trigger is a square wave when the input is sine wave or triangular
wave, where as if the input is a saw tooth wave then the output is a pulse wave.
CIRCUIT DIAGRAM:
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PROCEDURE:
3. Apply the input sine wave using function generator.
4. Connect the channel1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down voltages at positions on
sine wave where output changes its state. These voltages denote the Upper
threshold voltage and the Lower threshold voltage (see EXPECTED
WAVEFORMS below).
7. Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas given in the THEORY section above.
8. Sketch the waveforms by noting down the amplitude and the time period of the
input Vin and the output Vo.
EXPECTED WAVEFORMS:
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TABLE:
RESULT:
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b) SCHMITT TRIGGER CIRCUIT - USING IC555

AIM: To study the Schmitt trigger characteristics by using IC555 and compare theoretical
and practical values of the Upper Threshold voltage, VUT and the Lower Threshold voltage,
VLT.
APPARATUS:
Bread Board
Function Generator
CRO
Probes
Connecting wires
555 Timer, Resistors, Capacitors
THEORY:
555 timer can be used as Schmitt trigger. Here two internal comparators are tied
together and externally biased at VCC/2 through R1 & R2. Since the upper comparator will
trip at (2/3) VCC and the lower comparator at (1/3) VCC the bias provided by R1 & R2 is
centered within these two thresholds. Thus a sine wave of sufficient amplitude (> VCC /6 =
2/3 VCC VCC/2) to exceed the reference levels causes the internal flipflop to alternately
set and reset providing a square wave output.
CIRCUIT DIAGRAM:
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PROCEDURE:
3. Apply the input sine wave using function generator.
4. Connect the channel1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down positions on sine wave
where output changes its state. These positions denote the Upper threshold voltage
and the Lower threshold voltage (see EXPECTED WAVEFORMS below).
7. Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas given in the THEORY section above.
8. Sketch the waveforms by noting down the amplitude and the time period of the
input Vin and the output Vo.
EXPECTED WAVEFORMS:
RESULT:
QUESTIONS:
1. Which is type of comparator called Schmitt trigger using IC741?
2. What is the output wave of Schmitt trigger if the input is sine wave?
3. What type of waveform is obtained when triangular or ramp waveforms are applied
to Schmitt trigger circuit?
4. Explain how a square wave is obtained at the output of timer when sine wave input
is given?
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5. What is the Threshold voltage?

6. How do you calculate the theoretical values of VUT and VLT in the case of IC741
and IC555?
7. What is the Hysteresis width?
8. What is the minimum amplitude of the input sine wave in the case of Schmitt
trigger using IC741?
9. What is the minimum amplitude of the input sine wave in the case of Schmitt
trigger using IC555?
10. Why do we short pin 2 and pin 6 of IC555 timer for Schmitt trigger operation?
11. Why do we connect pin 4 of IC555 timer to Vcc?
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EXPERIMENT NO: 7
DATE
FUNCTION GENERATOR USING IC741
AIM: To design a Function Generator which generates Sine, Square and Triangular
waveforms using IC741 and to verify its various output waveforms.
APPARATUS:
Bread Board
CRO
Probes
THEORY:
Function generator using IC741 is a circuit which generates Sine wave, Square
wave and Triangular wave. This circuit is a combination of Wien Bridge oscillator, Zero
crossing detector (Comparator with zero reference voltage) and Integrator. The Wien
Bridge oscillator generates Sine wave which is fed to the input of Zero crossing detector.
This detector gives the square wave output which is connected to the input of the Integrator
which in turn produces the Triangular wave output.
The frequency of oscillations of the Sine wave output of Wien Bridge oscillator is
given by
fo = 1/2RC
The frequency of oscillations of Square and Triangular wave outputs will also be
the same frequency as that of the Sine wave output.
For theory of individual circuits i.e. Wien Bridge oscillator, Zero Crossing Detector
and Integrator, please refer to the THEORY section of respective experiments mentioned
earlier in this manual.
DESIGN for Wien Bridge Oscillator:
1. Choose a desired frequency of oscillation, say fo =500 Hz.
the equation for fo (fo = 1/2RC).
3. Choose a value for R1 (10 K) and calculate the value of Rf from the gain equation
(Av = 1+Rf/R1 = 3). (Note: In practical, the value of Rf may need to be varied to be
more than the calculated value.)
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CIRCUIT DIAGRAM:
Sine Wave Generator (Wien Bridge Oscillator):
Square Wave Generator (Zero Crossing Detector):
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Triangular Wave Generator (Integrator):
PROCEDURE:
Sine wave Generator:
3. Connect output to the CRO.
4. Adjust the potentiometer to get an undistorted waveform.
5. Note down the amplitude and the time period, T of the sine wave and calculate the
frequency of oscillation, fo = 1 / T.
6. Verify the practical frequency of oscillation calculated in the preceding step with
the theoretical value, fo =1/2RC.
7. Plot the waveform.
Square wave Generator:
1. Switch OFF the power supply.
4. Connect the input to the channel-1 of CRO and output to the channel-2 of CRO.
5. Observe the square wave output at channel-2 and note down the amplitude and time
period, T of the wave form.
6. Verify that the frequency of oscillation of both the input and the output waves is
same. Also verify that both the input and the output waves are in same phase.
7. Plot the output waveform in accordance with the input waveform.
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Triangular wave Generator:

1.
2.
3.
4.
5.
Switch OFF the power supply.

Connect the components/equipment as shown in the circuit diagram.
Switch ON the power supply.
Connect the input to the channel-1 of CRO and output to the channel-2 of CRO.
Observe the triangular wave output at channel-2 and note down the amplitude and
time period, T of the wave form.
6. Verify that the frequency of oscillation of both the input and the output waves is
same. Also verify that the output wave is inverted i.e. 180o phase shift from the
input wave.
7. Plot the output waveform in accordance with the input waveform.
CALCULATIONS:
THEORETICAL Frequency of Oscillation
fo =1/2RC
=
PRACTICAL Frequency of Oscillation
fo = 1/T
=
EXPECTED WAVEFORMS:
RESULT:
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QUESTIONS:
1. What is a Function Generator?
2. What are the different stages in a Function Generator and how they are connected?
3. Draw the output waveforms at different stages of Function Generator.
4. What is the relationship among the frequencies of output waveforms at different
stages of Function Generator?
5. Will there be any phase shift between the input and the output of any stage in the
Function Generator and what factor it depends on?
6. Why is Rcomp used in the circuit of Triangular wave generator?
7. Why is potentiometer used in the circuit of Wien Bridge Oscillator?
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PART-2
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EXPERIMENT NO: 8
DATE:
D FLIP FLOPS AND MASTER SLAVE JK FLIP FLOPS

AIM
To study the D Flip Flops using IC7474 and Master Slave JK Flip Flops using
IC7473.
APPARATUS
1. D Flip flops using 7474 and Master Slave JK Flip flops using 7473 trainer kit
2. Adapter (+5V @ 500 mA)
3. Set of Patch chords
THEORY
Electronic Counters find applications in many areas like A / D conversion,
Frequency Measurement, Scaling, Digital Computers, Waveform Generation etc. A counter
that count pulses from 0 to (n - 1) and then reset itself to 0 is called a modulo - n counter.
Thus a modulo - 8 counter counts the sequence 0, 1, 2, 3 ..................7 and then resets to
zero on the arrival of 8th pulse. A counter that counts BCD code sequence from 0 to 9, and
resets to zero after the arrival of 10th pulse in BCD counter. All counters invariably use
Flip Flops as building blocks. Though all Flip Flops like RS, D and T can be used for this
purpose.
Another important application of Flip Flops is shift register. Shift Registers are used
as storage elements, delay elements and shifting elements.
The flip-flop is one of the most versatile building blocks of digital computer
systems. The output of a flip- flop changes its state when driven by a trigger pulse. The
flip-flop can be used as a memory cell since it holds the information until the arrival of the
next trigger pulse at the input.
The flip-flops which find wide applications are:
1) D flip - flop
2) Master Slave JK flip-flop
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D- FLIP FLOP
This is essentially a one bit delay circuit. This is ideally started as a temporary store
for binary information. The D - flip flop can be realized from JK flip flop as shown in Fig 1.
IC 7474 TTL package (Fig- 3) contains two D-flip flops with direct preset (S) and
clear (R) inputs & complementary outputs (Q & Qbar). The input is transferred to the
output on the positive edge of the clock pulse, when the S & R inputs are high. S & R
inputs can be used to control the flip-flop independent of clock. The Truth Table for D flip flop is given in Truth Table -1.
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PROCEDURE
1. Connect S, R, & D terminals to the logic input switches.
2. Connect clock terminals to Bouncelesspulser high or low.
3. Connect Q & Qbar terminals to logic output indicators.
4. Set the S, R & D signals by means of the switches as per TruthTable-3.Verify
the Q & Qbar outputs.
Note: LED ON
LED OFF
- LOGIC 1 .
- LOGIC 0 .
MASTER SLAVE JK FLIP FLOP

The Master Slave JK Flip Flop basically two gated SR flip flops connected together
in a series configuration with the slave having an inverted clock pulse. The outputs from Q
and Q from the Slave flip flop are fed back to the inputs of the Master with the outputs
of the Master flip flop being connected to the two inputs of the Slave flip flop. This
feedback configuration from the slaves output to the masters input gives the characteristics
toggle of the JK flip flop as shown below.
The inputs signals J and K are connected to the Gated Master SR flip flops which
lock the input condition while the clock (clk) input is HIGH at logic level 1. as the clock
input of the slave flip flop is the inverse (complement) of the master clock input, the slave
SR flip flop does not toggle. The outputs from the master flip flop are only seen by the
gated slave flip flop when the clock input goes LOW to logic level 0. When the clock is
LOW the outputs from the master flip flops are latched and any additional changes to its
inputs are ignored. The gated slave flip flop now responds to the state of its inputs passed
over by the master section. Then on the LOW to HIGH transition of the clock pulse the
inputs of the master flip flops are fed through to the gate inputs of the slave flip flop and on
the High to LOW transition the same inputs are reflected on the output of the slave making
this type of flip flop edge or pulse triggered.
Then, the circuit accepts input data when the clock signal is HIGH, and passes the
data to the falling edge of the clock signal. In other words, The Master Slave JK Flip Flop
is a Synchronous device as its only passes data with the timing of the clock signal.
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PROCEDURE
1. Connect J1, K1, CLR1 and CLR2 to Logic Input switches.
2. Connect CLK and CLK to Bouncelesspulser generator.
3. Connect Q1, Q1 terminals to J2, K2 terminals through path chords.
4. Connect Q2, Q2 output terminals to the logic outputs and verify the truth table-2
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RESULT
QUESTIONS
1. what is flip-flop?
2. What is level sensitivity and edge sensitivity?
3. What is diffence between latch and flip-flop?
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EXPERIMENT NO: 9
DATE:
DECADE COUNTER AND UP-DOWN COUNTER

a) DECADE COUNTER
AIM
To study the operation of Decade counter trainer using IC 7490 and Binary to
Decimal decoder / driver using IC 7447.
APPARATUS
1. Decade counter trainer kit
2. Adapter
3. Set of patch chords
THEORY
A Counter is a special kind of register, designed to count the number of clock
pulses arriving at its input. We have two types of binary counters.
1. Asynchronous or Ripple counters and
2. Synchronous counters.
A counter is a register capable of counting the number of clock pulses that have
arrived at its clock input. In its simplest form it is the electronic equivalent of a binary
odometer. In ripple counters clock input is given to the clock input of the LSB flip-flop.
Its output is given to the next MSB flip-flop etc. So a ripple type operation occurs in as
synchronous counters. But in synchronous counters, clock is applied simultaneously to all
flip-flops. So synchronous counters are faster than ripple counters. maximum number of
clock pulses counted by a counter is depend on its no. of bits, suppose if we have a 4 bit
counter, highest no. of clock pulses counted by this counter is 24 = 16. I.e. from 0000 to
1111. This is also called a Modulus 16 counter. The modulus of a counter is the number of
output states it has. By changing the design we can produce a counter with any desired
modulus. So that Decade counter is a counter capable of counting maximum 10 no. of
clock pulses. It is also called modulus 10 counter.
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DECADE COUNTER USING IC 7490

7490 Decade counter consists of 4 flip flops connected as a divided by 2 counter
with in and A output and a divided by 5 counter with Bin and B,C, D outputs. Clock
input is applied to Ain and A output is connected to Bin
to a 10 counter with outputs
A,B,C and D out is the most significant bit with A out is the least significant bit with A
out is the least significant bit. The flip flops triggered at the negative edge of the clock
transition. The truth table of 7490 is shown below.
These 4 bits (DCBA) are decoded by IC 7447 Binary to decimal decoded / driver to
indicate the count number on 7 segment LED display.
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During the reset inputs R01, R02, R91 & R92 should be set as below.
The counter can be reset to 0 and Reset to 9 by putting R 01, R02, R91 & R92 as shown
below.
PROCEDURE
1. Switch ON the experimental board by connecting Power card to AC mains.
2. Reset the counter as per setting given in Reset to 0 state and observe the O/P in
7 segment display.
3. Now reset the counter to Reset the counter to Reset 9 state as per the settings
given in the Reset to 9 mode and observe the O/P in 7 segment display.
4. Set input to count mode.
5. Connect clock pulse to Ain. Connect Aout output to Ain. Observe the count
sequence in 7 segment display.
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RESULT
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9.b) UP-DOWN COUNTER
AIM
To study and verification of truth table of IC 74193, Up / Down decade counter.
APPARATURS
1. Up/Down counter trainer kit
2. Adapter
THEORY
The IC74192 is an Up/Down modulo -10 decade counter -separate count up and
count down clocks are used in either counting node the circuits, operate synchronously.
The outputs change state synchronous with the low-to- high transitions on the clock inputs.
Separate terminal count up and terminal count down outputs are provided, which are used
as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter
designs. Individual preset inputs allow the circuits to be used as programmable counters.
Both the parallel load and the master reset inputs synchronously over ride the clocks.
The description of various pins is as follows:
CPu
Count up clock input (active rising edge)
CPd
Count down clock input (active rising edge)
MR
Asynchronous master reset input (active high)
PL
Asynchronous parallel load input (active low)
P0 - P3
Parallel data inputs.
CD
Terminal count down (borrow) output (Active low)
CU
Terminal count up (carry) output (active low)
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CIRCUIT DESCRIPTION
The trainer is provided with two number of 74193 Up/ Down decade counter
connected as 8 bit Up/ Down counter. A DPDT switch is provided to select Up/Down
count. A two digit 7segment display is provided with built in decoder driver (IC 7447) to
display the decimal count.
A variable clock generator of 1Hz to 10Hz frequency is provided in the system.
PROCEDURE
1. Switch ON the trainer.
2. Connect the clock output to the input of the counter.
3. Put the switch in CPU position.
4. Observe the counting sequence of LEDs and corresponding count on the display
(00 -99).
5. Repeat the steps 2 to 4 for the selection of switch in CPD position.
6. The count goes from (99 - 00)
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RESULT
QUESTIONS
1. What is decade counter?
2. How to design modulo-10 counter?
3. What is up-down counter?
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EXPERIMENT NO: 10
DATE:
UNIVERSAL SHIFT REGISTER (74194)

AIM
To study the following applications of the Universal Shift Register using IC
(74194).
a) Shift Right Logic
b) Shift Left Logic
c) Parallel Load
APPARATUS
1. Universal Shift Register trainer kit
2. Adapter
THEORY
74194 - 4 Bit Bidirectional Universal Shift Register. The general description of the
shift register along with block diagram, pin configuration and mode select table are given
in the subsequent section. This trainer will provide a detailed understanding on the
operation of Shift Register. Data input switches, Digital Data Status indicators, Clock, DC
power supply are all in built in the trainer, so that the user need not feel the necessity for
other test equipment. Thus the trainer is a self contained, self sufficient source of learning
on Shift Registers.
4 BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER - 74194
This is a multipurpose 4 bit Shift Register used in a wide variety of applications like
serial to serial, shift left, shift right, parallel to serial, and parallel to parallel data transfer
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PROCEDURE
STEP: 1 MASTER RESET
Set the inputs as below and observe the outputs as per Table1
A logic 0 on MR resets all outputs to logic 0 irrespective of other inputs.

STEP: 2 PARALLEL LOAD
In this step we load the data parallely. Set the inputs as below and observe the
outputs
Here when S1 & S0
are both logic 1 the input data is transferred parallely to output
at the clock positive transition change the input data and observe the change at the output.
STEP: 3 SHIFT LEFT LOGIC 1S
Now switch DSL input to logic 1 and observe the shifting of logic 1s to left as
below. Observe the following outputs after each clock pulse and verify.
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STEP: 4 SHIFT LEFT LOGIC 0

While running the above step change the logic inputs DSL to logic 0 and then S0 to
logic 0 in the same sequence. Observe the following outputs after each clock pulse and
verify.
CONDITION: MR =1, S0 = 0, S1 = 1, DSL= 0, DSR = X
Truth Table -4
In the subsequent 4 clock pulses logic 0s are shifted left successively with each clock
pulse.
STEP: 5 SHIFT RIGHT LOGIC 1s
Now at this condition of all 0s at the outputs switch DSR to logic 1 this will
enable all logic is as serial data and logic 1s will be shifted successively with each clock
pulse as shown below : observe the following output and verify.
CONDITION: MR =1, S0 = 1, S1 = 0, DSL = X, DSR = 1
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STEP: 6 SHIFT RIGHT LOGIC 0s

Repeat step 4 and parallel load logic 1s in all the 4 outputs. Change the logic
inputs of DSR to logic 0 and then of S1 to logic 0 in the same sequence. Observe the
following outputs after each clock pulse and verify.
CONDITION: MR =1, S0 = 1, S1 = 0, DSL = X, DSR = 0
Truth Table 6
STEP: 7 HOLD
In the above steps for shift left or shift right operation (steps 3,4,5,6) if both the S0
& S1 switches are forced to logic 0 then shifting operation will cease and whatever is the
output data it will freeze or hold .Observe this condition and verify.
CONDITION: MR =1, S0 = X, S1 = X, DSL = 0, DSR = 0
Truth Table 7
STEP: 8
1 Bit Shift Left Operation
Select the following condition and follow the table given below. DSL to high and
select the bit by applying one clock pulse, then make DSL to low and apply clock pulses
for 1 bit shift left operation.
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2 Bit Shift Left Operation
Select the following condition and follow the table given below. Keep the DSL to
high and apply the two clock pulses for 2 bit selection, then make DSL to low by applying
clock pulses one can observe 2 bit shift left operation.
STEP: 10
1 Bit Shift Right Operation
Select the following condition and follow the table given below. DSR to high and
select 1 bit by applying one clock pulse, then make DSR to low. By applying clock pulses
one can observe 1 bit shift Right operation.
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2 Bit Shift Right Operation
Select the following condition and follow the table given below. Keep the DSR to
high and apply the two clock pulses for 2 bit right selection, then make DSR to low by
applying clock pulses one can observe 2 bit shift Right operation.
Note: For 3 bit shift operations select DSR/DSL to High until he 3 clock pulses applied and
then make DSR/DSL to low and apply clock pulses for 3 bit shift operations respectively
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RESULT
QUESTIONS
1. What is Universal Shift Register?

2. What are applications of universal shift register?
3. Explain design steps for universal shift register?
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EXPERIMENT NO: 11
DATE:
4-BIT MAGNITUDE COMPARATOR
AIM
To study the operation of a 4-bit magnitude comparator using IC 7485
APPARATUS
1. 4-Bit Magnitude comparator trainer kit

2. Adapter
THEORY
The 7485 is a high speed, expandable 4 - bit magnitude comparator which compares
two 4-bit words in any monolithic code (binary, BCD or other ) and generates three outputs
: A less than B , A greater than B and A equal to B. Three expansion inputs allow serial
(ripple) expansion over any word length without external gates.
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PROCEDURE
1. Switch ON the experimental board.
2. By changing the inputs A3 , A2, A1 , A0 and B3 , B2 , B1 , B0 observe the outputs.
For all possible combinations of A3, A2,A1,A0 and B3,B2,B1,B0 ,the combination
shows which is greater than the other or equal
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RESULT
QUESTIONS
1- What is comparator?
2- Explain 4-bit magnitude comparator operation?
3- What are different types of comparators?
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ECE, MRCET
EXPERIMENT NO: 11
DATE:
3 - 8 DECODER USING IC 74138

AIM
To study the operation of 3 - 8 DECODER USING 74138
APPARATUS
1. Decoder 74138 Trainer kit
2. Adapter (+5V / 350mA)
3. Set of Patch Chords
THEORY
The 74138 is a high speed 1 of 8 Decoder / Demultiplexer. This device is ideally
suited for high speed bipolar memory chip select address decoding. The multiple input
enables Parallel expansion to a 1 of 24 decoder using three 74138 devices or to a 1 of 32
decoder using four 74138 devices and demultiplexer. Demultiplexer outputs are indicated
by the LEDS.
By synchronizing the Multiplexer address and demultiplexer address the input
Channel on the multiplexer is connected directly to the corresponding output Channel. A
multiplexer or demultiplexer is something like a 1 POLE 8 WAY Switches.
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ECE, MRCET
PROCEDURE
1. Connect adopter and Switch ON the Trainer.
2. Connect patch chord at the line between Bounceless pulser and CP of address
generator (IC74163).
3. Connect address outputs Q0, Q1 and Q2 to inputs of A0, A1 and A3 of Decoder
(IC74138).
4. The output of address generator changes from 000 to 111 sequentially. By
pressing the push button switch from Bounceless pulser switch. Observe the status
on address LEDs A0, A1 and A2.
5. Select Data IN switch to 1 position.
6. Suppose if the output of the address generator is 000, channel 0 of Decoder
(IC74138) is activated. This can be observed by LED indicators of decoder output.
Changing the address generator output and observes output of decoder respectively.
7. Verify the table which indicates for each address location, which output is
activated and how the state of decoder output changes.
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ECE, MRCET
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ECE, MRCET
RESULT
QUESTIONS
1. What is decoder?
2. What are applications of decoder?
3. Design 3-8 decoder and explain operation?
4. What is encoder and what are different types?
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ECE, MRCET
EXPERIMENT NO: 12
DATE:
8 - 1 LINE MULTIPLEXER AND 2 - 4 DEMULTIPLEXER
AIM
To study the operation of 8-CHANNEL DIGITAL MULTIPLEXER AND
2-4 DEMULTIPLEXER.
APPARATUS
1. Multiplexer and demultiplexer trainer kit
2. Adapter
THEORY
To send multiple Data streams from one place to other, MULTIPLEXING of
signals process is used. MULTIPLEXING is the process of sending of number of separate
signals over the same channel, simultaneously without interference between them.
CIRCUIT DESCRIPTION
The 74151 is a High Speed 8 Input Digital Multiplexer. It provides in one package,
the ability to select one line of data from up to eight sources. 8 logic input switches are
provided on the Trainer to Set either zero or 1 level on the corresponding input channel. At
any time, which input is selected in the output depends upon the output of address
generator output at that instant. The 74161 / 74163 are high speed Synchronous Modulo 16 Binary Counter. They are Synchronously Presettable for application in Programmable
dividers and have two types of Count Enable inputs plus Terminal Count Output for
versatility in forming synchronous multistage counters. 3 output bits are used as address
inputs to the 8 - to - 1 Line Multiplexer 74151.
The 74138 is a high speed 1 -of -8 Decoder / Demultiplexer. This device is ideally
suited for high speed bipolar memory chip select address decoding. The multiple input
enables Parallel expansion to a 1 - of - 24 decoder using three 74138 devices or to a 1 - of -
77
ECE, MRCET
32 decoder using four 74138 devices and demultiplexer. Demultiplexer outputs are
indicated by the LEDS.
By synchronising the Multiplexer address and demultiplexer address the input
Channel on the multiplexer is connected directly to the corresponding output Channel. A
multiplexer or demultiplexer is something like a 1 POLE 8WAY Switchs.
PROCEDURE
MULTIPLEXER
1. Connect adopter and Switch ON the Trainer.
2. Set all input switches of 74151 multiplexer in 0 position.
3. The clock is internally connected to the Address generator.
4. The output of the address generator changes from 000 to 111sequentially by
pressing the push button switch.
Observe the status on Address LED s A0 , A1& A2.
5. Suppose, if the output of the address generator is 000, channel 0 of
74151(Multiplexer) is activated. This can be observed by LED indication at 74151
output. If we change the status on Channel 1, that will change the output status
of the multiplexer output. In this position, all other channels are inactive. Change
the input status of other channels which are not reflected in the output.
6. The same action will occur for different address settings. Change the address to
corresponding to CH4 (100). Observe that whatever input ( 1 or 0) in CH 4 is
reflected at the output. Any data ( 1 or 0) at all other channels are ignored.
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ECE, MRCET
DEMULTIPLEXER
1. Connect A0 to A0, A1 to A1 and A2 to A2 and then A2 must be low through ground.
2. Connect multiplexer output to input of demultiplexer. Now verify the table which
indicated for each address which channel is activated and how the state of channel changes.
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ECE, MRCET
RESULT
QUESTIONS
1. What is multiplexer?
2. What are applications of mux?
3. What is demultiplexer?
4. Design 8 input1 output multiplexer?
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ECE, MRCET
EXPERIMENT NO: 13
DATE:
RAM USING 74189
AIM
To study the operation of ram using IC 74189.
APPARATUS
1. RAM trainer kit
2. Adapter
THEORY
The memory of a computer is where the program and data are stored before the
calculations begin. During a computer run, the control section may store partial answers in
the memory, similar to the way we use paper to record our work. The memory is
therefore one of the most active parts of a computer, storing not only the program and data
but processed data as well.
The memory is equivalent to thousands of registers, each storing a binary word.
The latest generation of computers relies on semiconductor memories because they are less
expensive and easier to work with than core memories. A typical microcomputer has a semi
conductor memory with up to 65,536 memory locations, each capable of storing 1 byte of
information.
A random access memory (RAM), also called a read write memory, is equivalent to
a group of addressable registers. After supplying an address, you can either read the stored
contents of the memory location or write new contents into the memory location.
CORE RAMS
The core RAM was the workhorse of earlier computers. It has the advantage of
being non volatile; even though you shut off the power, a core RAM continues to store
data. The disadvantage of core RAMs is that they are expensive and harder to work with
than semiconductor memories
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.
SEMICONDUCTOR RAMs
Semiconductor RAMs may be static or dynamic. The static RAM uses bipolar or
MOS flip-flop ; data is retained indefinitely as long as power is applied to the flip - flops.
On the other hand, a dynamic RAM uses MOSFETs and capacitors that store data.
Because the capacitor charge leak offs, the stored data must be refreshed (recharged) every
few milli seconds. In either case, the RAMs are volatile, turn off the power and you lose
the stored data.
THREE STATE RAMS
Many of the commercially available RAMs, either static or dynamic, have three
state outputs. In other words, the manufacturer includes three state switches on the chip so
that you can connect or disconnect the output lines of the RAM from a data bus.
OPERATION
RAM IC 74189 is 16 words x 4 bit Read/Write Memory.
Stack and Queue
Queue: FIFO (First IN First OUT)
Stack: LIFO (Last IN First OUT)
PROCEDURE
This experiment has 2 stages.
(a). Data Entry (Write Operation)
(b). Data Verification (Read Operation).
(a) Write Operation
1. Assume that the following data has to be written on to the RAM.
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ECE, MRCET
2. Position the Stack/Queue switch in the Queue position.

3. Position the Read/Write switch in the Write position to enable the entry of data in
to the RAM.
4. Position the Load/Count switch in load position to allow the RAM address. MR switch
to Low.
5. Set the desired address (any address at random) using the address bit switches.
6. After each data entry, make a note of the location where data is entered. This is to
make sure that we are not re entering data in the same location.
7. Position the Read/Write switch in the Read position, to disable data entry.
8. This completes data entry.

(b) Read Operation
1. Position the Stack/Queue switch in the Queue position.
2. Position the Set Address switch in the Load position MR to Low and ME to Low.
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ECE, MRCET
3. Position Read/Write switch in the Read position, to disable unauthorized entry of

data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This
is because the data was written during the data entry procedure.
For Stack Operation:
1. Position the stack/Queue switch in stack position.
2. And observe the last address which you low entered as first data output.
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ECE, MRCET
RESULT
QUESTIONS
1. What is ram and explain operation?
2. What is difference between RAM and ROM?
3. What are applications of RAM?
4. Explain design steps for 16*4 RAM?
87

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IC Applications Lab Manual

MALLA REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY

IC Applications Lab Manual

INTRODUCTION - STUDY OF IC741 & IC555

ADDER, SUBTRACTOR & COMPARATOR USING IC741 OP-

INTEGRATOR AND DIFFERENTIATOR USING IC741 OP-AMP

ACTIVE LOW PASS & HIGH PASS BUTTERWORTH FILTERS

RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING

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SCHMITT TRIGGER CIRCUITS USING IC741 & IC555

FUNCTION GENERATOR USING IC741

D FLIP FLOPS AND MASTER SLAVE JK FLIP FLOPS

DECADE COUNTER AND UP-DOWN COUNTER

UNIVERSAL SHIFT REGISTER (74194)

4-BIT MAGNITUDE COMPARATOR

3 - 8 DECODER USING IC 74138

8 - 1 LINE MULTIPLEXER AND 2 - 4 DEMULTIPLEXER

RAM USING 74189

IC Applications Lab Manual

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Internal Power Dissipation

Operating temperature range

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Functional block diagram:

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Minimum Triggering Voltage

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ADDER, SUBTRACTOR & COMPARATOR USING IC741 OP-AMP

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INTEGRATOR AND DIFFERENTIATOR USING IC741 OP-AMP

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- circuit acts like a simple inverting amplifier and no integration results,

In the circuit diagram of Integrator, the values are calculated by assuming fa as 50

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3. Calculate the value of R using the equation

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Gain Magnitude Gain in dB =

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Gain Magnitude Gain in dB =

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RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC741 OP-AMP

a) RC Phase Shift Oscillator

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RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC741 OP-AMP

b) Wien Bridge Oscillator

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IC555 TIMER IN MONOSTABLE OPERATION