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Part 1
Introduction - (2)
Multiplexers - .. (3)
Part 2
Fundamentals of package - .. ()
Basics of structural modeling - ()
Formation of 16:1 multiplexer - .. ()
Appendix (A):
VHDL code of 4:1 multiplexer using behavior modeling----Xilinx simulated output and modelsim waveforms -----------Appendix (B):
VHDL code of package declaration----------------------------------VHDL code of 4:1 multiplexer----------------------------------------VHDL code of 16:1v multiplexer using structural modeling------Xilinx simulated output and modelsim waveforms ------------------/
Part1:
Introduction:
Multiplexer:
A multiplexer is a device that selects between a numbers of input signals. In a simple
form, a multiplexer has two signal inputs, one control output and one output.
Normally multiplexers are used to build digital semiconductors such as CPUs and
graphics controllers. In this applications, the number of inputs is generally a multiple of 2
(2, 4,8,16, etc.), the number of outputs is either 1 or relatively small multiple of 2, and
number of control signals is related to the combined number of inputs and outputs. For
example, a 2-input, 1-output multiplexer requires only 1 control signal to select the input,
while a 16-input, 4-output multiplexer requires 4 control signals to select the input and 2
to select the output.
Fundamentals of package:
A VHDL package declaration is identified by the package keyword, and is used to collect
commonly used declarations for use globally among different design units. the main
advantage is the item defined within a package can be made visible to any other design
unit in the complete VHDL design and this concept is used in the second task of the
assessment.
Appendix codes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.mux4to1_package.all;
entity mux16to1 is
Port ( d : in STD_LOGIC_vector(0 downto 15);
s : in STD_LOGIC_vector(3 downto 0 );
y : out STD_LOGIC);
end mux16to1;
architecture structure of mux16to1 is
signal m:std_logic_vector(0 downto 3);
begin
mux1:mux4to1 port map(d(3 downto 0),s(1 downto 0),m(0));
mux2:mux4to1 port map(d(7 downto 4),s(1 downto 0),m(1));
mux3:mux4to1 port map(d(11 downto 8),s(1 downto 0),m(2));
mux4:mux4to1 port map(d(15 downto 12),s(1 downto 0),m(3));
mux5:mux4to1 port map(m(3 downto 0),s(3 downto 2),y);
end structure;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sixteentoonemux is
Port ( d0,d1,d2,d3 : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end sixteentoonemux;
architecture Behavioral of sixteentoonemux is
begin
with s select
Outputs: