Power Semiconductor Devices

Robin Giese
Princeton University EE341
12/14/2000

Requirements for power devices

Primarily on/off control of high-I/V vs.
amplification
several 1000V, peak currents 3000A
reverse breakdown voltage important for reliable OFF state

effective switching
low ON state drop voltage (I=V/R)
high current density
low driving current

basic devices: (Power-) BJT, MOSFET

BJT: requires high gate current for both ON and OFF
MOSFET: somewhat more difficult to make

Topics covered

Requirements
Silicon Controlled Rectifier
lighting control
Insulated Gate Bipolar Transistor
High power device challenges
Manufacturing challenges

p-n-p-n diode

3 states:
reverse blocking
forward blocking
forward conducting
device pops from forward blocking to forward conducting
state
device recovers from conducting state to forward or
reverse blocking states after V is released

p-n-p-n diode: fwd blocking

Separate diodes: forward, reverse, forward bias

p-n diode: holes from p n, e from n p,
supplied from ohmic contacts
p-n-p-n J1: hole from ohmic contact on p1 wants
to cross to n1, needs e to exchange with n1 to
maintain space charge neutrality
n1 has no ohmic contact, J2 in reverse bias, no e
can be supplied no current

p-n-p-n diode in reverse blocking

Separate diodes: reverse, forward, reverse bias

J2 could conduct: holes from p2 to n1, etc.
However, no supply of holes from n2 through
reverse-biased J3 again, no current

p-n-p-n diode leakage

Go back to forward bias: J1/J3 forward biased, J2

reverse-biased
Recall: p1 is waiting for e to come from n1 through
J1, but n1 has no e supply
However: thermal EHP generation at J2 gives e to
n1, hole to p2 small leakage current
Sample applies to p-n-p-n in reverse bias

p-n-p-n forward conduction state

holes
E
Vrv

J2 in reverse bias
-> depletion region extends towards J1/J3 (base
width narrowing)
-> reverse E field, starting/ending near J1/J3
suppose thermal EHPGen brings e to n1, so p1 can
inject hole
hole in n1 grabbed by strong E field of J2, swept
into p2

p-n-p-n fwd conducting contd

holes
E
Vrv

Now have hole in p2 -> can offer hole to n2 (J3

conducts this hole)
n2 inserts electron into p2, electron swept up by Efield across J2 into n1
now n1 has a non-thermally-generated e, and with
that can conduct another hole from p1 to p2
-> escalating cycle, immediately reach forward
conducting stage

p-n-p-n states review

3 states:
reverse blocking, forward blocking, forward conducting
thermal EHP generation responsible for leak currents
high forward bias responsible for wide & strong E-field
across J2
E-field picks up miscellaneous holes/electrons to start
forward conducting build-up and sustenance

another factor: avalanche breakdown

Triggerable SCR

Regular p-n-p-n diode needs high reverse bias to

make E-field across J2 sufficient to sweep up
thermally generated e/holes
If we inject holes ourselves at p2 using a gate,
large E-field is not required
-> we can use the gate to yank the device into
forward conducting state

Alternative transistor model

Imagine two crossconnected pnp and npn
transistors
SCR gate = base of npn
apply Vgate
-> npn conducts
-> attached to pnp base
-> pnp conducts
-> entire device
conducts

SCR characteristics
Conducting state self-sustaining
can drop gate current after conducting state is initiated
must wait for Vbias to cede to return to blocking states

Controllable one-way current (rectification)

-> silicon controlled rectifier
also, thyristor

higher I/V capabilities than BJT

Zero-cross SCR wave modulation

Rise time 2s (too fast)

Dimmers: use chokes

buzzing of filaments
RFI/EMI
mechanical noise (choke resonating)
harmonic line noise (conduits)

Soft wave shaping

Cant do this with SCR IGBT

Insulated Gate Bipolar Transistor

SCR/BJT/MOSFET hybrid
positive Vgate n+/n- connected
p+-i-n junction
IGBTs: 3.5 Vdrop vs. 0.7 Vdrop for SCRs

Single injection

Usually:
single injection of e recombination centers filled
flow limited by space charge barrier

Double injection

Double injection:
high enough E-field transports h to cathode
lowered space charge barrier for e regenerative process

Similar: avalanche multiplication

Micro- and meso-plasmas

Double injection
open circuit stable
CCNR
small area goes up to
high B current
stable microplasmas
elevated temperatures
thermal EHP generation
meso plasma, second breakdown
destructive
any inhomogeneity causing localized dT can cause
mesoplasma

Preventing second breakthrough

Overlay (striped/ballasted) transistor

striping reduces lateral electrical and thermal instabilities

Other complications
Junction gradients
greater device depth non-abrupt junctions

Junction/depletion layer curvature

one solution: beveled junctions

Heat issues

Base material problems

Czochralski (CZ) process for Si growth
max. 100-200 -cm (Vb max. 750V)
carbon, oxygen common impurities softspots,
premature breakdown

Float Zone (FZ) Silicon

excellent purity, 1,000-12,000 -cm

Summary

Needs of high power devices

introduced SCR
illustrated ohmic load control
introduced IGBT
high power device problems
high power device manufacturing

Sources
Ghandhi, Sorab K. Semiconductor power devices
(New York: John Wiley & Sons, Inc. 1977)
Streetman, Ben G. Solid state electronic devices
(Upper Saddle River, NJ: Prentice Hall 2000)
Baliga, B. Jayant. Power transistors: device design
and applications (New York: IEEE 1984)
Ramshaw, Raymond. Power electronics (London:
Chapman and Hall Ltd 1973)
http://www.ies.nl/Info_IGBT/body_info_igbt.html