//Document all versions here

INTEL(R) PRO/1000 NDIS6.2 driver for Windows 7 - 32.

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11.8.35.0 (Pci Express) NOT Digitally signed
Date: 07/01/2010
Comments:
Version 11.8.35.0 is the initial driver version for this project.
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All Windows Versions 11.8.57.0 (Pci Express) NOT Digitally signed
Date: 08/03/2010
Comments:
Other
Changes Made:
Added checks for adapter context to resolve a race condition between
filter resource
requirement IRPs and MiniportInitialize
Defect
hsd_ladsw 3045223: PCH: e1k driver not reading the Half Duplex phy stat
istic counters
hsd_ladsw 3143668: SIPS and LSBS: Unnecessary link speed change occurs
at 10Mb
Other
Description:
Updated and corrected use of FPGA_SUPPORT.
Changes Made:
Turned off FPGA support by default. Replaced NIANTIC_FPGA_SUPPORT an
d TWINVILLE_FPGA_SUPPORT
with the generic FPGA_SUPPORT that everyone else uses. Removed some
Niantic FPGA code that
is no longer valid with the new FPGA machines.
Other
Changes Made:
Added new fn to check for PCH devices. Added port gen cfg in powerup
for Lewisville.
Other
Description:
New registry parameter TxDelay.
Changes Made:
Added registry parameter "TxDelay", which specifies a delay in micro
seconds after every write
to Tx Tail. The default is 0 (no delay). The code is wrapped in #ifd
ef FPGA_SUPPORT because
it is only used when working with an FPGA.
Other
Description:
To partially ease hotspots in RxProcessNextPacket, checksum offload
function was re-factored
Changes Made:
There is a new field called RxDescriptorStatus which is part of the
PRECEIVE_BUFFER, populated

in the RxProcessNextDescriptor so we do not need to dig into it in t

he CSO function. Convert
the if-else checks into a switch case statement.
Other
Changes Made:
Added the port gen cfg in init flow for lewisville.
Defect
hsd_ladsw 3332377: Lewisville fails WOL from Directed Packet
Root Cause:
This issue was root-caused to the fact that the SMBus Address was no
t programmed into the PHY
while going down to Sx on first boot. It is present in subsequent S0
->Sx cycles which is why
WoL works in these cycles.
Resolution Notes:
Modified the driver to always program the SMBus Address into the PHY
when going down to Sx states.
Testing Hints:
Ensure the WoL works in multiple S0->Sx cycles.
Other
Description:
Fixed ARP/ND offload DEBUGFUNC() related macro calls; adding string
quotes.
Changes Made:
Fixed ARP/ND offload DEBUGFUNC() related macro calls; adding string
quotes.
New Feature
Feature Description:
Allocate dedicated interrupt vectors for FCoE so that FCoE interrupt
s no longerdepend on RSS
either in terms of number of queues or in terms of RSS CPUscontrolle
d by the OS.
Changes Made:
Eight additional msix message resources are allocated just for FCoE,
and theircpu affinities
are spread across sockets so that FCoE is more likely to have asamesocket CPU to use for any
CPU on which storage traffic might be initiated.The total number of
MSIX messages requested
is now (max(16,numcores) + 2 + 8).The additional 8 for FCoE puts som
e additional pressure on
PCI resourcearbitration, so future changes might mitigate this by re
ducing the numcorespart
of the preceding equation (i.e. by not targetting every possible RSS
cpu).The small additional
pressure is unlikely to be a problem even withoutmitigation; it will
be very unlikely to
trigger fallback behavior any soonerthat it currently occurs.
Testing Hints:
Exercise FCoE and observe queues are statically associated with cpus

. Exercise RSS,
observe RSS OID's occurring (either with oids.exe to monitor stats o
r via debug output in
checked build of base driver), and observe that the FCoE cpus do *no
t* change when the RSS
cpus change.
Defect
hsd_ladsw 3331784: Low network througput with Jumbo Frames + Lewisville
Sugar Bay & Huron River.
Root Cause:
This issue is caused by a large number of missed packets that could
not be DMA-ed to host
memory, thereby resulting in bad throughput numbers. It is directly
related to the C6 CPU
state on the platform. If C6 is disabled in the BIOS, this issue doe
s not occur. The exit
latency from C6 appears to be more than the time required to get the
packet into Host memory
and hence large numbers of packets are dropped (because there is no
more space in the Packet
Buffer to hold them)
Resolution Notes:
Modified the ITR algorithm function to add a work-around that accoun
ts for missed packets (as
determined by the MPC register) and pegs the CurrentITRMode at Lowes
tLatency. The work-around
will ensure that the LowestLatency mode stays for at least 100 DPCs
before we allow it to
increment to the next order of magnitude (LowLatency)
Build Changes
hsd_ladsw 3332476: E1C driver does not set Host LinkSec Connection Acti
ve (LSECA) bit in the
H2ME register when enabling MACsec
Brief Description:
clears H2ME bits for linksec connections.
Other
Description:
Moved all LSC processing to a work-item thread to improve system per
formance
Changes Made:
Moved all of the Link Status Change (LSC) processing code from the D
PC function to a work-item
function. The advantage gained here is that work item threads run at
IRQL=PASSIVE_LEVEL and
hence do not stall the CPU (or the system) as it would when processe
d in a DPC
Other
Description:
Functions IncrementAdapterIndex() and GetAdapterIndex() need to retu
rn the index of the
adapter (usually AdapterNumber - 1)

Changes Made:
Modified IncrementAdapterIndex() and GetAdapterIndex() to properly r
eturn AdapterIndex of 1
less than AdapterCount.
Defect
hsd_ladsw 3332672: Spring Fountain - NDOS Tester 6.0 - 1c_faulthandling
test causes the system
to bug check
Other
Description:
A number of Klocwork fixes for null pointers, errors with classes, a
nd uninitialized variables
Changes Made:
A number of Klocwork fixes for null pointers, errors with classes, a
nd uninitialized variables
New Feature
Feature Description:
DCR 996 - Event Log Enhancement
Changes Made:
Added code to extract the bus, device and function corresponding to
the instance.
Added code to embed this informatio
n in the event log if the branding string (part of event log) exceeds the MAX li
mit, there by adding identification (which was lost earlier) for corresponding d
river instance.
Other
Description:
AIFS oid fixes got reverted, added back for HSD 3145287
Changes Made:
AIFS oid fixes got reverted, added back for HSD 3145287
Other
Description:
added full support for reading and writing to VF PCI config space
Changes Made:
pass untrapped calls to Ndis to get HW values
Defect
HSD LADSW 3332679 Customized LED value in NVM not applied with LV Beta S
W
Root Cause
The LED writes (and smbus address) were not taking effect because sw
has gated ppw and the
driver is checking for oem write enable bits
Resolution
Removed the check for oem write enable bits for Nahum5
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All Windows Versions 11.8.67.0 (Pci Express) NOT Digitally signed
Date: 08/19/2010

Comments:
Defect
hsd_ladsw 3332339: CERTS: Lewisville fails WoLMagicPacket
New Feature
Feature Description:
Interrupt refactoring to decouple User Priority to Traffic Class map
ping, so that FCOE will
use a fixed TC.
Changes Made:
Base driver reads the UP-TC mapping given by DCB to determine which
TC to use given the UP.
New Feature
Feature Description:
Iteration on new OID format to supply information on mapped queues
in redundant but more
convenient form.
Changes Made:
In addition to supplying a QueueBitmap for each cpu that has one or
more queues mapped,
supply an absolute queue number and a count indicating how many que
ues mapped to the CPU.
Queues>1 are not expected in practice, but the immutable nature of
the OID generally benefits
from fully complete expression.
Testing Hints:
Write FCoE query OID code per the new format. In the FCoE protocol
driver, read back Queue
and QueuesMapped values for CPUs that have queues mapped.
Defect
hsd_ladsw 3332727: Windows FCoE: Basic LUN connectivity issues with refactored RSS changes
Defect
hsd_ladsw 3332794: Lewisville B0 fails to link correctly when forced to
full duplex
Other
Description:
The FCoE driver saw asserts because the single ether type setting fo
r TC3 was incorrect.
Changes Made:
Queues 48-55 are for FCoE. The traffic on these queues is FCOE and ot
her packets for TC 3.
Therefore we cannot set single ether type flag just on a queue just b
ecause we detected an
fcoe packet. The driver now checks the ethertype of every NBL in the
list. If they are all
ethertype FCoE on the given queues, the single ether type flag is set
.
Other
Description:

Minor change to the handling of FIP packets.

Changes Made:
Removed the check for FIP packets that forced them out of the same T
C as FCOE packets.
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All Windows Versions 11.8.71.0 (Pci Express) NOT Digitally signed
Date: 09/07/2010
Comments:
Defect
hsd_ladsw 3331880: CERTS: Lewisville fails offloadchecksum
Root Cause:
K1 beacon duration was changed from 10 usec to 8 usec at 1G that res
olved the dropped packet
case between the phy and the mac
Additional Notes:
Built with v 3.9 of shared code that has K1 beacon fix and Jumbo Fra
mes code cleanup
Build Changes
Brief Description:
Code fix in powerdown to prevent Lewisville C0 from enabling ARP/NS
offload in Management Engine
Power Policy 1
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All Windows Versions 11.8.74.0 (Pci Express) DIGITALLY SIGNED: WHQL ID: 142683
1
Date: 09/20/2010
Comments:
Defect
hsd_ladsw 3333323: PROMOTE from sighting: Lewisville: RLSS links at 100
Mbps instead of 10Mbps
in Sx states
Root Cause:
This issue is caused by the fact that the ME programs the LPLU bits
in the PHY OEM bits
register by reading corresponding bits in the MAC PHYCtrl register.
The s/w driver is not
programming the MAC PHYCtrl LPLU bits when RLSS is checked/unchecked
.
Resolution Notes:
The LPLU bits are now written to both the PHY OEM bits register and
the MAC PHYCtrl
register when the 'Reduce link speed on standby' option is checked/u
nchecked.
Defect
hsd_ladsw 3704638: Lewisville - multiple adapter enable/disable causing
code 10 error on
Customer platform
Root Cause:

The Lewisville windows driver on system would occasionally code 10 a

fter multiple driver
resets. This was due to an unknown phy id. The phy reg read was inco
rrectly returning the
data from the previous phy reg read, so the phy id returned was eith
er all Fs when running
in fast mode (which occurred 100%), or 0x01540154 when running in sl
ow mode.
Resolution Notes:
Added a mac check for PCH2 to get the phy id only when in slow mode.
The phy transaction
logic takes 80us to complete a read or write, so a delay of 100us wa
s added to the mdic
read and write calls for PCH2. A mac check was added in the phy call
s rather than a phy
check in case the phy id is unknown when the function is called.
Testing Hints:
Disable and re-enable the driver multuple times and verify that the
driver does not code 10.
Next steps: Will update the HSD number for the errata sometime this
week.
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All Windows Versions 11.8.74.0 (Pci Express) No driver version change NOT DIGIT
ALLY SIGNED
Date: 10/19/2010
Comments:
Driver INF files updated to add the 4-part device ID for the Gold Coast
platform.
8086/1502/04AD/1028
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Windows 7 11.8.81.0 (Pci Express) Digitally Signed: WHQL ID 1431125
Date: 10/29/2010
Comments:
Defect
hsd_ladsw 3704590: Code changes from Si SV testing
Root Cause:
OEM bits not set for PCH2. gig disable and LPLU bits set for D0 inst
ead of D3
Resolution Notes:
Changes made to shared code in 3.9.0.3 v and tip. Changes to set oem
bits made in the
windows driver for driver unload
Customization
Brief Description:
Added a key to enable Lewisville JF performance at the expense of pi
ng timeouts
Customization
Brief Description:
Changed default Rx PBA on Lewisville to 18K, users can change to 14K
with registry key for
9K JF performance adjustment

Defect
hsd_ladsw 3705060: PROMOTE from sighting: AT7 -Power: ME doesn't answer
to ping in S3/S4 when
"wake on pattern match" is set in Host driver.
Defect
hsd_ladsw 3705217: PROMOTE from sighting: AT7 -Power:
lost in S3/M3 -ACDC
after Resume from S3-DC

AMT over LAN is

Root Cause:
The driver did not check for changes to the Offload ME state during
Power Up, only during
ME interrupts and driver enable/disable.
Resolution Notes:
- Always checks the ME valid bit and proxy enable bit after resume,
during MNG interrupts,
and before entering PowerDown flow (to avoid stalling the ME in Sx
).
- Disables ARP/NS offload in S5, there were times where the OS did n
ot remove the patterns,
so I force the disabling of offload in S5.
- Added a new key for keeping track if ARP and/or NS offload is acti
vated by NDIS or ME,
and gave the Reg keys it's own key.
API Change
Brief Description:
Issue found by SWE.
Changes Made:
For PCH2, the LAA MAC address was not offloaded in the ME-based ARP
offload flow. and that
the PHY based solution did offload the LAA address. This was because
updating the NVM
checksum auto-loads the NVM mac address. Writing the current MAC add
ress back into RAR0 in
the MAC and PHY resolves the bug.
Testing Hints:
Verify that the system wakes and offloads ARP from the LAA when pres
ent in the driver
advanced properties tab.
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