A Novel 2.

4GHz LNA with Digital Gain Control

using 0.18um CMOS
Kuo-Hua Cheng
1. Dept. of Communication engineering,
National Chiao Tung University,
Hsin Chu, Taiwan
2. Dept. of Computer and Communication,
SHU-TE University, Kaohsiung County, Taiwan
Email: khcheng1101@yahoo.com.tw
AbstractThis paper presents a novel gain control method
for 2.4 GHz LNA applications. In this design, a digital mode
gain control concept was implemented. This Chip can accept
an appropriate control bit that come from base band to
achieve power saving. With digital mode gain control to
achieve low noise and high 1dB compression point
simultaneously without increasing any circuit and power
consumption. Depend on receiving signal strength, there are
four gain modes can be selecting automatically. The compact
CMOS LNA is optimized for low-power-consuming ISM band
applications and is fabricated using commercial 0.18um
CMOS process. With current re-use technology, the power
consumption and linearity can be optimizing. The fully
integrated 2.4GHZ gain controllable LNA exhibits 15.2dB
maximum gain, 4.1dB minimum gain, respectively. Also, the
LNA has excellent noise performance at high gain mode;
1.55dB of noise figure is achieved in this work. The digital
modes gain controllable LNA produces a 1-dB compression
output power of -10 dBm. It consumes 2.5mA current from a
supply voltage of 1.8V.

I.

INTRODUCTION
Gain control mechanisms are used extensively in modern
communication systems. Through gain control mechanism,
circuits can achieve signal dynamic range extension, power
saving and good linearity. In recently year, portables RF
communication market is growth rapidly. Power
consumption is a key issue. The LNA is first circuit in any
RF receiver system that handles a high dynamic range RF
signals, such as -80dBm to -15dBm for Bluetooth. There
are tow problems at the front end of receiver. First is fading
effect. Second is reflection from a moving object. Both
effects can saturate or degrade receiver performance. A
LNA with gain control circuit can solve these problems.
The proposed novel gain control LNA integrates linear
gain controllability with digital control mode. Through
appropriate digital bit programmable, the LNA gain can be
variable from 4 dB to 15.2dB. The control ability of per bit
is 2.8dB/bit. A LNA with over 10dB gain controllable rage
is suitable for RF receiver application.
II.
GAIN CONTROL METHOD QUICK VIEW
There many gain control methods have been presented

0-7803-9433-X/05/$20.00 2005 IEEE.

Christina F. Jou
Dept. of Communication engineering,
National Chiao Tung University,
Hsin Chu, Taiwan
Email: christ@cc.nctu.edu.tw

before in literature [1-10]. The following are some gain

control techniques.
Technique 1: Load switching, its superiors are simple
structure and noise figure is not affected by
the gain modes. The drawbacks are potential
pose voltage problems and gain step very
sensitive to parasitic of load chain.
Technique 2: Current Splitting, power wastage is the most
important drawback and noise figure
performance will be serious degrade.
Technique 3: Extra gain control stage, it has good
performance in input and output isolation but
need more extra devices power consumption.
Technique 4: Bias control, the gain of LNA can be varied
with its bias voltage. Also, extra circuits that
convert control signal from base band is need.
The gain controlling scheme proposed here not only
achieves good NF but also extent the P1dB in low gain
mode. The gain control is circuitry also is simple and dont
put any extra circuits or waste more power consumption.
III.
LNA TOPOLOGY AND CIRCUIT DESIGN
The low noise amplifier is generally the first active stage
in RF receiver. Low noise figure, sufficient gain and higher
linearity are required. Also, input and output impedance
matching and power consumption are important, too. Noise
figure of LNA is key factor in receiver system, which
determined receiver system sensitivity. Equation (1) is the
total noise figure of a cascade multiple stages. In the
equation (1), the NF of first stage dominates the lower
bound of total system. Therefore, in order to achieve
sensitivity requirement of receiver, the LNA typically
requires a very low noise figure and sufficiently high gain
at desired frequency band to guarantee a low noise and
high sensitivity system.

NF = NF1 +

NF 1
NF2 1 NF2 1
+
+ ......+ n
G1
G1 G2
G1...Gn

(1)

The circuit diagram of the proposed gain control LNA is

shown in figure 1. The cascade topology with inductive

APMC2005 Proceedings

degeneration is frequently preferred, which offer low noise,

high gain, good input/output impedance matching and
stability. The M1 has to be optimized for noise figure.
While the noise figure of LNA is depends on gm of M1
transistor size, which depend on the bias current and width

Id and M1. Under this condition the input impedance is

given by

Zin s ( Lg + Ls ) +

1
+ T Ls
sC gs

(7)

At resonate condition (7) can be simplify

Zin T Ls

(8)
The gain control mechanism is achieved by M2 transistor
that split into N sub-transistor for gain control. Depend on
receiving signal strength; base band providing control
mode of active or sleep. There are 4 bits in the proposed
LNA. The gain bias voltage is control voltage Vctrl0 ~
Vctrl3 and are varied from 0 to 1.8V. The gain control bit
has about 3.5dB gain step/per bit. The advantage of this
scheme over other gain control methods [1-10] is that the
LNA dont need extra control circuits, designer can easy to
program the desirable gain control step by appropriate to
split M2 into n-bit control transistor and a simple circuitry
structure for RF design.

Figure 1. Low Noise Amplifier with gain control mechanism

of MOSFETs. The device scaling effects on the noise

parameters is derived by [11]. The four noise parameters
are as follows:

Fmin 1 +
Rn

(1 | c | 2
T

(2)

g d 0

Gopt

(3)

g m2

g mG gs
gd0

(1 | c | 2

The angular cutoff frequency T

Bopt C gs (1 c

(4)

gm
gd0

(5)
is inverse proportional
2

to Leff. In (3) Rn is proportional to 1/ g m that means

shorter device improve Rn. Equation (2)-(5) imply that the
large device width and minimum device channel length
offers the best noise performance. To achieve better noise
figure and reasonable power dissipation, optimum width of
transistor M1 is given by [12]

Wopt =

K (I )
.
1.2 0.8
L C ox
Rs
0.6
EFF

(6)

in which K(I) is a constant, depend on the biasing current

IV.
Simulation Result and Layout consideration
The LNA circuit simulation was using Mentor Graphic
Eldo-RF. Figure 2 shows the S21 curve of the LNA in
different gain control mode. It found that the gain of LNA,
S21, is centered at 2.4GHz with a high gain value of
15.2dB and low gain value of 4dB. The noise figure shown
in figure 3, it has minimum NF at high gain mode that
value is 1.5dB at 2.4GHz.
The 1 dB compression point P1dB is -8.5dBm at low
gain mode. Following the 9dB rule of thumb between P1db
and IIP3, which corresponding IIP3 is about -0.5dBm.
When control bit is set at 1111, the LNA is working at
high gain mode. Also, set at 0001, the LNA is working in
low gain mode. Table I shows that the low gain mode
(0001) consumes 25% less power than high gain mode
(1111). The P1db has 5.4dB improved at low gain mode
and excellent noise figure at high gain mode.
As we known, the silicon substrate of the CMOS
technology is very noise. The conventional signal PADs
are easily including noise and extra substrate loss from the
parasitic resistance between metal plate and substrate.
Therefore, we use shielding PAD as shown in figure 4[13],
to shield the undesired effects cause by the noisy substrate.
Figure 5 shows the novel gain control LNA layout. To
achieve higher on-chip inductor Q-factor, the symmetric
structure type was adopted. The optimum M1 size is
245um. There are some layout skills to improve the LNA
noise performance. First, use multiple finger layout to
reduce distributed gate resistance and both side gate contact
that can lower Rg about 1/12 [14]. Second, increase
substrate contacts to reduce substrate resistance, Rb [1516]. To isolate the noise substrate, all RF signal paths
should be with metal shield.

V.
CONCLUSION
A novel gain control LNA operating in 2.4GHz using
standard 0.18um 1P6M CMOS technology was
demonstrated. A simple and flexible gain control
mechanism is adopted in LNA design. With appropriate bit
control, the gain can vary from 4.18dB to 15.2dB. The
excellent noise figure performance, 1.5dB, is at high gain
mode. While a -8.5dB P1dB in low gain mode. The power
consumption for the mode of operation is 4.65mW at low
gain mode and 6.2mW at high gain mode.

20

Figure 4 Shielded signal PAD structure

15
10

dB

5
0
gain mode(1111)
gain mode(0111)
gain mode(0011)
gain mode(0001)

-5
-10
-15
1

Freq.(GHz)

Figure 2. S21 simulation result of LNA at 4 gain control mode

Figure 5. LNA layout view

10
gain
gain
gain
gain

9
8

m ode(1111)
m ode(0111
m ode(0011)
m ode (0001)

Table 1. 4 gain mode LNA specification simulation result

dB

6
5
4

Mode

S21(dB)

S11(dB)

NF(dB)

1111
0111
0011
0001

-18.8
-14.8
-13.1
-10.5

15.2
11.5
8.09
4.15

1.5
2.02
2.87
4.45

P1db
(dBm)
-13.9
-12.76
-13
-13.9

Power
Consumption
6.2mW
5.8mW
5.3mW
4.65mW

3
2
1
0
1

1.5

2.5

3.5

[1]

freq.(GH z)

Figure 3. Noise figure simulation result of LNA at 4 gain control mode

REFERENCES
Frank Ellinger and Heinz Jackel, Low-cost BiCMOS Variable gain
LNA at Ku-Band with Ultra-Low power consumption, IEEE MTT,
vol. 52, No2, pp702-707, Feb. 2004.

[2]

Y.S. Wang and L.-H. Lu, 5.7GHz low-power variable gain LNA in
0.18um CMOS, IEE Electronic Letter, vol. 41, No2. January 2005

[3]

Ken Long Fong, Dual band High linearity Variable Gain Low Noise
Amplifier for Wireless Application, IEEE Intl. Solid State
Conference, 1999.

[4]
[5]

[6]

Banerjee. B, Babak Matinpour et al, Development of IEEE 802.11a

WLAN LNA in silicon-base processes, in IEEE MTT-S Int.
Microwave Symposium Dig., vol.3, pp. 1573-1576, June 2003.
M.K. Raja, Terry Tear Chin Boon et al, A Fully Integrated Variable
Gain 5.75GHz LNA with on-chip active balun for WLAN, in IEEE
Radio Frequency Integrated Circuits Symposium, pp.439-442,June
2003.
C.D. Hull, J.L.Tham and R.R. Chu, A Direct Conversion Receiver
for 900MHz (ISM band) Spread Spectrum Digital Cordless
Telephone, IEEE JSSC, vol.31, No12, pp. 1955-1963, December
1996.

[7]

F. Plessas, G. Kalivas, A 5-GHz, Variable Gain, SiGe Low Noise

Amplifier, Proc. 24th Intl. conference on micro electronics, vol. 2,
pp.609-612, May 2004.

[8]

Mallesh Rajashekharaiah, Parag Upadhyaya and Deukhyoun Heo,

A compact 5.6GHz Low Noise Amplifier with New On-Chip Gain
Controllable Active Balun, IEEE workshop on Microelectronics
and Electron Devices, pp.131-132, 2004

[9]

Haigang Feng, Albert Wang and Li-wu Yang, A New 5.5GHz LNa
with Gain Control and Turn-off Control for Dual band WLAN
Systems, 7th Intl. conference on Solid State and Integrated circuits
technology, pp. 1248-1251, 2004

[10] Che-Hong Liao and Huey-Ru Chuang, A 5.7GHz 0.18um CMOS

Gain-Controlled Differential LNA with Current Reuse WLAN
Receiver, IEEE Microwave and Wireless Components Letters, vol.
13, No. 12,pp.526-528, December 2003

[11] Jung-suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu,

Thomas H. Lee and Robert W. Dutton, A Noise Optimization
Technique for Integrated Low-Noise Amplifiers, IEEE JSSC, vol.
37, No. 8, pp.944-1002, August 2002

[12] Francesco gtta, Enrico Sacchi, Francesco Svelto, Paolo Vilmercati

and Rinaldo Castello, A 2dB Noise Figure 900-HHz Differential
CMOS LNA, IEEE JSSC, vol. 36, No. 10, pp.1444-1452, October
2001
[13] Ryuichi Fujimoto,Kenji Kojima, and Shoji Otaka, A 7-GHz 1.8-dB
NF CMOS Low-Noise Amplifier, IEEE journal of solid-state circuits,
vol. 37, no. 7, July 2002
[14] B. Razavi, et al., Impact of Distributed Gate Resistance on the
Performance of MOS Devices, IEEE Trans. Circuits and Systems I.,
vol.41, pp. 750-754, Nov. 1994.
[15] Q. Huang, et al., Broadband 0.25um CMOS LNAs with sub-2dB
NF for GSM Applications, CICC 98 Proceedings, pp.67-70, May
1998.
[16] Y.Shin, et al., An Inductorless 900MHZ RF LNA in 0.9um CMOS,
CICC Proceedings, pp.513-516, 1997