Journal of Crystal Growth 352 (2012) 3942

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Journal of Crystal Growth

journal homepage: www.elsevier.com/locate/jcrysgro

Volume production of high quality SiC substrates and epitaxial layers: Defect
trends and device applications
a,n

St.G. Muller
, E.K. Sanchez a, D.M. Hansen a, R.D. Drachev a, G. Chung a, B. Thomas a, J. Zhang a,
a
M.J. Loboda , M. Dudley b, H. Wang b, F. Wu b, S. Byrappa b, B. Raghothamachar b, G. Choi b
a
b

Dow Corning Power Electronics, Midland, MI 48686-0994, USA

Department of Materials Science and Engineering, Stony Brook University, Stony Brook, NY 11794-2275, USA

a r t i c l e i n f o

abstract

Available online 7 November 2011

We review the progress of silicon carbide (SiC) bulk growth by the sublimation method, highlighting
recent advances at Dow Corning, which resulted in the commercial release of 100 mm n-type 4H-SiC
wafers with median micropipe densities (MPD) in production wafers o 0:1 cm2 and the demonstration of micropipe free material over a full 100 mm diameter. Investigations by Synchrotron White Beam
X-ray Topography (SWBXRT) and molten KOH etch pit analysis of 100 mm wafers demonstrate
threading screw dislocation densities o 500 cm2 . Additional results indicate the positive impact of
maintaining thermo-mechanical stress levels in the growing crystal below the critical resolved shear
stress on reducing basal plane dislocation densities to values as low as  3002400 cm2 in 100 mm
crystals. We summarize the steps of systematic quality improvements on increasing wafer diameter,
utilizing numerical simulations of the SiC growth system as a critical tool to guide this process. For the
economical production of SiC epitaxy, a 10  100 mm wafer platform has been established in a warmwall planetary chemical vapor deposition (CVD) reactor. The combined improvements in the epitaxy
process, pre-epi wafer surface preparation and the underlying substrate quality itself have led to a
reduction of the device killer defect density from 8 cm  2 to 1.5 cm  2 on a volume product like 100 mm
41 off-axis 6:5 mm epi-wafers. Dow Corning production epi-wafers routinely show Schottky diode yields
above 90% at a die size of 2 mm  2 mm. Additionally, 502100 mm thick epitaxy on 76 mm 41 off-axis
wafers with morphological defect densities of 26 cm  2, a surface roughness (RMS) r 1 nm as
measured by atomic force microscopy (AFM), and carrier lifetimes consistently in the range of
223 ms has been demonstrated.
& 2011 Elsevier B.V. All rights reserved.

Keywords:
A1. Defects
A1. Stresses
A2. Growth from vapor
A3. Chemical vapor deposition processes
B2. Silicon Carbide

1. Introduction

2. SiC bulk growth by the sublimation method

Within the last decade silicon carbide (SiC) has emerged as a

leading material for the next generation of high power semiconductor devices. The reduction of device yield limiting defects both
in bulk SiC substrates and epitaxial layers is critical for the broad
commercial adaptation of SiC based device technology [1]. At the
same time the increase of wafer diameter is necessary to take full
advantage of the economy of scale of advanced equipment in
existing power device fabrication lines. We review the progress of
the industrial SiC growth technology, highlighting recent advances
made at Dow Corning to support volume production of high quality,
large diameter SiC wafers and epitaxy.

2.1. History of SiC growth and wafer diameter progression

Corresponding author. Tel.: 989 496 4106; fax: 989 496 6360.

E-mail address: stephan.mueller@dowcorning.com (St.G. Muller).

0022-0248/$ - see front matter & 2011 Elsevier B.V. All rights reserved.
doi:10.1016/j.jcrysgro.2011.10.050

Sublimation growth by the modied Lely method [2] has become

the process of choice for the industrial volume production of SiC
semiconductor wafers [3]. However, the road to success, achieving a
wafer quality and diameter suitable for device production has taken
many turns over the last 50 years. Since the 1960s the potential of
SiC is discussed for electronic applications [4,5]. Although a number
of device feasibility studies were completed on SiC Lely-platelets
between the mid 1960s to the mid 1970s [6,7] a commercially
viable process for the production of large diameter substrates was
not available. This resulted in a strong decline of SiC related research
activities over the next 10 years in the USA, Western Europe and
Japan, while only in the former Soviet Union activities continued at
an approximately constant level. A rst renaissance of SiC started
with the development of the seeded sublimation technique [2,8] and
further with the market entrance of the rst commercial vendor

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St.G. M
uller et al. / Journal of Crystal Growth 352 (2012) 3942

for SiC substrates around 1987 [9]. Although initial wafer quality
suffered from a large amount of defects the commercial availability
of SiC wafers enabled device research activities at institutions without their own materials development program. Since then and
despite the specic challenges to control a SiC growth process at
high temperatures the historical rate of SiC wafer diameter progression up to a recently demonstrated 150 mm diameter [12] compares
favorably to the equivalent historical progress for Si and GaAs grown
from the melt by the Czochralski method (see Fig. 1 and cited
references). At Dow Corning volume production of low defect
100 mm n-type 4H-SiC wafers (see Section 2.2) has been established,
while larger wafer diameters with comparable quality (i.e. micropipe
densities (MPD) o 1 cm2 ) have been demonstrated (Fig. 2) and the
release of 150 mm wafers meeting the defect requirements for
commercial power device production is targeted for 2012.
2.2. Defect reduction in SiC wafers
The precise control of heat- and mass-transfer conditions
during SiC growth is critical to prevent or at least minimize the

Fig. 1. The history of wafer diameter progression of SiC [1012] compared to

Silicon (Si) [1316] and Gallium Arsenide (GaAs) [10,17] grown by the Czochralski
method. Two data points at the same diameter indicate the rst published
demonstration followed by a wider spread technology adaptation for commercial
production. Note for SiC: rst demonstration of 100 mm 6H SiC in 1999, rst
demonstration of 100 mm 4H SiC in 2001.

Fig. 2. Stress birefringence of a 41 off-axis 5-in n-type 4H-SiC wafer with a

micropipe density o 1 cm2 , indicating a low stress state and high quality (the
macroscopic contrast is due to the natural birefringence of off-axis SiC).

formation of crystallographic defects in SiC boules. As conditions

inside the growth crucible are not easily accessible at typical
growth temperatures above 2000 1C, numerical simulations have
been used to optimize thermal boundary conditions and mass
transfer processes. Specically, we have investigated the impact
of the crystal shape on the shear and von-Mises stress magnitude
and uniformity within the growing boule, impacting the generation and movement of dislocations, as well as the probability of
ingot cracking in post-growth processing steps [1820]. A key
nding indicates that any aggressive crystal expansion strategy to
increase SiC wafer diameters is problematic and needs to be
balanced carefully against the necessary development time to
step up from one commercial substrate size to the next.
Micropipes in SiC wafers are considered killer defects for device
production [1]. Recent progress at Dow Corning has allowed us to
rapidly decrease micropipe densities in both 76 mm and 100 mm
n-type 4H-SiC production lines to median levels o0:1 cm2 (Fig. 3)
and demonstrate micropipe free material over a full 100 mm
diameter as conrmed by Synchrotron White Beam X-ray Topography (SWBXRT). As micropipes at these low densities are not
considered to be the primary device yield limiting factor increased
emphasis is now put on reducing also elementary dislocations in SiC.
Studies on SiC pn-diodes indicate, that 1c-screw dislocations can
increase reverse leakage and soften the breakdown IV knee [21],
while basal plane dislocations in the substrate can transfer into the
device epitaxy, causing a drift of the forward voltage in bipolar
devices due to the phenomenon of stacking fault formation [22].
Investigations by SWBXRT and molten KOH etch pit analysis of
100 mm wafers demonstrate threading screw dislocation densities
o 500 cm2 . For a detailed discussion of observed mechanisms
contributing to the reduction of such dislocations during growth
see [2325]. As a direct result of reducing the shear stress srz on the
primary SiC slip systems ((0001) /1120S and 1100 /1120S
below the critical resolved shear stress of  1 MPa [18,23] relevant
for the formation of basal plane dislocations (BPD) we have also been
successful to decrease these types of dislocations down to values as
low as  3002400 cm2 in 100 mm wafers as conrmed by
SWBXRT(Fig. 4) [24]. Fig. 5 shows the systematic trend of reducing
BPDs and the total etch pit density in Dow Corning production
wafers over time as determined by molten KOH etch. This quality
improvement is also reected in the decrease of X-ray rocking curve
measurements to full width half maximum (FWHM) values of
 10 arcsec (near the resolution limit of the used X-ray system).

Fig. 3. Median micropipe densities in Dow Corning 76 mm and 100 mm n-type

4H-SiC production wafers vs. time.

St.G. M
uller et al. / Journal of Crystal Growth 352 (2012) 3942

Fig. 4. Example of SWBXRT of 100 mm 4H n-type SiC with low BPD density of
363 cm  2 (g-vector: [1120]).

41

in a recently acquired Aixtron VP2800WW 10  100 mm planetary

reactor (with an option to upgrade to 6  150 mm) to meet this
market demand. To speed up the process development we have
utilized a commercial CVD modeling software package (STR Group
Ltd.) to analyze the effects of process parameters such as gas ow
rates, temperature, pressure and C/Si ratio on the growth rate,
doping, and epi-layer thickness uniformity. The achieved surface
roughness on a typical 6:5 mm epi-layer on 41 off-axis wafers is
consistently o 1 nm (RMS on 20  20 mm2 ) as determined by
atomic force microscopy (AFM) measurement, with no step bunching observed under Normaski microscopy. Various morphological defects in SiC epitaxy such as triangles, pits and carrots are
commonly viewed as problematic for SiC device performance [1].
Epi defects have been analyzed by laser light scattering (LLS) and
device yield prediction maps were generated based on a correlation
study of device failure and epi killer defects. The combined improvements in the epitaxy process, pre-epi wafer surface preparation and
the underlying substrate quality itself have led to a reduction of
the device killer defect density from 8 cm  2 to 1.5 cm  2, averaging
4 90% device yield on a volume product like 100 mm 41 off-axis
wafers with 6:5 mm thick epi-layers. Epi-layer uniformity (s=mean)
within wafers is typically less than 3% for thickness and less than
10% for doping, respectively. The wafer-to-wafer variation is less
than 2% for both thickness and doping on a multi-wafer run with
excellent run-to-run repeatability.
3.2. Thick epitaxy on 41 off-axis wafers for high voltage applications

Fig. 5. Molten KOH etch pit analysis of 4H n-type SiC production wafers (Boxplots
with mean values for each year explicitly stated in the gures): (a) basal plane
dislocations (individual data points indicated as circles); (b) total etch pit count (stars
indicate outliers).

3. SiC epitaxy for power device applications

SiC device applications with blocking voltages in the range from

5 kV to 4 10 kV require epi-layers with a thickness of 50 to
4 100 mm. As 41 off-oriented layers usually require higher growth
temperatures than 81 off-oriented layers in order to inhibit the
formation of large 3C defects (tetrahedral-shaped pits) most published SiC thick epitaxy research is focussed on 81 off-axis substrates
and the number of groups reporting on the successful realization of
high voltage devices on 81 or 41 off-axis substrates is rather limited
[1,26]. At Dow Corning 502100 mm thick epi-layers have been
grown on 76 mm 41 off-axis Si-face substrates. Through careful
CVD experimentation optimal combinations of silicon source gas
ow, carbon source gas ow, temperature and pressure have been
found to achieve a balance of the epi-wafer properties of doping
uniformity, thickness uniformity, and morphological defects generated during the CVD process [27,28]. When the CVD epitaxy process
is implemented on low defect polished wafers (MPD 51 cm2 ,
RMS roughness o 1 nm, net scratch length o one wafer diameter)
the density of morphological defects on the epi-wafer surface is in
the range of 26 cm  2 (Fig. 6a). The epi-surface is optically smooth
and featureless in AFM scans on 20  20 mm2 areas with a RMS
roughness below or around 1 nm. Etching of the thick epitaxial lms
in molten KOH reveals basal plane defect densities as low as
110 cm  2. These thick lm epi-wafers have been characterized
using microwave photoconductive decay (m-PCD) spectroscopy and
consistently show carrier lifetimes in the range of 223 ms and as
high as 7:3 ms (Fig. 6b). Wafers with 502100 mm thick epi-layers
have been used to fabricate diodes and good spatial agreement of
failed die marked by LLS defects is found, while additional failure
modes still need to be resolved. High voltage testing has demonstrated blocking voltages near the theoretical values for 4HSiC and
recently near 10 kV Junction Barrier Schottky (JBS) diodes have been
demonstrated with an epitaxy thickness of 80 mm.

3.1. Growth in a 10  100 mm planetary reactor

4. Conclusion

As SiC power device production rapidly moves to larger

diameter SiC substrates, we have optimized our epitaxy process

We have presented the recent progress at Dow Corning in the

industrial fabrication of large diameter SiC wafers and device

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uller et al. / Journal of Crystal Growth 352 (2012) 3942

References

Fig. 6. The 100 mm thick epi on 76 mm 41 off-axis substrates (average doping:

4  1014 cm  3 and s/mean of 14.6%): (a) LLS map of morphological defects, assuming
a 2 mm  2 mm device area. The predicted yield is 92.5%, corresponding to a defect
density of 1.9 cm  2; (b) m-PCD carrier lifetime mapping (median lifetime: 7:3 ms).

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from R&D to volume production. Both the signicant quality
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SiC device technology a viable commercial platform for the next
generation of advanced high power devices.

Acknowledgements
This work was supported in part by ONR Contract No. N0001405-C-0324 (Program Ofcer Paul Maki) and by 2ARL Contract
2No. DAAD19-01-C-0067 (Program Ofcer: Dr. Bruce. Geil). We
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