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VHDL codes for common Sequential

Circuits:
Positive edge triggered JK Flip Flop with reset input
Here is the code for JK Flip flop which is positive edge triggered.The flip flop also has a reset input which
when set to '1' makes the output Q as '0' and Qbar as '1'.

--libraries to be used are specified here


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity JK_Flipflop is
port ( clk:
in std_logic;
J, K:
in std_logic;
Q, Qbar:
out std_logic;
reset:
in std_logic
);
end JK_Flipflop;
--architecture of entity
architecture Behavioral of JK_Flipflop is
--signal declaration.
signal qtemp,qbartemp : std_logic :='0';
begin
Q <= qtemp;
Qbar <= qbartemp;
process(clk,reset)
begin
if(reset = '1') then
qtemp <= '0';
qbartemp <= '1';
elsif( rising_edge(clk) ) then
if(J='0' and K='0') then
NULL;
elsif(J='0' and K='1') then
qtemp <= '0';
qbartemp <= '1';
elsif(J='1' and K='0') then
qtemp <= '1';
qbartemp <= '0';
else
qtemp <= not qtemp;
qbartemp <= not qbartemp;
end if;
end if;
end process;
end Behavioral;

--Reset the output.

--No change in the output


--Set the output.
--Reset the output.
--Toggle the output.

4 bit Synchronous UP counter(with reset) using JK flip-flops


Here is the code for 4 bit Synchronous UP counter.The module uses positive edge triggered JK flip flops for
the counter.The counter has also a reset input.The JK flipflop code used is from my previous blog.For simulating
this counter code,copy and paste the JK flipflop code available at the above link in a file and store the file in the
same directory with other .vhd files.
The top module code is given below:

--libraries to be used are specified here


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity syn_count4 is
port ( clk:
in std_logic;
reset:
in std_logic;
counter : out std_logic_vector(3 downto 0)
);
end syn_count4;
--architecture of entity
architecture Behavioral of syn_count4 is
--signal declaration.
signal J3,J4,Q1,Q2,Q3,Q4,Qbar1,Qbar2,Qbar3,Qbar4 : std_logic :='0';
begin
J3 <= Q1 and Q2;
J4<= J3 and Q3;
--entity instantiations
FF1 : entity work.JK_Flipflop
FF2 : entity work.JK_Flipflop
FF3 : entity work.JK_Flipflop
FF4 : entity work.JK_Flipflop
counter <= Q4 & Q3 & Q2 & Q1;
end Behavioral;

port
port
port
port

map
map
map
map

(clk,'1','1',Q1,Qbar1,reset);
(clk,Q1,Q1,Q2,Qbar2,reset);
(clk,J3,J3,Q3,Qbar3,reset);
(clk,J4,J4,Q4,Qbar4,reset);

Example : 4 bit Ring Counter with testbench


A ring counter is a digital circuit which consists of a series of flip flops connected together in a feedback
manner.The circuit is special type of shift register where the output of the last flipflop is fed back to the input of
first flipflop.When the circuit is reset, except one of the flipflop output,all others are made zero. For n-flipflop ring
counter we have a MOD-n counter. That means the counter has n different states.
The circuit diagram for a 4 bit ring counter is shown below:

I have written a VHDL code for a 4-bit ring counter which has the following states:
0001 - 0010 - 0100 - 1000 ....
The code is posted below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;
architecture Behavioral of ring_counter is
signal temp : unsigned(3 downto 0):=(others => '0');
begin
DAT_O <= temp;
process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;

Example : D Flip-Flop with Asynchronous Clear,Set and Clock


Enable
As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This
is the second one in the series, a basic D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge
clock).The code is self explanatory and I have added few comments for easy understanding.

--library declaration for the module.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Asynchronous Clear,Set and Clock
Enable(negedge clock).
--Note that the clear input has the highest priority,preset being the
next highest
--priority and clock enable having the lowest priority
entity example_FDCPE is
port(
Q : out std_logic;
-- Data output
CLK :in std_logic;
-- Clock input
CE :in std_logic;
-- Clock enable input
CLR :in std_logic; -- Asynchronous clear input
D :in std_logic;
-- Data input
PRE : in std_logic
-- Asynchronous set input
);
end example_FDCPE;
architecture Behavioral of example_FDCPE is
circuit.
begin

--architecture of the

--"begin" statement for architecture.

process(CLR,PRE,CLK) --process with sensitivity list.


begin --"begin" statment for the process.
if (CLR = '1') then --Asynchronous clear input
Q <= '0';
else
if(PRE = '1') then --Asynchronous set input
Q <= '1';
else
if ( CE = '1' and falling_edge(CLK) ) then
Q <= D;
end if;
end if;
end if;
end process;

--end of process statement.

end Behavioral;

Example : D Flip-Flop with Synchronous Reset,Set and Clock


Enable
As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This is
the first one, a basic D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clock).The code is
self explanatory and I have added few comments for easy understanding.

--library declaration for the module.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Synchronous Reset,Set and Clock
Enable(posedge clk).
--Note that the reset input has the highest priority,Set being the next
highest
--priority and clock enable having the lowest priority.
entity example_FDRSE is
port(
Q : out std_logic;
-- Data output
CLK :in std_logic;
-- Clock input
CE :in std_logic;
-- Clock enable input
RESET :in std_logic; -- Synchronous reset input
D :in std_logic;
-- Data input
SET : in std_logic
-- Synchronous set input
);
end example_FDRSE;
architecture Behavioral of example_FDRSE is --architecture of the
circuit.
begin --"begin" statement for architecture.
process(CLK) --process with sensitivity list.
begin --"begin" statment for the process.
if ( rising_edge(CLK) ) then --This makes the process
synchronous(with clock)
if (RESET = '1') then
Q <= '0';
else
if(SET = '1') then
Q <= '1';
else
if ( CE = '1') then
Q <= D;
end if;
end if;
end if;
end if;
end process; --end of process statement.
end Behavioral;