Flip Chip Underfill Reliability of CSP During IR Reflow Soldering

Yumiko Ohshima, Takahito Nakazawa, Kazuhide Doi, Hideo Aoki, Yoichi Hiruta
Advanced Packaging Development Section
Semiconductor Advanced Packaging Engineering Department
TOSHIBA Corporation

33, Shin-Isogo-cho, Isogo-ku, Yokohama 235, Japan

Phone: +81-45-759-1360 Fax: +81-45-759-1496 E-mail: ohshima@apat.mel.toshiba.co.jp

Abstract
Reliability of flip chip CSP ( Chip Scale Package ) w a
investigated. The underfill resin for CSP has high
saturation content of moisture absorption, compared to a
conventional mold resin.
The IR reflow test showed no delamination at the
underfill interfaces and no package cracking in a flip chip
CSP with a ceramic substrate and voidless underfill under
the JEDEC LEVEL 1 and 2 conditions. However, it was
found out that delamination and package cracking occurred
in the IR reflow test under the JEDEC LEVEL 1 when the
flip chip CSP has voids in the underfill.
The underfill reliability results by IR reflow test
confirmed superior reliability of the flip chip CSP with a
ceramic substrate and void controlled underfill.

Top view

Bottom view

Figure 2. Photo of fabricated CSP

The primary purpose of underfilling is to guarantee
interconnection reliability. Underfill resin absorbs stress
caused by the mismatch in the coefficient of thermal
expansion (CTE) between the chip and the substrate. The
underfill is formed by capillary action into the cavity
between the chip and the substrate [ 2 ] . Figure 3 shows the
relationships of filler content, viscosity and CTE.

Introduction
Flip chip technology has become important and
popular because of its effectiveness in realizing CSP and
high packing density for electronic products.
Figures 1 and 2 show the developed flip chip CSP with
the eutectic solder bumps [l].

150

4
a

. 40

b
.-3 10-

. 30
20

s1

6
0.5 I1.5mm

10

11

Solder Bump

20

40

60

Filler Content[wt%]

80

2
e

Figure 3. Filler content vs. viscosity and CTE

1.2"

Om5

The filler content of the unederfill resin is 40-60 wt %,

which is smaller than that of the mold resin which is 80-90
wt %. The results achieved by using a high filler content
are high viscosity and reduced resin flow, wherein
underfilling becomes impossible.
The CTE of the underfill is controlled by the filler
content as shown in Fig. 3. When the filler content is IOW,
the CTE value is high and when filler content is high, the
viscosity is high. By considering both of the viscosity and

Ceramic Carrier

Figure 1. Cross sectional view of flip chip package

0-7803-3575-9/97/$10.001997 IEEE

124

the CIE, the underfill resin with filler content of 55 wt %

was chosen.
The Fatigue life of this flip chip interconnection has
been investigated and interconnection reliability has been
confirmed by various kinds of the reliability test [1][3].
However, few paper had reported the underfill resin
reliability of flip chip CSP.
In this paper, underfill resin reliability is reported after
humidity exposure and IR reflow testing.

\ + /

Experiment

/+--

Initial

Moisture Absorption

Moistvure

(During Storage)
Reflow

@ Reflow
(Deramination I Expansion)

Presumable Mechanisms
The reliability of a conventional molded package has
been extensively investigated and analyzed, and measures
have been taken to ensure improved package cracking
reliability. Figure 4 shows the mechanism for cracking in a
conventional molded package. At first, the molded resin
absorbs moisture during storage. A delamination is
initiated at the high temperature of reflow soldering. Then
the delamination area at the interface is expanded by the
vaporization of the absorbed moisture, and this causes
resin cracking [4] [5].
Package cracking by absorbed moisture during storage
is thought to occur in underfill in a flip chip CSP as well.
In the case of flip chip CSP, voids in the underfill may be
introduced during the underfilling process in the case of
flip chip CSP. Because it is probable that air can be
trapped in the underfill when underfill is formed by
capillary action, or a volatile component of the underfill
resin can occur when the underfill is cured. It is probable
that this occurred void in the underfill is a bad influence on
underfill reliability. Therefore, voided flip chip CSP and
voidless flip chip CSP was investigated.
Figure 5 shows two probable types of package cracking
mechanisms that can be presumed to occur in the underfill.
The two presumed mechanisms (1) and (2) were described
as follow:
(1) The first type is the optimum flip chip CSP that is
voidless in the underfill. At first, the underfill absorbs
moisture during storage. Delamination is caused by
thermal stress during IR reflow soldering and occurs at the
underfill interfaces, where the absorbed moisture gets into
the delamination. Then, the delamination expands due to
moisture vaporization, which results in package cracking.
This is almost the same mechanism as seen with a molded
package.
(2)The second type is the voided flip chip CSP. The
package cracking mechanism is as follows. Initially, the
package contains voids in the underfill. The underfill
absorbs moisture during storage. The absorbed moisture
gets into the void. The delamination expands from the
position of the voids, due to the moisture vaporization. As
a result, package cracking occurs.

Package Cracking

Crack
!

Figure 4. Package cracking mechanism

for mold package

0 lnitini

@Moisture Absorption

Maistun

@ Pnckage Crncking

/
Cnek
(1)VOIDLESS

Crick

(2)VOID

Figure 5. Package cracking mechanism

for flip chip CSP

The Moisture Absorption Character

The nature of moisture absorption is important for
package cracking evaluation. Therefore, the moisture
absorption rate for underfill resin was measured. Cured
underfill resin was used as the test vehicle, and the size
was 30 mm square and 3 mm thick. The test vehicle was
baked completely dry, and the moisture absorption rate
was measured under three conditions : 85 C I 85 rh %,
85 C / 60 rh % and 85 C / 40 rh %. From the results,
the moisture absorption characteristics ( i.e., diffusion
coefficients, saturated content of moisture, density ) were
calculated.

Evaluation Method
Package cracking during IR reflow soldering was
tested by measuring the package deformation at reflow
temperature ( 240 C ) [l] [3] [4]. Figure 6 shows the
125

Evaluation results

schematic view of the reflow test apparatus.

Gap Sensor

Moisture Absorption Characteristics

Figure 8 shows the moisture absorption rate for the
underfill resin. Table 2 shows the calculated results of
moisture absorption characteristics.
The saturation condition of a flip chip CSP with a 10
mm square chip size was calculated from the results as
shown in Table 2. A flip chip CSP with this size didn't
extend to the saturation condition under 85 "c I 8 5 rh % 1
168 hr. Therefore the saturation time for the flip chip CSP
was calculated.

package
/

Figure 6. Schematic view of reflow test

10000

The test vehicles were stored under highly saturated

humid conditions achieving to JEDEC LEVEL 1 and 2.
Next, the test vehicles were immersed into an inactive fluid
at 240 "C for 75 seconds and then the package deformation
was measured by a probe with a gap sensor. Using this
method, it becomes clear whether or not package cracking
occurs. Flip chip CSPs were used as test vehicles. The
chip size was 10 mm X 10 mm X 0.65 mm (t) and the
substrate size was 12 mm x 12 mm x 0.45 mm (t).
Both voidless and void-in-the-underfill test vehicles were
prepared to inspect the two types of package cracking
mechanisms proposed earlier.
Next, the underfill for the test vehicles was observed
by the scanning acoustic tomograph.

.*

2
:
d

1000

.-*

5
100
1

10

100

10000

1000

Moisture Absorption Time[Hr]

Figure 8. Moisture absorption rate

Table 2. Underfill resin characteristics
package lmoisture condition1 density biffusion coefficied saturated moisture

Shear Strength
CSP

The underfill has interfaces between the chip and the

substrate. Shear tests were carried out to grasp the
delamination position and the adhesive strength. The test
vehicle used was a flip chip CSP of 5 mm square. The tests
were conducted before moisture absorption and after
JEDEC LEVEL 1 test conditions. Table 1 shows the test
conditions and Fig. 7 shows the shear test method.

Shear Height fmm]

Shear Speed [mm/sec]

[mg/"3?

[mmUh]

85/85

1.57

0.018

5600

85/60

1.54

0.025

4057

85/40

QFP

85/85

1.57

1.75

absorption rate [ppm]

0.031

0.044

3060

4200

The results show in Table 2, underfill resin was

regarded as Fick's type diffusion mechanism, because the
slopes of the moisture absorption curves are nearly parallel
for the same temperature and linear in behavior for the
early non-saturated times. The simplified equation of
Fick's law can be expressed as :

Table 1. Shear Test Condition

1 Shear Temperature ["c] I

[wt%]

240
0.035
0.31

I-?
Die Shear Tool

Test Vehicle

where t[hr], m(t) [ppm], m(s) [ppm], I["]

and D[mm2/h]
are the passage of time, moisture absorption rate, saturated
moisture absorption rate, the distance of the underfill and
diffusion coefficient.
From this equation (a) and the calculated results
( Table 2 ), it was calculated that the time for extending to
a saturated condition is 1090 hours in the flip chip CSP
with 10"
square chip size.

Figure 7. Schematic view of shear test

126

Results of Reflow Test

The reflow test was carried out for two kinds of flip
chip CSPs, in order to confirm the above presumed two
mechanisms. One was the usual flip chip CSP with a
voidless flip chip CSP. The other was the voided flip chip
CSP.
First, the test results of voidless flip chip CSP are
described. The number of cracked packages was 0 p I 5 p
under the 85 "c / 60 rh % 1 168 hr ( JEDEC LEVEL 2 )
and the 85
1 85 rh % 1 168 hr ( JEDEC LEVEL 1 ) test
conditions, each. In addition, the number of cracked
packages was Op l 5 p under the 85
I85 rh % I 1090 hr
test condition.
Next, the test results of voided flip chip CSP are
described. The number of cracked package was 6 p I 17 p
under the 85
1 85 rh % 1 168 hr test conditions
( JEDEC LEVEL 1). And the cracked package was
delaminated at the interface between the chip and the
underfill in all cases.
Figure 9 shows an example of the results for changes in
package thickness measured by the preceding reflow test
when the underfill was voidless and when it had voids.
Figures 10 and 11 show an example of the results observed
with a scanning acoustic tomograph for voidless and
voided flip chip CSP, respectively. Figure 12 shows a
cross section of the package cracking, as seen through a
scanning electron microscope.

Initial

After Reflow

"c

Figure 11.Results with scanning acoustic tomograph

for voided flip chip CSP

"c

"c

90
E 70
=i
50

.*
m

-30
-50

Moreover, the relationship between the void size and

the number of package cracking occurrences was obtained
( Figure 13 ). It was confirmed that packages with a void
area, whose size was more than 20% of the chip underfill
area. cracked.

r
I

&/

Voided Flip Chip CSP

30

10
-10

Figure 12. Package cracking cross section

1
'

15

30

\ 45

5 90

60

ij ::

Voidless Flip Chip CSP

p1

6o
50

$E

Time[sec]

Figure 9. Results for a change in package thickness

10
0

#I #2 #3 #4 #5 #6 It7 #8 #9#10#11#12#13#14#15#16#17

TEST VEHICLE
Figure 13. Occurrence rate of package cracking
for void area

Shear Test

Initial

After Reflow
The previously mentioned shear test was performed
before moisture absorption and under JEDEC LEVEL 1
test conditions. Tables 3 and 4 show the shear strength
value and the mode of fracture results.

Figure 10. Results with scanning acoustic tomograph

for voidless flip chip CSP
127

References :
Delamination
Mode

Vehicle
No.
1

Strength
[MPa]
4.93

11.41

Interface between the substrate and

the underfill

7.66

Interface between the substrate and

[1]C. Takubo, N.Hirano, K. Doi, H. Tazawa, E. Hosomi

and Y. Hiruta, Eutectic Solder Flip Chip Technology
for Chip Scale Package, in Proceedings of the IEMT
1996.
[2]T. Nakazawa, T. Masunaga, H. Aoki, Y. Ohshima, and
Y. Hideo, Epoxy Resin Under-filling for 250 ,U m pitch
Area Bump Interconnections, IEEE 1996 in
Binghamton, NY.
[3]N. Hirano, K. Doi, E. Hosomi, H. Tazawa, K.
Shibazaki, C. Takubo, T. Okada, Y. Hiruta and T. Sudo,
Flip-Chip Bonding Process for CSTP Interconnected
by Eutectic Solder Bumps, Workshop on VLSI and
Microsystem Packaging Techniques and Manufacturing
Technologies, in Italy, May 5, 1996.
[4]Y. Inoue K. Sawada N. Kawamura and T. Sudo, A
Synthetic Criterion for Level-1 Crack-free Package
Proposal of a Superior Package Structure, in
Proceedings of the 46th ECTC 1996, pp. 71-77.
[5]T. Nakazawa K. Sawada Y. Hiruta and T. Sudo,
Analysis of Package Cracking During The Reflow
Soldering Process. --Establishment of the Simplified
Cracking Estimation Method--, in Proceeding of the
IEICE,1992, pp. 45-52.

Leaving 50%
on the substrate and the chip

the underfill

Vehicle
No.
1

Strength
[MPa]
2.01

Delamination
Mode

2.20

Interface between the chip and the

underfill

2.00

Interface between the chip and the

underfill

Interface between the chip and the

underfill

The shear strength test average was 8 MPa before

moisture absorption and there were two delamination
modes. The first mode was at the interface between the
underfill and the substrate. The second mode was at the
both interfaces between the underfill and the substrate and
between the underfill and the chip.
The delamination mode under JEDEC LEVEL 1
condition changed to between the chip and the underfill
from that before moisture absorption. The shear strength
test average was 2.07 MPa and the delamination area was
at the interface between the chip and the underfill in all
cases under JEDEC LEVEL 1 condition. This
delamination area agreed with the package cracking
position.

Conclusions
The underfill resin showed high saturated moisture
absorption. In flip chip CSP with ceramic substrate, it was
confirmed that package cracking didnt occur, if the
underfill had no void. In addition, package cracking
occurs, if the package had void-in-the-underfill area which
exceeds 20% of the chip area.

The shear strength of the moisture absorbed vehicles

fell quarter compared to that of the moisture unabsorbed
vehicles before moisture absorption. The delamination
mode was at the interface between the chip and the
underfill. However, even this fallen strength causes no
problem in the case of viudless underfill.
Therefore, it is confirmed that the reliability during
reflow soldering for flip chip CSPs with a ceramic
substrate is assured when void formation in the underfill is
controlled.

128