Faster Close Webinar

IC Compiler 2009 Webinar Series
Faster Design Closure with

Congestion Minimization
Design Compiler Graphical & IC Compiler
JC Lin, R&D VP
Janet Olson, R&D Group Dir
June 9th, 2009
Synopsys2009
Welcome!
Congestion
Minimization
Previous topics:
Signoff-driven closure
In-design physical verification
In-Design
Physical
Verification
IC
Compiler
SignoffDriven
Closure
Upcoming topic:
In-design rail analysis on 6/25
Todays topic:
In-Design
Rail
Analysis
Congestion minimization
Recordings and presentations available at

www.synopsys.com
Synopsys2009
Welcome!
Presenters Introduction
Dr. JC Lin
R&D VP, Placement and CTS in IC Compiler
Janet Olson
R&D Group Dir, Design Compiler Graphical
Synopsys2009
Agenda
Routing congestion and its sources
Congestion causes schedule delays
Design Compiler Graphical and IC Compiler

Best solution for congestion minimization
Traditional congestion minimization flow

Iterations required between synthesis and place & route
Congestion minimization with Design Compiler Graphical

Faster convergence with higher schedule predictability
Summary
Synopsys2009
Agenda



Summary
Synopsys2009
Routing Congestion: A Problem

Almost Every IC Designer Faces
Congestion occurs
when the number of
wires going through a
routing region exceeds
its capacity
Congestion Map
To meet timing
To avoid blockages
Due to area constraints
To resolve congestion, Place & Route tools need to make
intelligent tradeoff between timing QoR and routability
Synopsys2009
Sources of Routing Congestion

Floorplan
i.e. macro-placement
RTL structures
Floorplan-related
i.e. MUX trees
High utilization
i.e. limited room
Synopsys2009
RTL-related
Congestion Can Be A Major

Contributor To Schedule Delays
Synopsys2009
Customer A
Customer B
3 months delay
RTL modifications
3 months delay
RTL modifications
90 nm
500K instances
Consumer Electronics
65 nm
400K instances
3G Wireless
Agenda



Summary
Synopsys2009
Galaxy Platform Evolution

From Dataflow to Smart Look Ahead Technology
Physical
Synthesis
Design
Planning
Synthesis
Signoff
Design
Planning
Synthesis
Signoff
Signoff
Synthesis
Place & Route
Place & Route

Place & Route
2002
Dataflow
Synopsys2009
10
2004
Correlation
2007
Look Ahead
Design Compiler + IC Compiler

Leading Choice for Design Implementation
Leading Choice For Synthesis
Signoff
Design
Compiler
Best-in-class QoR
Correlation w/ layout minimizes congestion
Automated & complete power synthesis
Faster TAT with in-built test
Leading Choice For Physical Design
IC
Compiler
Synopsys2009
11
Best-in-class QoR
45nm/32nm production proven
Optimized for power and DFM
Excellent signoff correlation
Design Compiler + IC Compiler

Topographical Technology for Predictability
Timing & Area
Power
Signoff
Design
Compiler
IC
Compiler
Synopsys2009
12
Test
Design Compiler Graphical + IC Compiler

Best Solution for Congestion Minimization
Accurate prediction of congestion

Design Compiler Graphical
Early physical visualization
Congestion optimization in synthesis

IC Compiler
MCMM synthesis
Shared technology with IC Compiler
Synopsys2009
13
Agenda


Expensive iterations required
Design Compiler Graphical congestion minimization

Summary
Synopsys2009
14
Traditional Flow For Handling Congestion

Synthesis
Synopsys2009
15
Focused on timing, power,

area & test

Synthesis
Gate level Netlist
Place and Route

High congestion
discovered
Congestion
minimization
techniques
Synopsys2009
16
P&R tries to resolve

congestion
Timing driven congestionremoval
Auto-area-recovery for
high density hot spots
Congestion analysis for
floorplan adjustment and
placement controls

Synthesis
Gate level Netlist
Place and Route

High congestion
discovered
Sometimes P&R succeeds to

resolve congestion
Congestion
minimization
techniques
Synopsys2009
17

Synthesis
Gate level Netlist
Place and Route

High congestion
discovered
Sometimes P&R does not

succeed
Congestion
minimization
techniques
Synopsys2009
18
Convergence Issues with Traditional Flow

1. Congestion is Detected too Late in the Design Cycle
Design is optimized
without considering the
effect of congestion
RTL optimizations are
optimistic
Congestion removal in
P&R leads to tradeoff
between timing QoR
and routability
Increased wirelength
degrades timing QoR
Synopsys2009
19
Synthesis
WNS: -0.46ns
Place & Route

WNS: -0.81ns
Area increase post
placement: 15%

2. Congestion Removal in P&R May Require FP Changes
Congestion removal
in P&R may need
floorplan adjustments
late in the flow
Schedule gets
impacted
Possible increase in
die size
Timing degradation
because of long paths
Synopsys2009
20
Congestion with
original channel size
Congestion with
increased channel size

3. Some Congestion Cannot Be Resolved in P&R
RTL structures can be

intrinsically congested
i.e. large MUX trees,
ROM
Not trivial to identify in
P&R
Intelligent synthesis
algorithms needed to
free logic from
intrinsic congestion
Synopsys2009
21
ROM
Conclusion
Reducing congestion in
P&R can be expensive
At times, congestion
cannot be resolved in P&R
Synthesis
Place &
Route
A solution that considers the effect of

congestion in RTL synthesis is needed
Synopsys2009
22
Ideal RTL Synthesis Solution

Tight correlation between synthesis and P&R
Shared technology
Early visibility into routing congestion

Assessing and fixing congestion in synthesis
Concurrent congestion optimization

Together with timing, area, power and test
Better starting point for layout

Faster convergence
Synopsys2009
23
Agenda



Summary
Synopsys2009
24

Introduction
Key capabilities
best practices
Synopsys2009
25

Extending Topographical Technology to Routing Congestion
Breakthrough synthesis
capabilities
DC Graphical
Congestion prediction
Congestion optimization
Physical visualization
MCMM Synthesis
Shares technology with ICC

IC Compiler
Synopsys2009
26

Delivering Unmatched Productivity
Accurate Congestion
Prediction
Early Physical
Visualization
Congestion
Optimizations
Early visibility into

congestion
Layout Viewer aids

debugging
Optimizations for
reduced congestion
Eliminate Iterations
due to congestion
Debug congestion
and timing Issues
Create a better startpoint for P&R
Synopsys2009
27

Utilizing ICC Technology to Address Routing Congestion
RTL &
Constraints
Optimization
Virtual placement is
congestion driven
using global route
Net Model
Accuracy
Netlist
Timing, power, area, test and
congestion optimized
Highly correlated to ICC
Synopsys2009
28
Congestion
optimization in
synthesis allows for
larger changes

Introduction
Key capabilities
Congestion prediction
Physical visualization
Congestion optimizations

best practices
Synopsys2009
29

Congestion Prediction Estimation
Global Route-based
congestion estimation
Design partitioned into

virtual array of Global
Route Cells (GRCs)
Shared Synopsys Global

Route technology
Virtual Grid
Virtual Route
i
Synopsys2009
Violation = # of wires max # allowed wires

30

Congestion Prediction - Reporting
Text based reporting with report_congestion

Similar format as IC Compiler
Provides quick assessment of congestion status

Design : Test
Version: B-2008.09-SP3
Date
: Fri Feb 13 11:38:50 2008
****************************************
Both Dirs: Overflow = 4651

H routing: Overflow = 2386
V routing: Overflow = 2265
i
Synopsys2009
Max = 5 (10 GRCs) GRCs = 3401 (0.59%)

Max = 3 (50 GRCs) GRCs = 1788 (0.31%)
Max = 3 (18 GRCs) GRCs = 1961 (0.34%)
Overflow = {Violation(i) x #GRCs with violation(i)}

31

Physical Visualization
Layout view
Congestion map
Congestion due
to Floorplan
Long path due
to macro location
Congestion
due to RTL
Debug timing issues due to

layout
Synopsys2009
Detect and debug sources of

congestion
Early Detection and Debug of Layout Issues

32

Physical Visualization - Congestion Analysis
Congestion Map in Layout Viewer
7
6
5
4
3
2
1
0
-20
0
0
Synopsys2009
33

7
6
5
4
3
2
1
0
-20
0
0
Synopsys2009
34

7
6
5
4
3
2
1
0
-20
0
0
Synopsys2009
35

7
6
5
4
3
2
1
0
-20
0
0
Synopsys2009
36

Congestion Optimizations
ROM Example
Optimizes highly connected
logic structures
4Kx16 ROM
case (a)
12'h000:
12'h001:
12'h002:
12'h003:
12'h004:
12'h005:
z
z
z
z
z
z
=
=
=
=
=
=
16'h991e;
16'hbf94;
16'hc0bf;
16'h991e;
16'hbf84;
16'hc0cf;
Creates self-contained substructures to minimize wire

crossing
::::::::::::::::::::::
12'hffe: z = 16'ha1af;
12'hfff: z = 16'h0c0c;
endcase
Performs congestion-driven
virtual layout optimizations
Timing/Area
Congestion-Aware
Creates a Better Starting Point for Place and Route

Synopsys2009
37
DC Graphical + IC Compiler Speed Up

Design Closure
IC Compiler
DC Graphical
Congestion
Prediction
Correlated
Congestion
Optimization
Correlated
Synopsys2009
38

Congestion Optimizations for Adaptive Scan Compression
High compression levels can
impact congestion
High number of global connections
for de/compressor logic
Many scan chains routes required
Adaptive scan compression

congestion optimizations
Routing friendly sharing of
compressor/de-compressor logic
Scan chain partitioning to reduce
congestion
Synopsys2009
39
Scan de-compressor logic

Congestion Optimization for 50X Adaptive Scan
Pre DFT
Post DFT
Post ICC
Pre DFT
Post DFT
Post ICC
No Congestion
Optimization
Congestion
Optimization
Synopsys2009
40

Congestion Optimizations Complement ICC
Source of Identify/Fix phase
congestion
Type of optimization
RTL structure
Identify in DC Graphical
Fix in DC Graphical
Logic based: netlist

structuring, mapping,
decomposition
Floorplan
or ICC
Fix in ICC
Floorplan based: MinChip,

manual floorplan updates
High cell
density
or ICC
Fix in ICC
Placement based: cell

spreading
Synopsys2009
41

Introduction
Key Capabilities
best practices
Synopsys2009
42

Best Practices For Faster Design Convergence
Use same logical and physical libraries
Use same library constraints
Ensure physical library cells exist for all logical library cells
Avoid synthesis with missing designs (black-boxes)
Use the same logical constraints

Avoid over constraining in Design Compiler
Use the same physical constraints

Use a floorplan, if available in DC
Shared global physical variable and optimization settings
See White Paper DC Ultra Accelerating Design Closure on
Synopsys2009
www.synopsys.com/Tools/Implementation/RTLSynthesis
43

Consistency Checker to Ensure Convergence
DC
Settings
ICDC
Compiler
Ultra
DC
Correlation issues often due to

inconsistent settings
Automated checking compares settings
and highlights differences for:
Netlist
Consistency
Checker
IC
ICCompiler
Compiler
ICC
Settings
Library setup
Variable/command settings
Timing constraints
Physical constraints
Available as SolvNet article 026366

https://solvnet.synopsys.com/retrieve/026366.html
Synopsys2009
44
Agenda



Summary
Synopsys2009
45

Delivers Faster Turnaround Time & Predictable Schedule
Tight correlation between synthesis and P&R

Shared technology
Early visibility into routing congestion

Assessing and fixing congestion in synthesis
Concurrent congestion optimization

Together with timing, area, power and test
Synopsys2009
46
Better starting point for layout

Faster convergence

Best Solution for Congestion Minimization
Congestion can be a major

contributor to schedule
delays
Traditional congestion
minimization flow may have
convergence issues
IC Compiler
Synopsys2009
47

addresses congestion during
synthesis providing a better
starting point for IC Compiler
for faster closure
Predictable Success
Synopsys2009
48

Faster Close Webinar

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Faster Close Webinar

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IC Compiler 2009 Webinar Series

Faster Design Closure with

IC Compiler 2009 Webinar Series

Recordings and presentations available at

IC Compiler 2009 Webinar Series

IC Compiler 2009 Webinar Series

Design Compiler Graphical and IC Compiler

Traditional congestion minimization flow

Congestion minimization with Design Compiler Graphical

IC Compiler 2009 Webinar Series

Design Compiler Graphical and IC Compiler

Traditional congestion minimization flow

Congestion minimization with Design Compiler Graphical

IC Compiler 2009 Webinar Series

Routing Congestion: A Problem

IC Compiler 2009 Webinar Series

Sources of Routing Congestion

i.e. MUX trees

IC Compiler 2009 Webinar Series

Congestion Can Be A Major

IC Compiler 2009 Webinar Series

Design Compiler Graphical and IC Compiler

Traditional congestion minimization flow

Congestion minimization with Design Compiler Graphical

IC Compiler 2009 Webinar Series

Galaxy Platform Evolution

Place & Route

Place & Route

IC Compiler 2009 Webinar Series

Design Compiler + IC Compiler

Leading Choice For Synthesis

IC Compiler 2009 Webinar Series

Design Compiler + IC Compiler

Timing & Area

IC Compiler 2009 Webinar Series

Design Compiler Graphical + IC Compiler

Accurate prediction of congestion

Early physical visualization

Congestion optimization in synthesis

Shared technology with IC Compiler

IC Compiler 2009 Webinar Series

Design Compiler Graphical and IC Compiler

Traditional congestion minimization flow

Design Compiler Graphical congestion minimization

IC Compiler 2009 Webinar Series

Traditional Flow For Handling Congestion

Focused on timing, power,

IC Compiler 2009 Webinar Series

Traditional Flow For Handling Congestion

Place and Route

P&R tries to resolve

IC Compiler 2009 Webinar Series

Traditional Flow For Handling Congestion

Place and Route

Sometimes P&R succeeds to

IC Compiler 2009 Webinar Series

Traditional Flow For Handling Congestion

Place and Route

Sometimes P&R does not

IC Compiler 2009 Webinar Series

Convergence Issues with Traditional Flow

Place & Route

IC Compiler 2009 Webinar Series

Convergence Issues with Traditional Flow