Depuracin mediante ChipScope Pro

Objetivos

Ver como se utiliza la herramienta ChipScope Pro para realizar

la depuracin del sistema en el dispositivo
Ver los distintos cores que se utilizan con la herramienta
ChipScope Pro

ChipScope Pro 2

Contenido

ChipScope Pro 3

Introduccin
Depuracin utilizando ChipScope Pro
Insertar un core ChipScope Pro
Resumen
Prctica 6: ChipScope Pro

Depuracin tradicional
Es problemtico acceder a las seales internas del sistema

No hay visibilidad interna

Pads
IO IO
Pads

Como accedo al bus de sistema?

IP
Core

IP Cores

Custom
Logic

No se puede acceder a la parte

interna de los cores

CPU
Core

Custom
Core
Memory
Array

Logic BIST
Access
Memory BIST
Custom Boundary Scan TAP Controller

ChipScope Pro 4

Utilizar JTAG
IO Pads

IO Pads

Embedded System Bus

Sobrecarga al sistema al establecer

la interface con el bloque JTAG

Depuracin tradicional
Pines dedicados conectados a un analizador lgico

Virtex-II Pro

External Logic
Pins

XC2VP20
FF1152

Analyzer

Probe
points

Requieresmucho I/O dedicado a depuracin

Llevar las seales a pines de I/O genera problemas de ruteo

Solucin poco flexible

Es muy dificultoso agregar pines de depuracin adicionales sin

reimplementar todo el sistema

La visibilidad a las seales internas es muy limitada

ChipScope Pro 5

Contenido

ChipScope Pro 6

Introduccin
Depuracin utilizando ChipScope Pro
Insertar un core ChipScope Pro
Resumen
Prctica 6: ChipScope Pro

Depuracin con Chipscope

Usar ChipScope Pro permite el acceso a todas las seales internas

Hay visibilidad completa del interior

de la FPGA

Pads
IO IO
Pads

ILA

ILA

Se utiliza la herramienta ChipScope Pro

Integrated Logic Analyzer

IBA Custom

IP
Core

Logic

Se puede acceder a los buses del

sistema

PPC405
Core
Memory
Array

Custom ILA
Core

Se utiliza la herramienta ChipScope Pro

Integrated Bus Analyzer

La depuracin es flexible

Se puede acceder a cada seal y/o

remover el acceso en cualquier
momento sin reimplementar el sistema

ILA
ICON

Boundary Scan TAP Controller

ChipScope Pro 7

IO Pads

IO Pads

Embedded System Bus

Utilizar los cores de acuerdo a la

necesidad
Virtual Input Output
Core (VIO)

Integrated Logic Analysis

Core (ILA)

Bridge

OPB Bus

PLB and OPB specific

Bus analysis cores
Protocol detection
Debug and verify control,
address, and data buses

Access internal nodes and signals

Debug and verify signal behavior
Define detailed trigger conditions

OPB GPIO

Arbiter

User Logic

PLB Bus

Integrated Bus Analysis

Core (IBA)

Aurora

Virtual Inputs and Outputs

Stimulate logic with pulse
trains

OPB SDRAM

Agilent Trace Core 2 (ATC2)

Agilent created core enabling

On-chip debug of Xilinx FPGAs using
Agilent FPGA Dynamic Probing

Los cores ChipScope Pro se colocan directamente sobre la lgica

Se puede acceder a cualquier seal y depurar a la velocidad del reloj de sistema
ChipScope Pro 8

Depuracin con ChipScope Pro

Integrated Logic Analyzer
ChipScope Pro
JTAG

Probe
points

ILA Block
RAM

Xilinx FPGA

No se necesitan pines de I/O para depuracin

Se accede a travs del puerto JTAG

Depuracin con ChipScope Pro

Integrated Bus Analyzer
ChipScope Pro
JTAG

System
Busses

IBA Block
RAM

Xilinx FPGA

No se necesitan pines de I/O para depuracin

Se accede a travs del puerto JTAG

On-Chip System Bus Analyzer

Puede analizar buses estandar [Processor Local Bus (PLB), On-Chip

Peripheral Bus (OPB)]
Incluye la depuracin de transacciones y detecciones de violaciones al
protocolo del bus

ChipScope Pro 10

Contenido

ChipScope Pro 11

Introduccin
Depuracin utilizando ChipScope Pro
Insertar un core ChipScope Pro
Resumen
Prctica 6: ChipScope Pro

Agregado de cores de depuracin

ChipScope Pro Core Inserter

Xilinx CORE Generator System

FPGA
FPGA Design
Design
HDL
or
HDL or Netlist
Netlist
Design
Design
Synthesis
Synthesis

Xilinx CORE Generator

Implementation
Implementation
JTAG

Real-time
Real
Real-time
Control
Control
Debug
Debug
Verification
Verification

ChipScope Pro Analyzer

ChipScope Pro 12

Netlist
Netlist Merge
Merge

Implementation
Implementation

Agrega un core en
cualquier momento

JTAG

ChipScope Pro Core Inserter

Genera y agrega cores

al comienzo del
proceso de diseo

New Source from Project

Navigator

FPGA
FPGA
Configuration
Configuration

FPGA
FPGA Design
Design
Netlist
Netlist

Agrega cores de
depuracin en sistemas
sintetizados

ChipScope Pro Analyzer

Permite ver las seales

internas del sistema

FPGA
FPGA
Configuration
Configuration
Real-time
Real
Real-time
Control
Control
Pass
Pass Fail
Fail
Margin
Margin Analysis
Analysis

ChipScope Pro Analyzer

Xilinx CORE Generator

Create New Project

Browse to directory,
give project name,
and click Save

Select core
Select family, part
ChipScope Pro 13

Xilinx CORE Generator

Define the number
of Trigger Ports
and maximum number
of sequence levels

Expanded Bit
Enable storage Values and Functions
qualifications Based on Match Type
ChipScope Pro 14

Xilinx CORE Generator

Archivo Readme con
un resumen de los
archivos generados y
su funcin

ChipScope Pro 15

ChipScope Pro Core Inserter

Insert ChipScope Pro Cores in an existing design

ChipScope Pro Core

Inserter

Add ILA and ATC2 Cores to

an Existing Design Netlist
ChipScope Pro and ISE
Integration

Set ChipScope Pro Core

Parameters and
Connections Via This Source

ChipScope File (.CDC) Added

to Project as a Source,
Associated With the Top Level
Design Source
User Double-Clicks .CDC to
Set Parameters and
Connections

Versions of ISE and

ChipScope Pro 16 Pro Must Match
ChipScope

Inserter Called
Automatically
During Translate
Stage

Automatically Launch
the ChipScope Pro
Analyzer

Chipscope Pro Core Inserter

Easily connect Chipscope Pro cores in the design

ChipScope Pro Core Inserter can now see entire

design

NGCBUILD is used
to merge top-level
netlist with all underlying
cores and sub-netlists
Encrypted files appear
as black-boxes with
ENCRYPTED tag
Cores appear as
levels of hierarchy
in Hierarchy Browser

ChipScope Pro 17

PC Based Interface Makes FPGA Debug

Easy

ChipScope Pro Analyzer functions as a logic

analyzer, bus analyzer, and control console

Access ChipScope cores via JTAG or user defined Trace port

Configure FPGA, define trigger conditions, and view data via
ChipScope Pro analyzer running on a PC
ChipScope Pro 18

Remote Debug and Verification

1. Start server on remote
system
2. Set up server host
connection on client system
3. Open cable connection from
client system
4. Configure device from client
system
5. Start debug and verification
using ChipScope Pro cores

ChipScope Pro Analyzer server connected

to fielded system enabled for remote debug
and verification
Debug remote systems from
your office via ChipScope Pro
Analyzer client

ChipScope Pro Analyzer server connected

to Xilinx development board enabled for
remote debug and verification

ChipScope Pro 19

Outline

ChipScope Pro 20

Introduction
Debugging Using ChipScope Pro
Inserting ChipScope Core
Summary
Lab 6: ChipScope Pro Lab

Summary
ChipScope Pro core provides improved visibility and access
Point access from within design
Minimal impact to design

Move to hardware faster

Accelerate evaluation, debug, and verification
Finish faster at the system rate

Increased productivity
Integrated into FPGA design flow
Rapid iteration
Share resources
ChipScope Pro 21

Outline

ChipScope Pro 22

Introduction
Debugging Using ChipScope Pro
Inserting ChipScope Core
Summary
Lab 6: ChipScope Pro Lab