ARM PROGRAMMING

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Assembly Programming
AREA subrout, CODE, READONLY
; Name this block of code
ENTRY
; Mark first instruction to execute
start
MOV r0, #10
; Set up parameters
MOV r1, #3
BL doadd
; Call subroutine
stop
MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026
; ADP_Stopped_ApplicationExit
SVC
#0x123456
; ARM semihosting (formerly SWI)
doadd ADD r0, r0, r1
; Subroutine code
BX lr
; Return from subroutine
END
; Mark end of file

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Define constant
NVIC_IRQ_SETEN0
EQU 0xE000E100
NVIC_IRQ0_ENABLE
EQU 0x1
LDR
R0,=NVIC_IRQ_SETEN0
MOV
R1,#NVIC_IRQ0_ENABLE
STR
R1, [R0]

MY_NUMBER
DCD 0x12345678
HELLO_TXT
DCB Hello\n,0

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{label} {instruction|directive|pseudo-instruction} {;comment}

Label: identify the location of program counter, can not

start by a number
Comment: any thing that follow a semicolon ; @ or C
style comment (/* */)

Addressing mode
MOV

MOV

LDR

LDR

LDR

R0,#1234
R0,R1
R0,[R1]
R0,[R1,#4]
R0,[R1,R2]

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The condition

Instruction with condition

All

instruction contain a
condition field which determines
whether the CPU will execute
them

ADD
ADDEQ

R0, R1,R2
R0,R1,R2

;R0 =R1+R2
;R0 = R1+R2 if zero flag is set

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For ARM Cortex M3, the conditional

execution sufxes are usually used for
branch instructions.

However, other instructions can also be
used with the conditional execution
sufxes if they are inside an IF-THEN
instruction block

By default, data processing operations

do not affect the condition flags (apart from
the comparisons where this is the only
effect).
To cause the condition flags to be
updated, the S bit of the instruction needs to
be set by postfixing the instruction (and any
condition code) with an S.
ADD R0,R1,R2
ADDS R0,R1,R2

;R0=R1+R2, flag will not affected

;R0=R1+R2, flag will be affected

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Thumb2 instruction set

Thumb-2 is a superset of the Thumb
instruction set

Thumb-2 introduces 32-bit instructions
that are intermixed with the 16-bit
instructions.

Thumb2 instruction set

Some of the operations can be handled by

either a Thumb instruction or a Thumb-2
instruction
ADDS R0, #1 ; Use 16-bit Thumb instruction
;by default
ADDS.N R0, #1 ; Use 16-bit Thumb
;instruction (N=Narrow)
ADDS.W R0, #1 ; Use 32-bit Thumb-2
;instruction (W=wide)

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Data Processing Instruction

All sharing the same instruction format.

Contains:





Arithmetic operations
Comparisons (no results - just set condition codes)
Logical operations
Data movement between registers

Remember, this is a load / store architecture






These instruction only work on registers, NOT memory.

They each perform a specific operation on one or two
operands.
First operand always a register - Rn
Second operand sent to the ALU via barrel shifter.

Arithmetic

Operations are:










ADD
ADC
SUB
SBC
RSB
RSC
MUL
UDIV
SDIV

operand1 + operand2
operand1 + operand2 + carry
operand1 - operand2
operand1 - operand2 + carry -1
operand2 - operand1
operand2 - operand1 + carry 1
operand1 * operand2
operand1 / operand2 (unsigned)
operand1 / operand2 (signed)

Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Examples:
ADD
SUB.N
SUBS.W

r0, r1
r3, #1
r3, r3, #1

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Using the suffix

When 16-bit Thumb code is used, an ADD

instruction changes the ags in the PSR.
32-bit Thumb-2 code can either change a ag
or keep it unchanged.
To separate the two different operations, the S
sufx should be used if the following operation
depends on the ags:
ADD.W R0, R1, R2 ; Flag unchanged
ADDS.W R0, R1, R2 ; Flag change

Comparisons

The only effect of the comparisons is to UPDATE

THE CONDITION FLAGS. Thus no need to set S bit.
Operations are:
CMP operand1 - operand2, but result not written
CMN operand1 + operand2 (signed), but result not written
TST operand1 AND operand2, but result not written
TEQ operand1 EOR operand2, but result not written

Syntax:

<Operation>{<cond>} Rn, Operand2

Examples:
CMP r0, r1
TSTEQ r2, #5

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Logical Operations

Operations are:
AND operand1 AND operand2
EOR operand1 EOR operand2
ORR operand1 OR operand2
BIC operand1 AND NOT operand2 [ie bit clear]

Syntax:
<Operation>{<cond>}{S} Rd, Rn,operand2
Examples:
AND r0, r1, r2
BICEQ r2, r3, #7
EORS r1,r3,r0

Data Movement

Operations are:

MOV{S}{cond} Rd, Operand2

MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2

Examples:
MOV r0, r1
MOVS r2, #10
MVNEQ r1,#0

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Loading full 32 bit

Instead of MOV, this instruction is
prefered:

LDR
Rd, =numeric constant

Ex:
LDR R0,=0x42

Commonly Used Memory Access

Instructions
LDRB Rd, [Rn, #offset]

Read byte from memory location Rn+ offset

LDRH Rd, [Rn, #offset]

Read half-word from memory location Rn+

offset

LDR Rd, [Rn, #offset]

Read word from memory location Rn+offset

LDRD Rd1,Rd2, [Rn, #offset]

Read double word from memory location

Rn+offset

STRB Rd, [Rn, #offset]

Store byte to memory location Rn+offset

STRH Rd, [Rn, #offset]

Store half word to memory location

Rn+offset

STR Rd, [Rn, #offset]

Store word to memory location Rn+offset

STRD Rd1,Rd2, [Rn, #offset]

Store double word to memory location

Rn+offset

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Multiple Memory Access Instructions

The exclamation mark (!) in the instruction speci es

whether the register Rd should be updated after the
instruction is completed. For example, if R8 equals
0x8000:
STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store
; (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store

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Pre-index Addressing

Post-index addressing

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Pre-index addressing
LDR

LDR

LDR

R0,[R1,#4]!
R0,[R1,R2]
R0,[R1,R2,LSL # 2]!

R0  [R1+4]
R1 = R1 + 4

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Post-index addressing
LDR

LDR

LDR

R0, [R1], #4
R0,[R1],R2
R0,[R1],R2,LSL # 2

R0  [R1]
R1 = R1 + 4

Branch instruction

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The BL and BLX command will save

return address into the LR of current
bank

To return from subroutine, restore the
PC from LR:
 MOV
PC,LR
 Another instruction to return is: BX LR

Nested function call

main
...
BL functionA
...
functionA
PUSH {LR} ; Save LR content to stack
...
BL functionB
...
POP {PC} ; Use stacked LR content to return to main
functionB
PUSH {LR}
...
POP {PC} ; Use stacked LR content to return to functionA

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If-then instruction (IT block)

IT<x><y><z> <cond>
instr1<cond>

<operands>

instr2<cond or not cond> <operands>

instr3<cond or not cond> <operands>
instr4<cond or not cond> <operands>

; IT instruction (<x>, <y>,

; <z> can be T or E)
; 1st instruction (<cond>
; must be same as IT)
; 2nd instruction (can be
; <cond> or <!cond>
; 3rd instruction (can be
; <cond> or <!cond>
; 4th instruction (can be
; <cond> or <!cond>

If-then instruction (IT block)

if (R1<R2) then
R2=R2-R1 and R2=R2/2
else
R1=R1-R2 and R1=R1/2
CMP
R1, R2
ITTEE LT

SUBLT.W R2,R1
LSRLT.W R2,#1
SUBGE.W R1,R2
LSRGE.W R1,#1

;
;
;
;
;
;
;
;
;
;

If R1 < R2 (less then)

then execute instruction 1 and 2
(indicated by T)
else execute instruction 3 and 4
(indicated by E)
1st instruction
2nd instruction
3rd instruction (notice the GE is
opposite of LT)
4th instruction

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PUSH and POP

PUSH {R0, R4-R7, R9}
POP {R2,R3}

; Push R0, R4, R5, R6, R7, R9 into

; stack memory
; Pop R2 and R3 from stack

Use POP as function return:

PUSH {R0-R3, LR}
....
POP {R0-R3, PC}

; Save register contents at beginning of

; subroutine
; Processing
; restore registers and return

Special register

Program Status Registers (PSRs)

Application PSR (APSR)

Interrupt PSR (IPSR)

Execution PSR (EPSR)

Interrupt Mask Registers

PRIMASK

FAULTMASK

BASEPRI)

Control Register (Control)

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Access the special registers

To access the special register, one can use MRS and

MSR command:
MRS
MRS
MRS
MSR
MRS
MSR
MRS
MSR
MRS
MRS
MRS
MSR
MSR
MSR

r0, APSR
r0, IPSR
r0, EPSR
APSR, r0
r0, PSR
PSR, r0
r0, CONTROL
CONTROL, r0
r0, BASEPRI
r0, PRIMASK
r0, FAULTMASK
BASEPRI, r0
PRIMASK, r0
FAULTMASK, r0

; Read Flag state into R0

; Read Exception/Interrupt state
; Read Execution state
; Write Flag state
; Read the combined program status word
; Write combined program state word
; Read CONTROL register into R0
; Write R0 into CONTROL register
; Read BASEPRI register into R0
; Read PRIMASK register into R0
; Read FAULTMASK register into R0
; Write R0 into BASEPRI register
; Write R0 into PRIMASK register
; Write R0 into FAULTMASK register

Block Data Transfer

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