SINGLE-PHASE GRID-CONNECTED PHOTOVOLTAIC SYSTEM USING RECTIFIED

SINUSOIDAL HYSTERESIS CURRENT CONTROL

MR. CHAINON CHAISOOK

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR

THE DEGREE OF MASTER OF ENGINEER (ELECTRICAL ENGINEERING)
FACULTY OF ENGINEERING
KING MONGKUTS UNIVERSITY OF TECHNOLOGY THONBURI
2002

Single-Phase Grid-Connected Photovoltaic System Using Rectified Siilusoidal

Hysteresis Current Control

Mr. Chainon Chaisook B.Eng. (Control System Engineering)

A Thesis Submitted in Partial Fulfillment of the Requirements for

the Degree of Master of Engineering (Electrical Engineering)
Faculty of Engineering
King Mongkut7sUniversity of Technology Tho~lburi
2002

Thesis Coillinittee
Chairman
(Assoc. Prof. Ake Chaisawad, P11.D.)
Co-Chairman
(Veerapol Monyaltul, Ph.D.)
blemii.(
,
......................................
Y' w
....,l.1.:,.............................

Member

...........................................&..................................

Member

(Asst. Prof. Udomsak Yangyuen)

(Assoc. Prof. Pitikhate Sooraksa, Ph. D. )

Copyright reserved
I S B N 974-456-186-6

ii

Thesis Title
Thesis Credits
Candidate
Thesis Advisors
Program
Field of Study
Department
Faculty
B.E.

Single-Phase Grid-Connected Photovoltaic System Using

Rectified Sinusoidal Hysteresis Current Control
12
Mr. Chainon Chaisook
Assoc. Prof. Dr. Ake Chaisawad
Dr. Veerapol Monyakul
Master of Engineering
Control System and Instrumentation Engineering
Control System and Instrumentation Engineering
Engineering
2545

Abstract
In most of grid-connected photovoltaic power system, a DC-DC converter boosts PV
voltage to be the DC voltage that exceeds grid voltage at high switching frequency. An
inverter then shapes the current into the sinusoidal waveform at high switching
frequency and injects the current into the grid. Unlike this research, a two-switch
forward converter has many obligations. The converter boosts PV voltage to exceed
grid voltage and shapes the output current to be rectified sinusoidal waveform at high
switching frequency; it also isolates PV voltage from the grid. The four-MOSFET
bridge inverter is only used to unfold the rectified sinusoidal current to be the sinusoidal
current at the exact grid frequency (50 5 Hz). An ADMC331, a DSP made by Analog
Device Inc., and a number of HCPL788J optical isolated sensors are used as the brain of
the system. Four variables must be measured and sent to the DSP, these variables are
PV voltage (Vpv), PV current (Ipv), output current (Io) and grid voltage (Vgrid). By using
HCPL788J these variables are isolated and measured. At the beginning of the process,
ADMC331 generates a rectified sinusoidal waveform (Isine) from Vgrid. The processor
simultaneously tracks the maximum power point of the PV panels from Vpv and Ipv by
controlling the output current so that dP/dV = 0. At the maximum power point, the
processor calculates a maximum current and generate a reference current (Iref) by
scaling Isine with the maximum current. The processor then uses hysteresis controller in
order to shape Io to match Iref. As the result, the output current has exact the same phase
and frequency as the grid voltage; the amplitude of Io is varied to match the maximum
power in which the photovoltaic array can provide. The processor is also programmed
to stop all process whenever the grid power is fail and/or the frequency of Io is over
range (50 5 Hz). This power system was tested during noon until 4 P.M. of February
and March, 2003. The system was connected with 120-W photovoltaic array which was
installed in the opened space and was reached by sunlight. The performance of the
systems (converter, inverter, control scheme and total system) was calculated and was
set as the performance table.
Keywords: Grid-Connected / Photovoltaic / Double Forward Converter / Hysteresis /
Current Control / Digital Signal Processor

iii

..

12

..
.

2545

50 Hz ADMC331
HCPL788J PV (Vpv),
PV (Ipv), (Io) (Vgrid) ADMC331
ADMC331 (Isine)
(dP/dV = 0) Vpv Ipv
Io ADMC331 (Iref)
Isine Io
Isine ADMC331 Io
Io 50 5 Hz
.. 2546 120 W
(, ,
)
: / / /
/ /

iv

ACKNOWLEDGEMENTS
This thesis is dedicated to my father and my mother who always dream that their
children would, at least, graduate the masters degree. Deeply thank to them for years
of support. The author wishes to express deepest gratitude to his advisors (Assoc. Prof.
Ake Chaisawad, Ph.D. and Dr. Veerapol Monyakul) for their continuing advice,
encouragement and dedication to this thesis. Both of them have instructed and given a
lot of significant advice to the author for years. Moreover, they also kindly provided
equipment and laboratory support. The author would like to show his appreciation to all
of the thesis committee, which includes Asst. Prof. Udomsak Yangyuen and Assoc.
Prof. Pitikhate Sooraksa, Ph.D. Not only being members of the committee, they also
provided several considerable suggestions and knowledge to the author. Moreover, the
author wishes to acknowledge Mr. Dumrong Amorndechapon, a lecturer of the Dept. of
Electrical Engineering. KMUTT; whose his technical supports the thesis are a great help
for the thesis to complete.
Thanks to friends (Keng, Sith, Murf and Nok) who always help the author challenge
many problems. Special appreciation must be demonstrated to Linzey Yeaung for the
best moral support. Without these people, the author would not have fulfilled the
masters degree.

CONTENTS
PAGE
ENLIGSH ABSTRACT
THAI ABSTRACT
ACKNOWLEDGEMENTS
CONTENTS
LIST OF TABLES
LIST OF FIGURES
LIST OF SYMBOLS
CHAPTER
1.
THESIS OVERVIEW
1.1
Thesis Overview
1.2
Literature Review
1.3
Thesis Objectives
1.4
Thesis Procedures
1.5
Thesis Concepts

ii
iii
iv
v
vii
viii
xi

1
1
1
6
6
6

2.

THEORIES
2.1
The Basic of Photovoltaics
2.2
Maximum Power Point Tracking (MPPT)
2.3
Forward Converter
2.4
Hysteresis Current Control
2.5
The Characteristics of ADMC331 Digital Signal Processor

8
8
10
12
19
20

3.

SYSTEM DEVELOPMENT
3.1
Hardware Development
3.1.1
System Overview
3.1.2
Photovoltaic Array
3.1.3
ADMC331 DSP Board
3.1.4
Rectified Sinusoidal Hysteresis Controller
3.1.5
Two-Switch Forward Converter
3.1.6
Single Phase Inverter
3.1.7
Gate Drivers
3.1.8
Sensors
3.1.9
Zero-Crossing Detector
3.2
Software Development
3.2.1
System Overview
3.2.2
Analog-To-Digital Converting Algorithm
3.2.3
Current Sink Algorithm
3.2.4
Maximum Power Point Tracking (MPPT) Algorithm
3.2.5
Iref Generating Algorithm
3.2.6
Islanding Algorithm

25
25
25
26
27
30
31
33
35
37
41
42
42
42
43
44
46
46

vi

4.

THE EXPERIMENTS AND RESULTS

4.1
Experiment 1: System Characteristics
4.1.1
Objectives
4.1.2
Instruments
4.1.3
Procedures
4.2
Experiment 2: System Performance
4.2.1
Objectives
4.2.2
Instruments
4.2.3
Procedures
4.2.4
Experimental Results

48
48
48
48
48
59
59
59
59
60

5.

CONCLUSIONS
5.1
Conclusions
5.2
Future Improvements
5.2.1
Current Controller
5.2.2
Harmonics Elimination

64
64
66
66
67

REFERENCES
APPENDIX
A
B
C

69

Specification Sheets of MSX-Lite 30 Solar Module

Transformer Design
Inductor Design

CURRICULUM VITAE

71
71
74
79
83

vii

LIST OF TABLES
TABLE
4.1
4.2
4.3
4.4
4.5

Measured Voc and Isc on March 2, 2003

Measured Vmp, Imp, and Pmax on March 2, 2003
Measured Vpv, Ipv, and Ppv on March 3, 2003
Measured Vgrid, Igrid, and Pgrid on March 3, 2003
Performance of the system

PAGE
60
61
62
62
63

viii

LIST OF FIGURES
FIGURE
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8

(a) Grid-interactive VCI; (b) Grid-interactive CCI

Line-commutated single-phase inverter
Self-commutated inverter with PWM technique
PV inverter using high-frequency transformer
Noninsulated current source
Flyback converter with a thyristor inverter
Buck converter with half-bridge transformer link
Conceptual diagram of the grid-connected PV system for this thesis
Principle of the operation of a solar cell [3]
Current vs voltage (I-V) and current vs power (I-P) characteristics for
a solar cell
PV in various configurations
Effect of temperature on a solar cell
Typical I-V characteristic curves for different radiation levels
Typical power vs voltage characteristics for increased radiation levels
PV array and load characteristics
Basic forward converter
Basic forward converter with its equivalent circuit model
Waveforms of the forward converter
Forward converter; (a) during subinterval 1 (b) during subinterval 2
(c) during subinterval 3
Two-switch forward converter
Secondary side forward converter switching waveforms
Hysteresis current control
Functional block diagram of ADMC331
ADSP-2100 core block diagram
ADC block diagram
The operation of ADC system
Programmable interval timer architecture
Block diagram of grid-connected power system
Configuration of a 120-Watt PV array
Diagram of control algorithms inside ADMC331
Schematic of the ADMC331 and TLV5618A circuit board
Diagram of the rectified sinusoidal hysteresis controller
Schematic of the rectified sinusoidal hysteresis controller
Hysteresis gap and the output of TLV5618A
Diagram of the two-switch forward converter

PAGE
2
3
4
4
5
5
6
7
8
9
9
10
10
11
11
12
13
13
14
16
17
20
21
22
23
23
24
25
27
28
29
30
30
31
31

ix

3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3. 29
3.30
3.31
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12

Schematic of the two-switch forward converter

Diagram of the single phase inverter
A voltage-bidirectional two-quadrant switch
Schematic of the single phase inverter
Diagram of the converter gate drive circuit
Schematic of the converter gate drive circuit
Diagram of the inverter gate drive circuit
Schematic of the inverter gate drive circuit
Diagram of where sensors are positioned
Function diagram of HCPL-788J
Diagram of Vgrid Sensor
Diagram of Vpv sensor
Diagram of Ipv Sensor
Diagram of Io sensor
Diagram of zero-crossing detector
Diagram shows control algorithms which are programmed into
ADMC331
Diagram of the ADC algorithm
Diagram of the current sink algorithm
Diagram of the MPPT algorithm
Characteristic diagram of dPpv dVpv versus Vpv

33
34
34
35
35
36
36
37
37
38
39
39
40
41
41
42

Diagram of the maximum power point tracking algorithm

Diagram of the Iref generating algorithm
Diagram of the islanding algorithm
Positions of probes which were installed to investigate Vpri and Ipri
of the isolated transformer
Voltage and current of the primary side of the isolated transformer
Positions of probes installed to investigate Vsec and Isec of the
transformer
Voltage and current of the secondary side of the isolated transformer
Positions of voltage-different probe and current probe
Voltage and current across the output inductor
Positions of probes installed to measure VO and IO of the output
inductor
Output voltage and output current of the two-switch forward
converter
Positions of probes which were connected to measure the voltage and
current of the distribution line.
Voltage and current which was transferred to grid.
Positions of probes which were installed to determine fsmin and Dmin.
Minimum switching frequency which was generated by hysteresis

45
46
47
49

43
44
44
45

49
50
50
51
52
52
53
54
54
55
55

4.13
4.14
4.15
4.16
4.17
4.18
5.1
5. 2
5.3
5.4
5.5

controller
Minimum duty cycle which was generated by hysteresis controller.
Positions of probes which were installed to determine fsmax and Dmax.
Maximum switching frequency which was generated by hysteresis
controller
Maximum duty cycle which is generated by hysteresis controller.
(a) Voc measurement, (b) Isc measurement, and (c) Pmax measurement.
Positions of probes which were used to investigate the system
efficiency
The conventional grid-connected PV system.
The grid-connected PV system designed in this thesis.
Basic current control scheme using SPWM.
Sinusoidal pulse-width modulation.
Harmonic trap filters; (a) the diagram (b) equivalent circuits.

56
57
57
58
60
61
64
65
66
67
68

xi

LIST OF SYMBOLS
iL
vc
vo
C
Ci
Co
D
Dmax
Dmin
fs
fsmax
fsmin
HB
iL(t)
iM(t)
K
N
Npri
Nsec
Ierr
Inorm
Imp
Io
Iph
Ipri
Ipv
Iref
Isc
Isec
L
LM
Lo
P
Pgrid
Pmax
Ppv
Rsense1
Rsense2
Rsense3
tck

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

T
TCRST
Tmax
Tmin
ton
toff
TPWM

=
=
=
=
=
=
=

peak-to-peak inductor ripple current (A)

peak-to-peak capacitor ripple voltage (V)
peak-to-peak output ripple voltage of a converter (V)
capacitor (F)
capacitor connected in parallel the PV array (F)
output capacitor of two-switch forward converter (F)
duty cycle (%)
maximum duty cycle (%)
minimum duty cycle (%)
switching frequency (Hz)
maximum switching frequency (Hz)
minimum switching frequency (Hz)
hysteresis band
current of an inductor (A)
magnetizing current (A)
magnitude of the reference current calculated by MPPT (A)
turn ratio of a transformer
turn number of the primary winding (Turn)
turn number of the secondary winding (Turn)
error current (A)
normalized grid voltage (V)
current at which solar cells generate the maximum power (A)
output current of the forward converter (A)
photocurrent which is current internally generated in solar cell (A)
current flows through the primary side of the isolated transformer (A)
output current of the photovoltaic array (A)
full wave sinusoidal reference current generated by DSP (A)
short circuit current of the solar cell (A)
current flows through the secondary side of the isolated transformer (A)
inductor (H)
magnetization inductance of a transformer (H)
output inductor of two-switch forward converter (F)
average power (W)
power which is transferred to the distribution line or grid (W)
maximum power (W)
power of PV array which is tracked by MPPT (W)
sensing resistance chosen to measure the PV array current (A)
sensing resistance chosen to measure the PV array voltage (V)
sensing resistance chosen to measure the converter output current (A)
the ADMC331 processing cycle which equals 38.5 ns at 13 MHz input
clock (s)
switching period (s)
PWMSYNC pulse width which by default is 1.54 s. (s)
maximum switching period (s)
minimum switching period (s)
turn-on time of a switching element (s)
turn-off time of a switching element (s)
PWM period defined in ADMC331 (s)

xii

vc(t)
Vg
Vgrid
vL(t)
VIN+
VINVmp
Vo
Voc
Vpri
Vpv
Vsec

mppt
inv
sys

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

capacitor voltage (V)

input voltage of a converter (V)
220V single phase grid voltage (V)
voltage across an inductor (V)
positive input voltage of HCPL-788J (V)
negative input voltage of HCPL-788J (V)
voltage which solar cells generate the maximum power (V)
output voltage of the forward converter (V)
open circuit voltage of the solar cell (V)
secondary side voltage of a transformer (V)
output voltage of the photovoltaic array (V)
secondary side voltage of a transformer (V)
phase shift (Rad)
firing angle (Deg)
efficiency of the maximum power point tracking algorithm (%)
efficiency of converter and inverter (%)
overall efficiency which includes MPPT, converter, and inverter (%)

CHAPTER 1 THESIS OVERVIEW

1.1 Thesis Overview
The Kyoto agreement on global reduction of greenhouse gas emissions has prompted
renewed interest in renewable energy system world wide. Many renewable energy
technologies today are well developed, reliable, and cost competitive with the
conventional fuel generators. The cost of renewable energy technologies is on a falling
trend as demand and production increases. There are many renewable energy sources
such as solar, biomass, wind, and tidal power. The solar energy has several advantages
for instance clean, unlimited, and its potential to provide sustainable electricity in area
not served by the conventional power grid. As a consequence of these reasons and the
tropical climate, solar energy is the most suitable renewable energy source in Thailand.
However, the solar energy produces the dc power, and hence power electronics and
control equipment are required to convert dc to ac power. There are two types of the
solar energy system; stand-alone power system and grid-connected power system. Both
systems have several similarities, but are different in terms of control functions. The
stand-alone system is used in off-grid application with battery storage. Its control
algorithm must have an ability of bidirectional operation, which is battery charging and
inverting. The grid-connected system, on the other hand, inverts dc to ac and transfers
electrical energy directly to power grid. Its control function must follow the voltage and
frequency of the utility-generated power presented on the distribution line. However,
this thesis only scopes on the grid-connected power system. Several inverter topologies
can be applied to the system; they all have the same objectives but are different in the
principles. Section 1.2 covers many research literatures in grid-connected applications.
The basic principles applied to achieve the thesis objectives are stated in section 1.5.
Several theories which involve in this thesis are presented in chapter 2. Those theories
include the basics of photovoltaic (PV), the forward converter, rectified sinusoidal
hysteresis current control, and the characteristics of ADMC331 digital signal processor.
In chapter3, those theories are first applied; the mathematical model of the system is
then built. The digital control functions are designed so that they follow the voltage and
frequency of the distribution line. MATLAB/SIMULINK is utilized to predict the
dynamic behavior of the system. The simulation results are presented at the end of
chapter 3. In chapter 4, the experiment is built following the simulation concept. All of
the control functions are programmed to ADMC331; a digital signal processor of
Analog Devices Inc. The experimental results are also presented at the end of the
chapter. Chapter 5 covers the conclusions and future works which can be adapted to
this thesis.

1.2 Literature Review

1.2.1 Inverter Classifications
The inverters used for grid interfacing are classified as voltage-source inverter (VSI)
and current-source inverter (CSI). Each type of the inverters can be subdivided based
on the control schemes; which are voltage-control inverter (VCI) and current-control
inverter (CCI) [1]. In VSI, the dc side is made to appear to the inverter as a dc source.
The voltage-source inverters have a capacitor in parallel with the dc input. The currentsource inverters, on the contrary, have an inductor in series with the dc input.

Photovoltaic arrays are fairy good approximation to a current source. However, most of
PV inverters are voltage-source inverters. Solar arrays in this thesis are also
implemented as a voltage source.
Figure 1.1(a) shows a single-phase full bridge bidirectional voltage-source inverter with
a voltage control and phase shift () control. The active power transfer from the PV
panels is accomplished by controlling phase angle between the inverter voltage and the
grid voltage. Therefore, the inverter voltage follows the grid voltage.
Figure 1.1b shows the VSI operated as a current-control inverter (CCI). The objective
of this control scheme is to control active and reactive components of the current fed
into the grid.

Figure 1.1 (a) Grid-interactive VCI; (b) Grid-interactive CCI

In this thesis, solar arrays are implemented as a voltage source, the inverter are designed
based on CCI. The output current of the inverter are controlled to follow phase angle
and frequency of the grid. As the consequences, this inverter appears as a current
source in parallel with the grid.

1.2.2 Inverter Types

Various types of inverter are in use for grid-connected power system, including the
following:
- Line-commutated inverter
- Self-commutated inverter
- Inverter with high-frequency transformer
- Other PV inverter topologies

1.2.2.1 Line-Commutated Inverter

The basic diagram for a single-phase line-commutated inverter is shown in Figure 1.2
[2]. The control scheme has to change the firing angle () from the rectifier operation
(0o< < 90o) to the inverting operation (90o< < 180o) [3, 4]. Thyrsistor- type inverters
requires a low-impedance grid interface connection for commutation purposes. If the
maximum power available from the grid is less than twice the rated PV inverter power,
then the line-commutated inverter should not be used [2]. The line-commutated
inverters are cheaper but can lead to poor quality. These inverters have poor power
factors that require an additional control to improve them. The harmonics injected into
the grid can be large unless taken care by adequate filters. Increasing the dc-side
inductor will decrease total harmonic distortion (THD); unfortunately the value of the
inductor is directly proportional to its cost and size [4].

Figure 1.2 Line-commutated single-phase inverter

1.2.2.2 Self-Commutated Inverter

To obtain low ac line current THD, the passive techniques described in previous section
rely on low-frequency transformers and/or reactive elements. The large size and weight
of these elements are objectionable in many applications. Self-commutated inverter
operates at the high switching frequency, much greater than the ac line frequency. The
reactive elements of the system are small, because their sizes depend on the converter
switching frequency rather than the ac line frequency. Moreover, the line current
harmonics injected into the grid are very low.
A switch-mode inverter using pulse-width modulated (PWM) switching control can be
used for the grid connection of PV systems. The basic block diagram for this type of
inverter is shown in Figure 1.3. The inverter bridges may consist of transistors,
MOSFETs, IGBTs or GTOs, depending on the type of application. GTOs are used for
higher-power applications, whereas IGBTs can be switched at higher frequencies, i.e.
20 kHz, and are generally used for many grid-connected PV applications.
Based on the switching control, voltage-source inverters can be further classified as
follows [3]:
- PWM inverters
- Square-wave inverters
- Single-phase inverters with voltage cancellations
- Programmed harmonic elimination switching.
- Current-controlled modulation

Figure 1.3 Self-commutated inverter with PWM technique

1.2.2.3 Inverter with High-Frequency Transformer

The 50-Hz transformer for a standard PV inverter with pulse width modulation (PWM)
switching scheme can be very heavy and costly. When the switching frequency is
greater than 20 kHz, a ferrite core transformer can be a better option [2]. A circuit
diagram of a grid-connected PV system using high-frequency transformer is shown in
Figure 1.4.
The high-frequency inverter with PWM is used to produce a high-frequency ac across
the primary winding of the high-frequency transformer. The high-frequency rectifier
rectified the voltage across the secondary winding. The dc is interfaced with a thyristor
inverter through a low-pass inductor filter and hence connected to the grid. The line
current is required to be sinusoidal and in phase with line voltage. To achieve this, the
grid voltage must be measured to establish the reference waveform for the line current.
This reference current is then multiplied by the transformer ratio gives the reference
current at the output of the high-frequency inverter. Current-control technique can be
applied in order to control the output of the inverter. Most of PV inverters appear at
present, including this thesis, are based on PV inverter with high-frequency transformer.
However, the inverter presented in Figure 1.4 has too many high-frequency switching
elements; this thesis tends to decrease the number of switching elements as many as
possible.

Figure 1.4 PV inverter using high-frequency transformer

1.2.2.4 Other PV Inverter Topologies

In this section, a number of PV inverters are discussed in various research papers.

a. Noninsulated Current Source

This type of topology is shown in Figure 1.5. The PV panels are configured to be a
current source by connecting with two inductors in series. The PV current is controlled,
through high-frequency MOSFET/IGBT inverter, so it has the same phase angle and
frequency with the distribution line. This configuration involves low cost and can
provide better efficiency compare to the noninsulated voltage source. Appropriate
controllers can be applied to reduce current harmonics. Moreover, this topology
provides an important idea of paralleling a current source with the grid. Paralleling the
current source with the voltage source avoids the problem such as imbalance voltage in
paralleling two voltage sources. Unfortunately, this topology lacks of the appropriate
step-up converter therefore it cannot be operated whenever the voltage across PV panels
is less than rated grid voltage [3].

Figure 1.5 Noninsulated current source

b. Flyback Converter with a Thyristor Inverter

With a proper PWM control scheme, this converter [4] steps up the PV voltage to dc
bus voltage. The higher dc bus voltage is interfaced with a thyristor inverter through a
low-pass inductor filter and hence connected to the distribution line, Figure 1.6. This
scheme is less complex, less cost and has fewer high-frequency switching elements. Its
compact size made it suitable for remote PV applications. Unfortunately, it is
commonly used at the 50 to 100 W power range [4].

Figure 1.6 Flyback converter with a thyristor inverter

c. Buck Converter with Half-bridge Transformer Link

Low voltage PV panels are connected to grid via a buck converter and half-bridge as
shown in Figure 1.7. In this scheme, the buck converter uses PWM to generate an
attenuated rectified 100-Hz sine wave current waveform [5]. The half-wave bridge is
only used to convert this rectified output to a 50-Hz current waveform which is feasible
for grid interconnection.
The advantage of this configuration is the requirement of
only one high-frequency switching element. To step up the output voltage, the lowfrequency transformer is required. The output voltage is quite low because buck
converter steps down the PV voltage; the turn ratio of the transformer is therefore high.
As these consequences, the low-frequency transformer is heavy and costly.

Figure 1.7 Buck converter with half-bridge transformer link

1.3 Thesis Objectives

-

Design and construct a system that can convert the solar energy into the
electrical energy and transfer this energy to the distribution line.
Design and construct the inverter which can convert the direct current to the
alternating current by using a rectified sinusoidal hysteresis current control.
Tend to reduce the number of the high frequency switching elements as
many as possible.
Design a controller in which it can control the system to operate at the
maximum power the photovoltaic array can provide.

1.4 Thesis Procedures

-

Study the characteristics of the PV array.

Design a two-switch forward converter and a single phase inverter.
Study and design controllers which include the hysteresis current control, the
maximum power point tracking (MPPT), and the islanding algorithm.
Program the controllers and download them into the ADMC331 16-bit
digital signal processor.

1.5 Thesis Concepts

In most of the grid-connected PV applications, a DC-DC converter tracks the maximum
power point in which the PV is able to provide. The converter also boosts the PV array
voltage to be a dc voltage which exceeds the grid voltage at high switching frequency.
In the mean time, a single phase inverter shapes the output current into the sinusoidal
waveform; which matches the frequency and phase of the distribution line; at high
switching frequency. As the consequence, the system converts the solar energy and
transfers the maximum energy into the distribution line.

In this thesis, however, the DC-DC converter tracks the PVs maximum power point
and shapes the PV array voltage into the rectified sinusoidal current at high switching
frequency. Because the converter consists of a high frequency transformer, the
converter hence isolates the distribution line from the PV array and the rest of the
system. The single phase inverter is only used to unfold this rectified current to be a
50 Hz sinusoidal current, the switching frequency is also 50 Hz. Note that this thesis
reduces high switching components from five components (one is for the converter,
others are for the inverter) to two components for the converter.

Figure 1.8 Conceptual diagram of the grid-connected PV system for this thesis

CHAPTER 2 THEORIES
Several theories involving in this thesis are discussed in details in this chapter. Those
theories include:

2.1 The Basic of Photovoltaics

The density of power radiated from the sun (referred to as the solar energy constant)
at the outer atmosphere is 1.373 kW/m2. Part of this energy is absorbed and scattered
by the earths atmosphere. The final solar energy that reaches the earths surface has
the peak density of 1 kW/m2 at noon in the tropics. The technology of photovoltaic
(PV) is essentially concerned with the conversion of the solar energy into suitable
electrical energy. The basic element of PV system is a solar cell. By settling solar cells
under the sunlight, they can convert solar energy directly to electricity. This electricity
can be modified to any consumer applications such as lighting, water pumping,
refrigeration, telecommunications, and so on. Solar cells rely on a quantum-mechanical
process known as the photovoltaic effect to produce electricity. A typical solar cell
consists of a p-n junction formed in a semiconductor material similar to a diode. Figure
2.1 shows a schematic diagram of the cross section structure through a crystalline solar
cell. It consists of a 0.2-0.3 mm thick monocrystalline or polycrystalline silicon wafer
having two layers with different electrical properties formed by doping it with other
impurities (e.g., boron and phosphorus). An electric field is established at the junction
between the negatively doped (using phosphorus atoms) and the positively doped (using
boron atoms) silicon layers [3]. If sunlight impacts the solar cell, the energy from the
sunlight (photons) creates free charge carries, which are separated by the electrical field.
An electrical voltage is generated at the external contacts, so that current flows when a
load is interfaced. The photocurrent (Iph), which is internally generated in solar cell, is
proportional to the radiation intensity.

Figure 2.1 Principle of the operation of a solar cell [3]

A number of semiconductor materials is suitable for the manufacture of solar cells. The
most common types using silicon semiconductor material (Si) are:
- Monocrystalline Si cells
- Polycrystalline Si cells
- Amorphous Si cells
Each type of these Si cells can deliver maximum electrical energy in the different period
time of the day; dues to the different wave length of the sunlight.

A solar cell can be operated at any point along its characteristic current-voltage curve,
as shown in Figure 2.2. There are two important points on this curve; the open circuit
voltage (Voc) and the short circuit current (Isc). The Voc is the maximum voltage which a
solar cell can provide at zero current, whereas the Isc is the maximum current which a
solar cell can provide at zero voltage. For a silicon solar cell under a standard test
condition, Voc is typically 0.6-0.7 V, and Isc is typically 20-40 mA for every square
centimeter of the cell area. To a good approximation, Isc is proportional to the
illumination level, whereas Voc is proportional to the logarithm of the illumination level.
A plot of power (P) against voltage (V) for this device shows that there is a unique point
on the I-V curve in which the solar cell generates the maximum power at any
illumination level. This is known as the maximum power point (Vmp, Imp). Note that the
maximum power condition always occurs at the knee of the characteristic curve.
Therefore, every PV application should be able to operate at the maximum power point.

Figure 2.2 Current vs voltage (I-V) and current vs power (I-P) characteristics
for a solar cell
Because silicon solar cells typically produce only about 0.5 V per cell, a number of cells
needs to be connected in series (called PV module). A PV panel is a collection of PV
modules physically and electrically grouped together on a support structure. A PV array
is a collection of PV panels.

Figure 2.3 PV in various configurations

The effect of temperature on the performance of a silicon solar cell is described in
Figure 2.4. Note that, Isc slightly increases in temperature, but Voc and maximum power
majority decrease in temperature.

10

Figure 2.4 Effect of temperature on a solar cell

Figure 2.5 shows the variation of PV current and voltage at different solar radiation
levels. According to Figure 2.4 and Figure 2.5, it can be concluded that the
characteristic of a solar cell at a given radiation level and temperature consists of a
constant-voltage segment and a constant-current segment. Its current is limited at the
short circuit current and its voltage is limited at the open circuit voltage. The maximum
power condition always occurs at the knee of the I-V characteristic curve.

Figure 2.5 Typical I-V characteristic curves for different radiation levels

2.2 Maximum Power Point Tracking (MPPT)

In Figure 2.6, the PV power output is plotted against the PV voltage for the radiation
level from 200 W/m2 to 1000 W/m2. The points of maximum power form a curve
termed as the maximum-power-point locus. A controller that tracks the maximumpower-point locus of the PV array is termed as a MPPT. Because of the high cost of PV
array, it is necessary to operate the system at its maximum-power-point locus. For
overall optimal operation of the system, the load line must match the PV arrays
maximum-power-point locus.

11

Figure 2.6 Typical power vs voltage characteristics for increased radiation levels
Referring to Figure 2.7, the load characteristics can be either curve OA or curve OB,
depending on the loads current and voltage requirement. If load curve OA is
considered and the load is only coupled to the solar array, the array will operate at point
A1, which will delivery only power P1. However, the maximum power available at the
given radiation is P2. In order to utilize the array at P2, a power conditioner coupled
between the PV array and the load is needed.

Figure 2.7 PV array and load characteristics

There are two possibilities to operate PV arrays at the maximum power point:
- Open-loop control.
- Closed-loop control.
The open-loop control scheme based on an assumption that the maximum-power-point
voltage (Vmp) is a linear function of Voc. For example, Vmp = 0.75* Voc. This assumption
is reasonably accurate even for large variations in Isc and temperature. This type of
MPPT is probably the most common type. A variation in this scheme involves
periodically measuring Voc.
With the closed-loop control scheme, more accurate maximum power point can be
tracked. It involves in varying the input voltage around the optimal value by giving it a
slightly increment or decrement alternately. As the consequences, the output power is
then assessed and a small correction is made to both input voltage and input current.
This method is also called a hill-climbing algorithm. The power output of PV array is

12

sampled at a proper sampling period and compared with the previous value. In the
event where the power is increasing, the solar array voltage is increased while the array
current is slightly decreased. On the contrary, if the power is decreasing, the array
voltage is decreased while the array current is slightly increased. The output power is
finally tracked around the maximum power point. Note that, the array current also can
be sampled and monitored as the system variable instead of monitoring the array
voltage.
The output power of the PV array can be expressed as
Ppv = Vpv * I pv

(2.1)

The conventional MPPT algorithm used dP/dV = 0 to obtain the maximum output
power point, hence the maximum output power of the PV array is also determined by
dPpv
dVpv

= I pv +

dI pv
dVpv

*Vpv

(2.2)

Therefore, the MPPT software algorithm can be developed by based on (2.2) [8].
Moreover, a PI controller or another AI controller can be merged with the conventional
MPPT. As the consequence, this hybrid MPPT algorithm will have faster settling time
compared with the conventional one.

2.3 Forward Converter

The forward converter is illustrated in Figure 2.8. This is a transformer isolated
converter based on the buck converter. It requires a single MOSFET. Its nonpulsating
output current, shared with other buck-derived converter, makes the forward converter
well suited for applications involving high output currents. The maximum switch duty
cycle is limited in value; for the common choice n1 = n2, the duty cycle is limited to the
range 0 D 0.5 .

Figure 2.8 Basic forward converter

The transformer magnetizing current is reset to zero while the switch is off-state. How
this phenomenon occurs can be understood by substituting the three-winding
transformer in Figure 2.8 with its equivalent circuit. The result is illustrated in Figure
2.9, and the typical waveforms of the converter are given in Figure 2.10. The
magnetizing inductance LM, in conjunction with D1, must operate in the discontinuous
conduction mode. The output inductor L, may operate either in discontinuous or
continuous conduction mode. The waveforms in Figure 2.10, however, are sketched in

13

the continuous conduction mode of the output inductor. According to Figure 2.10, three
switching intervals are then sketched in Figure 2.11.

Figure 2.9 Basic forward converter with its equivalent circuit model

Figure 2.10 Waveforms of the forward converter

During subinterval 1, switch Q1 conducts and the circuit of Figure 2.11(a) is obtained.
Diode D2 becomes forward-biased, while D1 and D3 are reverse-biased. Voltage Vg is
applied to the transformer primary winding, and hence the transformer magnetizing
current iM(t) is increased in the slope of Vg/ LM as shown in Figure 2.10. The voltage
across D3 is equal to Vg multiplied by the turn ratio of the transformer.

14

Figure 2.11 Forward converter

(a) during subinterval 1
(b) during subinterval 2
(c) during subinterval 3
The second subinterval begins when the switch Q1 is in off-stated. The circuit of Figure
2.11(b) is then obtained. The transformer magnetizing current iM(t) at this instant is
positive, and it continues to flow in the same direction. Since switch Q1 is switched off,
the equivalent circuit predicts that iM(t) must flow into the primary winding of the ideal
transformer. It can be seen that n1 iM flows out of the polarity mark of the primary
winding. An equal amount of current must flow into the polarity marks of the winding
2. The current iM*n1/n2 must flow into the polarity mark of winding2. Diode D1
becomes forward-biased; while D2 is reverse-biased and hence prevents current to flow
into the winding3. Voltage Vg is applied to winding 2, and voltage across the
magnetizing inductance is -Vgn1/n2, referred to the winding 1. This negative voltage
causes the magnetizing current to decrease with a slope -Vgn1/n2 LM. In the mean time,
diode D3 turns on to conduct the output inductor current i(t).

15

Subinterval 3 begins when the magnetizing current reaches zero and hence diode D1
becomes reverse-biased. Components Q1, D1, and D2 operate in the off state and the
magnetizing current remains zero for the balance of the switching period.
By applying the principle of inductor volt-second balance to the transformer
magnetizing inductance, the primary winding voltage v1(t) must have zero average.
Referring to Figure 2.10, the average of v1(t) is
v1 = D (Vg ) + D ( Vg n1 / n2 ) + D3 (0) = 0

(2.3)

Solution for D2 is given by

D2 =

n2
D
n1

(2.4)

Since D + D2 + D3 = 1 , and D3 can not be negative. Therefore

D3 = 1 D D2 0

(2.5)

Substitute (2.4) into (2.5) leads to

n
D3 = 1 D 1 + 2 0
n1

(2.6)

Therefore
D

1
n
1+ 2
n1

(2.7)

So the maximum duty cycle is limited. For the common choice n1 = n2, the limit
becomes
D

1
2

(2.8)

If this limit is violated, then the switch off-time is insufficient to reset the transformer
magnetizing current to zero before the end of the switching period. Transformer
saturation may occur.
The converter output voltage can be found by applying the inductor volt-second balance
to the output inductor L. The voltage across inductor L must have zero dc component,
and therefore the dc output voltage V is equal to the dc component of diode D3 voltage
vD3(t).
VD 3 = V =

n3
DVg
n1

(2.9)

It can be seen from (2.7) that the maximum duty cycle can be increased by decreasing
the turn ratio n2/n1. This will cause iM(t) to decrease more quickly during subinterval 2,
and hence resetting the transformer faster. Unfortunately, this also increases the stress
across the switch Q1. The maximum voltage across the switch during subinterval 2 may
be stated as

16

n
max ( vQ1 ) = Vg 1 + 1
n2

(2.10)

Note that, if n1 = n2 the voltage across the switch Q1 equals 2Vg. Therefore, decreasing
the transformer turn ratio n2/n1 allows increasing the maximum duty cycle, at the
expense of increasing the switch blocking voltage.
Figure 2.12 illustrates the two-switch version of the forward converter. The switch Q1
and Q2 are controlled by the same gate drive signal, they both conduct during
subinterval 1 and are switched off during subinterval 2 and 3. During subinterval 2, the
magnetizing current iM(t) forward-biases diodes D1 and D2. The primary winding is
then connected to Vg with the polarity opposite that of subinterval 1. The iM(t) then
decreases with slope -Vg LM. When iM(t) reaches zero, diode D1 and D2 is therefore
reverse-biased. The iM(t) then remains at zero for the balance of the switching period.
The secondary side of the converter is identical to the single-switch forward converter.
Diode D3 conducts during subinterval 1, while diode D4 conducts during subintervals 2
and 3. So the operation of the two-switch forward converter is similar to the singleswitch forward converter, in which n1 = n2. The duty cycle is also limited to D 0.5.
This converter has the advantage that the switch peak blocking voltage is limited to Vg
instead of 2* Vg. It also has the advantage that the transformer requires only two
windings.

Figure 2.12 Two-switch forward converter

Two-switch forward converter is also a transformer isolated converter based the buck
converter. The secondary side of the converter identically operates as a buck converter.
Its operations can be described as follow:
Mode 1 (0 < t ton)
At the beginning of a switching during mode 1, the switches Q1 and Q2 switch on, the
diode D2 becomes forward-bias, whereas the diode D3 is reverse-biased. Mode 1
equivalent circuit is illustrated as the secondary side equivalent circuit of two-switch
forward converter shown in Figure 2.11. The secondary side voltage of the transformer
Vsec connects with the output inductor L, and hence the output inductor current iL(t)
increases linearly from I1 to I2 during ton. Therefore,

17

vL (t ) = Vsec VO = L

I 2 I1
i
=L L
ton
ton

(2.11)

Note that iL(t) increases with a positive slope of

Slope =

iL Vsec VO
=
ton
L

(2.12)

Thus, mode1 is characterized by inductor charging and the storage of electrical energy
in magnetic form in the inductor.
Mode 2 (ton < t toff)
Mode 2 equivalent circuit is illustrated as the secondary side equivalent circuit of twoswitch forward converter shown in Figure 2.11. Mode 2 begins when the switching
elements are both switched off. Since it is not possible to change the current flowing
through the inductor instantaneously, the voltage polarity across the inductor
immediately reverses in an attempt to maintain the same current which is flowing just
prior toff. Hence, the diode D2 is reverse-biased, while the diode D3 becomes forwardbias. The secondary side of the isolated transformer disconnects from the output
inductor L. The inductor current decreases as the electrical energy stored in the inductor
is transferred to the output capacitor C and load. From Figure 2.11, the voltage across L
is
VO = L

I1 I 2
toff

(2.13)

Notice that iL(t) decreases with a negative slope of

Slope =

iL VO
=
toff
L

Figure 2.13 Secondary side forward converter switching waveforms

(2.14)

18

Figure 2.13 illustrates voltage and current waveforms of components on the secondary
side of the two-switch forward converter.
According to Figure 2.13, the current ripple iL is the same during mode 1 and mode 2
hence
iL =

(Vsec VO )ton VO toff

=
L
L

(2.15)

Substituting ton = DT and toff = (1 D)T into (2.15) gives

VO = DVsec =

n2
DVg
n1

(2.16)

The output voltage VO of the forward converter is the product of the duty cycle D, turn
ratio n2 / n1 , and the input voltage Vg. The duty cycle periodically changes in order to
maintain the desired output voltage during a load change and/or an input voltage
fluctuation. This periodic change of D is accomplished using a proper control scheme
such as, in this thesis, the rectified sinusoidal hysteresis current control. The ton and
toff are defined as
ton =

LiL
LiL
and toff =
Vsec VO
VO

(2.17)

The switching period T is the sum of ton and toff :

T =

LVsec iL
1
= ton + toff =
fs
VO (Vsec VO )

(2.18)

Therefore, for the steady-state operation, the current ripple in the output inductor L can
be expressed as
iL =

Vo (Vsec Vo )T
DVsec (1 D)
=
LVsec
Lf S

(2.19)

Thus, the current ripple in the output inductor is inversely proportional to the inductance
and switching frequency f S .
According to Figure 2.13, the average capacitor current is zero for a switching period
since the output capacitor is charged and discharged by the same amount during steadystate operation. However, the average capacitor current during T 2 t 3T 4 is
iC =

iL
4

The capacitor voltage vc(t) during T 2 t 3T 4 is

(2.20)

19

v
v

vC (3T 4) vC (T 2) = VO + C VO C
2
2

= vC
=

1
C

(2.21)

3T / 4

iC dt

T /2

The voltage ripple of the capacitor C is given by

vC =

1
C

3T / 4

iC dt

(2.22)

T /2

Substituting (2.20) into (2.22), therefore the voltage ripple is

vC =

1
C

3T / 4

T /2

iL
T iL
iL
dt =
=
4
8C
8Cf S

(2.23)

Finally, substituting iL from (2.19) into (2.23), the capacitor ripple voltage is
vC = vO =

DVsec (1 D) Vsec D(1 D)

=
fS L
16 LCf S2

(2.24)

Notice that, vc is also equal to the output ripple voltage vo since the output capacitor
is connected directly across the load. It can be seen that the vo is inversely
proportional to fs2 and LC product. Hence, to decrease the output ripple voltage, the
product LC should be large and the switching frequency should be high. Since the
output inductor L and output capacitor C form a low-pass filter, the choice of the value
of L and C determines the cutoff frequency of the output low-pass filter and ultimately
determines the amount of switching ripples and spikes in its output.

2.4 Hysteresis Current Control

In applications such as grid-connected system, dc and ac motor servo drives, it is the
output current that needs to be controlled, even though a VSI is often used. The current
control scheme has the advantage of limiting the output current.
Hysteresis current control is illustrated by Figure 2.14. For a sinusoidal reference
current iA*, the actual output iA is compared with the tolerance band around the
reference current associated with that phase. If the actual current in Figure 2.14 tries to
go beyond the upper tolerance band, TA- is turned on and TA+ is turned off. The
opposite switching occurs if the actual current tries to go below the lower tolerance
band. This control scheme is shown in a block diagram form in Figure 2.14.
The switching frequency depends on how fast the current changes from the upper limit
to the lower limit and vice versa. This depends on Vd, the load back-emf, and the load
inductance. Moreover, the switching frequency does not remain constant but varies
along the current waveform.

20

Figure 2.14 Hysteresis current control

2.5 The Characteristics of ADMC331 Digital Signal Processor

ADMC331 is a 16-bit digital signal processor manufactured by Analog Devices Inc.,
U.S.A. Its specifications and features are mentioned in its specification datasheet and
its users manual [6]. This section only describes its functions that involved in the
thesis. Figure 2.15 shows functional block diagram of ADMC331. ADMC331 is a
digital signal processor (DSP) based on ADSP-2100 architecture. ADMC331 consists
of the ADSP-2100 processor, analog-to-digital converters, a three-phase 16-bit PWM
generator, timers and communication ports. It is a fine designed DSP which is suitable
for motor drive applications. Its features are beyond needs for this thesis. However,
dues to the limited resources; this DSP is chosen for the thesis.

21

Figure 2.15 Functional block diagram of ADMC331

There are only three functions of ADMC331 required for this thesis:

2.5.1 ADSP-2100 Base Architecture

Figure 2.16 is an overall block diagram of the DSP core of the ADMC331, which is
based on the fixed-point ADSP-2171. Noted that the ADSP-2171 is the later version of
ADSP-2100, it is ADSP-2100 family code compatible. The flexible architecture and
comprehensive instruction set of the ADSP-2171 allows the processor to perform
multiple operations in parallel. In one processor cycle (38.5 ns with a 13 MHz CLKIN)
the processor core can:
- Generate the next program address.
- Fetch the next instruction.
- Perform one or two data moves.
- Update one or two data address pointers.
- Perform a computational operation.
These all take place while the processor continues to:
- Receive and transmit through the serial ports.
- Decrement the interval timer.
- Generate three-phase PWM waveforms for a power inverter.
- Generate two signals using the 8-bit auxiliary PWM timers.
- Acquire four analog signals.
- Decrement the watchdog timer.
The processor contains three independent computational units:
- The arithmetic and logic unit (ALU).
- The multiplier/accumulator (MAC).
- The shifter.
The ALU performs a standard set of arithmetic and logic operations; primitives
divisions are also supported. The MAC performs single-cycle multiply, multiply/add

22

and multiply/subtract operations with 40 bits of accumulation. The shifter performs

logical and arithmetic shifts, normalization, denormalization and derive exponent
operations. The shifter can also be applied to efficiently implement numeric format
control including floating-point representations. The internal result (R) bus directly
connects the computational units so that the output of any unit may be the input of any
unit on the next cycle.
Two data address generators (DAGs) provide address for simultaneous operand fetches
from data memory and program memory. Each DAG maintains and updates four
address pointers (I registers). Whenever the pointer is used to access data, it is postmodified by the value in one of four modify (M registers). A length value may be
associated with each pointer (L registers) to implement modulo addressing for circular
buffers.

Figure 2.16 ADSP-2100 core block diagram

2.5.2 Analog-To-Digital Converter (ADC)

The ADC of the ADMC331 is a 7-channel single slope analog data acquisition system
with 12-bit resolution. Data conversion is performed by timing the crossover between
the analog input and saw-tooth reference ramp. A simple voltage comparator detects
the crossover and latches the timed counter value into a channel-specific output register.
Figure 2.17 shows the functional block diagram of ADC in ADMC331.
The ADC system comprised of seven input channels to the ADC of which three (V1,
V2, V3) have dedicated comparators. The remaining four channels (VAUX0, VAUX1,
VAUX2, and VAUX3) are multiplexed into the fourth comparator and selected using
ADCMUX0 and ADCUX1 bits of the MODECTRL register. This allows four
conversions to be performed by ADC between successive PWMSYNC pulses.

23

Figure 2.17 ADC block diagram

The operation of ADC system may be explained by reference to Figure 2.17 and Figure
2.18. The reference ramp is connected with one input of all four comparators. This
reference is generated by charging an external timing capacitor with a constant current
source. On the falling edge of PWMSYNC, the capacitor begins to charge at a rate
determined by the capacitor and the current source value. The four input comparators
of the ADC system continuously compare the values of the four analog inputs with the
capacitor voltage. Each comparator output will go high when the capacitor voltage
exceeds the respective analog input voltage. The capacitor voltage is reset at the start of
PWMSYNC pulse, which by default is held high for forty CLKOUTs.

Figure 2.18 The operation of ADC system

The ADC timer block consists of a 12-bit counter clocked at either a rate of twice
CLKOUT period or a rate of CLKOUT period. Thus at the maximum CLKOUT
frequency of 26 MHz, this gives a timer resolution of 76.9 ns or 38.5 ns. The counter
resets during the high PWMSYNC pulse so that the counter commences at the
beginning of the reference voltage ramp. When the output of a given comparator goes

24

high, the counter value is latched into the appropriate 12-bit ADC registers. There is a
pair of four ADC registers (ADC1, ADC2, ADC3 and ADCAUX) corresponding to
each of the four comparators. Each pair is organized as master/slave. At the end, the
reference voltage ramp, which is prior to the next PWMSYNC, all four master registers
have been loaded with the new conversion count.
At the rising edge of the
PWMSYNC, the registered conversion count for each channel is loaded into the DSP
readable shadow registers, ADC1, ADC2, ADC3 and ADCAUX. The processor will
then read these shadow registers containing the previous conversion count, while
internally the master registers will be loaded with the current conversion count.
Because the operation of the ADC is intrinsically linked to the PWMSYNC interrupt
[6], the effective resolution of the ADC is a function of PWM switching frequency. For
a CLKOUT period of tck and a PWM period of TPWM, the maximum count of the ADC
is given by:
MaxCount = min ( 4095, (TPWM TCRST ) ) / 2tck at MODECTRL bit 7 = 0

(2.1)

MaxCount = min ( 4095, (TPWM TCRST ) ) / tck at MODECTRL bit 7 = 1

(2.2)

2.5.3 Timers
A programmable interval timer is also included in the DSP core and can be used to
generate periodic interrupts. These periodic interrupts are generated; based on the
processors cycle time. The timer architecture is shown in Figure 2.19.

Figure 2.19 Programmable interval timer architecture

The timer includes two 16-bit registers, TCOUNT and TPERIOD and one 8-bit register,
TSCALE. TSCALE is the scaling register; with a given scaling factor the timer will
decrease the counting value every n-cycle of processors cycle time. TCOUNT stores
the counting value. TPERIOD contains the value in which the interrupts will occur.
When the timer is enabled, TCOUNT is first loaded with TPERIOD. The timer will
decrease TCOUNT value every n processor cycles. When the TCOUNT reaches zero, a
timer interrupt thus occurs. TCOUNT is then reloaded with TPERIOD and the timer
start decrement again.

CHAPTER 3 SYSTEM DEVELOPMENT

3.1 Hardware Development
3.1.1 System Overview
Figure 3.1 illustrates the block diagram of grid-connected power system which is
designed in the thesis.

Figure 3.1 Block diagram of grid-connected power system

A 120-Watt PV array is paralleled with a 4700F input capacitor (Ci) so that the PV
array acts as a voltage source. The current sensor CS1 senses the PV array current
through Rsense1 while the voltage sensor VS1 senses the PV array voltage across Rsense2.
Both voltage and current of PV array are monitored by an ADMC331 DSP and then are
controlled in order that the PV array always transfers the maximum power to the
system. A two-switch forward converter receives the maximum electrical energy from
PV array. A 6.5 turn ratio isolated transformer, a part of the converter, amplifies the
input voltage so that the output voltage of the converter is larger than grid voltage. The
ADMC331 DSP is again utilized to generate a rectified sinusoidal reference waveform,
Iref, the magnitude of Iref correlates with the maximum power transferred from PV array.
The current sensor CS2 senses the output inductor current Io through Rsense3. Hysteresis

26

controller compares Io with Iref and shapes the output inductor current to match Iref at
high switching frequency. This rectified sinusoidal current is finally unfold and
transferred to the distribute line by a single phase inverter.

3.1.2 Photovoltaic Array

In this thesis, four 30-Watt PV modules are connected in series to form a 120-Watt PV
array. Figure 3.2 illustrates the configuration of this PV array. Each PV module is
manufactured by Solarex Inc., USA and is named as MSX-30 LITE. Each module
has the typical electrical characteristics of :
- Maximum power (Pmax)
= 30 W
- Voltage@ Pmax (Vmp)
= 17.1 V
- Current@ Pmax (Imp)
= 1.75 A
- Guaranteed minimum Pmax = 27 W
- Short-circuit current (Isc)
= 1.90 A
- Open-circuit voltage (Voc)
= 21.1 V
The further details of MSX-30 LITE are shown in the specification sheets in appendix
A.
According to Figure 3.2, four MSX-30 LITEs are connected in series to provide a 120Watt PV array. A 4,700F capacitor (Ci) is paralleled the PV array so that the PV array
has the characteristic of a voltage source. This capacitor also has the obligation of
limiting the input ripple voltage. With this configuration, the PV array has the electrical
characteristics of :
- Maximum power (Pmax)
= 120 W
- Voltage@ Pmax (Vmp)
= 68.4 V
- Current@ Pmax (Imp)
= 1.75 A
- Guaranteed minimum Pmax = 108 W
- Short-circuit current (Isc)
= 1.90 A
- Open-circuit voltage (Voc)
= 84.4 V
Note that, first, the array voltage at Pmax is approximately 81.0% of the array opencircuit voltage, and hence
Vmp 0.81 VOC

(3.1)

Second, the array current at Pmax is about 92.1% of the array short-circuit current, hence
I mp 0.921 ISC

(3.2)

Therefore, equations (3.1) and (3.2) can be applied to estimate Vmp and Imp of Voc and Isc
at the instantaneous array power. The change of array power depends on the solar
energy, as mentioned in Chapter1 and Chapter2, Isc always varies as the solar radiation
varies. Voc, on the other hand, slightly varies as the radiation doses but it significantly
decreases while the operating temperature rises.

27

Figure 3.2 Configuration of a 120-Watt PV array

3.1.3 ADMC331 DSP Board

ADMC331, a 16-bit digital signal processor (DSP) manufactured by Analog Devices
Inc., U.S.A, is chosen to implement the control algorithm in this thesis. Its advantages
are mentioned earlier in Chapter 2. Its specifications and features are mentioned in the
specification sheet and the users manual [6]. This thesis needs only three significant
functions of ADMC331; which are a fixed-point ADSP-2171 core processor, analog-todigital converters, and timers. These three DSP functions perform important roles in
controlling the system. Control algorithms are well designed and programmed into the
DSP.
Figure 3.3 presents the diagram of control algorithms inside the ADMC331. The DSP
receives four measured signals from the system, which are the PV array voltage (Vpv),
the PV array current (Ipv), the grid voltage (Vgrid), and the zero-crossing signal. The
DSP receives the zero-crossing signal through an input/output port, PIO1.6; this signal
tells DSP the conditions of the grid voltage. These conditions include the frequency of
grid voltage and the grid voltage is a positive signal. The DSP always waits for the first
zero-crossing signal, PIO interrupt occurs, and then starts executing the control
algorithms. At the beginning of the algorithm, the DSP enables PMWSYNC interrupt
which allows DSP to sample the analog inputs at the sampling frequency of 25 kHz.
Note that the procedure used to set the desired sampling frequency is mentioned in
Section 2.5.2, [6] and [7]. Three of analog signals (Vpv, Ipv, and Vgrid) are digitalized by
ADC and stored in three registers (ADC1, ADC2, and ADCAUX respectively). Vpv and
Ipv are inputted to the maximum power point tracking algorithm (MPPT). MPPT
calculates the instance power of the PV array and estimates the magnitude of the
reference current (K) that will draw the maximum electrical energy from the PV array
and transfer this energy to the converter. Vgrid is then normalized to be Inorm. By
multiplying Inorm with K, the DSP generates the digitalized reference current Iref.

28

TLV5618A, a digital-to-analog converter manufactured by TI, converts the digitalized

Iref back to be the analog Iref which is applied by the hystersis controller. In the mean
while, the current sink algorithm receives the digitalized Vgrid, then calculates the death
time and finally generates the gate drive commands for the inverter via PIO0.6 and
PIO0.7. PIO0.6 is responsible for driving the inverter during the positive Vgrid. PIO0.7,
on the contrary, has the responsibility of driving the inverter during the negative Vgrid.
The islanding algorithm is programmed for the security precaution; it monitors the grid
voltage via the zero-crossing signal. In the other words, this algorithm must monitor
two fault conditions, which are over/under grid frequency and zero grid voltage. The
zero-crossing signal, itself, is generated at every rising edge of the grid voltage. As the
consequence, the zero-crossing signal has the exact frequency as the Vgrid has, and this
signal will not be generated if the Vgrid is equal to zero. Hence, the islanding algorithm
uses a DSP timer to monitor the frequency of the zero-crossing signal. If there is no
fault condition, the islanding algorithm will allow the program to resume its duties.
However, if any fault conditions occur, the algorithm will halt the program and then
will use the watchdog timer to reinitiate all parameters and finally will wait for a proper
grid condition.

Figure 3.3 Diagram of control algorithms inside ADMC331

Figure 3.4 illustrates the full detail schematic of the ADMC331 and TLV5618A circuit
board. The printed circuit is basically constructed on this schematic.

29

Figure 3.4 Schematic of the ADMC331 and TLV5618A circuit board

30

3.1.4 Rectified Sinusoidal Hysteresis Controller

The rectified sinusoidal hysteresis controller has an obligation of controlling and
shaping the output current in such it matches the reference current. Figure 3.5 presents
the conceptual diagram of the rectified sinusoidal hysteresis controller.
According to Figure 3.5, the controller receives two inputs, the reference current (Iref)
and the output current (Io). Iref is generated by the DSP and TLV5618A, as mentioned in
section 3.1.3. The output current (Io) is measured and signal-conditioned by
HCPL788J, an optical isolated sensor. A difference amplifier, OP-07D with unity gain,
then subtracts both inputs; hence the error signal is generated by
I err = I O I ref

(3.3)

Figure 3.5 Diagram of the rectified sinusoidal hysteresis controller

The hysteresis controller, THS4021ID, compares the error signal whether it is out of the
allowance gap or not, as referred in Figure 3.6. This allowance gap, referred to Figure
3.7, is also called hysteresis gap or hysteresis band (HB), and is defined by
Hysteresis band = HB =

Ri
*VDD , whereVDD = 12 V.
Ri + R f

(3.4)

Figure 3.6 Schematic of the rectified sinusoidal hysteresis controller

If the error signal goes beyond the hystersis band, the controller will command the
converter switching elements to switch off. On the contrary, if the error signal goes
below the hyteresis band, the controller will switch on the switching elements of the

31

converter. Otherwise, the controller commands the switching elements to remain their
prior statuses. Finally, a 2N7000, a general purpose MOSFET, converts the output
signal from the hysteresis controller to a TTL signal. This TLL signal is the gate drive
command for the two-switch forward converter.

Figure 3.7 Hysteresis gap and the output of TLV5618A

3.1.5 Two-Switch Forward Converter

This section informs the procedures used to design the components of the two-switch
forward converter. Figure 3.8 illustrates the diagram of the forward converter.
The converter consists of three passive components; which are the isolated transformer,
the output inductor and the output capacitor; two switching elements and four recovery
diodes.

Figure 3.8 Diagram of the two-switch forward converter.

32

3.1.5.1 The Isolated Transformer

The isolated transformer not only isolates the PV array voltage from the grid voltage,
but it also amplifies the PV array voltage so that the output voltage of the converter can
be greater than the grid voltage. Therefore, the proper turn ratio must be investigated.
Considering the primary stage of the converter, the switches, Q1 and Q2, always turn on
and off at the switching frequency fS, the voltage across the primary side of the
transformer (Vpri) is hence given by
Vpri = D *Vpv

(3.5)

Whereas, D is the duty cycle and Vpv is the PV array voltage. If N is defined as the turn
ratio of the isolated transformer, the voltage across the secondary side of the transformer
is therefore defined as
Vsec = N *Vpri

(3.6)

And because the two-switch forward transformer is based on the step-down converter
(buck converter), hence the output stage of the converter is given by
VO = D *Vsec

(3.7)

Substitute (3.5) and (3.6) into (3.7), hence

VO = D *Vsec = D * N *Vpri = D * N *( D *Vpv ) = D 2 * N *Vpv

(3.8)

Finally, rewriting (3.8) yields

D=

VO
N *Vpv

(3.9)

N =

VO
D *Vpv

(3.10)

In order to determine the turn ratio (N), letting Vo is the grid voltage, the duty cycle (D)
is 50% and the PV array voltage is the voltage at the maximum power point (Vmp) which
is 68.4 V. Therefore,
Turn ratio ( N ) = 6.5

(3.11)

With the desired turn ratio, the proper turn number (Npri and Nsec) of the transformer can
be determined as showing in Appendix B.

3.1.5.2 The Output Inductor

The output inductor (L) is the output current ripple limiter. The larger the inductor is,
the smaller the current ripple will be. Unfortunately, if the inductor is too large, the
output current will not be shaped as the sinusoidal waveform because there will be too
much energy stored in the inductor. To determine the value of the output inductance,
the equation 2.19 is first calculated but the inductance still has not been the proper one
yet. Several trials should be taken, yields
Output inductor ( L) = 6 mH

(3.12)

33

The output current ripple and the slope of the current trail can be determined, referred to
section 2.3. Whereas, Appendix C presents the algorithm which is used to determine
the turn number and the air gap of the inductor.

3.1.5.3 The Output Capacitor

The output voltage ripple is limited by the output capacitor. Similar to the inductor, the
larger the capacitor is, the smaller the voltage ripple will be. However, the output
current will not be shaped as the sinusoidal waveform if the capacitor is too large.
Again, in order to determine the value of the capacitance, the equation 2.23 but, still,
several trials must be taken for the proper value. Hence
Output capacitor (C ) = 1F

(3.13)

The output voltage ripple also can be determined in equations presented in section 2.3.

3.1.5.4 The Switching Elements

Two IRFP450s, n-channel power MOSFET, are chosen as the switches Q1 and Q2.
They can withstand the voltage of 450 V across their terminals and the current of 14 A.
They can also operate over hundred kilohertz of switching frequency.

3.1.5.5 The Recovery Diodes

The recovery diodes must be able to operate at the same switching frequency with the
switches Q1 and Q2. Hence, MUR4100s, ultra fast recovery diodes, are chosen. Please
refer to their specification sheets for further details.

Figure 3.9 Schematic of the two-switch forward converter

3.1.6 Single Phase Inverter

The main purpose of the single phase inverter is to unfold the 100-Hz rectified
sinusoidal current so that the current can become a 50-Hz sinusoidal current. This
inverter, illustrated in Figure 3.10, consists of four switching elements and four fast
recovery diodes in which they are constructed four voltage-bidirectional two-quadrant
switches.

34

Figure 3.10 Diagram of the single phase inverter

The voltage-bidirectional two-quadrant switch, shown in Figure 3.11 and referred to [3],
has the properties of blocking both positive and negative voltage, but conducts only
positive current. When the switch is intended to be in the off state, the controller turns
the MOSFET off. The diode then blocks negative voltage, and the MOSFET blocks
positive voltage. The series connection can block negative voltages up to the diode
voltage rating, and positive voltages up to the MOSFET voltage rating. However, the
positive current will flow from the converter to the distributed line only if when the
converter output voltage is greater than the grid voltage plus diode forward-biased
voltage.

Figure 3.11 A voltage-bidirectional two-quadrant switch

(a) Implementation circuit
(b) Idealized switch characteristics
In this thesis, four power MOSFETs, IRFP450, and fours fast recovery diodes, FR407,
are chosen to construct the inverter. The full detail schematic of single phase inverter is
illustrated in Figure 3.12. However, IGBTs should be chosen instead of MOSFETs in
order to construct a larger scale of the system because IGBTs are cost effective as the
rated power increases.

35

Figure 3.12 Schematic of the single phase inverter

3.1.7 Gate Drivers

Because six switching elements are required in this system, two are for the forward
converter and the others are for the inverter, hence six gate drive circuits are also
required. However, these circuits are divided into two groups and are separately
grounded; the first group is for the converter and another is for the inverter as illustrated
in Figure 3.13 and Figure 3.15, respectively. All of the gate drive circuits are based on
TLP250, the optical isolated gate drive circuits. TLP250 has the maximum operating
frequency of 25 kHz and the maximum isolated voltage of 2500 Vrms which is
sufficient for this thesis. For further details, please refer to its specification sheets.

3.1.7.1 Gate Drivers for Two-Switch Forward Converter

Figure 3.13 illustrates the diagram of the gate drive circuit for the converter. The
hi-side circuit is powered by VDD1, a +12Vdc voltage source respects to an analog
ground COM, and has an obligation of controlling the switch Q1 via the SW1
command. The switch Q2, however, is controlled by the lo-side circuit which is
powered by VDD2, a +12Vdc voltage source respects to an analog ground 1. The full
detail of the converter gate drive circuit is shown in Figure 3.14.

Figure 3.13 Diagram of the converter gate drive circuit

36

Figure 3.14 Schematic of the converter gate drive circuit

3.1.7.2 Gate Drives for Inverter

The single phase inverter comprises of four switching elements, hence two hi-side gate
drive circuits and two lo-side gate drive circuits are required. Each of hi-side circuit
must be separately powered and grounded, as shown in Figure 3.15, because the switch
Q3 and Q4 are not electrically connected. The first hi-side circuit is powered by VDD3
and provides Hi1 command, while another hi-side circuit is powered by VDD4 and
commands the switch Q4 via Hi2 command. In contrast, both of the low-side circuit
can be powered and grounded by the same power supply, which is VDD5 respected to
an analog ground 2, because both of switches Q5 and Q6 are electrically connected.
Further details of the gate drive circuit are illustrated in Figure 3.16.

Figure 3.15 Diagram of the inverter gate drive circuit

37

Figure 3.16 Schematic of the inverter gate drive circuit

3.1.8 Sensors
Figure 3.17 illustrates the diagram of where sensors are positioned in the system. Two
voltage sensors are required in order to measure two voltage variables, which are the PV
array voltage and the grid voltage. Other two current sensors are applied to measure the
PV array current and the output current. The HCPL-788Js, optical isolated amplifiers,
are chosen to measure the PV array voltage, the PV array current, and the output
current. The grid voltage, however, is measured by using a 50-Hz voltage transformer.

Figure 3.17 Diagram of where sensors are positioned

3.1.8.1 HCPL-788J (Optical Isolated Amplifier with Short Circuit and

Overload Protection)
The HCPL-788J is an optical isolated amplifier; its internal function diagram is
illustrated in Figure 3.18. At the beginning, it converts the analog input to a digital
signal using a sigma-delta analog-to-digital converter (- ADC). This ADC samples
the input six million times per second and generates a high speed 1-bit output
representing the input very accurately. The encoder encodes this 1-bit data stream and
transmits data via a light emitting diode over the optical barrier. The detector converts
the optical signal back to a bit stream. This bit stream is decoded and drives a 1-bit
digital to analog-to-digital converter (DAC). Finally, a low pass filter and output buffer
drive the output signal which linearly represents the analog input signal. The output
signal full-scale range is determined by the external reference voltage. Another output,
the rectified output (ABSVAL), is also provided. The short-circuit fault output
(FAULT) is activated when the analog input exceeds 256 mV.

38

Equation (3.14) shows that the output voltage of HCPL-788J is proportional to the
analog input. If a positive analog input is applied, the output voltage then becomes
greater than a half of the reference voltage. However, if the input is zero, the output is
equal to the reference voltage. Otherwise, the output voltage is less than the reference
voltage.
Vout =

Vref * (VIN+ VIN- )

504 mV

(3.14)

The ABSVAL represents only the magnitude of the analog input signal and is
determined by
ABSVAL =

2*Vref *(VIN+ VIN- )

504 mV

(3.15)

For further details, please refer to HCPL-788J specification sheets.

Figure 3.18 Function diagram of HCPL-788J

3.1.8.2 Voltage Sensors

Two voltage sensors must be used in the thesis.

a. Vgrid Sensor
This sensor has an obligation of measuring the grid voltage. The 220-Vrms grid voltage
is attenuated to be a 9-Vrms voltage by using a 50-Hz voltage transformer. This
9-Vrms voltage is signal-conditioned by a difference amplifier, OP-07D, in order to
match the ADC specification of ADMC331. Finally the signal is inputted to ADCAUX,
the auxiliary ADC channel of ADMC331.

39

Figure 3.19 Diagram of Vgrid Sensor

b. Vpv Sensor
Typically, the PV array provides the open-circuit voltage (Voc) of 84.4 V. This Voc must
be voltage-divided to be 252 mV and is inputted to the HCPL-788J, therefore a
2,994.7 resistor is chosen as Rsense2, referred to (3.16).
Vpv =

Rsense2
*84.4 V
1M+Rsense2

(3.16)

Rsense2 2,994.7
However, the PV array provides the voltage of 68.4 V at typical maximum power
rating; hence the input voltage of the sensor is approximate 204 mV, referred to (3.17) .
Vpv =

Rsense2
*68.4V = 204mV, where Rsense2 2,995 (3.17)
1M + Rsense2

According to Figure 3.20, the analog input signal is amplified to the full-scale voltage
of 3.16 V by HCPL-788J. An OPA4228, which is constructed as a difference amplifier,
levels up the ABSVAL signal so that it matches the ADMC331 specification. Finally,
the measured Vpv signal is inputted to ADC1, the first ADC channel of ADMC331.

Figure 3.20 Diagram of Vpv sensor

40

3.1.8.3 Current Sensors

Two current sensors are also needed in this system.

a. Ipv Sensor
In general, the PV array provides 1.9 A of the short-circuit current (Isc). Therefore,
Rsense1 must be chosen so that the HCPL-788J input voltage reaches 252 mV at Isc.
Referred to (3.15), Rsense1 is given by
ABSVAL =

2*Vref * I pv * Rsense1
504 mV

2*Vref *1.9A * Rsense1

504 mV

= Vref

(3.18)

Rsense1 0.13
HCPL-788J amplifies the analog input and generates the ABSVAL, referred to (3.15)
and (3.18). Lastly, OPA4228 shifts the ABSVAL and inputs it to ADC2, the second
ADC channel of ADMC331.

Figure 3.21 Diagram of Ipv Sensor

b. Io Sensor
This sensor is designed to measure the output current of the forward converter, in fact it
measures the current which flows through the output inductor (Lo). The maximum
output current is carefully chosen to be 1 A. Therefore, Rsense3 is given by
2*Vref * I O * Rsense3 2*Vref *1A * Rsense3
=
504 mV
504 mV
= Vref

ABSVAL =

(3.19)

Rsense1 0.25
However, changing Rsense3 is also possible if the larger Io is required in the larger scale
system.
Similar to Ipv sensor, HCPL-788J amplifies the analog input and generates the
ABSVAL, referred to (3.15) and (3.19). Finally, OPA4228 raises the ABSVAL and
inputs it to the hysteresis controller.

41

Figure 3.22 Diagram of Io sensor

3.1.9 Zero-Crossing Detector

The zero-crossing detector is a sensor which detects the rising edge of grid voltage; it
generates the periodic pulse signal representing the frequency and the positive signal of
grid voltage. This periodic signal is utilized in two control algorithms. First, under the
current sink algorithm, the DSP detects it as the PIO interrupt and starts executing the
rest of the program after the interrupt has occurred. Second, it is used in islanding
algorithm; this algorithm monitors the grid frequency and halts program if any fault
conditions occur.
According to Figure 3.23, the 220-Vrms grid voltage is attenuated to be a 9-Vrms
voltage by a 50-Hz voltage transformer. The zener diode, 1N5231B, limits this
attenuated voltage to a 5-Vpk signal. LM339, a quad-comparator IC, reconstructs this
signal into a square wave signal. Finally, 74LS123, a monostable multivibrator,
converts the square wave signal to the periodic pulse signal.

Figure 3.23 Diagram of zero-crossing detector

42

3.2 Software Development

3.2.1 System Overview
Control algorithms can be divided into three groups, as illustrated in Figure 3.24, and all
of them are programmed into ADMC331. The first group contains the main program,
the second group is the PIO interrupt subroutine, and the last group is the PWMSYNC
interrupt subroutine. At the beginning, the main program initiates all parameters
required in all control algorithms and then waits until the first PIO interrupt occurs.
When the PIO interrupt request occurs, the program sequencer pushes the current value
of the program counter onto the PC stack and then executes the PIO interrupt
subroutine. Under the PIO interrupt subroutine, the program enables the PWMSYNC
interrupt (this allows execution of the PWMSYNC interrupt subroutine whenever it is
requested) and starts the islanding algorithm. When the PWMSYNC interrupt request
occurs, the program executes the PWMSYNC interrupt subroutine which continues to
execute the ADC algorithm, the current sink algorithm, the MPPT algorithm and the Iref
generator in sequence. Upon the return from either interrupt subroutine, the PC and
status stacks are popped and the execution resumes with the next instruction of the main
program.

Figure 3.24 Diagram shows control algorithms which are programmed into ADMC331

3.2.2 Analog-To-Digital Converting Algorithm

Figure 3.25 illustrates the diagram of the ADC algorithm. As mentioned earlier in
section 2.5, ADMC331 contains four ADC channels; three analog inputs are directly
connected to ADC1, ADC2, and ADC3, while other four analog inputs are multiplexed
and connected to ADCAUX. The ADC algorithm is executed under PWMSYNC
interrupt. After the PWMSYNC interrupt occurred, the DSP has finished converting all
analog inputs to the digital data. At the beginning of the algorithm, the DSP starts

43

receiving the digital data from the first ADC channel and then stores the data in the
desired variable. The algorithm then checks whether all four analog inputs are received
or not. If not, execute the algorithm again. Otherwise, exit this algorithm and execute
other instructions.

Figure 3.25 Diagram of the ADC algorithm

3.2.3 Current Sink Algorithm

The current sink algorithm, illustrated in Figure 3.26, is the algorithm that is designed to
generate the gate drive commands for the inverter. It receives the 50-Hz grid voltage
from the ADCAUX register and determines the midpoint voltage. It then computes the
upper threshold voltage (Vth1) and the lower threshold voltage (Vth2). Both Vth1 and Vth2
are used in the algorithm as the threshold level which will be applied to the decision
making algorithm in order to generate the inverter drive commands.
With a given threshold voltage (Vth), Vth1 is defined as
Vth1 = Vmidpoint + Vth

(3.20)

While Vth2 is defined as

Vth2 = Vmidpoint Vth

(3.21)

Note that, the larger Vth is, the longer the switch death time will be.
After Vth1 and Vth2 are computed, the decision making algorithm will take place. This
algorithm compares the instance Vgrid with the Vth1 and Vth2. If Vgrid is greater than Vth1,
switches Q3 and Q6 are turned on while switches Q4 and Q5 are turned off. On the
contrary, If Vgrid is less than Vth2, switches Q3 and Q6 are off while the others are on.
Otherwise, all switches are turned off.

44

Figure 3.26 Diagram of the current sink algorithm

Figure 3.27 Diagram of the MPPT algorithm

3.2.4 Maximum Power Point Tracking (MPPT) Algorithm

The MPPT algorithm is designed for tracking the PV array power in order that the
forward converter draws the maximum power from the array and transfers this power to
the system. The MPPT algorithm is a necessary algorithm for every PV system because
the PV array is expensive therefore it is reasonable to operate the system at its best
performance, mentioned earlier in Section 2.2.

45

The MPPT algorithm, which is used in this thesis, is based on [8]. The algorithm must
monitor the change of the PV array power (Ppv) correlated to the change of the array
voltage (Vpv), as expressed in (3.22) and (3.23).
Ppv = Vpv * I pv

(3.22)

Take the derivative of Ppv to Vpv, yields

dPpv
dVpv

= I pv +

dI pv
dVpv

*Vpv

(3.23)

where dIpv and dVpv are the changes of PV array voltage and current, respectively.
From (3.23), the dPpv dVpv can be replaced with I pv + (dI pv dVpv ) *V , making the
calculation practical for the ADMC331 16-bit DSP.

Figure 3.28 Characteristic diagram of dPpv dVpv versus Vpv

Figure 3.29 Diagram of the maximum power point tracking algorithm

46

Figure 3.28 depicts the diagram of dPpv dVpv versus Vpv.

When dPpv dVpv < 0 ,

decreasing the reference voltage (or increasing the reference current) forces dPpv dVpv
to approach zero. When dPpv dVpv > 0 , increasing the reference voltage (or increasing
the reference current) forces dPpv dVpv to approach zero. When dPpv dVpv = 0 , the
reference value does not need any change. The software diagram of MPPT algorithm is
also illustrated in Figure 3.29. In Figure 3.29, Vpv and Ipv are the instant PV voltage and
current, whereas Vprior and Iprior are the previous PV array voltage and current,
respectively.

3.2.5 Iref Generating Algorithm

Figure 3.30 illustrates the diagram of the Iref generating algorithm. This algorithm has
an obligation of generating Iref signal. At the beginning, DSP receives the digital data
which is converted by ADCAUX. This digitalized rectified sinusoidal signal is
normalized so that its magnitude is equal to one or 0x7FFF. Now, DSP receives the
scaling factor (K) which represents the magnitude of Iref. The digital Iref is determined
by
I ref = K * I norm

(3.24)

DSP sends this digital Iref to TLV5618A, the 12-bit digital-to-analog converter, via the
serial communication port. Finally, Iref is converted back to an analog Iref signal by
DAC.

Figure 3.30 Diagram of the Iref generating algorithm

3.2.6 Islanding Algorithm

As mentioned earlier in Chapter 2, the islanding algorithm acts as the precaution
algorithm. It monitors the grid voltage from two fault conditions, which are over/under
frequency and zero-grid voltage. Figure 3.31 represents the diagram of the islanding
algorithm. Timer T1 is assigned to monitor over frequency condition of the grid
voltage. At every rising edge of the zero-crossing signal, Timer T1 sets T1 Flag to
logic 1 and latches this flag for 22.22 ms; after that the flag is reset to logic 0.
Timer T2, on the other hand, is assigned to monitor under frequency condition. Timer

47

T2 starts latching T2 Flag to logic 1 at the moment the Timer T1 has reset T1
Flag. The T2 Flag is latched for 4 ms, after that it will be reset.
At the proper condition, where the grid frequency is 50 5 Hz, the zero-crossing signal
occurs while T1 Flag is logic 0 and T2 Flag is logic 1. As the result, the
islanding algorithm allows the program to resume its last execution. When the over
frequency condition occurs, the islanding algorithm detects that the zero-crossing signal
occurs while T1 Flag is logic 1 and T2 Flag is logic 0; these yield the islanding
algorithm to force the program to halt, reinitiate parameters and wait for the proper
condition. When the under frequency condition occurs, the algorithm detects that the
zero-crossing signal is risen while T1 Flag and T2 Flag is logic 0; these yields the
algorithm to reset, reinitiate the program and wait for the proper condition. Note that
zero-grid voltage condition also generates the 0-Hz zero-crossing signal in which the
islanding algorithm can be detected as the under frequency condition.

Figure 3.31 Diagram of the islanding algorithm

This chapter presents hardware designing and software programming. Hardware
designing started from seeking the proper theories and adapting those theories to the
practical hardware. The system hardware was divided in parts such as the PV array, the
forward converter, the single-phase inverter, the ADMC331 DSP board and so on.
Each part was discribed its function and schematic in this chapter. The software was
presented as diagrams. The diagrams presented how the software was excuted and what
the software was designed to do. The software was downloaded to the ADMC331 DSP
which was used as the brain of the system. In the next chapter, Chapter 4, the
experiments were set. The system was operated under the experimental constrains and
the experimental data were collected and discussed.

CHAPTER 4 THE EXPERIMENTS AND RESULTS

4.1 Experiment 1: System Characteristics
4.1.1 Objectives
-

To investigate voltage waveform and current waveform of the isolated

transformer, the output inductor and the output capacitor.
To investigate the switching frequency and the duty cycle of the system.

4.1.2 Instruments
The instruments used in this experiment are as follow
- DC Power supplies
: Model GPR3030 manufactured by Good Will
Instrument Co., Ltd.
: Model APS-1 manufactured by ANA-DIGIT
Group Co., Ltd.
- Digital multimeter
: METRA Hit 29S (digital power meter, digital
true RMS multimeter) manufactured by
Gossen-Metrawatt GMBH, Germany.
- Digital oscilloscope
: THD210 digital real-timer oscilloscope,
60MHz bandwidth and 1GS/s sampling rate,
manufactured by Tektronix INC, U.S.A.
- Current probe
: Model A6306 manufactured by Tektronix INC.
- Current probe amplifier : Model TM502A manufactured by Tektronix
INC, U.S.A..
- Voltage-different probe : 1 kVdc or 700 Vac rms input voltage.
Attenuation ratio is either 1:20 or 1:200.

4.1.3 Procedures
-

Connect two dc power supplies in series to build a 120-W 84-V dc power

supplies. These amounts of supplied power represent a 120-W PV array
with the open-circuit voltage (Voc) of 84.4 V.
Connect the current probe amplifier and a BNC connector of the voltage
probe to the digital oscilloscope.
Connect the current probe and the voltage-different probe to the positions
which intends to investigate, as illustrated in Figure 4.1, Figure 4.3, Figure
4.5, Figure 4.7, and Figure 4.9.

49

4.1.4 Experimental Results

4.1.4.1 Investigating Voltage and Current of the Primary Side of the
Isolated Transformer
This experiment was set to investigate voltage across the primary side of the isolated
transformer (Vpri) and to investigate current flows through the transformer (Ipri).
Figure 4.1 illustrates the positions of the voltage-different probe and the current probe
which were connected at the primary side of the transformer.

Figure 4.1 Positions of probes which were installed to investigate Vpri and Ipri of the
isolated transformer

Figure 4.2 Voltage and current of the primary side of the isolated transformer
Figure 4.2 illustrates voltage and current of the primary side of the transformer.
Whereas:
- CH1 = Voltage across the primary side of the isolated transformer.
- CH2 = Current flows through the primary side of the isolated transformer.
- Voltage-different probe was set to 1:20 attenuation ratio, hence

50

Vpri = 20* Scope _ read _ out (V/Div)

-

(4.1)

Current probe was set to 2 A/Div, hence

I pri =

2* Scope _ read _ out

(A/Div)
10 mV

(4.2)

4.1.4.2 Investigating Voltage and Current of the Secondary Side of the

Isolated Transformer
In this experiment, the voltage across the secondary side of the isolated transformer
(Vsec) and the current flows through the transformer (Isec) were investigated. Figure 4.3
illustrates the positions of the voltage-different probe and the current probe which were
connected at the secondary side of the transformer.

Figure 4.3 Positions of probes installed to investigate Vsec and Isec of the transformer

Figure 4.4 Voltage and current of the secondary side of the isolated transformer

51

Figure 4.4 shows voltage and current of the secondary side of the transformer.
Whereas:
- CH1 = Voltage across the secondary side of the isolated transformer.
- CH2 = Current flows through the secondary side of the isolated transformer.
- Voltage-different probe was set to 1:200 attenuation ratio, hence
Vsec = 200* Scope _ read _ out (V/Div)
-

(4.3)

Current probe was set to 0.5A/Div, hence

I sec =

0.5* Scope _ read _ out

(A/Div)
10 mV

(4.4)

4.1.4.3 Investigating Voltage and Current Across the Output Inductor

In this section, the voltage across the output inductor (VL) and the current flows through
it (IL) were measured. Figure 4.5 illustrates the locations where the voltage-different
probe and the current probe were installed.

Figure 4.5 Positions of voltage-different probe and current probe

52

Figure 4.6 Voltage and current across the output inductor

Figure 4.6 shows voltage and current of the inductor. Whereas:
- CH1 = Voltage across the output inductor.
- CH2 = Current flows through the output inductor.
- Voltage-different probe was set to 1:200 attenuation ratio, hence
VL = 200* Scope _ read _ out (V/Div)
-

(4.5)

Current probe was set to 0.5A/Div, hence

IL =

2* Scope _ read _ out

(A/Div)
10 mV

(4.6)

4.1.4.4 Investigating Output Voltage and Output Current of the Converter

In this experiment, the output voltage of the converter (VO) and the output current (IO)
were investigated. Figure 4.7 shows the position where the voltage-different probe and
the current probe were connected.

Figure 4.7 Positions of probes installed to measure VO and IO of the output inductor

53

Figure 4.8 Output voltage and output current of the two-switch forward converter
Figure 4.8 shows voltage and current of the secondary side of the transformer.
Whereas:
- CH1 = Output voltage of the two-switch forward converter.
- CH2 = Output current of the two-switch forward converter.
- Voltage-different probe was set to 1:200 attenuation ratio, hence
VO = 200* Scope _ read _ out (V/Div)
-

(4.7)

Current probe was set to 2A/Div, hence

IO =

0.5* Scope _ read _ out

(A/Div)
10 mV

(4.8)

4.1.4.5 Investigating Voltage and Current Transferred to the Distribution

Line
This experiment was set to investigate the grid voltage (Vgrid) and the current flows
through the distribution line (Igrid). Figure 4.9 illustrates the positions where the
voltage-different probe and the current probe which were installed in order to measure
Vgrid and Igrid.

54

Figure 4.9 Positions of probes which were connected to measure the voltage and
current of the distribution line
Figure 4.10 shows voltage and current of the distribution line.
Whereas:
- CH1 = Voltage of the distribution line.
- CH2 = Current flows through the distribution line.
- Voltage-different probe was set to 1:200 attenuation ratio, hence
Vgrid = 200* Scope _ read _ out (V/Div)
-

(4.9)

Current probe was set to 2A/Div, hence

I grid =

0.5* Scope _ read _ out

(A/Div)
10 mV

Figure 4.10 Voltage and current which was transferred to grid

(4.10)

55

4.1.4.6 Investigating Minimum Switching Frequency and Minimum Duty

Cycle Generated by Hysteresis Controller
In this experiment, the minimum switching frequency (fsmin) and the minimum duty
cycle (Dmin), which is generated by hysteresis controller, were investigated. The
voltage-different probe was connected across the output inductor and the current probe
was also connected to measure the current which flows through the inductor, shown in
Figure 4.11. The digital oscilloscope was used to investigate the switching frequency
and the duty cycle.

Figure 4.11 Positions of probes which were installed to determine fsmin and Dmin

Figure 4.12 Minimum switching frequency which was generated by hysteresis

controller
Figure 4.12 illustrates the minimum switching frequency (fsmin) while Figure 4.13
illustrates the minimum duty cycle (Dmin).
Whereas:
- CH1 = Voltage across the output inductor.
- CH2 = Current flows through the output inductor.

56

Voltage-different probe was set to 1:200 attenuation ratio, hence

VL = 200* Scope _ read _ out (V/Div)

(4.11)

Current probe was set to 0.5A/Div, hence

IL =

0.5* Scope _ read _ out

(A/Div)
10 mV

(4.12)

In Figure 4.12, the fsmin can be measured by using the cursor of the digital oscilloscope.
f smin = 7.353kHz

(4.13)

The period is given by

Tmin =

1
fsmin

= 136 s

(4.14)

Again, Figure 4.13 shows the measuring of the turn-on time (ton), hence
ton = 26 s

(4.15)

The minimum duty cycle can be expressed as

Dmin =

ton
= 0.2
Tmin

(4.16)

Figure 4.13 Minimum duty cycle which was generated by hysteresis controller

57

4.1.4.7 Investigating Maximum Switching Frequency and Maximum Duty

Cycle Generated by Hysteresis Controller
This experiment was set to determine the maximum switching frequency (fsmax) and the
maximum duty cycle (Dmax) which were generated by the hysteresis controller. In
Figure 4.14 the position of the voltage-different probe and the current probe are
presented. These probes were used to measure the voltage across the output inductor
and the current flows through the inductor, respectively.

Figure 4.14 Positions of probes which were installed to determine fsmax and Dmax

Figure 4.15 Maximum switching frequency which was generated by hysteresis

controller
The cursor of the digital oscilloscope was applied to determine Tmax and ton, as depicted
in Figure 4.15 and Figure 4.16 respectively.
Whereas:
- CH1 = Voltage across the output inductor.
- CH2 = Current flows through the output inductor.
- Voltage-different probe was set to 1:200 attenuation ratio, hence

58

VL = 200* Scope _ read _ out (V/Div)

-

(4.17)

Current probe was set to 0.5A/Div, hence

IL =

0.5* Scope _ read _ out

(A/Div)
10mV

(4.18)

In Figure 4.15, the maximum switching frequency is determined as

f smax = 9.434 kHz

(4.19)

The period is given by

Tmax =

1
fsmax

= 106s

(4.20)

Again, Figure 4.13 shows the measuring of the turn-on time (ton), which is
ton = 36s

(4.21)

The minimum duty cycle can be expressed as

Dmin =

ton
= 0.34
Tmin

(4.22)

Figure 4.16 Maximum duty cycle which is generated by hysteresis controller

59

4.2 Experiment 2: System Performance

4.2.1 Objectives
-

To investigate the efficiency of the converter and the inverter.

To investigate the efficiency of the MPPT.

4.2.2 Instruments
The instruments used in this experiment are as follow
- Digital multimeter
: METRA Hit 29S (digital power meter, digital
true RMS multimeter) manufactured by
Gossen-Metrawatt GMBH, Germany.
- Digital oscilloscope
: THD210 digital real-timer oscilloscope,
60MHz bandwidth and 1GS/s sampling rate,
manufactured by Tektronix INC.
- Current probe
: Model A6306 manufactured by Tektronix INC.
- Current probe amplifier : Model TM502A manufactured by Tektronix
INC.
- Voltage-different probe : 1 kVdc or 700 Vac rms input voltage.
Attenuation ratio is either 1:20 or 1:200.

4.2.3 Procedures
-

Connect the PV array to the system.

Connect the current probe amplifier and a BNC connector of the voltage
probe to the digital oscilloscope.
Connect the current probe and the voltage-different probe to the positions
which intends to measure, as illustrated in Figure 4.17.
Measure Voc and Isc.
Connect a variable resistance load with the PV array as illustrated in Figure
4.17.
Measure Vmp, Imp, and Pmax.
Set the experiment as illustrated in Figure 4.18.
Measure Vpv, Ipv, Vgrid and Igrid.
Calculate the power of PV array which is tracked by MPPT (Ppv).
Calculate the power which is transferred to the grid (Pgrid).
Calculate the efficiency of the system.

60

4.2.4 Experimental Results

The experiment started by measuring PV characteristics such as the open-circuit voltage
(Voc), and the short-circuit current (Isc). The positions of probes are resented as Figure
4.17(a) and (b), respectively. In Figure 4.17 (c), the PV array was connected to a
variable resistance load; the value of load was varied from maximum to minimum. As
the results, the maximum power (Pmax), which the PV array was able to produce at a
given solar radiation, could be investigated. Whereas, Vmp represents the voltage which
the PV array generates at Pmax, Imp represents the current which the PV array generates
at Pmax.

Figure 4.17 (a) Voc measurement, (b) Isc measurement, and (c) Pmax measurement
The measurement of Voc, Isc, Vmp, Imp, and Pmax are summarized in Table 4.1 and Table
4.2.
Table 4.1 Measured Voc and Isc on March 2, 2003
Characteristics of PV array
Time

Open-circuit voltge (Voc)

Short-circuit current (Isc)

(V)

(A)

12:00 A.M.

77.200

1.576

12:30 P.M.

76.900

1.521

1:00 P.M.

76.500

1.423

1:30 P.M.

75.900

1.313

2:00 P.M.

75.400

1.200

2:30 P.M.

74.800

1.140

3:00 P.M.

74.100

0.986

3:30 P.M.

73.500

0.830

4:00 P.M.

72.900

0.677

61

Table 4.2 Measured Vmp, Imp, and Pmax on March 2, 2003

Characteristics of PV array
Time

Voltage at max.

Current at max.

Maximum power of

power (Vmp) in (V)

power (Imp) in (A)

PV (Pmax) in (W)

12:00 A.M.

62.532

1.450

90.7

12:30 P.M.

62.289

1.399

87.1

1:00 P.M.

61.965

1.309

81.1

1:30 P.M.

61.479

1.208

78.7

2:00 P.M.

61.074

1.104

67.4

2:30 P.M.

60.588

1.049

63.5

3:00 P.M.

60.021

0.907

54.4

3:30 P.M.

59.535

0.764

45.5

4:00 P.M.

59.049

0.623

36.8

According to Table 4.1 and 4.2, the PV array generated power less than its maximun
value (120 W) because it was cloudy during the end of February and the mid of March.
As the consequence, the solar radiation was low which caused PV array generated less
energy.
Note that, the maximum power of the PV array (Pmax) was later used to determine the
efficiencies.
Now, let set up the experiment which will be used to investigate Vgrid, Igrid, Vpv, and Ipv.
Figure 4.18 depicts the positions of voltage-different probes and current probes which
were installed in the system in order to investigate the efficiency of the system. The
experimental results were summarized in

Figure 4.18 Positions of probes which were used to investigate the system efficiency

62

Table 4.3 Measured Vpv, Ipv, and Ppv on March 3, 2003

Characteristics of the system

Time

PV array voltge (Vpv)

PV array current (Ipv)

PV power under

(V)

(A)

MPPT (Ppv) in (W)

12:00 A.M.

64.303

1.230

79.3

12:30 P.M.

64.504

1.195

77.1

1:00 P.M.

64.848

1.216

78.9

1:30 P.M.

63.963

1.211

77.5

2:00 P.M.

63.707

1.157

73.7

2:30 P.M.

62.754

1.112

69.8

3:00 P.M.

63.214

0.987

62.4

3:30 P.M.

61.733

0.898

55.4

4:00 P.M.

61.312

0.747

45.8

Table 4.4 Measured Vgrid, Igrid, and Pgrid on March 3, 2003

Characteristics of the system

Time

Grid voltage (Vgrid)

Grid current (Igrid)

Power transferred to

(V)

(A)

grid (Pgrid) in(W)

12:00 A.M.

111.600

0.641

71.5

12:30 P.M.

111.200

0.627

69.7

1:00 P.M.

110.800

0.648

71.8

1:30 P.M.

111.500

0.619

69.0

2:00 P.M.

111.500

0.599

66.8

2:30 P.M.

110.800

0.567

62.8

3:00 P.M.

111.000

0.503

55.8

3:30 P.M.

110.600

0.455

50.3

4:00 P.M.

111.600

0.364

40.6

As a final point, the maximum power of PV array (Pmax), the PV array power under
MPPT (Pmppt), and the power transferred to grid (Pgrid) were the variables which were
used to investigate the performance of the system as summarized in Table 4.5.

63

Table 4.5 Performance of the system

Characteristics of the system

mppt =100* Ppv P max

inv =100* Pgrid P pv

sys = 100* Pgrid P pv

(%)

(%)

(%)

12:00 A.M.

85.4

90.2

77.1

12:30 P.M.

85.7

90.4

77.5

1:00 P.M.

86.1

91.0

78.4

1:30 P.M.

85.9

89.3

76.8

2:00 P.M.

84.8

90.6

76.8

2:30 P.M.

86.1

90.0

77.5

3:00 P.M.

86.4

89.5

77.2

3:30 P.M.

86.1

90.8

78.1

4:00 P.M.

85.7

88.7

76.0

Time

As mentioned eariler, it was cloudy during the end of February and the mid of March.
The solar radiation was low because of the weather, hence the PV array could generate
less electrical energy than it maximum value (120 W). According to Table 4.5, the PV
array generated 85.9 W at 1.30 P.M. which is less than the generated power at 3.00 P.M.
because the cloud blocked the solar radiation. On the contrary, the sky was a bit clearier
at 3.30 P.M., therefore the PV array could generated electrical energy up to 78.1 W.

CHAPTER 5 CONCLUSIONS
5.1 Conclusions
The conventional grid-connected PV system consists of a step-up converter, a single
phase inverter and a low-frequency transformer. The converter, which operates at high
switching frequency, steps up the PV array voltage. It also tracks the PV output power
and tends to transfer the maximum power to the inverter. The single phase inverter then
shapes the output current to be 50-Hz sinusoidal waveform by using high frequency
pulse-width modulation. Therefore, at least five switching elements (depending on the
converter topologies) must be operated at high switching frequency.

Figure 5.1 The conventional grid-connected PV system

This thesis scopes on the grid-connected PV system which tends to reduce the number
of the high switching frequency elements. The system consists of a two-switch forward
converter (a transformer isolated step-up converter) and a single phase inverter. The
two-switch forward converter has several obligations; it tracks the PV power by using
the MPPT so that it can transfer the maximum power in which the PV can provide at a
given solar radiation. By using grid voltage as the reference waveform and a rectified
sinusoidal hysteresis controller, the converter is able to shape the output current
waveform to match frequency and phase of the grid voltage. The magnitude of the
output current, which is calculated by the MPPT, is the value that PV array can transfer
the maximum electrical energy to the distribution line. Moreover, the forward converter
is a transformer isolated version of buck converter, therefore a high frequency
transformer is a necessary component of this converter. This transformer isolates the
PV array voltage from the grid voltage which prevents any damages could occur to the
PV array and the control circuits. Because the cost and size of a transformer is
significantly decreasing as the operating frequency is rising, hence, the high frequency
transformer is more reasonable choice than the low-frequency transformer. The inverter
consists of four switching elements and it is operated at the switching frequency of 50
Hz. Its only function is to unfold the rectified sinusoidal current to be the sinusoidal
current. In conclusion, the converter consists of two switching elements which are
operated at high switching frequency; the inverter consists of four switching elements
which are operated at low switching frequency. Therefore, the number of the high
frequency switching elements is reduced from five switches to two switches.

65

Figure 5.2 The grid-connected PV system designed in this thesis

The system performance (sys) depends on two factors; the MPPT efficiency (mppt) and
the converter-inverter efficiency (inv). The MPPT efficiency (mppt) is the efficiency of
the maximum power point tracking algorithm, it is calculated by
mppt =

Vpv * I pv
Vmp * I mp

*100 =

Ppv
Pmax

*100

(5.1)

Where:
-

Ppv = PV output power in which the MPPT algorithm tracks along the
maximum power locus (W).
- Pmax = actual maximum power in which the PV array can provide at a given
solar radiation (W).
The second factor is the converter-inverter efficiency (inv). This factor is the efficiency
of the converter and the inverter which is calculated by
inv =

Vgrid * I grid
Vpv * I pv

*100 =

Pgrid
Ppv

*100

(5.2)

Where:
-

Pgrid = power which is transferred into the distribution line (W).

Ppv = PV output power which is also the input power of the two-switch
forward converter (W).
Therefore, the overall efficiency of the system is given by
sys =

Pgrid
Pmax

*100 = mppt *inv

All of the efficiency is calculated and summarized in Table 4.5.

(5.3)

66

5.2 Future Improvements

5.2.1 Current Controller
Even though the rectified hysteresis current controller is easy to implement for both
hardware and software, it also generates wide ranges of switching frequency.
According to section 4.1.4.6 and section 4.1.4.7, the maximum frequency is about 10
kHz whereas the minimum frequency is about 7 kHz. Generally, a given switching
frequency causes the significant harmonic at the same as a frequency of the switching
frequency. As the consequence, the hysteresis current controller generates several
harmonics depending on the switching frequencies. The harmonics cause the aliasing
output current wave form, as illustrated in Figure 4.9 and Figure 4.10.
Instead of using a fixed-tolerance band hysteresis current control scheme (a type of
hysteresis control scheme [1] which also the same type of control scheme purposed in
this thesis), more advance hysteresis current control schemes might be considered to
overcome the current harmonic issues. These more advance control schemes are, for
example, the fixed-frequency control scheme [1], and the adaptive hysteresis band
current control techniques [15, 16, and 17].
A sinusoidal pulse-width modulation (SPWM) may be a better choice instead of the
rectified hysteresis current controller. In SPWM, a sinusoidal signal is compared with a
fixed-frequency triangular signal; the comparator output is the gate drive signal for the
converter as the depicted in Figure 5.3. The comparator output always has the same
frequency as the triangular signal, as the results, there is only the switching frequency
which is the same frequency as the triangular signal. In conclusion, the harmonic
generated by SPWM is more predictable and is easier to be eliminated.

Figure 5.3 Basic current control scheme using SPWM

Figure 5.4 illustrates the comparison between the triangular reference signal and the
error signal of the output current. Figure 5.4 also shows the comparator output signal
which is inputted to the gate drive circuit.

67

Figure 5.4 Sinusoidal pulse-width modulation

5.2.2 Harmonics Elimination

Harmonic trap filters are the reasonable choice in order to reduce the current harmonics
generated by the system. The filter network is designed to pass the fundamental and to
attenuate the significant harmonics such as the third, fifth, seventh and perhaps several
higher-order odd nontriplen harmonics. Such filters are constructed by using resonant
tank circuits tuned to the particular harmonic frequencies.
A diagram of the filter network is illustrated in Figure 5.5. The distribution system is
modeled by the thevenin-equivalent network containing voltage source and a series
inductor LS. The inverter and its current harmonics are modeled by current source.
Shunt impedances, Z1, Z2, and so on, are tuned such that they have low impedance at the
particular harmonic frequencies, and hence the harmonic currents tend to flow through
the shunt impedances rather than into the distribution system. These shunt impedances
called harmonic trap filters. The filter transfer function HF(S) is given by the current
divider ratio
H F ( s) =

igrid ( s )
iO ( s)

Z1 P Z 2 P Z 3 P ...
Z Ls + Z1 P Z 2 P Z3 P ...

(5.4)

So if the third harmonic currents are decided to be attenuated, the filter elements must
be chosen such that the series resonant frequency f1 coincides with the third harmonic
frequency. This frequency is simply the resonant frequency of the shunt impedance Z1,
yields
f1 =

1
1
=
2
2 L1C1

(5.5)

68

To eliminate other significant harmonics, filter elements must be properly chosen in the
same ways as the third harmonic trap filter is designed.

(a)

(b)
Figure 5.5 Harmonic trap filters
(a) the diagram
(b) equivalent circuits

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APPENDIX A
Specification Sheet of MSX-Lite 30 Solar Module

72

73

APPENDIX B
Transformer Design

75

Appendix B presents the formulas which are used to calculate the characteristics of the
isolated transformer such as the primary winding turn number, the secondary winding
turn number, the magnetizing inductance, and so on. These formulas are referenced
from [4]. After redeveloping these formulas as an M-file, MATHLAB6.1 can finally be
used to determine the transformer characteristics. Note that, the sentences which follow
% are the programmers comments, whereas other are the formulas under M-file
format.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
%
%
The following quantities are specified by the designer.
%
%
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Power Output
Po
(W)
Pin = 119.7;
% Input Voltage
Vin
(V)
Vin = 68.4;
% Output Voltage
Vo
(V)
Vorms = 220;
Vo = Vorms*sqrt(2);
% Input current
I1
(A)
Iin = 1.75;
% Output current
I2
(A)
Iorms = 0.54;
Io = Iorms*sqrt(2);
% Primary Votage
V at D = 0.5
Vp = Vin;
% Secondary Votage
V at D = 0.5
Vs = 440;
% Primary RMS Current
A at D = 0.5
Ip = Iin;
% Secondary RMS Current
A at D = 0.5
Is = 0.54;
% Frequency
f
(Hz)
f = 10000;
% Efficiency
n
n = 1;
% Regulation
Reg (%)
Reg = 1.0;
% Flux density
Bm
(T)
Bm = 0.3;
% Winding fill factor
Ku
Ku = 0.5;
% Applied primary volt-seconds
% Lamda = Intergral of positive cycle v(t) by dt (V-sec)
Lamda = 0.00342;
% Core material:
% Core Type:
% Core cross-sectional area

FDK 6H20
ETD-49
Ac
(cm2)

76

Ac = 2.11;
% Core window area
Wa = 2.71;
% Mean length per turn
MLT = 8.51;
% Macnatic path length
lm = 11.4;
% Constant
Role = 1.724e-6;
Kf = 4.44;
u0 = 4*pi*1e-7;
u = 0.00125;
Ap = Wa*Ac;

Wa

(cm2)

MLT (cm)
lm

(cm)

% For a sine wave

%(H/m)
% u = B/H = material permeability at B<=5 mT

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
%
%
Transformer formulas are as follow.
%
%
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% 1. Calculate the transformer input and output power
%
Pp = Vp*Ip
(W)
%
Ps = Vs*Is
(W)
Pp = Vp*Ip;
Ps = Vs*Is;
sprintf('\b\b\b\b\b\b\b1. Calculate the transformer input and output power.\n\tPp
= %0.5g W',Pp)
sprintf('\b\b\b\b\b\b\b\b\b\tPs = %0.5g W',Ps)
% 2. Calculate the total apparent power Pt:
%
Pt = Pp+Ps

(W)

Pt = Pp+Ps;
sprintf('\b\b\b\b\b\b\b\b2. Calculate the total apparent power.\n\tPt = %0.5g
W',Pt)
% 3. Calculate the electrical conditions:
%
Ke = 0.145*Kf^2*f^2*Bm^2*1e-4
Ke = 0.145*Kf^2*f^2*Bm^2*1e-4;
sprintf('\b\b\b\b\b\b\b\b3. Calculate the electrical conditions.\n\tKe = %0.5g
,Ke)
% 4. Calculate the core geometry coefficient:
%
Kg = Pt/(2*Ke*Reg)

(cm5)

Kg = Pt/(2*Ke*Reg);
sprintf('\b\b\b\b\b\b\b\b4. Calculate the core geometry coefficient.\n\tKg >=
%0.5g cm5',Kg)

77

% 5. Calculate the number of primary turns Np:

%
Np = (Vp1*1e4)/(Kf*Bm*f*Ac)

(Turns)

Np = (Vp*1e4)/(Kf*Bm*f*Ac);
sprintf('\b\b\b\b\b\b\b\b5. The number of primary turns.\n\tNp = %0.5g Turns.'
,Np)
% 6. Calculate the primary current Ip:
%
Ip = (Pp)/(Vp*n)

(A)

Ip = (Pp)/(Vp*n);
sprintf('\b\b\b\b\b\b\b\b6. The primary current.\n\tIp = %0.5g A.',Ip)
% 7. Calculate the current density J:
%
J = (Pt*1e4)/(Kf*Ku*f*Bm*Ap)

(A/cm2)

J = (Pt*1e4)/(Kf*Ku*f*Bm*Ap);
sprintf('\b\b\b\b\b\b\b\b7. Calculate the current density.\n\tJ = %0.5g A/cm2.',J)
% 8. Calculate the wire size of the primary Aw1:
%
Aw1 = Ip/J

(cm2)

Aw1 = Ip/J;
sprintf('\b\b\b\b\b\b\b\b8. Calculate the wire size of the primary.\n\tAw1 =
%0.5g cm2.',Aw1)
sprintf('\b\b\b\b\b\b\b\b\b\t** Select a wire size from the table. Remember: If
the wire area isnt within 10 percent, take the next smallest size. **')
% 9. Calculate the number of secondary turns Ns:
%
Ns = ((Np*Vs)/Vp)*(1+(Reg/100)) (Turns)
Ns = ((Np*Vs)/Vp)*(1+(Reg/100));
sprintf('\b\b\b\b\b\b\b\b9. The number of secondary turns.\n\tNs = %0.5g
Turns.',Ns)
% 10. Calculate the wire size of the secondary Aw2:
%
Aw2 = Is/J
(cm2)
Aw2 = Is/J;
sprintf('\b\b\b\b\b\b\b\b10. Calculate the wire size of the secondary.\n\tAw2 =
%0.5g cm2.',Aw2)
sprintf('\b\b\b\b\b\b\b\b\b\t** Select a wire size from the table. Remember: If
the wire area isnt within 10 percent, take the next smallest size. **')
% Check the winding resistance.
sprintf('\b\b\b\b\b\b\b\b\b\n11. Check the calculations.')

78

% Magnetizing inductance, referred to winding 1

%
Lm = (u*n1^2*Ac)/lm

(H)

Lm = (u*Np^2*Ac)/lm;
sprintf('\b\b\b\b\b\b\b\b\b\n\tMagnetizing inductance referred to winding1.
\n\tLm = %0.5g H',Lm)
% Magmetization reluctant
%
R = lm/(u*Ac)
R = lm/(u*Ac);
sprintf('\b\b\b\b\b\b\b\b\b\n\tMagnetization reluctant.\n\tR = %0.5g ',R)
% Peak ac magnetizing current, referred to winding 1
%
Impk = lamda/(2*Lm)
(A)
Impk = Lamda/(2*Lm);
sprintf('\b\b\b\b\b\b\b\b\b\n\tPeak ac magnetizing current referred to winding1.
\n\tImpk = %0.5g A',Impk)
% Magnetizing Resistance, referred to winding 1
%
Rm = Vp/Impk

(Ohm)

Rm = Vp/Impk;
sprintf('\b\b\b\b\b\b\b\b\b\n\tMagnetizing Resistance referred to winding 1.
\n\tRm = %0.5g Ohm',Rm)
% Winding resistances
%
R1 =(Role*n1*MLT)/(Aw1)
%
R2 =(Role*n2*MLT)/(Aw2)

(Ohm)
(Ohm)

Rp =(Role*Np*MLT)/(Aw1);
Rs =(Role*Ns*MLT)/(Aw2);
sprintf('\b\b\b\b\b\b\b\b\b\n\tWinding resistances.\n\t Rp = %0.5g Ohm',Rp)
sprintf('\b\b\b\b\b\b\b\b\b\tRs = %0.5g Ohm',Rs)

APPENDIX C
Inductor Design

80

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
%
%
The following quantities are specified by the designer.
%
%
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Inductor
L
(H)
L = 100e-3;
% Output Voltage
Vo
(V)
Vorms = 220;
Vo = Vorms*sqrt(2);
% DC Current
Io
(A)
Iorms = 1;
Io = Iorms*sqrt(2);
% AC Current
dI
(A)
dI = 0.1;
% Output Power
Po
(W)
Po = 220;
% Frequency
f
(Hz)
f = 10000;
% Efficiency
n
n = 1;
% Regulation
Reg (%)
Reg = 1.0;
% Flux density
Bm
(T)
Bm = 0.9;
% Winding fill factor
Ku
Ku = 0.5;
% Applied primary volt-seconds
% Lamda = Intergral of positive cycle v(t) by dt (V-sec)
Lamda = 0.00342;
% Core material:
% Core Type:
% Core cross-sectional area
Ac = 2.11;
% Core window area
Wa = 2.71;
% Mean length per turn
MLT = 8.51;
% Macnatic path length
lm = 11.4;
% G Dimention = 2*F I guess!
G = 2*1.77;
% Constant
Role = 1.724e-6;
Kf = 4.44;
u0 = 4*pi*1e-7;
u = 0.00125;
Ap = Wa*Ac;

FDK 6H20
ETD-49
Ac
(cm2)
Wa

(cm2)

MLT (cm)
lm

(cm)

(cm)

% For a sine wave

% (H/m)
% u = B/H = material permeability at B<=5 mT

81

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
%
%
Inductor formulas are as follow.
%
%
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% 1. Calculate the energy-handing capability:
%
E = (L*(Iorms+(dI/2))^2)/2
W-s
E = (L*(Iorms+(dI/2))^2)/2;
sprintf('\b\b\b\b\b\b\b1. Calculate the energy-handing capability.\n\tE = %0.5g
W-s',E)
% 2. Calculate the electrical conditions:
%
Ke = 0.145*Po*Bm^2*1e-4
Ke = 0.145*Po*Bm^2*1e-4;
sprintf('\b\b\b\b\b\b\b\b2. Calculate the electrical conditions.\n\tKe = %0.5g
,Ke)
% 3. Calculate the core geometry coefficient:
%
Kg = E^2/(Ke*Reg)
cm5
Kg = (E^2)/(Ke*Reg);
sprintf('\b\b\b\b\b\b\b\b3. Calculate the core geometry coefficient.\n\tKg >=
%0.5g cm5',Kg)
% 4. Calculate the current density J:
%
J = (2*E*1e4)/(Bm*Ap*Ku) (A/cm2)
J = (2*E*1e4)/(Bm*Ap*Ku);
sprintf('\b\b\b\b\b\b\b\b4. Calculate the current density.\n\tJ = %0.5g A/cm2.',J)
% 5. Calculate the bare wire size of the primary Aw1:
%
Aw = (Iorms+(dI/2))/J
(cm2)
Aw = (Iorms+(dI/2))/J;
sprintf('\b\b\b\b\b\b\b\b5. Calculate the wire size of the primary.\n\tAw = %0.5g
cm2.',Aw)
sprintf('\b\b\b\b\b\b\b\b\b\t** Select a wire size from the table. Remember: If
the wire area isnt within 10 percent, take the next smallest size. **')
% 6. Calculate the effective window area Waeff.
%
A typical alue for S3 is 0.75, as shown in Chapter 6.
%
Waeff = Wa*S3
(cm2)
S3 =0.75;
Waeff = Wa*S3;
sprintf('\b\b\b\b\b\b\b\b6. Calculate the effective window area.\n\tWaeff =
%0.5g cm2.',Waeff)

82

% 7. Calculate the number of primary turns N:

%
A typical alue for S2 is 0.6, as shown in Chapter 6.
%
N = (Waeff*S2)/(Aw) (Turns)
S2 = 0.6;
N = (Waeff*S2)/Aw;
sprintf('\b\b\b\b\b\b\b\b7.
The number of primary turns.\n\tN = %0.5g
Turns.',N)
% 8. Calculate the required gap and use the iron area Ac:
%
lg = (0.4*N^2*Ac*1e-8)/L
(cm)
lg = (0.4*N^2*Ac*1e-8)/L;
sprintf('\b\b\b\b\b\b\b\b8. Calculate the required gap.\n\tlg = %0.5g cm.',lg)
lg = lg*393.7;
%(mils)
sprintf('\b\b\b\b\b\b\b\b\b\tlg = %0.5g mils.' ,lg)
sprintf('\b\b\b\b\b\b\b\b\b\t** Round off to the nearest even mil. **')
lg = input(' Round off lg =');
lg = lg*2.54*1e-3;
%(cm)
sprintf('\r\b\b\b\b\b\b\b\b\b\tlg = %0.5g cm.' ,lg)
% 9. Calculate the amount of fringing flux F:
%
F = 1+(lg*log(2*G/lg)/Ac);
F = 1+(lg/Ac*log(2*G/lg));
sprintf('\b\b\b\b\b\b\b\b9. Calculate the amount of fringing flux.\n\tF =
%0.5g.',F)
% 10. Calculate the new number of turns by inserting the fringin flux:
%
N = (lg*L)/(0.4*pi*Ac*F*1e-8)
(turns)
F = 1;
N = sqrt((lg*L)/(0.4*pi*Ac*F*1e-8));
sprintf('\b\b\b\b\b\b\b\b10. Calculate the new number of turns by inserting the
fringin flux.\n\tN = %0.5g turns.',N)
% 11. Calculate the winding resistance:
%
R = MLT*N*1e-6
(Ohm)
R = MLT*N*1e-6;
sprintf('\b\b\b\b\b\b\b\b11. Calculate the winding resistance.\n\tR = %0.5g
Ohm.',R)

83

CURRICULM VITAE
NAME

Mr. Chainon Chaisook

DATE OF BIRTH

20 April 1976

EDUCATIONAL RECORD
HIGH SCHOOL
High School Graduation
Wicheinmatu School, 1993
BACHELORS DEGREE
Bachelor of Engineering (Electrical Engineering)
King Mongkuts University of Technolgy Thonburi, 1997
MASTERS DEGREE
Master of Engineering (Electrical Engineering)
King Mongkuts University of Technolgy Thonburi, 2002
PUBLICATION

Chaisook, C., Chaisawat, A. and Monyakun, W., 2001,

The Large-Signal Modeling of CUK Converter Using
Switching Flow-Graph Modeling Technique, EECON24, 22-23 November 2001, KMITL, Vol. 1, pp.518-523.

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