Course: VT-VM :: OVM & UVM (Open/Universal Verification Methodology) + UVC

Development + 1 Complex Project

Course Features :

8 Weeks Course (UVM Training Bangalore, Next Batch Starting Date : 13-Dec-2014)
Weekend Course :
o 4 Hours on Saturday & 4 Hours on Sunday(9:30AM - 1:30PM on both days)
o Includes 2 full day practical sessions, one during middle of course, other towards
end of course.
Focused on student developing complete testbench environment, testcases
& debugging
Tools Used : Questasim (Mentor Graphics)
Demo Class : Attend 1st session of UVM Training course as a Demo class

Course Fee : INR 12,000/OVM & UVM Training Course Structure :

1. Verification Methodologies: UVM & OVM
2. Universal Verification Component(UVC or OVC) Development : AHB Protocol
3. Module(IP) Level Verification Project
o Project#1 :SV & UVM/OVM Based Verification Project (Memory Controller,
Bridge, etc)
4. UVC/OVC use in System on Chip(SoC) Testbench Setup
5. Mock Interviews & Group Discussions
6. Student assignments for weekday practice

Detailed Course Structure :

1. Verification Methodologies: UVM & OVM (Session# 1 - 5)
o AHB Interconnect verrifiation project used as reference design to learn UVM &
OVM
o AHB Interconnect will be verified from scratch while teaching all aspects of
UVM
o UVM/OVM TB Architecture
o UVM Class Library, Macros, Utilities
o UVM Factory, Synchronization, Containers, Policies
o UVM Components, Comparators, Sequences, Sequencers
o Stimulus Modeling, Sequences & Sequencers
o Creating UVCs and Environment
o UVM/OVM Simulation Phases
o TLM Overview, Components
o Configuring TB Environment
o Register Layer, Configuration DB & Resource DB

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6.

Connecting multiple UVCs

Creating TB infrastructure
AHB Interconnect Functional Verification using UVM (Session# 6 - 8)
o AHB Protocol : Features, Signals, Timing Diagrams
o AHB Interconnect Testbench Architecture
o AHB Universal Verification Component Development
o AHB UVC used in AHB Interconnect Testbench setup
o Verification Component Coding
o Testcase Development & Debug
Module(IP) Level Verification Projects (Session# 9 - 15)
o Project#1 :SystemVerilog & UVM/OVM Based Project
Project Category : Complex module (USB/MemoryController/Bridge
protocols etc)
Specification analysis
Verification Plan creation
Feature & Scenario Listing down
TB architecture creation
Building Top level verification environment
TB component coding and integration
Sanity test case and environment bring up
Complete test case coding
Building regression test suite
Functional coverage and code coverage analysis
UVC/OVC use in System on Chip(SoC) Testbench Setup (Session# 16)
o TB Architecture creation using UVC
o Building top level verification environment
o UVM Sequences usage in testcase development
Mock Interviews & Group Discussions (Session# 16)
o UVM interview questions covering all aspects of UVM, AHB, AHB UVC and
USB2.0
o UVM Training Group Discussion on Projects worked on as part of course
Assignments provided to student during course
o OVC/UVC Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
o Verification of PCIEx Physical Layer LTSSM FSM from scrach
o Functional Verification of UART/AXI-DMA/OCP2AXI Bridge from scratch