Novel MOSFET-Like Transistor Structures

Jason C.S. Woo

University of California,
California Los Angeles
Electrical Engineering

Jason Woo

IWSG2009

Outline

Jason Woo

Needs for novel Device concepts

Asymmetric Channel Devices
Schottky Transistors
Tunnel Source (PNPN)MOSFET
Heterojunctions CMOS
Graphene MOSFETs
IWSG2009

Scaling
g Challenges
g
Challenges arising due to scaling in the sub-nm regime
Source/Drain-to
Channel
Electrostatic
Coupling

Jason Woo

Channel Transport
Limitation
(Mobility Reduction,
Reduction
Velocity saturation)

Parasitic Effects
(Source/Drain
Resistance/Capacitance
Resistance/Capacitance,
Gate Leakage)

IWSG2009

End of Scaling in CMOS?

End-of-Scaling
Frequency Vs. Node

Power vs. Node

95

Power Consumption (W/cm2)

400
350

Freq. = 20GHz
Freq. = 50GHz
Freq. = 80GHz

300
250
200
150
100
50
0

switching frequen
ncy (GHz)

450

85

P=50W/cm2
P=100W/cm2
P=200W/cm2

75
65
55
45
35
25
15

30

40

50

60

70

Node (nm)

80

90

100

30

40

50

60

70

80

90

100

node (nm)

Further scaled CMOS beyond 40nm will

soon hit performance limit due to lessscalable parameters like Vth, Vdd , signal-tonoise-[distortion] ratio
ratio, current leakage and
substrate conductivity
Jason Woo

IWSG2009

Impact of CMOS Scaling

Scaling
(Interconnect)

0.25m
(1P5M)

0.18m
(1P6M)

0.13m
(1P8M)

0.09m
(1P9M)

Vdd(V)

2.5

1.8

1.2

1.0-1.2

Vth(V)

0.46

0.42

0.34

0.29

ft(GHz)

30

60

80

120

fmax(GHz)

40

80

120

150

Ion(A/m)

600

600

550

510

Ioff(A/m)

10

20

320

10,000

gm(mS/m)

0.3

0.4

0.6

1.0

ro(Km)

129

67

24

gmro

39

27

14

Ath(mVm)

5.5

4.5

3.6

2.0

1.9

1.8

1.7

A(%m)

Ath = Vth W L
Jason Woo

A =

W L

Pros:

Higher ft and fmax

Higher
g
gm
More interconnect levels
Lower switching power
consumption

Cons:

Lower signal headroom

Lower breakdown voltage
Lower effective g
gain (gmro)
Higher Vth & mismatch
Higher device leakage
Higher gate resistance

Less-scalable
properties:
Vdd, Vth
Signal,
Signal noise,
noise S/N,
S/N
I/O impedance
Substrate conductivity
IWSG2009

Impact of Scaling on Analog Performance

100

Vth=0.25 - 0.35 V

Vth=0.25 0.35 V
For Mid gap gate
FDSOI MOSFET
Black: Bulk
Green: PDSOI
Blue: FDSOI

Intrrinsic Gaiin

80
60

Ids =100A/m
Vds =0.8V
Xj=10nm
10nm
TSi =15nm
Tox =1.5nm
f oper=1GHz

40
20
0

Jason Woo

Lg =60nm
Lg =100nm
100
Lg=150nm
Lg=250nm

50

100
fT (GHz)
(GH )

150

200

IWSG2009

70
60

2001 ITRS
Physical Gate Length

50

Max. Ratio of Rsd to Ideal Rch

60
50
40

40
30
30
20

20
10

Rsd / Rcch,ideal [%]

Gate Length or S
SDE Depth
h [nm]

SDE & Series Resistance Scaling Trends

10

SDE Junction Depth

0
0
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018

Year
Lch t ox
(V gs Vth )
1
Rsd Rsh
N sd X j
Rch

Jason Woo

Scaled with Lg (Lch , tox)

Difficult to scale Rsh Rsd/Rch
(Nsd , Xj )

IWSG2009

Relative Contributions of Resistance

Components
500
400

NMOS scaled by ITRS

Rext

300

Rdp

200

Rcsd

100
0

Rov

32 nm

53 nm

70 nm

100 nm

Physical Gate Length

Relattive Contriibution [%]

S/D Seeries Resisttance [m

m]

NMOSFETs
70
60
50

Rcsd

NMOS

40

Rext

30

Rov

20
10
0

Rdp
32 nm

53 nm

70 nm

100 nm

Physical Gate Length

Assumptions : Scaled according to ITRS projection

Gradual doping & midgap silicide material
Rcsdd will be a dominant component for highly scaled nanometer transistor
( Rcsd/Rseries is rising up to >> ~ 60 % for LG < 53 nm)
Jason Woo

IWSG2009

 PMOSFETs

700
600

PMOS scaled by ITRS

500
400

Rov
Rextt

300
200

Rdp

100

Rcsd

32 nm

53 nm

70 nm

100 nm

Physical Gate Length

Rela
ative Contrribution [%
%]

S/D Seeries Resisstance [m

m]

Relative Contributions of Resistance

C
Components
t
70

Rcsd

60

PMOS

50
40
30

Rov

20

Rext

10
0

32 nm

53 nm

Rdpp
70 nm

100 nm

Physical Gate Length

Relatively large Rov contribution, but still largest in Rcsd

( Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 % for LG < 53 nm)
Jason Woo

IWSG2009

S/D
D Series R
Resistancce [m]

Ad
Advanced
d S/D E
Engineering
i
i
300
270
240
210
180
150
120
90
60

LG

Graded Junction
= 53 nm
Midgap Silicide
Rov
B Profile
Box
P fil
Rext
Midgap Silicide R

Box Profile
Low-Barrier Silicide
(B = 0.2 eV)

dp

Rcsd

30
0

Source/Drain Engineering

Jason Woo

Potential solutions for

advanced S/D
Engineering:

Box-shaped highlydoped ultrashallow SDE

junction
(i.e., laser annealing)
Schottky Barrier
lowering
(i.e., ErSi for NMOS,
PtSi2 for PMOS
PMOS, and
lower bandgap Si1-xGex
layer)
IWSG2009

Proposed
P
dS
Solutions
l ti
for
f High
Hi h Performance
P f
Low Power Transistors
New Materials with Higher Mobilities
New Gate Stack to Reduce Tunneling
New Contact Materials (Metal and
Semiconductor) to reduce Rco
New S/D Structures (e.g. Raised S/D) for Small
RS/D
SOI, DG, to improve SCE

Jason Woo

IWSG2009

2-D MOSFETs-- Double Gate FETs

Jason Woo

P. Wong

IWSG2009

3D FETs -- Nanowire Transistors

(1D Transport)

Samsung 2005

Jason Woo

IWSG2009

I-V ((Ballistic,, DOS Capacitance)

p
)

Taur, TED 2008

Jason Woo

IWSG2009

Essentially, Try to Make Scaled

MOSFET Follow
MOSFETs
F ll Scaling
S li
Behavior of Long
Long Channel
Device Miniaturization by
improving Electrostatic and
T
Transport
t (mobility
( bilit and
d v))
Jason Woo

IWSG2009

Alternatives?
New Device Architectures
Novel Transports Mechanisms
Incorporate QM Effects

New Materials
High Mobilities
Bnadgap Engineering

Others

Jason Woo

IWSG2009

Lateral Asymmetric Channel (LAC) MOSFET

LAC

Tilt angle

poly
poly BF2 (NMOS)
S

Impurrity
Concentrration
(cm --3)

Conventional
10

20

10

19

1018
10

Lgate=0.12
m D
LAC: Tilt=10o

Conv.

17

1016
10

15

-0.1

LAC
-0.05 0
0.05 0.1
Lateral Position (m)

Formation of Channels in the

Simulated channel profiles for devices

LAC and conventional structures. with same Vth from source to drain
1.5 nm away from the SiO2/Si interface.
Usual tilt angle: 10o-15o

Jason Woo

IWSG2009

LAC Transistor
Avee Carrier Veelocity (107cm
m/s)

Ey (1005V/cm)

LAC
DP
Conventional

-0.05

0.05

Lateral Position y (m)

1.5

LAC
DP
Conventional

0.5

-0.05

0.05

Lateral Position y (m)

LAC Devices: Higher doping near the source end

High lateral electric field near the source end in channel region
High average carrier drift velocity near the source end in channel region
High current drive, Ids = W Cox(Vgs-Vth(y)-V(y))v(y)

Jason Woo

IWSG2009

LAC DEVICES: ANALOG PERFORMANCE

g m ((mS/ m)

0.3

LAC Tox =25

LAC Tox =36
Conv. T ox =25

Conv. T ox =36

0.2

0.1 NMOS
Vds =0.8V
=0 8V
I same at same Lg & Tox
0 ds
0
0.2
0.4
0.6
0.8
Lg(m)

15

Vgt =0.3V, V ds =0.8V for Conv.

Vds =0.8V, I ds same as Conv.
for SP(Vgt~0.15-0.3V).
~0 15-0 3V)

10

g m //Id(V-1)

0.4

1.0

NMOS
0

0.2

LAC
Tox=25
LAC
Tox=36
Conventional, T ox=25
Conventional, T ox =36
0.4
0.6 0.8
1.0
Lg(m)

g m is higher in SP devices
g m/Id ratio is very high compared to conventional devices when biased at same
current density :
- due
d tto hi
high
h currentt d
drive,
i small
ll V
Vgtt iis needed.
d d Al
Also hi
high
h gm
Jason Woo

IWSG2009

Issues with LAC Transistors

High
g doping
p g near the source Lower Mobility
y
Sharp doping profile in sub45 nm transistors
Difficult

Jason Woo

IWSG2009

Split Gate Design

0.5

Source

p ote ntial (V )

1.1

H gate

Vds=0.2 V
Vds=0.4 V
Vds=0.6 V
Vds=0.8 V
Vds=1.0 V

0.9

Drain

07
0.7

0.5
10.0

p- sub
20.0

30.0
40.0
50.0
Channel p osition (nm)

60.0

Lateral E-F
L
Field (MV//cm)

Potential profile for the HL devic e

1.3

The work-function of the H gate

is higher than that of the L gate

H-L gate
H gate

0.3 Lg
Lg=45nm
45nm
WH-WL=0.3eV
0.1 Vgt=0.2V, Vds=0V

-0.1
0.1

60
EX (kV/cm)

H -- L gate

-0.3
-0.5
-0.7
0.0

H gate
H - L gate

40
20

Vd 0 8 V
Vds=0.8
20.0

0
0

5
10 15
Channel-X (nm)

40.0

Channel position (nm)

60.0

An electric field peak is generated in the channel close to the source

side which enhances source carrier injection into the channel ( gm).
Rout can be
b increased
i
d due
d to
t the
th reduced
d d channel-length-modulation.
h
ll
th
d l ti
Jason Woo

IWSG2009

Simulation: Gm and Rout in scaled MOSFETs

Empty Symbol: H device
Solid Symbol: HL device

50
40

Gm(mS
S/mm)

Routt (K)

1750

1250
Lg = 45 nm
Lg = 90 nm
Lg = 130 nm
Lg = 180 nm

750

250

400

Rout (K)

2250

100

200

300

400

Bias current (/ m)

500

30

Solid symbol: HL gate

200

Lg = 130 nm

100
0

20

50

100 150 200 250

Bias current (/ m)

10
0

Empty symbol: H gate

300

Lg = 45 nm
0

100

200

300

Bias current (/ m)

400

Both gm and rout can be improved

p
by
y using
g this split
p ggate design
g
for different channel length considered.
Jason Woo

IWSG2009

Sb-induced Work Function Shift in the NiSi Gate

NiSi/Oxide Capacitor, 100m x m

Tox = 2.6nm

2.6nm

Capatancce (pF)

100

undoped NiSi
Sb doped NiSi
15
-2
50 (1.5x10 cm )

0
-2.0

-1.5

-1.0
-0.5
0.0
Gate Bias (V)

0.5

NiSi Gate: Gate full silicidation and no oxide degradation.

Antimony implantation in the polysilicon gate reduces the
NiSi gate work function (~0.25eV)
(~0 25eV) due to the dopant
segregation effect at the NiSi/oxide interface.
Jason Woo

IWSG2009

Process Flow
Sb

PR

Oxide/Poly/LTO:

LTO
SiN

Poly oxide
Si

Poly

4.5nm/50nm/200nm

SiN

Sb implant
p
energy,
gy,
dose and angle: 25KeV,
1.5x1015 cm-2, 30o

Si

(a)

(c)

Nitride
Nit id spacer width
idth :
~ 80nm

L TO
SiN

Jason Woo

SiN

NiSi

SiN

N iSi

Si

Si

(b)

(d)

SiN

NiSi

Silicide conditions:
10mins @ 450 oC

IWSG2009

Id-Vg and Id-Vds curves

(Substrates are undoped)
Drain cu
urrent (A / 10 m)

Drain cu
urrent (A/ 10m)

5.0m

1E-4

1E-5

Lg=0.6m
Lg=0
6m
VDS=0.1 V
Undoped NiSi

1E-6
1E-7

Tilt-angle Sb
-doped NiSi
-00.5
5 0.0
0 0 00.5
5 1.0
1 0 1.5
15
Vg (V)

20
2.0

4.0m

tilt-angle doped(Sb) NiSi gate

U d
Undoped
d NiSi gate
Vg=2 V

Lg=0.6m

Vg=1 5 V
Vg=1.5

3 0m
3.0m

Vg =1.0 V

2.0m
1.0m

Vg=0.5 V

0.0

Vg=0 V
25
2.5

00
0.0

05
0.5

10
1.0

15
1.5

Vds (V)

20
2.0

Improved current drive capability is observed for the NiSi gate

ddevice
i with
ith tilt angle
l Sb implantation
i l t ti from
f
the
th drain
d i side,
id i.e,
i the
th
split-gate device.
Jason Woo

IWSG2009

Scalable?
Empty Symbol: H device
Solid Symbol: HL device

1750
50

1250

40
Rout (K)

gm (mS/m
mm)

2250

750

30
20
10

Lg = 45 nm 0 0
250 0
Jason Woo

100

100
200
300

Bias Current ( A/ m)

400

200
300
400
500
Bias Current (A/m)
IWSG2009

Improved speed-gain performance

Vth=0.15--0.25
Vth=0.25--0.35

350

Lg=45nm
IDS =100 A/m

FT(G
GHz)

300

L 45 nm
Lg=45

250
Lsp=27.5 nm
Lsp=30 nm
Lsp=35 nm
Lsp=40 nm
Lsp=45 nm

200
Empty symbol: H device
Solid symbol: H-L
H L device

15010

20

30

Intrinsic Gain

40

SplitSplit-gate HL MOSFETs have improved gaingain- frequency

performance compared with conventional MOSFETs
Jason Woo

IWSG2009

Laterally Asymmetric SiGe MOSFET

Conventional MOSFET Design: Constant Vth across the
channel
Channel Engineering using Band gap Engineering Concept: Modification
of threshold voltage across the channel
Vth (Source Side)>Vth (Drain Side)

Conduction Band offset (Ec) between materials changes Vth

across the channel

Jason Woo

IWSG2009

Band Gap Engineering for MOSFET Channel

z

Tension

Si1-xGex

Si1-yCy

z
Strained
Si1-yCy

z
Ec Ec~0.6x [eV]

Ec
Strained
Si1-xGex

Si
Ev

Suitable for
NFET
Jason Woo

Si1-xGex

Ec~5y [eV]

Tension

Si

Si

Si

Compression

Si

Strained -Si

Ec
Si1-xGex

Ev~0.5x [eV]

Ev
Suitable for
PFET

Ev
Suitable for
NFET
IWSG2009

Novel Asymmetric SiGe/Strained

SiGe/Strained-Si
Si MOSFET
Gate
Drain

Source
Poly-Si

n+ Si0.30Ge0.70 P Si0.30Ge0.70 P Strned-Si n+ Strned-Si

BOX
Si

Jason Woo

IWSG2009

Digital Performance: Ion/Ioff Comparison

Lg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3
Ioff same, VDS=1.0V

-3

1.6x10

10

-3

1.4x10

-3

1.2x10

Asymmetric
Ch
Channel
l MOSFET

-3

1.0x10

-4

8.0x10

-4

6.0x10

Conventional
Si MOSFET

-4

4 0x10
4.0x10

Drain current(A
A/m)

Drain current ((A/m)

D

Asymmetric
Channel MOSFET

-3

-4

1x10

Conventional
Si MOSFET

-5

1x10

-6

10

-4

2.0x10

-7

10

0.0

0.2

0.4

0.6

0.8

Gate Voltage(V)

1.0

0.0

0.2

0.4

0.6

0.8

1.0

Gate Voltage(V)

Improved Ion/Ioff ratio (15% improvement)

Comparable Subthreshold Swing (S)
Jason Woo

IWSG2009

Analog Performance Trends: Gm & Rout Comparisons

Lg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3
Ioff same, VDS=1.0V

-3

2.2x10

3.0x10
-3
3

2 0 10
2.0x10

Asymmetric
Channel MOSFET

-3

Asymmetric
Channel MOSFET

2.6x10

2.4x10

-3

1.6x10

Rout (/
m)

Gmsat (S//m)

1.8x10

2.8x10

-3

1.4x10

Conventional
Si MOSFET

-3

1.2x10

2.2x10

2.0x10

1.8x10

1.6x10

Conventional
Si MOSFET

1.4x10

-3

1.2x10

1.0x10

1 0x10
1.0x10
-4

8.0x10

8.0x10

6.0x10

-4

6.0x10

4.0x10

100

200

300

400

500

Ibias (A/m )

100

200

300

400

500

Ibias (A/m )

Higher gm & gm/Ids ratio (low power) due to enhanced source injection
Higher output resistance due to reduced CLM
Higher Intrinsic gain (gm x rout)
Jason Woo

IWSG2009

Best Semiconductor Junctions

Bandgap Engineering?

Jason Woo

S.M. Sze Semiconductor devices Wiley, 1985

IWSG2009

III-V/Si Co-Integration
g
Issues
Issues:

Incompatibility
co pat b ty with
t Si
S CMOS
C OS process/infrastructure
p ocess/ ast uctu e in large
a ge a
area
ea
material growth and wafer bonding
Poor device yield
Poor device reliability
S i
Serious
th
thermall mismatch
i
t h

Potential Solutions:

Jason Woo

Embedded
E
b dd d h
heterogeneous
t
growth
th att th
the nanoscale
l device
d i llevell in
i
selective drain/channel/source areas
Choose the best heterojunctions for the best circuit functions
Exploit bandgap engineering for higher injection efficiency,
efficiency faster
carrier transport, higher breakdown and lower leakage currents
Continue to use silicon as a substrate for mass production
compatibility

IWSG2009

Selective Heterojunctions for Functions

Metal?

P l Si
Poly
Si

Oxide
Si/SiGe
Si Substrate/SOI

Si/SiGe CMOS

High-K Insulator

Si

INSb/ InSb/InAs/Ge?
InP
GaN
?
InAs/Ge
Si Substrate/SOI
COSMOS CMOS

Nano scale heterogeneous integration in selective

Nano-scale
device areas may lead to ultra-high performance
and excellent reliability

Jason Woo

IWSG2009

Swiitching F
Frequen
ncy (GH
Hz)

Low Power High Performance Digital

195
175
155
135
115
95
75
55
35
15
100

Jason Woo

Potential
P=10W/cm2

P=50W/cm2
P=100W/cm2
P=200W/cm2
Scaled CMOS

90

80

70
60
node (nm)

50

40

30
IWSG2009

Potential for High Performance Mixed

Mixed-Signal
Signal
Analog Behavior
260
27000
22000

160

> 10X
> 4X

110
60
10

17000
12000

Silicon CMOS

7000

170 150 130 110

90

70

50

ft * G
Gain (GH
Hz)

fft (GHz))

210

COSMOS
Goals

2000

30

Node ((nm))
Jason Woo

IWSG2009

Novel Source Injection MOSFET

I. Asymmetric
y
Schottkyy Tunnelingg
Source Injection MOSFET
A novel device structure incorporating gate controlled
source injection by schottky barrier tunneling

Jason Woo

IWSG2009

Motivation
Scaled MOSFET performance is increasingly limited by:
1. Parasitic Resistances :
Source / Drain junction resistance

Metal Source/ Drain junctions

2. Electrostatics and transport :

Non Scalability of subthreshold swing
(diffusion limited) as well as built in
voltage of p-n junctions
Source injection of carriers through
different gate controlled mechanism

Schottkyy Source Tunnelingg MOSFET:

Fully Silicided Source/Drain junctions
Gate controlled source injection through schottky barrier
tunneling
Jason Woo

IWSG2009

Schottky Barrier FETs

Metal

Source

Gate

Issues and Problems

Drain

Large
g b causes reduction in drive current
Drain Side SB causes reverse drain leakage as
well as degradation in current in the linear region
High resistance region under the spacer causes
potential drop

Resistance like
behavior observed
in the linear region
of the ID-VD curves
Q. T. Zhao et al, Microelectronic Engineering,
Engineering,
Vol.. 70
Vol
70,, pp
pp.. 186
186,, 2003.
2003.
Jason Woo

IWSG2009

Schottky Barrier FETs

Potential solutions
9 U
Use small
ll b (minimum:
( i i
0.28eV
0 28 V (ErSi2)
(E Si2) for
f
electrons and 0.25eV (PtSi) for holes)
but b always positive
also increases back injection leakage
9 Use doped extension under the spacer
Reduces drop at the junction by
reducing eff. b
Eliminates high Resistance region
under the gate
but transistor becomes conventional
like
eliminates advantages of
Schottky Barrier
Jason Woo

Gate

Source

Drain

Doped extension

The sourcesource-channel and

drain channel contacts
are now ohmic and not
schottky in nature
IWSG2009

How about Analog Applications

Source injection of carriers by tunneling at
the source schottky junction
N+ Region on the drain side to form ohmic
contact between drain and channel
J T h e r m io n ic

The gate controls tunneling

through the schottky barrier
by changing the tunneling
width as well as the available
density of states on the
semiconductor side

Jason Woo

Condu
uction Band Edg
ge (eV)

0 .4 5
0 .3 0

I n c r e a s in g
G a t e V o lt a g e

J T u n n e lin g

0 .1 5
0 .0 0

Source

- 0 .1 5
- 0 .3 0
-4

-2 0
2
4
6
8 10 12 14
D i s t a n c e a lo n g c h a n n e l ( n m )

IWSG2009

Effect of Barrier Height (b)

At same tOX, subthreshold
char dominated by tunneling
char.
at high b

1x10

1x10

b = 0.25eV

1x10

0.45eV

ID (A/m)

-1

1x10

-2

1x10

0.65eV
tOX = 20

-3

1x10

-4

1x10

VD = 0.1V
VD = 1.0V

-5

1x10

-6

1x10

Jason Woo

00
0.0

02
0.2

00.44 0.6
06
VG (V)

08
0.8

10
1.0

For small b, the current

is limited by the virtual
cathode point in the channel
(diff i limited)
(diffusion
li it d)
However, Short Channel
Eff t (DIBL) are
Effects
considerably improved with
tunneling at high b
IWSG2009

Effect of Drain pocket (NDrn)

ID (A/m)

1200
900

no drain pocket
Vg=1.0 V
with drain pocket
b = 0.45eV
Vg=0.8 V
tOX = 5

600

Vg=0.6 V

300

Vg=0.4 V

0
0.0 0.2 0.4 0.6 0.8 1.0
VD (V)

Degradation in ID mainly caused

due to a drop across the forward
biased schottky junction at the drain
side.

Increase in IOFF due to back injection

of holes from drain to source
A n+ type pocket makes the drain side
junction ohmic and hence prevents backinjection

Jason Woo

10
1

100n
10n
1n
100
100p
10p
1p

IOFFF (A/m)

1500

00
0.0

Sim.
no pocket

n+ drain
pocket
04
0.4

00.8
8 1.2
12
VD (V)

16
1.6

IWSG2009

0.30

150

0.25

SOI-FET
SOI
FET 120
(b=0.25eV) 90
(b=0.45eV)
(b=0.65eV)) 60

0.15
0.10

30

0.05
60

90 120 150 180

LG (nm)

The junction at the

source side is not affected
by
y drain voltage
g ((immune
to drain field)
Jason Woo

Dramatic Improvement in
VTH roll
roll-off
off and Drain
Induced Barrier Lowering
(DIBL) with increasing b

0
Co
onduction Band Edg
ge

0.20

DIB
BL (mV/V
V)

Vth (V)

Scalability of the STS-FET

0.45
0.30
0.15

Immune to
increase in VD

0.00
-0.15
-0.30

Increasing Drain
Voltage

-0 45
-0.45
0
20 40 60 80 100
Distance along channel (nm)
IWSG2009

Analog Performance: gm

1200

Gm (S/m)

1000
800
600
400

FD
B H
B H
B H

200
0

50

-S
=
=
=

O I
0 .3 0 e V
0 .4 5 e V
0 .5 5 e V

100

150
200
B ia s C u rre n t ( A / m )

At low bias currents, gm of the STSFET is higher than that of the conv.
SOI-FET
SOI
FET due to the difference in injection mechanisms.
mechanisms The gain in gm
is higher as the barrier height decreases.
Jason Woo

IWSG2009

Rout (K-m)

Analog Performance: ROUT

10

10

10

10

F D -S
B H =
B H =
B H =
0

50

O I
0 .3 0 e V
0 .4 5 e V
0 .5 5 e V

100

150
200
B ia s C u rre n t ( A / m )

At low bias currents, ROUT of STSFET is superior to conv. SOIFET due

to improved DIBL.
DIBL The ROUT ~ constant w.r.t
w r t b.
Tunneling mechanism high ROUT
Jason Woo

IWSG2009

Gaain (Av)

Analog Performance: Gain (AV)

10

10

10

10

FD
B H
B H
B H

50

-S
=
=
=

O I
0 .3 0 e V
0 .4 5 e V
0 .5 5 e V

100

150
200
B ia s C u rre n t ( A / m )

The gain is ~10X more than that of conventional SOI-FET

Increase in gm and ROUT for low bias currents (<200A/m) makes it
an ideal candidate for low power high performance circuit design
Jason Woo

IWSG2009

Frequency-Gain Performance
3

STS-FET
SOI-FET

Ibias = 100 (A/m)

2

10

Vth = 0.2 - 0.35V

30

60
90
ft (GHz)

120

IIntrinsic Gain

IIntrinsic Gain

10

10

STS-FET
SOI-FET

2.0x10
1.5x10

Ibias = 100 (A/m)

1.0x10

Vth = 0.2 - 0.35V

2

5 0x10
5.0x10

0.0

30

60
90
ft (GHz)

120

Improvement in Frequency-Gain performance for different

technology nodes
Suitable for High performance, low power transistors
Jason Woo

IWSG2009

N-FET device

-6

1x10

VG (V)

Observed drain leakage due to backinjection of h+ (ambipolar transport)

Subthreshoold Swing
(mV/d
dec)

350

S im . D a ta
E xp . D a ta

300
250
200
150
100
50

S S = 6 0 + 4 .7 x t O X

10
1
100n
10n
1n
100p
10p
1p

IOFF (A
A/m)

ID (A/m)

ID-VG char. for the NiSi STS nFET LG = 0.15m

3
1x10
2
VD=1.6V 1.1V
1x10
Sh k
Schottky
1
0.6V
1x10
Tunneling
Current
0
0.1V
1x10
-1
1x100
-2
1x10
-3
1x10
-4
Lg=0.15
Lg
0.15m
1x10
-5
tOX=30
1x10

0.0

Jason Woo

1 0 20 30 4 0 50
O x id e th ick n ess ( )

Sim.
Exp.
no pocket

n+ drain
pocket
0.4

0.8 1.2
VD (V)

1.6

IWSG2009

Summary
Need to explore alternate structures to achieve high
pperformance low p
power transistors
Asymmetric Schottky Tunneling Source MOSFET
concepts
t introduced
i t d d
b ~ 0.3 0.65eV, EOT < 10,
Drain-side pocket to improve linear characteristics

Optimized device structure highly immune to Short

Channel Effects Very Scalable Transistor Structures

Jason Woo

IWSG2009

 gm is higher than conv. SOI-FET at low bias currents

making it ideal for low power,
power high performance
applications
Big Improvement in ROUT and intrinsic gain
(gmxROUT) even at LG < 90nm at low currents
Exceptional frequency-gain performance for low
power high performance applications
power,
Promising Alternative for mixed mode, RF and SOC
applications
Jason Woo

IWSG2009

Novel Source Injection MOSFET

II. QM-Injection Transistors
Vs/db
unscaled
S

Vth

Vsupply

Ioff

Ion

Hi h Ioff andd reduced

Higher
d d Ion/Ioff ratio
i

Exploit novel device physics

concepts made possible by
nano-dimensions to achieve
steep
t
subthreshold
bth h ld swing
i and
d
ballistic carrier transport to
give high Ion.

Vs/db Source/Drain-Substrate Junction Potential

Vth Threshold Voltage
S Subthreshold Swing
Jason Woo

IWSG2009

Background
g
Challenges arising due to scaling in the sub-30nm regime
Source/Drainto Channel
Electrostatic
Coupling

Channel Transport
Limitation
(Mobility
Reduction, Velocity
saturation)
t ti )

Parasitic Effects
(Source/Drain
Resistance/Capac
itance, Gate
L k )
Leakage)

VDD scaling:
Subthreshold Swing >
60mV/Decade
min VTH for given
Ioff
low Ion/Ioff

Proposed Solutions
Improved Device Architecture (Double or Tri-gate MOSFETS)
New materials to enhance transport (SiGe or Ge channel)
gate leakage
g ((High-K
g
dielectrics))
New Gate Dielectrics to reduce g
Rationale of these approaches:
Make the device Long-channel like
(instead of exploiting new device physics opportunities
afforded by nano-dimensions)
Jason Woo

54

IWSG2009

VDD Scaling
g
Low power devices with continued VDD scaling need
- Reduced Vth to have reasonable ION at low VDD
- Small IOFF even with low Vth
Conv. MOSFET Subthreshold Swing limited to
60mV/dec (@300K) due to diffusion mechanism
Alternate mechanisms of carrier injection not limited
by diffusion limited swing:
Tunneling
Potential reduction in subthreshold swing
Impact Ionization
Need of high VDD (> EG/q) to have working FETs
Jason Woo

55

IWSG2009

Motivation
In order to continue scaling of transistors for low power
digital and analog circuits,
circuits alternate structures must be explored
These alternate structures must be optimized for both analog
and digital
g
pperformance conducive to SOC applications
pp

The Tunnel Source MOSFET:

(PNPN
(
FET))

Hi h Resistance
High
R i
to SCEs
SCE
Jason Woo

Significant low-power
f
iimprovement
Performance
Over conventional devices
56

E t
Extremely
l scalable
l bl
IWSG2009

Tunnel Transistors
Previous efforts on p-i-n structure using gate modulated
tunnelingg injection
j

Vertical TFET
Bhuwalka et al, TED, vol. 51, 2, pp. 279, 2004

TFET (P-I-N)
Nirschl. T et al, EDL, vol. 28, 4, pp. 315, 2007

Hitoshi Kisaki,
Kisaki Proc.
Proc IEEE,
IEEE vol.
vol 61,
61 No.
No 7,
7 pp.
pp 1053-1054,
1053 1054 1973
W. M. Reddick and G. A. J. Amaratunga, APL., vol. 67, no. 4, pp. 494497, 1995
Qin Zhang, Wei Zhao, Alan Seabaugh, EDL, Vol. 27, No. 4, 2006, pp. 297-300

Simple Structure to fabricate,

fabricate but large drop at the tunneling
junction causes 100X reduction in current
Jason Woo

57

IWSG2009

Tunnel Transistors

p-i-n FET
K. Boucart et al, ESSDERC 2006, pp. 383

Experimental TFET
W. Y. Choi et al, EDL, vol.28, 8, pp. 743

Experimental verification of the p-i-n concept, however a 100X

reduction in current compared to conv. FET
ambipolar nature of the device
Jason Woo

58

IWSG2009

Alternative Tunnel Transistor

Possible solutions

Make the tunneling junction more abrupt

Increase the lateral electric field at the source side
junction and reduce tunneling width
Asymmteric structure to eliminate ambipolar conduction
Alternative Solution:
Tunnel source PNPN-FET has advantages over p-i-n

Reduced potential drop at the tunnel junction

Improved drive current
Reduced ambipolar conduction
Jason Woo

59

IWSG2009

Device Concept
Novel device concept based on Band-to-Band Tunneling
Gate controlled tunneling junction is a source of electrons
(Tunneling width is reduced by the fully depleted N+ layer)
Silicide
n+ source fully
depleted
pocket

Silicide
n+ source
fully
depleted
pocket

Gate
Pol
Poly

P+ Source

N+ Drain

Poly

P+ Source

N+ Drain
Bulk (p)

BOX

Jason Woo

Gate

60

IWSG2009

Tunnel Source ((PNPN)) n-MOSFET

Gate Electrode controls the source-to-channel tunneling
currentt by
b
band-alignment
alignment between the valence
modulating the band
band of the tunneling-source junction and the conduction
band of the channel, thus modulating the availability of
density of states for tunneling
modulating
d l i the
h tunneling
li width
id h (which
( hi h is
i already
l d made
d
small because of the narrow and fully depleted n-pocket)

Jason Woo

61

IWSG2009

Device Concept
Conduction Band

Conduction Band

(b)

( )
(a)

Valence Band

Valence Band

When VG < VTurnon, I is small since the electrons from the P+

valence band can tunnel only to the trap states
When VG > VTurnon, electrons from the P+ source valence
band tunnel to empty states in the conduction band of the
channel
(VTurnon Gate voltage required for conduction and valence
bands to overlap)
Jason Woo

62

IWSG2009

1.5

W= 4 nm

1.0

Electron
n Energy ((eV)

Electron
n Energy (eV)

FD Pocket Essential
0.5
0.0
-0.5

EV

EC

-1.0
10
-1.5

Just Full Depletion

-2.0
25
-2.5
0.00

0.05

0.10

0.15

1.5

W= 15 nm

1.0
0.5
0.0
-0.5

EV

-1.0
-1.5
-2.0
-2.5
0.00

0.20

Distance along channel (m)

EC

Partial Depletion
0.05

0.10

0.15

0.20

Distance along channel (m)

W width of the n+ pocket

Band diagrams illustrate the importance of full depletion of the

pocket. For pocket which is only partially depleted, injection
mechanism is no longer tunneling
Jason Woo

63

IWSG2009

Device Simulation
Quantum Mechanical Tunneling
((Band-to-Band)
a d to a d)

governedd by
b

Tunneling Probability (Tt)

dependent on the
Tunneling width
(incorporating phonon
energy term)

governed by

Fermi Selection Rule

FV (E)* [1
[1--FC (E)]*u(E)
Where u(E) =1 if there is availability of states
to tunnel to; 0 otherwise. FV(E) and FC(E) are
Fermi-Dirac distribution functions for the
initial and final energy states.

Tunneling current: Esaki Diode integral

IV-C=A FV (E)*nV (E)*Tt *[1-FC (E)]*nC (E)* u(E)dE

Jason Woo

64

IWSG2009

Methodology for ATLAS simulations

Initial Guess for ATLAS
Band-to-Band tunneling
parameter (BB.A)

Solution converged
Used as starting guess
for next bias point

Yes

Jason Woo

ATLAS Device Simulator

with Band-to-Band tunneling
M d l on used
Model
d tto evaluate
l t
channel current (Ichan)
Esaki tunnel diode formalism used
to calculate tunneling current (Itun)
at the tunneling source junction using
simulated structure from ATLAS

0.999 < Itun/Ichan < 1.001?

65

No

Tweak parameter
BB.A

IWSG2009

Device Calibration
Currrent Density (A/cm
m2)

Parameters:
Effective mass m,
tuned to obtain a fit
with
i h the
h
experimental data
f
from
silicon
ili
tunnel
t
l
diodes
Reverse Voltage (V)

Theoretical Reverse bias tunneling diode

p
p+/n+
current matched with experimental
diodes. Ref: M.W. Dashiell et al, TED, Vol.
47, no.9, 1707 (2000)
Jason Woo

66

IWSG2009

Pocket Design
19

20

-3

Pocket Doping = 5x10 cm

240

1.6x10

W=4nm
W=15nm
Conv SOI

-3
N DM
(cm
)
MAX

SS ((mV/dec)

300

180
120
60
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VG - VT (V)

20

1.2x10

19

8.0x10

19

4.0x10

0.0

ID = 1 nA/m
ID = 100 nA/m

80
70
60
50
40
30

SS (m
mV/dec)

360

20

2
4
6
8
10
Pocket Width W (nm)
Pocket should be fully depleted for subthreshold swing to go below
60mV/dec
Pocket width should be small (<6nm) for SS to be appreciably below the
diffusion limit
(Doping x Width1.4 Constant)
(Doping
For all subsequent slides: Pocket width = 4nm and Pocket doping = 5x1019cm-3
Jason Woo

0.1

67

IWSG2009

Device Scalability
260
240

DIBL (m
D
mV/V)

VTHLIN (V)

0.32
0.30
0.28
0.26
PNPN
0.24
SOI
0.22
0.20
0.18
40 50 60 70 80 90 100
Ch
Channel
lL
Length
h LG (nm)
( )

220
200
180
160
140

Optimized structure is very scalable

Suppression of short channel effects as compared to conv.
conv SOI-FET
SOI FET with
respect to Vth roll off and DIBL
Jason Woo

68

IWSG2009

Low Standby Power Performance

6

1x10

PNPN

ION/IIOFF

1x10

1x10

TOX = 1.1nm
TOX = 2.5nm
TSI=60nm

1x10

1x10

1x10

Conv SOI

40 50 60 70 80 90 100
LG (nm)

Degradation in subthreshold swing and IOFF with scaling is

negligible for the tunneling device
As a result, ION/IOFF is improved by 3 orders over conventional
SOI with scaling highly beneficial for low standby power
Jason Wooapplications
IWSG2009
69

40
35
30
25
20
15
10
5
0

TOX = 1.1nm
TOX = 2.5nm

(a)

LG = 45nm
VTH = 0.3-0.35 V
PNPN

GM x ROUT

ROUTT (Km
m)

Low Operating Power Performance

Conv. SOI

0 200 400 600 800 10001200

ID (/m)

35
30
25
20
15
10
5
0

TOX = 1.1nm
TOX = 2.5nm

(b)

LG = 45nm
45
PNPN VTH = 0.3-0.35V

Conv. SOI

0 200 400 600 800 10001200

ID (/m)

Tunnel n-FET also exhibits an improvement in ROUT over the

conventional SOI for the given channel length as in (a). This can be
attributed again to reduced drain coupling and resistance to SCEs.
Intrinsic gain (GM x ROUT) is higher than the conventional device, as
shown in (b), especially at low IBIAS.
Jason Woo

70

IWSG2009

Vertical PNPN MOSFET

Tunneling junction doping profile needs to be sharp,
which is easier to achieve with growth techniques rather +
p Source
than ion implantation

n+ pocket
k t

Vertical PNPN Transistor

Gate

71

p channell

Jason Woo

Gate

In addition, vertical transistors have the advantages:

Immunity to short-channel effects (multi-gate
structure))
Lithography independent critical dimensions (less
process variation)
Higher on-current (multiple channels in one device)
Potential in 3-dimensional integration

n+ Drain

IWSG2009

Summary
Need to explore alternate structures to continue scaling for low
power applications
The Tunnel Source MOSFET (PNPN tunnel nFET) has very low
standbyy ppower due to smaller than 60mV/dec subthreshold swingg
Optimized device structure highly immune to Short Channel
Effects Very Scalable Transistor Structures
Achievement of Sub-threshold swing well below the diffusion
limit of 60mv/dec (at 300K) with Very Low IOFF and consequently a
hi h ION/IOFF ratio
higher
i
Improvement in intrinsic gain (gmxROUT) even for sub-90nm
channel lengths at low bias current levels
Jason Woo

72

IWSG2009

Ultimate High-Mobility Channel

Monolayer UTB FETs Graphene?

Jason Woo

IWSG2009

0D
fullerenes

3D
graphite

1D
carbon nanotube

0D fullerenes, 1D carbon
nanotube and 3D graphite can be
regarded as the wrap and stacks
of several layers of graphene.
Graphene:
single sheet of graphite
unwrapped SWNT

Jason Woo

2D
Graphene

IWSG2009

Graphene Deposition Methods

Mechanical exfoliation

Philip
hili Kim,
i et al.
l (2005)
(
)
Jason Woo

K.S.Novoselov, et al. (2004)

IWSG2009

Graphene Deposition Methods

Epitaxial growth ---- thermal desorption of Si on (0001) face of single
crystal 6H-SiC;

Walt A.de Heer, et al. (2006)

Jason Woo

IWSG2009

Chemically
y Converted Graphene
p
Review: Graphite is oxidized via modified Hummers method and
simultaneously reduced and dispersed in anhydrous hydrazine.
N2H5+

N2H5+

Thermally anneal

N2H5+
N2H5+

Solution processable chemically converted graphene has been

developed by the Kaner Group for electrical testing and nucleation
growth tests with the CERA team.
Jason Woo

77

IWSG2009

Chemically
y Converted Graphene
p
1. Reduction of these new graphite oxides have been achieved
2. Single
g sheet dispersions
p
using
gp
purification techniques
q
previously described is being investigated
3. These films are useful for the development of Graphene
channel FETs and for the study of graphene electrical
propoerties.

10 um

Jason Woo

78

IWSG2009

Graphene Deposition Methods

4. Chemical vapor deposition using Ni as catalyst.

Alfonso Reina, et al. Nano Lett. (2009)

Jason Woo

IWSG2009

Graphene Deposition Methods

Chemical synthesize from reduced graphite oxide.

N2H4

Spin coat on
substrate

Vincent Tung, et al. Nature Nanotech., (2009)

Jason Woo

IWSG2009

Graphene Deposition Methods

Radio frequency plasma-enhanced chemical vapor deposition.

J.J.Wang, et al. (2004)

Jason Woo

IWSG2009

Graphene Film Formation over Large Areas:

Current Technology
1. Mechanical Exfoliation

Scotch tape is used to peel and stamp single and/or few layers from
HOPG (the yield is exceedingly low).

2. Reduction of Silicon Carbide

1,100C can be used to make very small regions of

graphitic carbon

3 Intercalation and Exfoliation

3.
Difficulty is the strong van der Waals forces between sheets

Graphene properties demonstrated to date are marginal for RF

Electronics not clear that this process can be easily enhanced to
improve materials or applicable to large silicon wafers.
Jason Woo

IWSG2009

Fundamental Challenges of CVD Graphene

on Ni
Common characteristics of the reported results:

Non-homogeneity of graphene thickness;

The presence of wrinkles;
The expected grain boundaries in graphene.

Basic challenges:
The multiple grained structure of blank Ni films on
vvarious
ous substrates:
subs
es:
The unavoidable multiple nucleation of graphene;
The inability to control the location of graphene grain
boundaries.
Jason Woo

83

IWSG2009

Large size monolayer graphene and the Raman spectra

OneL

TwoL

30um

Two layer graphene

O i
OMimageofthegraphene
f h
h

Large size high quality 11-22 layer

graphene film without grain boundary

One layer graphene

Jason Woo

84

IWSG2009

Graphene transfer using PDMS

Continuous film
Pickup

Transfer

PDMS
(Grapn/Ni/)SiO2/Si

tGraphene

Sample062920093

(1) Pick-up process : Attaching the PDMS with the CVD-grown Grapn/Ni/SiO2/Si and
etching Ni/SiO2 (FeCl3 solution or HCl)
(2) Transfer process : Putting the FLG/PDMS onto the 300 nm SiO2/Si substrate to transfer

-We achieved the transfer yield as high as 95% with the size of a quarter
of 2 inch diameter wafer.
Jason Woo

85

IWSG2009

Graphene as grown and after transferred

Graphene was synthesized by CVD
usingg camphor
p
as carbon source

SEM image of the graphene

grown on Ni poly-crystaline
surface at 850oC.

SEM image of the graphene

after transferred onto SiO2
surface.
Jason Woo

Transfer
2699

Raman spectrum of the transferred

graphene which indicates the graphene.
86

IWSG2009

Single Grain Patterned Ni

1. Pattern and etch of annealed Ni film;
2. Thick Ni film deposited on patterned surfaces +
anneal + CMP
3. Annealingg of patterned
p
Ni with a capping
pp g layer
y

Jason Woo

IWSG2009

Process flow
TiN

SiO2
Ni

SiO2
Si substrate
Pattern TiN/SiO2
substrate

Deposit Ni/SiO2
on SiO2

Anneal
at
1000C 5min

TiN
Ni
SiO2
Si

Jason Woo

CMP to
t gett
flat surface

R
Remove
SiO2

88

IWSG2009

Part 1

SEM p
picture of annealed
sample

Over 90% Ni patterns have

become single crystal
Jason Woo

89

IWSG2009

Structure of Graphene

Jason Woo

2-dimensional Dirac-Fermions
In plane: honey comb structure
with
ith diff
differentt atoms
t
A and
dB
Out of plane: Van de Waals force
Zero band-gap
Linear E-k relationship
IWSG2009

Physical
y
Properties of Graphene
Semi-metal with zero band-gap and large
number of carriers even in intrinsic
intrinsic .
High mobility in the plane ( ~15,000cm2/Vs
at room temperature
p
)
Nearly ballistic transport in m scale
( velocity ~108cm/s )
2D structure more compatible with
current MOSFET process technology.
---- Graphene has great potential to be used
as a channel material in MOSFET devices.

Jason Woo

IWSG2009

Carrier Densities in Monolayer Graphene

Linear E-k relationship
E = F|k|,
| |,

is reduced Planck constant,,

F is Fermi velocity ~ 1x106m/s

Carrier Densities per unit area in monolayer graphene

ne =

gsgv
d
,
(+Ec EF )/ kT
2
2(hF ) 0 1+e
+

gsgv
d
,
nh =
(Ev +EF )/ kT
2
2(hF ) 0 1+e
gs = 2, gv = 2

Intrinsic Carrier Density

ni ~ 1011/cm2-1012/cm2
Jason Woo

ne ,,nh (x1012 cm-2)

electron density
hole densityy

6
5
4

ni =1011cm-2

3
2
1
0
-0.3

-0.2

-0.1

0.1

0.2

0.3

EF-E
Ec,v (V)
IWSG2009

Metal-Oxide-Graphene Capacitor Structure

VG
Metal

0.8

Oxide

07
0.7

SiO2

Ctot//Cox

Graphene

0.6
0.5
0.4
0.

monolayer graphene ~ 3.37

gate oxide: tox=2nm
metal-graphene =00
Jason Woo

0.3
-1

-0.5

0.5

VG (V)
IWSG2009

Graphene Field-effect Transistors with Metal Source and

Drain - Simulation
G

n
Metal Metal
Metal Metal
+
Graphene
p
p-Si
SiO
SiO

22

tgraphene ~ 3.37
gate oxide: tox=2nm
metal-graphene =0

Hole dominates
101

IDS (mA/m
m)

Total Current

10-1
10-3

Hole Current

Electron Current

10-5
10-77

-1.0

Ambipolar conduction: IDS = Ie+Ih

Ion/Ioff ~ 45 ffor VGS=1V
1V and
d VGS=0V
0V
Jason Woo

Electron dominates

-0.5

0.0

0.5

1.0

VGS (V)

IWSG2009

Issues of Graphene Field-effect Transistors

Top-gate dielectric deposition:
-- Function layer needed
-- Cause transport degradation
in graphene

Choose different gate

workfunction for VTH tuning

Source

Gate
Dielectric
Graphene

Drain

Bottom dielectric
Si substrate

Contact resistance

Series resistance

Add to parasitic resistances and

degrade the conduction

Jason Woo

Interaction between graphene

and bottom dielectric
-- cause transport
t
t degradation
d
d ti
Trap states in graphene consume
charges but not conductive
IWSG2009

Effect of Parasitic Resistance and Capacitance on Current

ID =

VD
L
, R c (VG ) =
, Qc is conductive charge, Rs is parasitic resistance.
Qc W
Rc (VG ) + Rs

C gra Cox
I D W (VD Rs I D ) 2 Qc Qc
,
=
=

VG
L
VD
VG VG Cox + C gra + Cdef
d f
=

W
L

CoxVD (

C gra
VD Rs I D 2
)
VD
Cox + C gra + Cdef

Ideal expression
Effect of parasitic resistance
Effect of quantum capacitance of graphene and defect capacitance.

Jason Woo

IWSG2009

Effect of Parasitic Resistance

on Current
Ideal case, on/off ~ 68
Rs=50,
50 on/off
/ ff ~ 30
Rs=100, on/off ~ 20
Rs=200, on/off ~ 12

IDS (mA
A/m)

0.25
0.20
0.15

Assume:
W/L=1;
=15,000cm2/Vs
tox=2nm
2nm
VDS=10mV

VDS=0.01V
0 01V

0.10
0 05
0.05
0

0.2

0.4

0.6

0.8

VGS ((V))

Jason Woo

Reduce IDS: Rs=50, IDS @VGS=1V

decrease ~57%
Reduce gm: change the shape of IDS-VGS
Reduce Ion/Ioff: Rs=50, on/off ratio
decrease >50%

IWSG2009

Back-gated Graphene Field-effect Transistors

Highly resistive silicon substrate

Thermally grown SiO2 or ALD high-k
high k materials as
back-gate dielectric
Spin coat chemical synthesized graphene
E-beam evaporated
p
2nm Cr and 50nm Au as
source/drain contacts
a.

Cr/Au
Cr/Au
Graphene
Dielectric

Cr/Au

Cr/Au
Graphene

Si
Al2O3

Jason Woo

IWSG2009

Evaporated SiO2 on Exfoliated Graphene

20nm SiO2 deposited together

with gate metals using e-beam
evaporation
ti and
d lift
lift-off
ff process
Current degraded (~30%) after
top-gate stack deposition

M. C. Lemme, etc. Solid-State Elec.

2008
Jason Woo

IWSG2009

ALD Al2O3 on Graphene

Defect
Defect-free
free pristine graphene
no dangling bonds or functional groups to
assist oxide deposition

Al2O3 using functional group

Non-interacting
Non interacting layer between graphene and
Al2O3
A layer catalytically suitable for ALD Al2O3
formation

Jason Woo

IWSG2009

ALD Al2O3 using O3 as Function Layer

(a) HOPG surface treated by ozone pretreatment. (b) ALD Al2O3 surface on
ozone-treated HOPG. (c) TEM image of cross-section after Al2O3 deposition.

Fresh HOPG sample

Pre-treated by ozone, oxygen atoms absorbed on the surface
ALD Al2O3 using TMA+O3
Bongki Lee
Lee, et al.
al Appl.
Appl Phys.
Phys Lett
Lett. (2008)

Jason Woo

IWSG2009

ALD Al2O3 using NO2 as Function Layer

First applied on single wall carbon nanotubes

NO2 attracted on carbon surface through physical
adsorption
Aluminum centers of TMA attracted to oxygen end of
NO2
Further deposition with TMA+H2O

Demon B. Farmer, et al, Nano. Lett. (2006)

J. R. Williams, et al. Science (2007)

Jason Woo

IWSG2009

ALD Al2O3 process

Jason Woo

gr
ap
SiO hen
e

gr
ap
he
ne
Si O

Al[CH3]3 (trimethylaluminum) and H2O precursors

Physisorption of NO2
50 cycles of the ALD process

IWSG2009

ALD Al2O3 using Evaporated Al as Function Layer

Graphene, covered by Al2O3

E-beam evaporate 1~2nm Al on graphene

Al being
g oxidized in ambient before ALD
ALD Al2O3 deposited on oxidized Al
Seyoung Kim, etc. Appl. Phys. Lett. 2009

Jason Woo

IWSG2009

Graphene FETs with Al2O3 Dielectrics

IBM, IEDM 2008

Jason Woo

IWSG2009

Ambipolar Conduction of Graphene

Simulation of Graphene FET with
metal
t l contacts
t t
1.6
1.2

Electron dominates

0.8
0.4
-0.5

0.0

0.5

1.0

1.6
-0.5

0.0

0.5

1.0

VG (V)
The sum of electron and hole
current is ambipolar.
Electron (or hole) current only is
unipolar.
Jason Woo

1.2

VG (V)

04
0.4
0.0
-1.0

Electron current

0.0
-1.0

0.8

ID (mA
A/m)

ID (mA/m
m)

Hole dominates

ID (mA/m)

1.6

1.2

Hole current

0.8
0.4
0.0
-1.0

-0.5

0.0

0.5

1.0

VG (V)
IWSG2009

Schottky Tunneling Structure Applied in Graphene FETs

S
n+-Si

n
Metal
Metal n+-Si
Graphene +
p-Si
SiO
SiO22

EFn
EC

EV

to suppress ambipolar
conduction
increase Ion/Ioff

Schottky junction at source:

B =0.6eV
=0 6eV
EC=EV

VDS =0.01V

Sili
Silicon
S
Source Graphene
G h
Ch
Channell
Jason Woo

Employ
p y Schottky
y jjunctions at
source/drain

Graphene is semi-metal
semi metal
band-bending near the junction
always electrons tunneling
through the barrier

Schottky junction at drain:

n+ drain supplies only few holes
small Ih
IWSG2009

Graphene FETs with Schottky Tunneling Source/Drain Experimental

LPCVD Polysilicon on insulated surface

Etch
tc Polysilicon
o ys co to form
o sou
source/drain
ce/d a
Spin coat chemical synthesized graphene
Top-gate dielectric deposition
Etch dielectric in source/drain area and e-beam
e beam
evaporate 500nm Al contacts on Polysilicon
E-beam evaporate 500nm Al as gate
Al

Al

Al

Dielectric Poly-Si
Poly-SiGraphene
SiO2

Poly

Poly
G h
Graphene

Si
Al2O3

Jason Woo

IWSG2009

ALD Al2O3 with Evaporated Al on CVD Graphene

CVD graphene transferred to SiO2 substrate

E
Evaporate
t 2nm
2
Al using
i e-beam
b
evaporation
ti
Immediately transfer to ALD machine
ALD Al2O3 using TMA + H2O

Graphene
SiO2
Si

Jason Woo

ALD Al2O3

Graphene
SiO2

Oxidized Al

Si

IWSG2009

AFM Images of Al2O3 on CVD Graphene

Before Al2O3 deposition

a) CVD Graphene on SiO2

~3.05nm

SiO2
2.05m

Graphene

b) 2nm evaporated Al on surface

~3.05nm

After Al2O3 deposition

SiO2
2.05m

c) 8nm ALD Al2O3 on top of Al

Graphene

Jason Woo

~3.05nm

IWSG2009

Summary
y
Potential CVD Graphene Synthesis
Graphene Proporties Inteface Issues
Graphene MOSFET Processes
Graphene Channel FET Structures
Graphene FETs Processing

Jason Woo

IWSG2009

Conclusion
New Device Structures Exploiting Physical
Mechanisms Made Feasible by Nanometer
di
dimensions
i
to Achieve
A hi
ULPE
Exploiting
p
g EG not jjust High
g mobilities --Bandgap Engineering
Tunnel-Source
Tunnel Source Transistors Promising
What about other junctions?
Jason Woo

IWSG2009