3.

CMOS Inverters: Switching Characteristics

The switching characteristics combined with interconnect effects determine the overall
operating speed of digital systems. Therefore, the switch speed of gates and interconnect
effects must be estimated and optimized very early in the design phase to ensure circuit
reliability and performance. This section investigates the dynamic (time domain)
behaviour (switch speed) of the inverter.

Introduction
Consider the cascade connection of two CMOS inverter circuits shown in Fig. 3.1. The
parasitic capacitances associated with each MOSFET are:

C gd

and C gs : The gate to drain and gate to source capacitance are primarily due to the
gate overlap with diffusion.
C db and C sb : The drain to body and source to body capacitances are voltage
dependent junction capacitances.
C g : the gate capacitance is due to the thin-oxide capacitance over the gate area.
C int : The interconnect capacitance represents the parasitic capacitance contribution of
the metal or polysilicon connection between the two inverters.

It is assumed that a pulse wave form is applied to the input of the first-stage inverter. The
objective is to analyze the time-domain behaviour of the first-stage output Vout .

Figure 3.1 Cascaded CMOS inverter stages

The problem of analyzing the output voltage waveform is fairly complicated, even for
this relatively simple circuit, since a number of nonlinear voltage dependent capacitances
are involved. To simplify the problem, the capacitances of Fig 3.1 are converted to a
lumped linear capacitance connected between the output node of the inverter to ground,
as shown in Fig. 3.2, where C load is defined as
C load C gd , n C gd , p C db, n C db, p C int C g

(3.1)

Note some of the parasitic capacitance components shown in Fig. 3.1 do not appear in
this lumped capacitance expression. Since the source-to-substrate voltages of both
transistors are always equal to zero, the capacitances C sb,n and C sb, p are zero. The
capacitances C gs ,n and C gs , p are also not included because they are connected between the
input node and ground (or power supply).
Using Fig 3.2, the inverter transient response is reduced to finding the charge-up and
charge-down times of a single capacitance which is charged and discharged through one
transistor. The delay times calculated using a single using C load may be slightly
overestimate the actual inverter delay, but this is not considered a significant deficiency in
a first-order approximation.

Figure 3.2 First stage CMOS inverter with lumped output load capacitance

Delay-Time Definitions
This section describes some commonly used delay definitions. The input and output
voltage waveforms of a typical inverter are shown in Fig. 3.3. The propagation delay
times PHL and PLH determine the input-to-output signal delay during high-to-low and
low-to-high transitions of the output, respectively. By definition, PHL is the time delay
between the V50% -transition of the rising input voltage and the V50% -transition of the
falling output voltage. Similarly, PLH is defined as the time delay between the V50% transition of the falling input voltage and the V50% -transition of the rising output voltage.

Figure 3.3 Input and output voltage waveforms of a typical inverter and the definitions of
propagation delay times. The input voltage waveform is idealized as a step response.
To simplify the analysis of the delay expressions, the input voltage is usually assumed
to be an ideal step pulse with zero rise and fall times. Under this assumption, PHL
becomes the time required for the output voltage to fall from VOH to V50% level, and PLH
becomes the time required for the output voltage to rise from VOL to V50% level. The
voltage V50% is defined as
V50% VOL

1
1
(VOH VOL ) (VOH VOL )
2
2

(3.2)

The propagation delay times PHL and PLH labelled in Fig. 6.3 are defined as
PHL t1 t 0
PHL t 3 t 2

(3.3)

The average propagation delay P of the inverter characterizes the average time required
for the input signal to propagate through the inverter
P

PHL PLH
2

(3.4)

Fig. 3.4 provides the definitions of the output voltage rise and fall times. The rise time
rise is defined here as the time required for the output voltage to rise from the V10% level
to the V90% level. Similarly, the fall time fall is defined here as the time required for the
output voltage to fall from the V90% level to the V10% level. The voltage levels V10% and
V90% are defined as

Figure 3.4 Output voltage rise and fall time

V10% VOL 0.1(VOH VOL )
V90% VOL 0.9(VOH VOL )

(3.5)
(3.6)

Thus the rise and fall times defined in Fig. 3.4 are obtained:
fall t B t A
rise t D t C

(3.7)

Note that other delay definitions using 20% and 80% voltages levels have also been used.

Calculation of Delay Times

The section describes the average capacitance current method and the capacitance state
equation method to estimate the propagation delay times of PHL and PLH .

Average Current Method

A simple way to calculate the propagation delay times PHL and PLH is based on
estimating the average capacitance current during charge down and charge up,
respectively. Using the following relationship (i.e. I avg C (V / T ) ), if the capacitance
current during an output transition is approximated by a constant average current I avg , the
delay times are found as
PHL
PLH

C load V HL
I avg , HL
C load V LH
I avg , LH

Cload (VOH V50 % )

I avg , HL
C load (V 50% VOL )
I avg , LH

(3.8)
(3.9)

The average current during high-to-low transition and low-to-high transition can be
calculated by using the current values at the beginning and end of the transitions as

1
iC (Vin VOH , Vout VOH ) iC (Vin VOH , Vout V50% )
2
1
iC (Vin VOL , Vout VOL ) i C (Vin VOL , Vout V50% )
2

I avg , HL

(3.10)

I avg , LH

(3.11)

While the average-current method is relatively simple and requires minimal

calculations, it neglects the variations of the capacitance current between the beginning
and end points. Therefore, this approach provides a rough first-order estimates of the
charge-up and charge-down

Capacitance State Equation Method

The propagation delay times can be found more accurately by solving the state equation
of the output node in the time domain. The differential equation associated with the
output nodes is:
C load

dV out
i C i D , p i D, n
dt

(3.12)

For the rising input case, the output voltage is assumed to be VOH . When the input
voltages switches from low VOL to high VOH , the nMOS transistor is turned on and it
starts to discharge the load capacitance. At the same time, the pMOS transistor is
switched off and
i D, p 0

(3.13)

The circuit in Fig. 3.2 can now be reduced to Fig. 3.5. The differential equation
describing the discharge event of Fig. 3.5 is

Figure 3.5 Equivalent circuit of the CMOS inverter during high to low output transition.

C load

dV out
i D , n
dt

(3.14)

The input and output voltage waveforms during this high-to-low transition are illustrated
in Fig. 3.6. When the nMOS transistor starts conducting, it initially operates in the
saturation region. When the output voltage falls below (V DD VT ,n ), the nMOS transistor
starts to conduct in the linear region (These two operating regions are labelled in Fig.
3.6). First, consider the nMOS transistor operating in saturation.
i D,n

Kn
K
(Vin VT , n ) 2 n (VOH VT ,n ) 2
2
2

for (VOH VT ,n ) Vout VOH

(3.15)

Since the saturation current is practically independent of the output voltage (neglecting
channel-length modulation), the solution of (3.14) is the time interval t 0 to t1' (labelled in
Fig. 3.6) is
'

t t 1

t t

V out V OH V T ,n

dt C load

V out V OH

1
i D, n

2 Cload
dV out

K n (VOH VT , n ) 2

V out VOH V T ,n

out V OH

dVout

(3.16)

Evaluating (3.16), yields

t1' t 0

2 Cload VT ,n
K n (VOH V T , n ) 2

Figure 3.6 Input and output voltage waveforms during high-to-low transition

(3.17)

At t t1' , the output voltage will be equal to (VOH VT ,n ) and the transistor will be at the
saturation-linear region boundary. Next, consider the nMOS transistor operating in the
linear region.
i D ,n

Kn
K
2
2
2(Vin VT ,n )Vout Vout
n 2(VOH VT ,n )Vout Vout
2
2

for Vout (VOH VT ,n )

(3.18)

Substituting (3.18) into (3.14) for the time interval t1' and t1 , yields
t t1

t t

'
1

V out V 50%

dt Cload

Vout V OH VT ,n

i
D,n

1
dVout Cload V out V 50%
Vout VOH VT ,n K 2(V V )V V 2

OH
T ,n
out
out
n

dV
out

(3.19)
Evaluating (3.19), yields
t1 t1'

2(VOH VT ,n ) V50 %
ln
VT , n )
V50 %

C load
K n (VOH

(3.20)

The propagation delay time from high to low output ( PHL ) can be found by adding (3.17)
and (3.20) and substituting V50% (VOH VOL ) / 2 to obtain
PHL

2VT , n
4 (VOH VT , n )

Cload

ln
1

K n (VOH VT ,n ) VOH VT ,n
V OH VOL

(3.21)

For the CMOS inverter, VOH V DD and VOL 0 , thus (3.21) can be written as
PHL

2VT , n
4 (V DD VT , n )

Cload

ln
1

K n (VDD VT , n ) VDD VT ,n
V DD

(3.22)

When the input voltage switches from high VOH to low VOL , the nMOS transistor is cut
off, and the load capacitance is being charged up through the pMOS transitor. Following
a very similar derivation procedure, the propagation delay time PLH obtained is
PLH

K p (VOH

2 | VT , p |
2 (VOH VOL | VT , p |)

C load

ln
1

VOL | VT , p |) VOH VOL | VT , p |

VOH V50%

(3.23)

Substituting V50% (VOH VOL ) / 2 , VOH V DD and VOL 0 , into (3.23) yields
PLH

2 | VT , p |
4 (V DD | VT , p |)

C load

ln
1

K p (V DD | VT , p |) VDD | VT , p |
V DD

(3.24)

Comparing the delay equations of (3.22) and (3.24), the sufficient conditions required
for PHL PLH ,
VT , n | VT , p | and K n K p or ( W p / W n n / p )
(3.25)

RC Time Constant Method

The RC time constant method calculates the propagation delay by approximating the
nMOS and pMOS transistors as resistors. To calculate the propagation delay time from
high to low output ( PHL ), the pMOS transistor is in cut off, while the nMOS transistor
operates first in the saturation region and then moves in the linear region. The input
voltage of the inverter under this scenario is Vin VOH V DD and the resistance of the
nMOS transistor is approximated as

R av

V SAT V LIN

I
SAT I LIN

(3.26)

where V SAT and V LIN correspond to two points on the I D - V DS curve. For example, Fig
3.7 selects the two points at
V SAT V DD
V LIN (V DD VT ,n ) / 2

(3.27)
(3.28)

At Vout V SAT , the nMOS transistor is in saturation mode, while at Vout V LIN , the nMOS
transistor is in linear mode. Thus, the currents I SAT and I LIN labelled in Fig 3.7 are
calculated as

ID

Vin=VGS=VDD

I SAT

ILIN

VLIN=(VDD+VT,n)/2

VSAT=VDD

Vout=VDS

Figure 3.7 How to approximate the MOS transistor as a resistor

I SAT
I LIN

Kn
(V DD VT , n ) 2
2

(3.29)

2
(V DD VT , n ) (V DD VT , n ) 3
K n
(V DD VT , n ) 2

2 (V DD VT , n )

8
2
2
2

(3.30)

The discharge of the load capacitance from high to low output voltage is obtained by
solving the RC circuit in which the resistor R av is connected with C load to obtain
Vout V DD e t /( Rav Cload )

(3.31)

To calculate the propagation delay (3.31) is set to Vout / VDD 0.5 , as

PHL

0.5 e PHL /( Rav C load )

Rav Cload ln(0.5) 0.69 Rav Cload

(3.32)

A similar approach can be developed to calculate the propagation delay from low to high
output PLH .

Propagation Delay for Finite Rise/Fall Times of Input Signals

The exact calculation of the output voltage delay times is more complicated under the
more realistic assumption that the input signal has a finite rise and fall times, r and f .
To simplify the estimation of the actual propagation delays, the following empirical
expressions can be used.
2
2
PHL ( actual ) PHL
( step input ) r / 2

2
PLH ( actual ) PLH
( step input )

/2

(3.33)
(3.34)

The values PHL ( step input ) and PLH ( step input ) denote the propagation delay time values
calculated assuming a step pulse input waveform at the input. While the expressions of
(3.33) and (3.34) are purely empirical, they provide a simple estimation of how much the
propagation delays are increased as a result of nonzero input rise and fall times.

Methodologies to Improve Propagation Delay Calculations

The delay calculations of (3.8), (3.9), (3.22), (3.24) and (3.32) were derived using the
simple current-voltage relationships originally developed for long-channel transistors
(shown below for the nMOS transistor).
i D,n

Kn
2
2(VGS VT , n )V DS V DS
2

(linear or triode region) VGS Vt , V DS VGS Vt

i D,n

Kn
(Vin VT , n ) 2
2

(saturation region) VGS Vt , V DS VGS Vt

(3.35)

The equations of (3.35) can be replaced with more accurate current-voltage relationships
to improve the propagation delay calculations; however this usually increases the
computational complexity of the problem.

Calculation of Output Voltage Rise and Fall Times

The average current method, the differential equation method and the RC time constant
method can also be used to calculate the output voltage rise and fall times (i.e. fall and
rise ). The equations for the average current method are:

C (V90 % V10% )
C V

1
I avg
I (Vin VOH , V out V 90% ) I (Vin V OH , V out V10% )
2
C (V90% V10% )
C V

1
I avg
I (Vin V OL , V out V90% ) I (V in VOL , Vout V10% )
2

fall

rise

(3.36)
(3.37)

Next, the rise and fall time equations are derived using the differential equation approach.
To calculate fall , the nMOS transistor operates in the saturation region for
VOH VT 0, n V out V90% and operates in the linear region for V10% V out VOH VT 0, n .
Following an approach similar to (3.16) and (3.19), the fall time fall is obtained by
solving the following integral

fall

2 C load
K n (VOH VT , n )

V out V OH VT 0 ,n

Vout V10 %

Vout V90 %

V out VOH VT 0, n

dVout 2C load

dVout

2
K n 2 (V OH VT , n )V out Vout

(3.38)

The solution of (3.38) yields

fall

2 Cload (VT , n V90 % V OH )

K n (VOH VT ,n ) 2

2 (V OH VT , n ) V10 %
ln
VT , n )
V10%

C load
K n (V OH

(3.39)

Using (3.5), (3.6) and setting VOL 0 , VOH V DD (3.39) becomes

fall

2 C load (VT , n 0. 1V DD )
K n (V DD VT ,n ) 2

1. 9V DD 2VT , n
ln
VT , n )
0 .1V DD

C load
K n (V DD

Following a similar procedure, the rise time rise can be found as

(3.40)

 rise

2C load (| VT , p | V10% VOL )

K n (VOH VOL | VT , p |) 2

Cload
K n (V OH V OL | VT , p

2 (V OH V OL | VT , p |) (VOH V90% )

ln

|)
VOH V90%

(3.41)
Using (3.5), (3.6) and setting VOL 0 , VOH V DD (3.41) becomes
rise

2Cload (| VT , p | 0 .1VDD )
2

K n (VDD | VT , p |)

1 .9VDD 2 | VT , p |
Cload

ln

K n (VDD | VT , p |)
0 .1VOH

(3.42)

The rise and fall times of the output voltage (i.e. fall and rise ) can also be calculated
using the RC time constant method. Using (3.31), the transition time of fall is measured
between the time at which Vout 0.9V DD and Vout 0.1V DD as

fall

0. 1
R av C load ln
2 .2 R av C load
0 .9

(3.43)

In (3.43), R av is obtained by selecting the two points on the I D - V DS curve to estimate

the average resistance of the transistor between Vout 0.9V DD and Vout 0.1V DD . An
equation similar to (3.43) can also be used to calculate rise .

Inverter Design with Delay Constraints

The design of CMOS logic circuits based on timing (delay) specifications is one of the
most fundamental issues in digital circuit design which ultimately determines overall
performance of complex systems. In most cases, the delay constraints should be
considered together with other design constraints such as noise margins, logic (inversion)
threshold, silicon area, and power dissipation.
The goal in this section is to determine the channel dimensions ( Wn , W p ) of the nMOS
and pMOS transistors which satisfy certain timing requirements. The load capacitance
C load in (3.1) consists of intrinsic components (parasitic drain capacitances which depend
on transistor dimensions) and extrinsic components (interconnect/wiring capacitance and
fan-out capacitances which are usually independent of transistor dimensions of the
inverter under consideration).

When Cload Consists Mainly of Extrinsic Capacitance Components

If C load mainly consists of extrinsic components, then the overall load capacitance does
not significantly change by the transistor dimensions. Under this assumption, C load is
treated as a constant value, independent of the transistor dimensions. Given a required
*
(target) delay value of PHL
and using (3.22) and K n n C ox (W n / Ln ) , the require (W/L)ratio of the nMOS transistor can be found as

 Wn

Ln

2VT ,n

C load
4 (V DD VT ,n )

ln
1
*

V
V

C
(
V

V
)
DD
T
,
n
DD

PHL n ox
DD
T ,n

(3.44)

*
Similarly, the (W/L)-ratio of the pMOS transistor to satisfy a given target value of PLH

Wp

Lp

2 | VT , p |
4(V DD | VT , p |)
Cload

ln
1
*

V | VT, p |
V DD

PLH p C ox (V DD | VT , p |) DD

(3.45)

In most cases, the transistor sizes found from delay requirements must also meet other
design requirements such as noise margins and logic inversion threshold.

When Cload is Effected by Intrinsic Capacitance Components

For the case when the intrinsic capacitance causes significant change in the load
capacitance C load , increasing the device dimensions W n and W p increases the load
capacitance C load . Thus (3.1), which describes the components of the output load
capacitances becomes
C load C gd , n (W n ) C gd , p (W p ) C db,n (W n ) C db, p (W p ) C int C g f (W n , W p )

(3.46)

Note, that the fan-out capacitance C g is also a function of the device dimensions in the
next-stage gate(s). Note that any effort to increase the channel width of nMOS and pMOS
transistors in order to reduce delay will inevitably increase the intrinsic components of the
load capacitance.
To gain some insight into the transistor sizing problem under delay constraints, and to
simplify the analysis, the load capacitance of equation (3.46) is typically expressed as a
linear function with respect to the device dimensions W n and W p , as
C load 0 nW n pW p

(3.47)

where 0 , n and p are positive constant coefficients derived by technology-related

parameters such as doping densities, minimum channel length and physical geometry
(layout design rules). Using (3.47), the propagation delay expressions of (3.22) and (3.24)
can be written as
0 ( n R p )Wn
PHL n
Wn

0 ( n / R p )W p
PLH p

Wp

(3.48)

(3.49)

where R is referred to as the transistor aspect ratio, defined as R W p / W n , and

n

Ln
n C ox (V DD

2VT ,n
4(V DD VT , n )

ln
1

VT , n ) V DD VT , n
V DD

Lp
p C ox (V DD | VT , p

2 | VT , p |
4(V DD | VT , p |)

ln
1

|) V DD | V T , p |
V DD

(3.50)
(3.51)

Note that the channel lengths Ln and L p are usually fixed and equal to each other and are
*
set by the process technology that is being used. Given the target delay values of PHL
and
*
PLH , the minimum channel widths of the nMOS and pMOS transistors which satisfy
these delay constraints can be calculated from (3.48) and (3.49), by solving W n and W p ,
respectively.
An important conclusion from (3.48) and (3.49), is that there exists an inherent
limitation to the switching speed in CMOS inverters, due to the parasitic capacitances
that are functions of W n and W p . It can be seen that increasing W n and W p to reduce the
propagation delay times will have a diminishing influence upon delay beyond a certain
value, and the delay values will asymptotically approach a limit value for large W n and
W p . From (3.48) and (3.49), the limit delay values are

p n / R p

PHL n n R p
PLH

(3.52)
(3.53)

To illustrate some of the fundamental issues of this section, consider the design of a
CMOS inverter using 0.8m technology parameters (i.e. The channel lengths of the
nMOS and pMOS transistors are Ln L p 0.8m ). The power supply voltage is 3.3V; the
extrinsic capacitance component of the load is 100fF. The transistor aspect ratio is
R (W p / W n ) 2.75 . Fig. 3.8 shows the SPICE simulations when the transistor width is
varied from W n 2m to W n 20m . As expected, the inverter with the smallest transistor
dimensions ( W n 2m and W p 5.5m ) has the largest propagation delay. The delay is
reduced by increasing the channel widths of both the nMOS and pMOS devices. Initially,
the amount of delay reduction can be significant, however, the delay reduction gradually
diminishes when the transistor widths are further increased, and the delays approach limit
values due to the technology-related parameters described by (3.52) and (3.53). Fig. 3.9
shows the propagation delay PHL as a function of the nMOS channel width. The delay
asymptotically approaches a limit value of about 0.2ns, which is mainly determined by
technology-specific parameters.

Figure 3.8 Simulated output voltage waveforms of CMOS inverter obtained for five
different designs

Figure 3.9 Propagation delay PHL as a function of the nMOS channel width (obtained by
SPICE simulation)

Calculating the Parasitic Capacitances

This section describes how to calculate the load capacitance components of (3.46) in
terms of the width W n and W p

Gate to drain capacitance: C gd ,n and C gd , p :

C gd , n C ox W n L D ,n and C gd , p C ox W p L D , p

Drain to body capacitance: C db,n and C db, p :

C db,n W n X n C j 0,n K eq, n (2 X n W n ) C jsw,n K eq, n

C db , p W p X p C j 0, p K eq , p (2 X p W p ) C jsw, p K eq , p

Gate capacitance is a function of the device dimensions in the next gate and is equal
to.
C g C gb,n C gb, p where C gb, n C ox W n Lmask , n and C gb, p C ox W p Lmask , p

C int :

The interconnect capacitance represents the parasitic capacitance contribution of

the metal or polysilicon connection between the two inverters.

where

is the oxide capacitance defined as C ox ox / t ox ( ox 3.9 o 3.45e 11 F / m is the

permittivity of silicon and t ox is the thickness of the oxide layer)
C j 0 is the zero-bias junction capacitance per unit area
C jsw is the zero-bias sidewall junction capacitance per unit length
K eq is the voltage equivalent factor and ranges from 0 K eq 1
W, L and X are defined in Fig. 3.10
C ox

W
LD

Lmask
L

Figure 3.10 Layout of nMOS transistor used to calculate parasitic capacitances

Propagation Delay versus Area

The propagation delay due to the sizing of transistors is inherently limited by the parasitic
capacitance. In fact, the increase in silicon area can be viewed as a design trade-off for
delay reduction, since the circuit speed improvements are typically obtained at the
expense of increased transistor dimensions. Figure 3.11 shows the (Area x Delay) product
of the previous example. Based on these results, it can be argued that increasing W n
beyond about 4-5 m will result in a waste of valuable silicon area, since the obtainable
delay reduction is very small beyond that point.
A practical measure used for quantifying design quality is (Area x Delay) product,
which takes into account the silicon-area cost of transistor sizing for delay reduction.
While the propagation delay asymptotically approaches a limit value for increasing
channel widths, the (Area x Delay) product exhibits a clear minimum around W n 4m ,
indicating the optimum choice both in terms of speed and overall silicon area.

Figure 3.11 Area x delay product of CMOS inverter

Switching Power Dissipation of CMOS Inverters

It was shown in the previous chapter that the DC static power dissipation of a CMOS
inverter is quite negligible. However, during switching events, where the output load
capacitance is charged up or charged down, the CMOS inverter inevitably dissipates
power. This section will derive the expressions for dynamic power consumption of the
CMOS inverter.
Consider the CMOS inverter of Fig. 3.2. It is assumed that the input voltage waveform
is an ideal step waveform with negligible rise and fall times. The typical input and output
voltage waveforms and the expected load capacitor current waveforms are shown in Fig.
3.12. When the input switches from low to high, the pMOS transistor is turned off and
the nMOS transistor starts conducting. This causes C load to discharge through the nMOS
transistor. When the input switches from high to low, the nMOS transistor is turned off

and the pMOS transistor starts conducting. This causes C load to charge through the pMOS
transistor.
Assuming periodic input and output waveforms, the average power dissipated by any
device over one period T, is:
Pavg

1
v( t) i( t) dt
T 0

(3.54)

During switching, the nMOS and pMOS transistors in a CMOS inverter conduct current
for one-half period each. The average power dissipated by the CMOS inverter is
calculated as
Pavg

1
T

T / 2
dVout
V out C load

dt

T
dV out

dt (V DD Vout ) C load
dt

T/2

dt

(3.55)

Evaluating (3.55), yields

Pavg

1
2
2
C load V DD
fC load V DD
T

(3.56)

Figure 3.12 Typical input output voltage and the capacitor current waveform during
switching of the CMOS inverter

where f 1 / T . The average power dissipation of a CMOS inverter is proportional to the

switching frequency f. Therefore, the low power advantage of CMOS circuits becomes
less prominent in high-speed operation, where the switching frequency is high.
Furthermore, the average power dissipation is independent of all transistor characteristics
and transistor sizes.
The switching power expression derived for the CMOS inverter also applies to general
CMOS circuits as shown in Fig 3.13. For an ideal step waveform with negligible rise and
fall times, it is assumed that either the pMOS block or nMOS block can conduct
depending on the input voltage combination. Thus, for general CMOS circuits, switching
power is dissipated mainly for charging and discharging the output capacitance.

Figure 3.13 Generalized CMOS logic circuit

Measuring Power using SPICE Simulation

The following technique can be used to estimate the average power dissipation of
arbitrary circuits (including the effects of short circuit and leakage currents). Consider the
circuit shown in Fig. 3.14. The additional circuitry consists of a zero volt independent
voltage source connected in series with the power supply voltage, a linear currentcontrolled current source, a capacitor and a resistor. The current equation at voltage node
V y (Fig. 3.14) is expressed as
Cy

dV y
dt

is

Vy
Ry

The time domain solution of V y for an initial condition of V y (0) 0 is

(3.57)

Figure 3.14 The power meter circuit used for the simulation of average dynamic power
dissipation of an arbitrary circuit

V y ( t)
Cy

R C
y y

i DD ( )d

(3.58)

Setting the resistance and capacitance values to satisfy R y C y T

V DD C y / T , reduces (3.58) reduces to
V y ( t) VDD

and setting

1
i DD ( )d
T 0

(3.59)

Note that (3.59) corresponds to the average power drawn from the power supply source
over one period. Thus the voltage V y at t=T gives the average power dissipation.
The power meter circuit of Fig. 3.14 can easily be implemented in SPICE to calculate
the average power dissipation of arbitrary circuits. In addition, this technique takes into
account the additional power dissipation due to short-circuit currents, which may arise
because of nonideal input conditions as well as leakage currents.

Power-Delay Product
The power delay product is the average energy required for a gate to switch its output
voltage from low to high and from high to low and is defined as

PDP E average v(t ) i(t ) dt

0

(3.60)

Following the analysis of (3.55)-(3.56), the amount of energy required to switch the
output is
2
PDP C load V DD

(3.61)

The energy of (3.61) is mainly dissipated as heat when the nMOS and pMOS transistors
conduct current during switching.
Note that calculating PDP using (3.61) and average power using (3.56) may result in a
misleading interpretation of the amount of energy/power used by the circuit (due to
leakage and short-circuit currents) . Thus design engineers often use (3.56) and (3.61) for
performance comparisons.