ISSN 2319-8885

Vol.03,Issue.38
November-2014,
Pages:7751-7754
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An Efficient Modified High Speed Square Root Carry Select Adder

D.SRIMATHI1, S.ASHVINI2, G.N.JAYABHAVANI3
1

Dept of Applied Electronics, IFET College of Engineering, Villupuram, India, E-mail: srimathi.oec@gmail.com.
Dept of Applied Electronics, IFET College of Engineering, Villupuram, India, E-mail: ashvinisugu@gmail.com.
3
Dept of ECE, IFET College of Engineering, Villupuram, India, E-mail: jayabhavaniece@gmail.com.

Abstract: An adder is used to perform the arithmetic operations. Carry select adder(CSLA) is one of the high-speed adder
which compute the fast arithmetic operations. The carry select adder works according to the input carry(C in).The CSLA can
perform fast arithmetic operations when compared to other kind of adder such as Ripple carry adder. The Modified high speed
square root (SQRT) carry select adder (CSLA) has less delay and area when compared to the Conventional square root carry
select adder (CSLA) and binary to excess-1 convertor (BEC)-based SQRT CSLA employed in square root architecture. In the
customized design the carry has been produced prior to the final sum. The Modified high speed (SQRT) CSLA does not involve
the same logical operations. The result shows that the proposed scheme involves less area and delay compared to the Existing
methods.
Keywords: Adder, Binary To Excess-1 Convertor, High Speed Adder, Conventional Square Root (SQRT) Carry Select Adder,
Carry Select Adder (CSLA).
I. INTRODUCTION
The goal of VLSI design is to reduce the area, delay and
power. The requirement of advanced digital system is less
complex design of an adder. The high performance adder will
improve the effectiveness of digital system. In ripple carry
adder(RCA) n number of full adders has been used to
compute the arithmetic operations. But the carry propagation
delay is higher in Ripple carry adder. To overcome this
problem a Conventional carry select adder has been designed.
A conservative carry select adder consists of two ripple carry
adder(RCA) which produces the sum and carry according to
the fixed input carry Cin. In which the next stage sum and
carry generation depend upon the previous stage carry
out[1].The aim of SQRT CSLA to reduce the propagation
delay for higher bit widths. Even though conventional carry
select adder is better than ripple carry adder(RCA) its
architecture is not desirable. To improve the efficiency of
CSLA a new technique has been introduced in which instead
of one ripple carry adder an n+1 bit BEC is used. This
technique provides a better results than existing
method[2].The square root architecture has been employed in
BEC based CSLA to increase the efficiency of CSLA[3].
redundant logic operations is used in proposed scheme.
The paper is organized as below. Section II illustrates the
Conventional carry select adder. Section III employs the BEC
In the proposed scheme the number of logical elements has
been reduced and the carry has been scheduled earlier to
reduce the delay. When compared to the existing system less
based CSLA. Section IV describes the modified high speed
SQRT CSLA. SectionV describes the experimental

results. Section VI will provide the conclusion and future

work.
II. CONVENTIONAL SQRT CSLA
Conventional square root carry select adder architecture
consists of two ripple carry adder(RCA) and multiplexer.
Both the ripple carry adder(RCA) generate the sum and
carry according to the input carry Cin. When Cin=0 the RCA1 generate the n-bit sum and carry. When Cin=1 then RCA-2
generate the corresponding sum and carry. The mux will
select the final sum and carry from RCA-1 or RCA-2
according to the input carry Cin. The Conventional carry
select adder consumes higher area and delay due to the use of
dual RCA.

Fig1(a). Ripple carry adder.

Fig.1(a) represents the Ripple carry adder(RCA). The
ripple carry adder consists of n-bit full adders .The full adder
will perform the arithmetic operations according to the input
carry. While S represents Sum and C represents Carry.
(1)
(2)
The logical equations for full adders are shown above. By
using these equations the RCA generates the final sum and

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D.SRIMATHI, S.ASHVINI, G.N.JAYABHAVANI

carry. While the AND and OR operations are performed in
Carry the XOR operation is performed in Sum.

Fig2(b). 32 bit BEC based SQRT CSLA.

Fig1(b). 32 bitConventional SQRT CSLA.
Fig.1 (b) represents the Conventional square root(SQRT)
carry select adder(CSLA) structure in which the RCA are
connected in different bit widths. The mux will choose the
corresponding sum and carry according to the input carry C in.
III. BEC BASED SQRT CSLA
The main work of BEC based SQRT CSLA is to reinstate
the n+1 bit BEC in place of RCA-2.It will increment the
input value by one. It perform the same operation performed
by the RCA-2 with less delay. The general structure
composed of RCA-1, BEC logic and MUX. The sum and
carry generated by the RCA-1 enter in to the BEC unit it will
levitate the input value by one. When input carry Cin=0 the
RCA-1will generate the corresponding sum and carry.
Similarly when Cin=1 the BEC unit will generate the sum and
carry.

Fig.2 (b) represents the BEC based SQRT CSLA. It is

constructed with different multiple bit widths. Due to this
arrangement the delay was balanced in each stage.
IV. MODIFIED HIGH SPEED SQRT CSLA
In the proposed work the carry generation and final sum
generation is different from the existing methods. It consists
of partial sum generation(PSG) unit, carry origination(CO)
unit, carry choosing(CC)unit, final sum generation(FSG)
unit. The PSG unit obtain two n-bit input(A and B) and
produce n-bit partial-sum (Sp) and partial carry (Cp).The carry
origination unit is separated in to two units such as CO 0and
CO1 according to the input carry Cin=0 and 1.It receives both
the partial sum and partial carry from the PSG unit and
generate two n-bit full carry C1and C2 according to the Cin
value. Then, the carry choosing(CC) unit choose any one
carry among two according to the Cin value(0,1).When Cin=0,
it choose CO0 or else it will choose CO1.The final carry(C) is
produced by the carry choosing unit. The output carry Cout is
obtained from the MSB bit of C. The (n-1) MSB bits of finalsum(Sf) is obtained by performing XOR operations between
(n-1) LSB bits of C and (n-1) MSB bits of partial
sum(Sp).The LSB of final sum(Sf) is generated by executing
the XOR operations between Cin and LSB of SP.

Fig2(a). Binary to Excess-1 Convertor.

Fig.2(a) represents the general BEC structure in which the
logical gates such as AND, XOR, NOT gates are used.
(3)
(4)
(5)
(6)
The above logical equations represent the BEC logic.
Depend upon the above equation the sum and carry were
generated. The parameters A0, A1, A2 represents the sum of
RCA while the A3 represents the carry of the RCA unit.

Fig3(a). Modified high speed CSLA.

International Journal of Scientific Engineering and Technology Research

Volume.03, IssueNo.38, November-2014, Pages: 7751-7754

An Efficient Modified High Speed Square Root Carry Select Adder

Fig.4(a) illustrate the number of logical elements used by
(7)
the Conventional SQRT CSLA.
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)

Fig4(b). Delay of Conventional SQRT CSLA.

Fig.4(b) describes about the delay of the Conventional
SQRT CSLA without any failed paths.

In the above equations (7 and 8) represents the partial sum

and partial carry generated by the PSG unit. Then equation (9
and 10) represents the carry produced by the CO unit. The
equation(13) describes the output carry generated by the CC
unit. The remaining equations(14 and 15) represents the final
sum generated by FSG unit.

Fig3(b). Modified high speed SQRT CSLA.

Fig4(c). Area of BEC based SQRT CSLA.

Fig.3(a) (b) describes Modified high speed SQRT CSLA. In

this structure the RCA is connected in series with the
Modified high speed CSLA in dissimilar bit widths. Due to
the earlier carry selection the delay will reduce.

Fig.4(c) illustrate the number of logical elements used by

the BEC based SQRT CSLA.

V. EXPERIMENTAL RESULTS
The proposed work is implemented by using the language
Verilog HDL in QUARTUS II 9.1software.The following
result illustrate about the area and delay of the Conventional
SQRT CSLA,BEC based SQRT CSLA and Modified high
speed SQRT CSLA. The comparison made between the
Existing and Proposed work is shown.

Fig4(d). Delay of BEC based SQRT CSLA.

Fig.4(d) describes about the delay of the BEC based
SQRT CSLA without any failed paths.

Fig4(e). Area of Modified high speed SQRT CSLA.

Fig4(a). Area of Conventional SQRT CSLA.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.38, November-2014, Pages: 7751-7754

D.SRIMATHI, S.ASHVINI, G.N.JAYABHAVANI

Fig.4(c) show the number of logical elements used by the
[6] Ceiang, T. Y. and Hsiao. J.,,Carry-Select Adder Using
Modified high speed SQRT CSLA.
Single Ripple Carry Adder,Electron. Lett., Vol. 34,no. 22,
pp. 21012103, Oct1998.
[7] A. Tyagi, A Reduced Area Scheme For Carry-Select
adders, IEEE Trans. On Computer,Vol.42.pp.11631170,1993.
[8]N.Vijayabala and T.S.Saravana Kumar,Area Minimization Of Carry-Select Adder Using Boolean Algebra,
International Journal of Advances in Engineering &
Fig4(f). Delay of Modified high speed SQRT CSLA.
Technology, Vol. 6, Issue 3, pp. 1250-1255, July 2013.
[9]Ramkumar,B., Kittur, H.M. and Kannan ,P.M,ASIC
Fig.4(f) demonstrate about the delay of the Modified high
Implementation Of Modified faster Carry Save Adder,Eur.
speed SQRT CSLA without any failed paths.
J.Sci. Res., Vol. 42, no. 1,pp.5358.,2010 .
TABLE I: Comparison of Area and Delay for Existing
and Proposed methods

The Table.1 shown that the Area and Delay of Proposed

method is lesser than the Existing Methods.
VI. CONCLUSION
The
proposed
work
was
implemented
using
QUARTUSII9.1.The area was reduced owing to the usage of
less number of logic gates. Due to the earlier carry selection
the delay was reduced. Along with that the proposed work
was performed in square root (SQRT) architecture which
helps to reduce the delay. The carry choosing unit and carry
origination unit of the proposed method is distinct from the
existing methods. In the BEC based SQRT CSLA delay has
reduced but the area have increased when compared to the
conventional SQRT CSLA. In case of proposed method both
area and delay has been reduced when compared to the
conventional SQRT CSLA method and BEC based SQRT
CSLA. Thus the result shows the proposed work is efficient
than the existing methods in terms of area and delay.
VII. REFERENCES
[1]O.J.Bedriji,Carry-Select Adder, IRETrans. Electron.
Comput., Vol.EC- 1 1,no.3, pp.340-344, Jun.1962.
[2]K Allipeera, S Ahmed Basha, An Efficient 64-Bit Carry
Select Adder
With Less Delay and Area
Application,ISSN: 2248-9622 Vol. 2,Issue 5, SeptemberOctober 2012.
[3] He,Y.,Chang,C.H.,Area Efficient 64-Bit Square Root
Carry Select Adder for Low Power Application,in Proc.
IEEE Int.Symp.Circuits Syst.,Vol.4,pp.4082-4085,,J.,2005.
[4]Youngjoon Kim and Lee-Sup Kim, A Low Power Carry
Select Adder
With Reduced Area, IEEE International
Symposium on Circuits and Systems, Vol.4, pp.218-221,
May 2001.
[5]Padma Devi, AshimaGirdher, Balwinder SinghImproved,
Carry Select Adder With Reduced Area and Low Power
Consumption, International Journal of Computer
Applications Vol 3-No.4,2010.

Authors Profile:
D.Srimathi was born in Tamilnadu on 1991.
She is a M.E. student of Applied Electronics
department in IFET College of Engineering,
Villupuram, India. She completed her
Bachelor of degree in Electronics and
Communication Engineering in Oxford
Engineering College, Trichy, India in the year 2013.
S.Ashvini was born in Tamilnadu on 1992.
She is a M.E. student of Applied Electronics
department in IFET College of Engineering,
Villupuram, India. She completed her
Bachelor of degree in Electrical and
Elecronics Engineering in Sri Manakula
Vinayagar Engineering College, Puducherry,
India in the year 2013.
Ms.G.N.Jayabhavani is currently working
as Assistant Professor in IFET College of
Engineering,
Villupuram.
She
has
completed her Master degree in the field of
Communication System at SASTRA
University, Thanjavur. In the year 2013.
She holds 12 publications out of which 6 in
IEEE and rest in Scopus Indexed journals. She has also
presented papers in several poster presentations.

International Journal of Scientific Engineering and Technology Research

Volume.03, IssueNo.38, November-2014, Pages: 7751-7754