DIGITAL SYSTEM

DESIGNS AND PRACTICES

Using Verilog HDL and FPGAs
Ming-Bo Lin
Department of Electronic Engineering
National Taiwan University of Science and Technology
Taipei, Taiwan

John Wiley & Sons (Asia) Pte Ltd

CONTENTS
PREFACE
CHAPTER 1 INTRODUCTION
1.1 Introduction
1.1.1 Popularity of Verflog HDL
1.1.2 Simple Examples of Verflog HDL
1.1.3 HDL-Based Design
1.2 Introduction to Verflog
1.2.1 Module Concept
1.2.2 Lexical Conventions
1.2.3 Value Set
1.2.4 Constants
1.2.5 Data Types
1.2.6 Primitives
1.2.7 Attributes
1.3 Module Modeling Styles
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5

Modules
Structural Modeling
Dataflow Modeling
Behavioral Modeling
Mixed-Style Modeling

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1.4 Simulation

21

1.4.1 Basic Simulation Constructs

1.4.2 Related Compiler Directive and System Tasks
1.4.3 A Tutorial Example
Summary
References
Problems

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CHAPTER 2

STRUCTURAL MODELING

31

2.1 Gate-Level Modeling

31

2.1.1 Gate Primitives

32

2.1.2 Tristate Buffers

2.1.3 Wired Logic
2.2 Gate Delays
2.2.1 Delay Models
2.2.2 Delay Specifications

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46

2.3 Hazards
2.3.1 Static Hazards
2.3.2 Dynamic Hazards
2.4 Switch-Level Modeling
2.4.1 MOS Switches
2.4.2 CMOS Switch

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2.4.3 Bidirectional Switches

2.4.4 Delay Specifications
2.4.5 Signal Strength

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2.4.6 t r i r e g Net
Summary
References
Problems

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CHAPTER 3

69

DATAFLOW MODELING

3.1 Dataflow Modeling

3.1.1 Continuous Assignment
3.1.2 Expressions

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3.1.3 Delays
3.2 Operands
3.2.1 Constants
3.2.2 Data Types

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3.2.3 Bit-Select and Part-Select

3.2.4 Array and Memory Elements
3.3 Operators
3.3.1 Bit-wise Operators
3.3.2 Arithmetic Operators

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86

3.3.3
3.3.4
3.3.5
3.3.6
3.3.7

Concatenation and Replication Operators

Reduction Operators
Logical Operators
Relational Operators
Equality Operators

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CONTENTS

3.3.8 Shift Operators

3.3.9 Conditional Operator
Summary
References
Problems
CHAPTER 4

BEHAVIORAL MODELING

4.1 Procedural Constructs

4.1.1 i n i t i a l Block
4.1.2 a l w a y s Block
4.2 Procedural Assignments
4.2.1 Procedural Assignments
4.2.2 Blocking Assignments

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103

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4.2.3 Nonblocking Assignments

4.2.4 Blocking versus Nonblocking Assignments
4.3 Timing Control
4.3.1 Delay Timing Control
4.3.2 Event Timing Control

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118

4.4 Selection Statements

4.4.1 i f - e l s e Statement
4.4.2 c a s e Statement
4.4.3 c a s e x and c a s e z Statements
4.5 Iterative (Loop) Statements

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4.5.1 w h i l e Loop Statement

4.5.2 f o r Loop Statement

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4.5.3 r e p e a t Loop Statement

4.5.4 f o r e v e r Loop Statement
Summary
References
Problems

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CHAPTER 5

TASKS, FUNCTIONS AND UDPS

145

5.1 Tasks
5.1.1 Task Definition and Call
5.1.2 Types of Tasks

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149

5.2 Functions
5.2.1 Function Definition and Call

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152

5.2.2 Types of Functions

5.2.3 Constant Functions
5.2.4 Sharing Tasks and Functions

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5.3 System Tasks and Functions

5.3.1 Simulation-Related System Tasks
5.3.2 File I/O System Tasks
5.3.3 String Formatting System Tasks
5.3.4 Conversion System Functions

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5.3.5 Probability Distribution System Functions

5.3.6 Stochastic Analysis System Tasks
5.3.7 Command Line Arguments
5.4 User-Defined Primitives
5.4.1 UDP Basics
5.4.2 Combinational UDP

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5.4.3 Sequential UDP

Summary
References
Problems

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CHAPTER 6 HIERARCHICAL STRUCTURAL MODELING

6.1 Module
6.1.1 Module Definition
6.1.2 Parameters
6.1.3 Module Instantiation
6.1.4 Module Parameter Values
6.1.5 Hierarchical Names
6.2 g e n e r a t e Statement
6.2.1 Generate-Loop Statement
6.2.2 Generate-Conditional Statement
6.2.3 Generate-Case Statement
6.3 Configurations
6.3.1 Library
6.3.2 Basic Configuration Elements
Summary
References
Problems

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CONTENTS

CHAPTER 7

ADVANCED MODELING TECHNIQUES

7.1 Sequential and Parallel Blocks

7.1.1 Sequential Blocks
7.1.2 Parallel Blocks
7.1.3 Special Features of Blocks
7.1.4 The d i s a b l e Statement
7.2 Procedural Continuous Assignments
7.2.1 a s s i g n and d e a s s i g n Statements
7.2.2 f o r c e and r e l e a s e Statements
7.3 Delay Models and Timing Checks
7.3.1 Delay Models
7.3.2 Specify Blocks
7.3.3 Timing Checks
7.4 Compiler Directives

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7.4.1 v d e f i n e and ' u n d e f Compiler Directives

7.4.2 ' i n c l u d e Compiler Directive
7.4.3 ' i f d e f , ' e l s e , ' e l s i f , ' e n d i f and ' i f n d e f Compiler
Directives
7.4.4 v t i m e s c a l e Compiler Directive

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261

7.4.5 Miscellaneous Compiler Directives

263

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Summary

265

References

266

Problems

266

CHAPTER 8

COMBINATIONAL LOGIC MODULES

8.1 Decoders
8.1.1 Decoders
8.1.2 Expansion of Decoders
8.2 Encoders

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278

8.2.1 Encoders

278

8.2.2 Priority Encoders

28

8.3 Multiplexers
8.3.1 Multiplexers
8.3.2 Expansion of Multiplexers
8.4 Demultiplexers
8.4.1 Demultiplexers
8.4.2 Expansion of Demultiplexers

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8.5 Magnitude Comparators

8.5.1 Magnitude Comparators

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8.5.2 Cascadable Magnitude Comparators

8.6 A Case Study: Seven-Segment LED Display
8.6.1 Seven-Segment LED Display

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296

8.6.2 Multiplexing-Driven Seven-Segment LED Display

Summary
References
Problems

299

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304

CHAPTER 9

307

SEQUENTIAL LOGIC MODULES

9.1 Flip-Flops
9.1.1 Flip-Flops

307

9.1.2 Metastable State

9.1.3 Synchronizers
9.1.4 A Switch-Debouncing Circuit
9.2 Memory Elements

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321

9.2.1
9.2.2
9.2.3
9.2.4

Registers
Register Files
Synchronous RAM
Asynchronous RAM

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325

9.3 Shift Registers

9.3.1 Shift Registers
9.3.2 Universal Shift Registers
9.4 Counters

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334

9.4.1 Ripple Counters

9.4.2 Synchronous Counters
9.5 Sequence Generators
9.5.1 PR-Sequence Generators
9.5.2 CRC Generator/Detectors

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349

9.5.3 Ring Counters

9.5.4 Johnson Counters
9.6 Timing Generators
9.6.1 Multiphase Clock Generators
9.6.2 Digital Monostable Circuits
Summary
References
Problems

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358

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CONTENTS

CHAPTER 10

DESIGN OPTIONS OF DIGITAL SYSTEMS

10.1 Design Options of Digital Systems

10.1.1 Hierarchical System Design
10.1.2 Design Options of Digital Systems
10.1.3 ASIC Designs
10.1.4 Design with Field-Programmable Devices

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378

10.2 PLD Modeling

10.2.1 ROM
10.2.2 PLA

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385

10.2.3
10.2.4
10.3 CPLD
10.3.1
10.3.2
10.4 FPGA

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406

PAL
PLA Modeling
XC9500 Family
MAX7000 Family

10.4.1 Xilinx FPGA Devices

10.4.2 Altera FPGA Devices
10.5 Practical Issues

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418

10.5.1 I/O Standards

10.5.2 Voltage Tolerance
Summary
References
Problems

419
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424

CHAPTER 11

427

SYSTEM DESIGN METHODOLOGY

11.1 Finite-State Machine

11.1.1 Types of Sequential Circuits
11.1.2 FSM Modeling Styles
11.1.3 Implicit versus Explicit FSM
11.2 RTL Design
11.2.1 ASM Chart

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438
438

11.2.2 ASM Modeling Styles

11.2.3 Datapath and Controller Design
11.3 RTL Implementation Options
11.3.1 Single-Cycle Structure
11.3.2 Multiple-Cycle Structure
11.3.3 Pipeline Structure

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11.3.4 FSM versus Iterative Logic

469

11.4 A Case Study: Liquid-Crystal Displays

477

11.4.1
11.4.2
11.4.3
11.4.4
Summary
References
Problems

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479
484
487
495
496
497

Principles of LCDs
Commercial Dot-Matrix LCD Modules
Datapath Design
Controller Design

CHAPTER 12 SYNTHESIS

5(H

12.1 Design Flow of ASICs and FPGA-Based Systems

12.1.1 The General Design Flow
12.1.2 Timing-Driven Placement
12.2 Design Environment and Constraints

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12.2.1 Design Environment

509

12.2.2 Design Constraints

12.2.3 Optimization
12.3 Logic Synthesis
12.3.1 Architecture of Logic Synthesizers
12.3.2 Two-Level Logic Synthesis
12.3.3 Multilevel Logic Synthesis
12.3.4 Technology-Dependent Synthesis

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522

12.4 Language Structure Synthesis

12.4.1 Synthesis of Assignment Statements
12.4.2 Synthesis of Selection Statements

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525

12.4.3 Delay Values

12.4.4 Synthesis of Positive and Negative Signals
12.4.5 Synthesis of Loop Statements
12.4.6 Memory and Register Files
12.5 Coding Guidelines

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530
533
533

12.5.1 Guidelines for Clocks

12.5.2 Guidelines for Resets
12.5.3 Partitioning for Synthesis
Summary
References
Problems

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539

CONTENTS

CHAPTER 13

VERIFICATION

XV

543

13.1 Functional Verification

13.1.1 Design Models

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544

13.1.2 Simulation-Based Verification

13.1.3 Formal Verification
13.2 Simulation
13.2.1 Types of Simulations and Simulators
13.2.2 Architecture of HDL Simulators

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549
549
551

13.2.3 Event-Driven Simulation

13.2.4 Cycle-Based Simulation
13.3 Test Bench Design

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556

13.3.1
13.3.2
13.3.3
13.3.4

Test Bench Design

Clock Signal Generation
Reset Signal Generation
Verification Coverage

556
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567

13.4 Dynamic Timing Analysis

13.4.1 Basic Concepts of Timing Analysis
13.4.2 SDF and SDF Generation
13.4.3 Delay Back-Annotation

570
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571
572

13.4.4 SDF Format

13.5 Static Timing Analysis
13.5.1 Fundamentals of Static Timing Analysis
13.5.2 Timing Specifications

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577

13.5.3 Timing Exceptions

13.6 Value Change Dump (VCD) Files
13.6.1 Four-State VCD Files
13.6.2 VCD File Format

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582
ses

13.6.3 Extended VCD Files

13.7 A Case Study: FPGA-Based Design and Verification
Flow
13.7.1 ISE Design Flow

586

13.7.2 Dynamic Timing Simulations

13.7.3 An RTL-Based Verification Flow
Summary
References
Problems

594
599
599
601
601

588
588

CHAPTER 14

ARITHMETIC MODULES

605

14.1 Addition and Subtraction

14.1.1 Carry-Look-Ahead Adder

605
eoe

14.1.2 Parallel-Prefix Adder

14.2 Multiplication
14.2.1 Unsigned Multiplication
14.2.2 Signed Multiplication
14.3 Division
14.3.1 Restoring Division Algorithm

609
615
615
623
626
626

14.3.2 Nonrestoring Division Algorithm

14.3.3 Nonrestoring Array Divider
14.4 Arithmetic and Logic Unit
14.4.1 Shift Operations

627
629
632
632

14.4.2 ALUs
14.5 Digital-Signal Processing Modules
14.5.1 Finite-Impulse Response Filters
14.5.2 Infinite-Impulse Response Filters
Summary
References
Problems

635
638
638
640
642
643
644

CHAPTER 15

649

DESIGN EXAMPLES

15.1 BUS

649

15.1.1 Bus Structures

15.1.2 Bus Arbitration
15.2 Data Transfer
15.2.1 Synchronous Data Transfer
15.2.2 Asynchronous Data Transfer
15.3 General-Purpose Input and Output

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657
657
659
664

15.3.1 Basic Principles

15.3.2 A Design Example
15.4 Timers
15.4.1 Basic Timer Operations
15.4.2 Advanced Timer Operations
15.5 Universal Asynchronous Receiver and Transmitter
15.5.1 UART
15.5.2 Transmitter

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683

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XV

15.5.3 Receiver
15.5.4 Baud-Rate Generator
15.5.5 UART Top Module
15.6 A Simple CPU Design
15.6.1 Fundamentals of CPU
15.6.2 Datapath Design
15.6.3 Control Unit Design
Summary
References
Problems

685
689
691
693

699
701
706
708
708

CHAPTER 16

DESIGN FOR TESTABILITY

16.1 Fault Models

16.1.1 Fault Models
16.1.2 Fault Detection
16.1.3 Test Vector
16.1.4 Difficulty of Sequential Circuit Test
16.2 Test Vector Generation
16.2.1 Fault Table Approach
16.2.2 Fault Simulation

7n
712
714
716
717
719
719
721

16.2.3 Boolean Difference

16.2.4 Path Sensitization and >-Algorithm
16.3 Testable Circuit Design
16.3.1 Ad hoc Approach
16.3.2 Scan-Path Method

723
726
731
731
732

16.3.3 BIST
16.3.4 Boundary-Scan Standard-IEEE 1149.1
16.4 System-Level Testing
16.4.1 SRAM BIST and March Test
16.4.2 Core-Based Testing

733
739
752
752
755

16.4.3 SoC Testing

Summary
References
Problems

756
757
758
758

APPENDIX A

763

VERILOG HDL SYNTAX

A . l Keywords

763

xviii

CONTENTS

A.2 Source Syntax

A.2.1 Library Source Text
A.2.2 Configuration Source Text
A.2.3 Module and Primitive Source Text
A.2.4 Module Parameters and Ports
A.2.5 Module Items
A 3 Declarations
A.3.1 Declaration Types
A.3.2 Declaration Data Types
A.3.3 Declaration Lists
A.3.4 Declaration Assignments
A.3.5 Declaration Ranges
A.3.6 Function Declarations

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766
767
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768
769
769
770
770

A.3.7 Task Declarations

A.3.8 Block Item Declarations
A.4 Primitive Instances

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771
771

A.4.1 Primitive Instantiation and Instances

A.4.2 Primitive Strengths
A.4.3 Primitive Terminals
A.4.4 Primitive Gate and Switch Types
A. 5 Module and Generated Instantiation
A.5.1 Module Instantiation

771
772
772
773
773
773

A.5.2 Generated Instantiation

A.6 UDP Declaration and Instantiation
A.6.1 UDP Declaration
A.6.2 UDP Ports

773
774
774
774

A.6.3 UDP Body

A.6.4 UDP Instantiation
A.7 Behavioral Statements

774
775
775

A.7.1 Continuous Assignment Statements

A.7.2 Procedural Blocks and Assignments
A.7.3 Parallel and Sequential Blocks

775
775
776

A.7.4
A.7.5
A.7.6
A.7.7
A.7.8

776
777
777
778
778

Statements
Timing Control Statements
Conditional Statements
Case Statements
Looping Statements

CONTENTS

A.7.9 Task Enable Statements

A.8 Specify Section
A.8.1 Specify Block Declaration
A.8.2
A.8.3
A.8.4
A.8.5

Specify
Specify
Specify
System

Path Declarations
Block Terminals
Path Delays
Timing Checks

A.9 Expressions
A.9.1 Concatenations
A.9.2 Function Calls
A.9.3
A.9.4
A.9.5
A.9.6

Expressions
Primaries
Expression Left-Side Values
Operators

A.9.7 Numbers
A.9.8 Strings
U O General
A. 10.1 Attributes
A. 10.2
A. 10.3
A. 10.4
A. 10.5
INDEX

Comments
Identifiers
Identifier Branches
White Space

Xix
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