802-16 Ofdm Phy Tech Spec

Confidential
802.16 OFDM Phy

Technical Description
Confidential
REV 1.13
802.16 OFDM Phy Technical Description

1/7/05
Page 1 of 89
Confidential
RESTRICTED PROPRIETARY INFORMATION

The information disclosed herein is the exclusive property of SiWorks Inc. and is not to
be disclosed without the written consent of SiWorks Inc. No part of this publication may
be reproduced or transmitted in any form or by any means including electronic storage,
reproduction, execution or transmission without the prior consent of SiWorks Inc. The
recipient of this document by its retention and use, agrees to respect the security status of
the information contained herein.
This document is intended for limited circulation.
The information contained in this document is subject to change without notice and
should not be construed as a commitment by SiWorks Inc. unless such commitment is
expressly given in a covering document.
Copyright SiWorks Inc. (2004)
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Table of Contents
1
2
3
5
6
Purpose........................................................................................................................ 7
Overview..................................................................................................................... 7
Programming Model ................................................................................................. 10
3.1
Transmitter........................................................................................................ 11
3.2
Receiver ............................................................................................................ 11
Top Level Interface Description ............................................................................... 12
4.1
Port Definitions................................................................................................. 12
4.2
802.16 SOC System Block Diagram ................................................................ 13
4.3
Register Description.......................................................................................... 15
Reset Logic ............................................................................................................... 18
ARC/PHY Interface ................................................................................................. 19
6.1
ARC/PHY Interface and Timing ...................................................................... 19
6.2
FIFO Control/Status.......................................................................................... 21
6.3
Miscellaneous (RF,AFE,etc) Control Registers................................................ 23
6.4
Interrupts ........................................................................................................... 27
6.5
Frame Timer: .................................................................................................... 33
6.6
Preamble and AGC Memory Interface ............................................................. 36
Transmitter................................................................................................................ 39
7.1
Overview........................................................................................................... 39
7.2
Transmitter Control Word and Register Description........................................ 40
7.3
Transmitter Timing ........................................................................................... 42
7.4
Transmit Channel Encoder ............................................................................... 43
7.5
IFFT .................................................................................................................. 47
7.6
Transmit Front End ........................................................................................... 49
7.7
Transmit Test Circuitry..................................................................................... 50
Receiver .................................................................................................................... 52
8.1
Overview........................................................................................................... 52
8.2
Receiver Control Word & Register Description............................................... 54
8.3
AFE Rx Interface, Rx FIFO, AGC & Decimation Filters ................................ 58
8.4
Frequency Correction........................................................................................ 67
8.5
Timing Recovery, Synchronization & AFC ..................................................... 69
8.6
FFT.................................................................................................................... 76
8.7
Timing Correction............................................................................................. 76
8.8
Channel Estimator............................................................................................. 77
8.9
Channel Decoder............................................................................................... 78
8.10 Receive Test Circuitry ...................................................................................... 82
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List of Figures
Figure 1: WMAN_PHY System Block Diagram............................................................... 7
Figure 3: 802.16 SOC System Block Diagram................................................................. 14
Figure 5: PHY Reset Circuitry......................................................................................... 18
Figure 7: ARC/PHY Interface Block Diagram ................................................................ 19
Figure 9: ARC/PHY Write Cycle Timing..................................................................... 20
Figure 11: ARC/PHY Read Cycle Timing ....................................................................... 20
Figure 13: rx_en, tx_en & tr_sw timing: TDD Mode....................................................... 25
Figure 15: rx_en/tx_en timing: FDD Mode ...................................................................... 25
Figure 17: rx_en, tx_en & tr_sw control logic.................................................................. 26
Figure 19: Transmitter Block Diagram............................................................................ 39
Figure 21: Transmit Burst Timing no Offset ................................................................. 42
Figure 23: Transmit Burst Timing with Offset .............................................................. 42
Figure 25: Scrambler LFSR .............................................................................................. 43
Figure 27: Convolutional Encoder.................................................................................... 44
Figure 29: Pilot LFSR..................................................................................................... 46
Figure 31: Frequency Response of 39-tap Halfband Tx Interpolation Filter.................... 49
Figure 33: Receiver Block Diagram ................................................................................ 53
Figure 35: ADC Interface & Rx FIFO.............................................................................. 58
Figure 36: AGC System Level Block Diagram ................................................................ 60
Figure 38: AGC Timing.................................................................................................... 61
Figure 21: AGC External Timing Diagram ...................................................................... 65
Figure 22: Frequency Response of 39-tap Halfband Rx Decimation Filter ..................... 66
Figure 24: Freq_Corr Block Diagram............................................................................... 68
Figure 26: SYNC Block Diagram..................................................................................... 70
Figure 28: Sequencing of Timing Recovery Operations in SYNC block......................... 71
Figure 30: Timing Correction Block Diagram.................................................................. 76
Figure 32: Channel Decoder Sub-blocks .......................................................................... 78
Figure 34: Demapper Sub-Block ...................................................................................... 78
Figure 36: De-Interleaver / De-Puncturer Sub-block........................................................ 79
Figure 37: Viterbi Sub-block ............................................................................................ 80
Figure 38: Descrambler Sub-block ................................................................................... 81
Figure 39: SED Register (SEDR) .................................................................................... 84
Figure 52: SED Timing Diagram...................................................................................... 84
Figure 41: SED Channel Estimate Magnitude & Phase Timing Diagram........................ 85
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List of Tables
Table 1: IEEE 802.16 Modulation Modes .......................................................................... 8
Table 3: Max Data Rates for Supported Channel Bandwidths ........................................... 9
Table 5: WMAN_PHY Top Level Interface .................................................................... 12
Table 6: WMAN_PHY Register Description: 0x00 - 0x1F............................................. 15
Table 7: WMAN_PHY Register Description: 0x20 0x49 ............................................. 16
Table 8: WMAN_PHY Register Description: 0x4B 0x4D............................................ 17
Table 9: FIFO Register (FCR & FSR) Description .......................................................... 22
Table 11: Miscellaneous Control Register (MCR) Description ....................................... 23
Table 12: Delay Timer Control Register (DTCR) Description ........................................ 24
Table 13: Interrupt Enable Register (IER) Description .................................................... 27
Table 14: Interrupt Register (ISR) Description ................................................................ 29
Table 15: Interrupt Register (IR) Description................................................................... 30
Table 16: Interrupt Information Register (IIR) Description ............................................. 31
Table 17: Interrupt Clear Register (ICR) Description ...................................................... 32
Table 18: Cyclic Prefix Lengths ....................................................................................... 33
Table 19: Frame Timer Register (FTR) Description ........................................................ 35
Table 20: Preamble Memory Control (PMCR) and Data Register (PMDR) Description 38
Table 21: Transmit Control Word Description................................................................. 40
Table 22: Transmit Control Register (TCR0,1) Description ............................................ 41
Table 23: Transmit Status Register (TSR) Description .................................................... 41
Table 24: Block Sizes per Modulation Format ................................................................. 44
Table 26: Puncture Patterns .............................................................................................. 45
Table 27: Interleaver Block Sizes ..................................................................................... 45
Table 29: Transmit Modulation Register (TMR0-2) description ..................................... 47
Table 31: Typical Transmit Modulation Scale Values ..................................................... 47
Table 33: IFFT Scaling Example...................................................................................... 48
Table 35: Transmit Test Register (TTR) Description....................................................... 50
Table 36: Transmit DAC Register(TDR) Description...................................................... 51
Table 37: Transmit Test Tone Selection Table................................................................ 51
Table 38: Receive Control Word Description .................................................................. 54
Table 39: Receive Control Registers (RCR0-3) Description............................................ 55
Table 40: Receive Control Registers (RCR4-6) Description............................................ 56
Table 41: Receive Status Registers (RSR0-8) Description............................................... 57
Table 42: AGC Power Compare (APCR0-4) and AGC Attenuatior (AAR0-2) Register
Descriptions .............................................................................................................. 64
Table 44: Preamble 64 Coefficient Registers (P64CR0-3) Description ........................... 72
Table 36: Preamble 64 Coefficient Registers (P64CR4-7) Description ........................... 73
Table 37: Preamble 128 Coefficient Registers (P128CR0-3) Description ....................... 74
Table 48: Preamble 128 Coefficient Registers (P128CR4-7) Description ....................... 75
Table 39: Typical Demap Scale Values............................................................................ 79
Table 40: Receive AveragingControl Register (RACR) Description............................... 83
Table 42: Receive I&Q Averaging Register (RAVGR) Description................................ 83
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Definitions
CC Convolutional Coding
DDS Direct Digital Synthsis
FEC Forward Error Correction
FCH Frame Control Header
PDU Protocol Data Unit
PHY Physical Layer
RS Reed- Solomon
RS-CC Concatenated Reed-Solomon/Convolutional Coding FEC
Fixed-point numbers are specified as follows:

<4.4>
<4.4u>
<8.0>
<8.0u>
- An 8-bit signed number with 4 integer bits (including sign) and four binal
bits. Eg. 0x77 = 7.875, 0x82 = -7.875.
- An 8-bit unsigned number with 4 integer bits and four binal bits Eg. 0x82 =
8.125
- An 8-bit signed integer number Eg. 0x82 = -126
- An 8bit unsigned integer number Eg. 0x82 = 130
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1 Purpose
The purpose of this document is to provide a technical description of the WirelessMan
OFDM Phy, herein described as the WMAN_PHY.
2 Overview
The WMAN_PHY implements the Wireless MAN OFDM Phy layer as described in the
802.16revD_D3, of the 802.16 specifications. The WMAN_PHY operates in
conjunction with an ARC-Tangent processor subsystem which implements the Transmit
Convergence Sublayer (TC_Sublayer), performs initial set-up of the Phy and also
performs Frame Control Header (FCH) decode of incoming packets. A system level
block diagram of the WMAN_PHY is shown in Figure 1.
WMAN_PHY
ARC
AFE
Tx Front End
Tx Data
Tx
FIFO
Tx Channel
Encoder
256-pt
IFFT
CP
Insert
Int.
Filter
AFE Tx
Interface
Control
Status
Rx Data
Rx Front End: Rx_FE

Rx
FIFO
Rx Channel
Decoder:
Channel
Estimator
256-pt
FFT
AFC,
AGC
&
Timing
Dec.
Filter
AFE Rx
Interface
Figure 1: WMAN_PHY System Block Diagram
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The WMAN_PHY will support the following features:

Channel Bandwidths:
Channel bandwidths ranging from 1.5 to 20 MHz are supported. The bandwidths
are assumed to be selectable upon power up of the chip and will be otherwise
fixed during normal operation. An external DDS will be used to generate the
appropriate clocks for the WMAN_PHY.
Transmitter:
Channel coding including implementation of the mandatory concatenated ReedSolomon/Convolution Code (RS-CC) FEC
Support for the modulation and code rates as shown in Table 1. The optional 64QAM modulation mode is included.
When subchannelization is applied in the uplink, the FEC shall bypass the RS
Decoder and use the Overall Coding Rate as the CC Code Rate as indicated in
Table 1.
Support for up to 16 subchannels
Ability to generate long, short and custom preambles
Modulation
BPSK
BPSK
QPSK
QPSK
16-QAM
16-QAM
64-QAM
64-QAM
Overall Coding
Rate
2/3
RS Code
CC Coding Rate
(12,12,0)
(12,12,0)
(32,24,4)
(40,36,2)
(64,48,8)
(80,72,4)
(108,96,6)
(120,108,6)
1/2
3/4
2/3
5/6
2/3
5/6
5/6
Table 1: IEEE 802.16 Modulation Modes

Receiver:
Synchronization using long, short and custom preambles
Support for a maximum coded data rate of 72.6 Mbps corresponding to 64-QAM
transmission over a 20 MHz channel bandwidth as shown in Table 2
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Channel
Bandwidth
(MHz)
Fs/Bw
1.5
3
5.5
1.75
3.5
7
10
14
20
7/6
7/6
7/6
8/7
8/7
8/7
8/7
8/7
8/7
Max
Uncoded Data
Rate for
QAM-64
(Mbps)
7.6
15.3
27.4
8.7
17.5
34.9
49.9
69.8
96.8
Max
Coded Data
Rate for
QAM-641
(Mbps)
5.7
11.5
20.6
6.6
13.1
26.2
37.4
52.4
72.6
Front End
(FECLK)
Clock Rate
2xFs
(MHz)
3.5
7
12.83
4
8
16
22.86
32
45.71
Table 2: Max Data Rates for Supported Channel Bandwidths

Analog Front End:
The receiver will interface to dual 10-bit ADCs running at a maximum sample
rate of 45.71 MHz (assuming a 20 MHz channel bandwidth)
The transmitter will interface to dual 10-bit DACs running at a nominal sample
rate of 45.71 MHz (assuming a 20 MHz channel bandwidth).
Assumes R=5/6 for coding rate at Viterbi decoder
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3 Programming Model
The 802.16 OFDM Phy specification requires support for frame based transmission
where a frame2 consists of a downlink subframe and an uplink subframe. Downlink
subframes consist of a single downlink Protocol Data Unit (PDU) while uplink subframes
consist of contention slots for initial ranging and bandwidth requests followed by one or
multiple uplink PDUs..
A Downlink PDU consists of the following elements:
Preamble
Frame Control Header
Downlink burst 1,, m
Note that a Downlink subframe consists of a single Downlink PDU

An Uplink PDU consists of the following elements
Preamble
Uplink Burst
Note that one or multiple Uplink PDUs can be concatenated together in an Uplink
Subframe.
The interface to the Phy has been designed to enable burst based transmission and
reception of 802.16 compliant frames. For Subscriber Station operation, frame timing is
acquired by the Phy during initial synchronization to the Base Station. For BS operation,
frame timing is initialized in the Phy by the external processor. The Phy maintains the
frame time and allows the external processor to synchronize itself to the Phy frame timer
via programmable interrupts.
In the following sections the interface and partitioning between the MAC and the Phy for
the transmitter and receiver are described.
See section 8.3.4.1 of 802.16Revd-D2
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3.1 Transmitter
The Phy assumes that the variable length PDUs from the MAC are transformed into
fixed length FEC blocks before they are input to the Phy. This requires that
concatenation of short PDUs or segmentation of long PDUs is accomplished externally.
In addition, encryption and Cyclic Redundancy Check (CRC) calculations are assumed to
be external to the Phy.
Transmit bursts in Uplink or Downlink format are provided to the Phy by the external
processor. A Transmit Control Word (TCW) is associated with each transmit data burst
and is applied to the Phy by the external processor in conjunction with the transmit data
through separate control and data FIFOs. The transmit control word is a multi-element
control signal which describes the format and timing for an associated burst of data
contained in the Tx data FIFO. All elements of the transmit burst from start time,
modulation type and burst size to scrambler seed, midamble type and number of data
bytes can be specified through the Tx Control Word. In cases where the number of data
bytes to be transmitted is not equal to an integer number of OFDM symbols, the phy will
pad the data with 0xFF as required.
3.2 Receiver
Receive bursts in Uplink or Downlink format are decoded by the Phy and provided to the
external processor. A Receive Control Word (RCW) is applied to the Phy by the external
processor. The RCW is a multi-element control word which is used to control the
synchronization, decoding and descrambling operations of the receiver. The receiver in
the WMAN_Phy has been designed to have extremely low latency allowing functions
such as Frame Control Header (FCH) decode to be provided by the external processor.
Upon completion of synchronization, AGC and timing/frequency recovery the receiver is
programmed by the external processor to decode the incoming bursts on a burst by burst
basis. For Subscriber Station operation, the reception of the FCH is performed during the
initial receiver synchronization phase and the receiver must be programmed to receive the
proper QPSK rate 1/2 modulation rate. The received FCH is then read and processed by
the external processor. The processor decodes the rate for the next burst from the FCH,
generates a new RCW and applies it to the Phy. The available time between FCH being
available and the MAC writing the control word for burst #1 is currently 600 phy clock
cycles.
In addition, the external processor must decode the DL and UL MAP and the UCD &
DCD messages. The incoming burst profiles are decoded from the messages and the
receiver programmed accordingly.
Receiver Base Station operation is more straightforward as the BS has specified to the SS
the format of the uplink data transmission and when it should occur.
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4 Top Level Interface Description

4.1 Port Definitions
Clock
Port
Direction
Type
arc_clk
fe_clk
phy_clk
reset_n
addr
bs_sync_in
in
in
in
in
in
in
std_logic
std_logic
std_logic
std_logic
std_logic_vector(6 downto 0)
std_logic
cs_n
datai
in
in
std_logic
Description
Domain
ARC Clock (160 MHz)

Front End Clock
Phy Clock (100 MHz)
Asychronous reset
Register address bus
Resets the frame timer on the
rising edge
Chip select
Input data
lock_det
in
std_logic
Lock Detect active high
lock_det_n
in
std_logic
Lock Detect active low
arc_clk
arc_clk
arc_clk
rd_n
in
std_logic
Read enable
arc_clk
rf_enable
rx_i
in
in
std_logic
RF enable
ADC I data
fe_clk
rx_q
in
ADC Q data
fe_clk
wr_n
adc_2s_cmp_sel
in
out
std_logic
std_logic
arc_clk
fe_clk
adc_dac_clk_en_n
out
std_logic
adc_out_en_n
adc_pd
agc
agc_stb
out
out
out
out
std_logic
std_logic
std_logic_vector(9downto 0)
std_logic
bandgap_pd
out
std_logic
bs_sync_out
out
std_logic
dac_pd
data_valid
datao
ft_int
int0_n
rx_en
sed_clk
out
out
out
out
out
out
out
std_logic
std_logic
std_logic
std_logic
std_logic
std_logic
sed_data
out
std_logic
sed_fs
out
std_logic
tr_sw
tx_en
tx_i
tx_q
vref_pd
out
out
out
out
out
std_logic
std_logic
std_logic
Write enable
Selects 2's complement otherwise
offset binary
Enables fe_clk to be driven to the
ADCs and DACs
Enables ADC output
Puts ADC in power down
AGC value
Pulses when the AGC value
changes
Powers down the bandgap
reference
Pulses high for 100 ms each time
the frame timer is reset.
Puts DAC in power down
datao is valid
output data
Output from frame timer interrupt 0
Interrupt 0
receive enable
serial interface clock for the symbol
error display
serial interface data for the symbol
error display
serial interface frame
synchronization signal
transmit switch
transmit enable
DAC I data
DAC Q data
Powers down the voltage reference
arc_clk
fe_clk
fe_clk
fe_clk
phy_clk
fe_clk
arc_clk
arc_clk
arc_clk
arc_clk
fe_clk
fe_clk
fe_clk
Table 3: WMAN_PHY Top Level Interface
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4.2 802.16 SOC System Block Diagram

The WMAN_PHY is designed to be integrated into a complete 802.16 baseband SOC. It
is interfaced to an on-chip ARC micro-controller and on-chip I&Q ADCs and DACs. A
system level block diagram is shown in Figure 2.
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SAMP_CLK?
fe_clk
PHY_CLK(100 MHz)
phy_clk
ARC_CLK(160 MHz)
arc_clk
ARC
rd_n
WMAN_PHY
adc_dac_clk_en_n
IADC
rx_i(9:0)
DO(9:0)
adc_2s_cmp_sel
adc_out_en_n
OMODE
OUTDIS
adc_pd
bandgap_pd
vref_pd
PDADC
PDBGR
PDVR
wr_n
cs_n
addr(6:0)
datai
datai(31:0)
datao(31:0)
QADC
PDVR
PDBGR
PDADC
data_valid
int0_n
OUTDIS
OMODE
rx_q(9:0)
RESET_PHY_n
reset_n
DO(9:0)
IDAC
dac_pd
tx_i(9:0)
PD
D(9:0)
QDAC
PD
tx_q(9:0)
LDB
lock_det
lock_det_n
RF_ENABLE
rf_enable
LD
agc(9:0)
agc_stb
AGC(9:0)
STROBE
rx_en
tx_en
RX_EN
TX_EN
tr_sw
TR_SW
sed_clk
sed_data
sed_stb_n
BS_SYNC_IN
bs_sync_in
D(9:0)
bs_sync_out
ft_int
SED_CLK?
SED_DATA?
SED_STROBE_N?
BS_SYNC_OUT
FT_INT
Figure 2: 802.16 SOC System Block Diagram
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4.3 Register Description

Register
Address
Name
(hex)
Initial
R/W
Description
Reference
Value
(hex)
FCR
00
R/W
FIFO Control Register
FSR
01
FIFO Status Register

Rx FIFO Data
RXDF
02
TXDF
03
Tx FIFO Data
RXCF
04
Rx Control FIFO
TXCF
05
Tx Control FIFO
IER
06
R/W
Interrupt Enable Register
IR
07
Interrupt Register
00000000
00000000
ISR
08
Interrupt Status Register
IIR
09
Interrupt Information Register
ICR
0A
Interrupt Clear Register
00000000
FTCR
0B
R/W
Frame Timer Control Register
00000000
FTSR
0C
Frame Timer Status Register
FTINTR0
0D
R/W
Frame Timer Interrupt 0
00000000
FTINTR1
0E
R/W
00000000
FTINTR2
0F
R/W
00000000
FTINTR3
10
R/W
00000000
FTINTR4
11
R/W
00000000
FTINTR5
12
R/W
00000000
MCR
13
R/W
Miscellaneous Control Register
00000000
DTCR0
14
R/W
Delay Timer Control Register 0
00000000
DTCR1
15
R/W
Delay Timer Control Register 1
00000000
PMCR
16
R/W
Preamble Memory Control Register
00000000
PMDR
17
Preamble Memory Data Register
PMSR
18
Preamble Memory Status Register
TCR0
19
R/W
Transmit Control Register 0
00000000
TCR1
1A
R/W
Transmit Control Register 1
00000000
TSR
1B
Transmit Status Register
TMR0
1C
R/W
Transmit Modulation Register 0
TMR1
1D
R/W
00000000
TMR2
1E
R/W
00000000
TTR
1F
R/W
Transmit Test Register
00000000
00000000
Table 4: WMAN_PHY Register Description: 0x00 - 0x1F
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Register
Address
Name
(hex)
Initial
R/W
Description
Reference
Value
(hex)
TDR
20
R/W
Transmit DAC Register
00000000
RCR0
21
R/W
Receive Control Register 0
00000000
RCR1
22
R/W
00000000
RCR2
23
R/W
00000000
RCR3
24
R/W
00000000
RCR4
25
R/W
00000000
RCR5
26
R/W
00000000
RCR6
27
R/W
00000000
RSR0
28
Receive Status Register 0
RSR1
29
RSR2
2A
RSR3
2B
RSR4
2C
RSR5
2D
RSR6
2E
RSR7
2F
RSR8
30
RSR9
31
P64CR0
32
R/W
P64 Coefficient Register 0
00000000
P64CR1
33
R/W
00000000
P64CR2
34
R/W
00000000
P64CR3
35
R/W
00000000
P64CR4
36
R/W
00000000
P64CR5
37
R/W
00000000
P64CR6
38
R/W
00000000
P64CR7
39
R/W
00000000
P128CR0
3A
R/W
00000000
P128CR1
3B
R/W
00000000
P128CR2
3C
R/W
00000000
P128CR3
3D
R/W
00000000
P128CR4
3E
R/W
00000000
P128CR5
3F
R/W
00000000
P128CR6
40
R/W
00000000
P128CR7
41
R/W
00000000
APCR0
42
R/W
AGC Power Compare Register 0
00000000
APCR1
43
R/W
00000000
APCR2
44
R/W
00000000
APCR3
45
R/W
00000000
APCR4
46
R/W
00000000
APCR5
47
R/W
00000000
AAR0
48
R/W
AGC Attenuator Register 0
00000000
AAR1
49
R/W
00000000
AAR2
4A
R/W
00000000
AAR3
4B
R/W
00000000
Table 5: WMAN_PHY Register Description: 0x20 0x49

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Register
Address
Name
(hex)
Initial
R/W
Description
Reference
Value
(hex)
RACR
4C
R/W
Receive I&Q Averaging Control Register
00000000
RAVGR
4D
Receive I&Q Averaging Register
00000000
SEDR
4E
Symbol Error Display Register
00000000
Table 6: WMAN_PHY Register Description: 0x4B 0x4D
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5 Reset Logic
A block diagram of the WMAN_PHY reset logic is shown in Figure 3. A single active
low reset signal, reset_n, is provide to the phy. It is assumed that the reset_n signal is
asynchronously asserted and synchronously removed based on the arcclk and lasts at
leasts one arcclk clock cycle. Inside the PHY Module, reset_n is used to generate two
more reset signals re-timed based on phyclk and feclk to reset the PHY Core and the
PHY/AFE interface respectively. The circuit has been designed so that the proper resets
will be generated independently of the power-up state of the flip flops.
reset_n
arc_clk
arc_reset
CLK
phy_reset
D
CLK
CLK
CLK
phy_clk
fe_reset
D
CLK
CLK
CLK
fe_clk
Figure 3: PHY Reset Circuitry
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6 ARC/PHY Interface
A description of the ARC/PHY interface, the interface timing and descriptions of the
FIFO, control, status and interrupt registers are given in the following sections.
6.1 ARC/PHY Interface and Timing

A block diagram of the ARC/PHY interface is shown in Figure 4. The interface is a set
of memory mapped registers and memories accessible by the ARC.
phy_clk (100 MHz)

arc_clk (160 MHz)
ARC
rd_n
wr_n
cs_n
WMAN_PHY
ARC/PHY
Interface
Tx
Data
FIFO
Transmitter
Tx
Control
FIFO
datai
datao
data_valid
int0_n
Rx
Data
FIFO
Receiver
Rx
Control
FIFO
Figure 4: ARC/PHY Interface Block Diagram

Timing diagrams for the read and write access of the register interface are shown in
Figure 5 and Figure 6.
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arc_clk
addr(6:0)
cs_n
wr_n
datao(6:0)
Figure 5: ARC/PHY Write Cycle Timing
arc_clk
addr(6:0)
cs_n
rd_n
datao(6:0)
data_valid
0-? cycles
Figure 6: ARC/PHY Read Cycle Timing

The ARC is clocked at 160 MHz compared with the WMAN_PHY which is clocked at
100 MHz. As a result of the two separate clock domains the register interface is required
to be retimed internally which results in limitations on read/write access. In a read access
the data_valid signal is used to halt the ARC read cycle until the data is present. The
data_valid signal can last between ?-? clock cycles depending on the relative timing
between the two clocks.
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6.2 FIFO Control/Status

The PHY contains four FIFOs; a Tx Data FIFO, a Tx Control FIFO, a Rx Data FIFO and
an RX Control FIFO. A brief description of the FIFOs are given below:
Tx Data FIFO:
Tx Control FIFO:
Rx Data FIFO:
Rx Control FIFO:
Contains payload data for the Phy transmitter and is written from
the ARC. This FIFO is of size 127x32 bits or approximately four
OFDM symbols.
Contains the Transmit control frame which is written from the
ARC to the Phy. The FIFO is of size 12x32 bits. Each transmit
control frame contains three words so the FIFO can contain 4
control frames.
Contains payload data from Phy receiver and is read by the ARC.
This FIFO is of size 127x32 bits.
Contains the Rx control frame which is written from the ARC to
the Phy. The FIFO is of size 12x32 bits. Each receive control
frame consists of 3 words so the FIFO can contain 4 control
frames.
The FIFO Control and Status Register are used to set up the FIFOs and are described in
Table 7.
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Register
Name
Addr
Field
# of
(hex) R/W
Name
Bits Slice
Description
FCR
00
R/W
txdfTl
6:0
Tx Data FIFO trigger level sets the number of words below which
causes the Tx Data FIFO watermark interrupt.
FCR
00
R/W
txdfRst
Tx Data FIFO reset resets all status flags, indices, etc. when set to
1. Does not clear contents of FIFO
FCR
00
R/W
txcfRst
Tx Control FIFO reset resets all status flags, indices, etc. when set
to 1. Does not clear contents of FIFO
FCR
00
R/W
rxdfTl
FCR
00
R/W
rxdfRst
16
Rx Data FIFO reset resets all status flags, indices, etc. when set to
1. Does not clear contents of FIFO
FCR
00
R/W
rxcfRst
17
Rx Control FIFO reset resets all status flags, indices, etc. Does not
clear contents of FIFO
FCR
00
R/W rxdfLpbkEn
18
FCR
00
txdfOverClr
19
FCR
00
txcfOverClr
20
FCR
00
rxdfUnderClr
21
FCR
00
rxcfOverClr
22
Tx/Rx Data FIFO Loop Back Register when this bit is set to 1,
data from the Tx Data Fifo is written to the Rx Data FIFO
Tx Data FIFO overrun clear when this bit is 1, the txdfOverrun flag
is cleared in the FSR. The bit is automatically cleared.
Tx Control FIFO overrun clear when this bit is 1, the txcfOverrun
flag is cleared in the FSR. The bit is automatically cleared.
Rx Data FIFO underrun clear when this bit is 1, the rxdfUnderrun
Rx Control FIFO overrun clear when this bit is 1, the rxcfOverrun
FSR
01
txdfLevel
6:0
FSR
01
txcfLevel
10:7 Indicates number of words present in Tx Control FIFO
FSR
01
rxdfLevel
17:11 Indicates number of words present in Rx Data FIFO
FSR
01
rxcfLevel
21:18 Indicates number of words present in Rx Control FIFO
FSR
01
txdfOverrun
22
FSR
01
txcfOverrun
23
FSR
01
rxdfUnderrun
24
FSR
01
rxcfOverrun
25
15:9 Rx Data FIFO trigger level sets the number of words above which
causes the Rx Data FIFO interrupt and flag
Indicates number of words present in Tx Data FIFO
Too many words were written to the Tx Data FIFO - the bit can be
cleared using txdfOverClr in the FCR.
Too many words were written to the Tx Control FIFO - the bit can be
cleared using txcfOverClr in the FCR.
Too many words were read from the Rx Data FIFO - the bit can be
cleared using rxdfUnderClr in the FCR.
Too many words were written to the Rx Control FIFO - the bit can be
cleared using rxcfOverClr in the FCR.
Table 7: FIFO Register (FCR & FSR) Description
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6.3 Miscellaneous (RF,AFE,etc) Control Registers

The Miscellaneous Control Register (MCR) contains various control bits for the Analog
Front End (AFE) and external txEn/rxEN operation.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
dacPd_n
MCR
13
R/W
MCR
13
R/W
0 DAC powered-down
MCR
13
R/W
1 DAC enabled
MCR
13
R/W
MCR
13
R/W dac2sCmpSel
*** Inverter required on output of DAC_PD as polarity on DAC is

opposite of the above
This bits select the numeric format for the DAC output
MCR
13
R/W
MCR
13
R/W
MCR
13
R/W
MCR
13
R/W
0 ADC powered-down
MCR
13
R/W
1 ADC enabled
MCR
13
R/W adc2sCmpSel
MCR
13
R/W
0 Offset binary
MCR
13
R/W
1 Twos complement
MCR
MCR
MCR
MCR
13
13
13
13
R/W
R/W
R/W
R/W
adcOutEn_n
overrideEn
MCR
13
R/W
txEn
If OverrideEn = 1, the tx_en output will follow the state of this bit
MCR
MCR
13
13
R/W
R/W
rxEn
trSwEn
1
1
7
8
If OverrideEn = 1, the rx_en output will follow the state of this bit
If OverrideEn = 1, the tr_sw output will follow the state of this bit
MCR
13
R/W
fddSel
MCR
MCR
MCR
13
13
13
R/W
R/W
R/W
reserved
FDD/TDD Mode Select - controls the operation of rx_en and tx_en

outputs as long as en_override = 0.
0 TDD Mode
1 FDD Mode
Reserved
MCR
13
R/W bandgapPd_n
MCR
13
R/W
MCR
13
R/W
MCR
13
R/W
MCR
13
R/W
0 voltage reference powered-down
MCR
13
R/W
1 voltage reference enabled
MCR
13
R/W adcDacClkEn_n
MCR
13
R/W
0 fe_clk is driven to the ADCs and DACs
MCR
13
R/W
1 fe_clk is not driven to the ADCs and DACs
Description
DAC power down
0 Offset binary
1 Twos complement
adcPd_n
10
11
ADC power down
This bits select the numeric format for the ADC output
ADC Output Enable

0 Outputs enabled
1 Outputs set to 0
Override Enable turns off the automatic rx_en, tx_en output logic
and causes the state of the rx_en and tx_en signals to follow the
state of the rxEn and txEn bits in this register.
Bandgap reference power down

0 bandgap reference powered-down
1 bandgap reference enabled
vrefPd_n
12
13
Voltage reference power down
Enables fe_clk to be driven to the ADCs and DACs.
Table 8: Miscellaneous Control Register (MCR) Description
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The Delay Timer Control Register (DTCR) allows programmable delays to be specified
for controlling the relative timing of the rx_en, tx_en and tr_sw outputs. The exact
operation of rx_en and tx_en depends on whether the modem is in TDD mode or FDD
mode and the status of the override signals from the registers and external logic.
FDD/TDD Mode selection is accomplished through the tddSel bit in the MCR. The
operation of tr_sw is independent of TDD/FDD mode.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
9:0
Description
DTCR0
14
R/W
txStartDelay
10
DTCR0
14
R/W
txStopDelay
10
19:10 time in samples from end of data being sent to the interpolating filter
until tx_enable active
DTCR0
14
R/W
txRxDelay
10
29:20 TDD Mode only - time in samples from tx_enable_inactive to rx_en

active
DTCR1
15
R/W
rxStartDelay
10
DTCR1
15
R/W
trSWDelay
10
9:0
time in samples from rx_en active to data being sent to the

interpolating filter
FDD Mode only - time in samples from rx_en active to samples

being taken from the decimating filter
19:10 time in samples from tx_en active to tr_sw active
Table 9: Delay Timer Control Register (DTCR) Description
A diagram of the relative timing of rx_en, tx_en and tr_sw is shown in Figure 7 for TDD
operation. It is assume that the override and any external gating signals are not active.
Note that the timing of rx_en is fixed relative to tx_en in this mode. The delay from
tx_en going high to data output is specified by txStartDelay. During this time zeros are
transmitted. It is assumed that the Tx Control Word is written to the FIFO at least
txStartDelay before the data is actually required to be transmitted. The delay from Tx_en
going low to Rx_en high is specified by txRxDelay. In addition, the delay from the end
of Transmit Data to tx_en low is specified by txStopDelay. This allows a programmable
number of zeros to be output by the transmitter before it is shut off.
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rx_en
tx_en
txRxDelay
Tx Data from Phy
txStartDelay
txStopDelay
tx_en
tr_sw
trSwDelay
Figure 7: rx_en, tx_en & tr_sw timing: TDD Mode

A diagram of the timing for rx_en and tx_en is shown in Figure 8 for FDD operation.
Note that the timing of rx_en is independent of tx_en in this mode. The delay from tx_en
going high to data output is specified by txStartDelay. During this time zeros are
transmitted. tr. The delay from the end of Transmit Data to tx_en low is specified by
txStopDelay. This allows a programmable number of zeros to be output by the
transmitter before it is shut off. For rx_en, the time, rxStartDelay, from the rising edge of
rx_en going high to the actual frame time that reception of data starts can be set. This
allows the RF receiver to be turned on prior to the time when the OFDM receiver is
actually enabled. It is assumed that the Rx Control Word is placed in the FIFO at least
rxStartDelay before the time at which reception of data actually occurs.
rx_en
rxStartDelay
tx_en
Tx Data from Phy
txStartDelay
txStopDelay
Figure 8: rx_en/tx_en timing: FDD Mode
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The delays are specified in terms of the number of samples (1 OFDM Symbol = 319
samples) through a 10-bit register in the DTCR. Note that the delay times are dependent
on the channel bandwidth of the modem and should be calculated accordingly. A 10-bit
delay timer range provide up to 38 us delay with 0.037 us resolution at 20 MHz channel
bandwidth and 484 us delay with 0.47 us resolution at 1.5 MHz channel bandwidth.
Internal signals, rx_enable and tx_enable are gated by external control logic according to
the diagram in Figure 9 in order to produce the rx_en and tx_en outputs. The internal
signals rx_enable and tx_enable have the same timing and functionality as described in
above for rx_en and tx_en. Three input signals; Lock Detect (Active High) lock_det,
Lock Detect (Active Low) lock_det_n and RF Enable rf_enable are used to gate the
enable signals. In addition the override logic is also shown.
MCR.overridEn
MCR.txEn
tx_enable (internal)
Sel
In1
Out
In0
tx_en
Sel
In0
Out
In1
rx_en
Sel
In0
Out
In1
tr_sw
lock_det
rf_enable
ld_n
rx_enable (internal)
MCR.rxEn
tr_sw (internal)
MCR.trSw
Figure 9: rx_en, tx_en & tr_sw control logic
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6.4 Interrupts
The WMAN_PHY generates an active low interrupt, INTB, to the ARC. The PHY
interrupt sources are enabled through the Interrupt Enable Register or IER. The Interrupt
Register (IR) provides the status of the interrupt after it has been sampled. The Interrupt
Information Register (IIR) provides the status of the interrupt before it has been sampled
and can be used to monitor the states of level-sensitive interrupts. The Interrupt Clear
Register (ICR) is used to clear the sampled interrupts.
Register Addr
Name
(hex) R/W
IER
06
R/W
IER
06
IER
Field
# of
Name
Bits Slice
txdfTrigEn
Description
Setting this bit to 1 enables the Tx Data FIFO Trigger interrupt Tx

FIFO data has fallen below the trigger threshold
R/W txdfUnderrunEn
Setting this bit to 1 enables the Tx Data FIFO Underrun interrupt

Phy has attempted to read data but no data was present
06
R/W
txcfEmptyEn
Setting this bit to 1 enables the Tx Control FIFO Empty interrupt
IER
06
R/W
rxdfTrigEn
Setting this bit to 1 enables the Rx Data FIFO Trigger interrupt Rx

FIFO data has exceeded the trigger threshold
IER
06
R/W rxdfOverrunEn
Setting this bit to 1 enables the Rx Data FIFO Overrun interrupt Phy
has attempted to write data to FIFO but FIFO was full
IER
06
R/W
Setting this bit to 1 enables the Rx Control FIFO Empty interrupt
IER
06
R/W txBurstDoneEn
Setting this bit to 1 enables the transmit burst done interrupt
IER
06
R/W
scramErrorEn
Setting this bit to 1 enables the tx scrambler underflow error interrupt
IER
06
R/W rxBurstDoneEn
Setting this bit to 1 enables the receiver burst done interrupt
IER
06
R/W
Setting this bit to 1 enables the receiver sync done interrupt
IER
06
R/W pilotUpdateEn
10
Setting this bit to 1 enables the receiver pilot update interrupt
IER
06
R/W
rsUpdateEn
11
Setting this bit to 1 enables the receiver Reed Solomon error update
interrupt
IER
06
R/W
berUpdateEn
12
Setting this bit to 1 enables the receiver Viterbi bit error rate update
interrupt
IER
06
R/W
fti0En
13
Setting this bit to 1 enables Frame Timer Interrupt 0
IER
06
R/W
fti1En
14
IER
06
R/W
fti2En
15
IER
06
R/W
fti3En
16
IER
06
R/W
fti4En
17
IER
06
R/W
fti5En
18
IER
06
R/W illegalAccessEn
19
Setting this bit to 1 enables the illegal access interrupt
IER
06
R/W
20
Setting this bit to 1 enables a pulse to be output on the ft_int pin

everytime the conditions programmed in FTINT0 are satisfied.
rxcfEmptyEn
syncDoneEn
ftIntEn
Table 10: Interrupt Enable Register (IER) Description
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The Interrupt Status Register or ISR provides the status of all interrupts, enabled or not.
Register Addr
Name (hex) R/W
Field
Name
# of
Bits
Slice
Description
Tx Data FIFO Trigger interrupt interrupt is set to 1 when the

number of words in the Tx Data FIFO falls below the trigger
threshold. The interrupt register can be cleared by writing a 1 to this
location in the ICR. The interrupt source is cleared by writing
sufficient data to the FIFO so that the trigger threshold is met or
alternatively resetting the FIFO
Tx Data FIFO Underrun interrupt this interrupt is set to 1 when the
phy has attempted to read data from the Tx Data FIFO and no data
was present - use ICR to clear
Tx Control FIFO Empty Interrupt this interrupt is set to 1 when the
Tx Control FIFO is empty. The interrupt register can be cleared by
writing a 1 to this location in the ICR. The interrupt source is cleared
by writing data to the FIFO
Rx Data FIFO Trigger interrupt this interrupt is set to 1 when the
number of words in the Rx Data FIFO exceeds the trigger threshold.
The interrupt register can be cleared by writing a 1 to this location in
the ICR. The interrupt source can be cleared by reading data from
the Rx FIFO so that the number of words is below the trigger
threshold or alternatively by resetting the FIFO
Rx Data FIFO Overrun interrupt this interrupt is set to 1 when the
phy has attempted to write data to the Rx Data FIFO and the FIFO
was full - use ICR to clear
Rx Control FIFO Empty Interrupt this interrupt is set to 1 when the
Rx Control FIFO is empty. The interrupt register can be cleared by
writing a bit to this location in the ICR. The interrupt source is
cleared by writing data to the FIFO
Transmit Burst Done Interrupt Status this interrupt is set to 1 when
a burst from the transmitter has been sent. The sequence number
of the burst (burstSeqNum) is reported back in the Tx Status
Register (TSR). This interrupt can be cleared by writing a 1 to the
ICR at this bit location.
Transmit Scrambler Error Interrupt Status this interrupt is set to 1
when a scrambler error has been detected. The sequence number
of the burst with the error (ScramSeqNum) is reported back in the Tx
Status Register (TSR). This interrupt can be cleared by writing a 1 to
the ICR at this bit location.
Recieve Burst Done Interrupt Status this interrupt is set to 1 when
a burst has been received by the receiver. The sequence number of
the burst (burstSeqNum) is reported back in the Rx Status Register
(RSR0). This interrupt can be cleared by writing a 1 to the ICR at
this bit location.
Recieve Sync Done Interrupt Status this interrupt is set to 1 when
the receiver has completed a synchronizing search and has updated
the sync status registers. The results of the search can be read
from RSR1 - RSR4. This interrupt can be cleared by writing a 1 to
the ICR at this bit location.
Recieve Pilot Update Interrupt Status this interrupt is set to 1 when
the receiver has updated the pilot status registers. The results can
be read from RSR5 and RSR6. This interrupt can be cleared by
writing a 1 to the ICR at this bit location.
Recieve Reed Solomon Update Interrupt Status this interrupt is set
to 1 when the number of errors corrected by the Reed Solomon
decoder has been updated. The results can be read from RSR7.
This interrupt can be cleared by writing a 1 to the ICR at this bit
location.
ISR
08
txdfTrigInt
ISR
08
txdfUnderrunInt
ISR
08
txcfEmptyInt
ISR
08
rxdfTrigInt
ISR
08
rxdfOverrunInt
ISR
08
rxcfEmptyInt
ISR
08
txBurstDoneInt
ISR
08
scramErrorInt
ISR
08
rxBurstDoneInt
ISR
08
syncDoneInt
ISR
08
pilotUpdateInt
10
ISR
08
rsUpdateInt
11
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ISR
08
berUpdateInt
12
Recieve Bit Error Rate Update Interrupt Status this interrupt is set
to 1 when the soft bit error rate from the Viterbi decoder is updated.
The results can be read from RSR7. This interrupt can be cleared
by writing a 1 to the ICR at this bit location.
ISR
08
ISR
08
fti0Int
13
Frame Timer Interrupt 0 Status use ICR to clear
fti1Int
14
ISR
08
ISR
08
fti2Int
15
fti3Int
16
ISR
ISR
08
fti4Int
17
08
fti5Int
18
ISR
08
illegalAccessInt
19
Illegal Access Interrupt Status this interrupt is set to 1 when an

access to an undefined register address is detected or if a write
operation is performed to a read-only register. This interrupt can be
cleared by writing a 1 to the ICR at this bit location.
Table 11: Interrupt Register (ISR) Description
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The Interrupt Register or IR provides the status of all enabled interrupt sources.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
IR
07
txdfTrigSt
IR
07
txdfUnderrunSt
IR
07
txcfEmptySt
IR
07
rxdfTrigSt
IR
07
rxdfOverrunSt
IR
07
rxcfEmptySt
IR
07
txBurstDoneSt
IR
07
scramErrorSt
IR
07
rxBurstDoneSt
IR
07
syncDoneSt
IR
07
pilotUpdateSt
10
IR
07
rsUpdateSt
11
IR
07
berUpdateSt
12
IR
07
fti0St
13
IR
07
fti1St
14
IR
07
fti2St
15
IR
07
fti3St
16
IR
07
fti4St
17
IR
07
fti5St
18
IR
07
illegalAccessSt
19
R
R
Description
Status of the signal that generates the txdfTrigInt if the interrupt is
enabled.
Status of the signal that generates the txdfUnderrunInt if the
interrupt is enabled.
Status of the signal that generates the txcfEmptyInt if the interrupt is
enabled.
Status of the signal that generates the rxdfTrigInt if the interrupt is
enabled.
Status of the signal that generates the rxcfEmptyInt if the interrupt is
enabled.
Status of the signal that generates the txBurstDoneInt if the interrupt
is enabled.
Status of the signal that generates the rxBurstDoneInt if the interrupt
is enabled.
Status of the signal that generates the syncDoneInt if the interrupt is
enabled.
Status of the signal that generates the pilotUpdateInt if the interrupt
is enabled.
Status of the signal that generates the rsUpdateInt if the interrupt is
enabled.
Status of the signal that generates the berUpdateInt if the interrupt is
enabled.
Status of the signal that generates the fti0Int if the interrupt is
enabled.
enabled.
enabled.
enabled.
enabled.
enabled.
Status of the signal that generates the illegalAccessInt if the
Table 12: Interrupt Register (IR) Description
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The Interrupt Information Register provides information on level based interrupts at the
point before the interrupt is sampled and fed to the ISR. This allows level based interrupt
sources to be monitored directly.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
txdfTrigInf
Description
IIR
09
State of the signal feeding the Tx Data FIFO Trigger interrupt
IIR
09
reserved
Reserved
IIR
09
txcfEmptyInf
State of the signal feeding the Tx Control FIFO Empty Interrupt
IIR
09
rxdfTrigInf
State of the signal feeding the Rx Data FIFO Trigger interrupt
IIR
09
reserved
Reserved
IIR
09
rxcfEmptyInf
State of the signal feeding the Rx Control FIFO Empty Interrupt
Table 13: Interrupt Information Register (IIR) Description
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The Interrupt Clear Register allows interrupts and interrupt status flags in the Interrupt
Status Register to be cleared. The interrupts are cleared by writing a 1 to the specified bit
location. The ICR is self-clearing so if a bit is set high it will automatically be cleared
after it has been written.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
ICR
0A
txdfTrigClr
Setting this bit to 1 clears the Tx Data FIFO Trigger interrupt Tx

FIFO data has fallen below the trigger threshold
ICR
0A
txdfUnderrunClr
Setting this bit to 1 clears the Tx Data FIFO Underrun interrupt Phy
has attempted to read data but no data was present
ICR
0A
txcfEmptyClr
Setting this bit to 1 clears the Tx Control FIFO Empty interrupt
ICR
0A
rxdfTrigClr
Setting this bit to 1 clears the Rx Data FIFO Trigger interrupt Rx

FIFO data has exceeded the trigger threshold
ICR
0A
rxdfOverrunClr
Setting this bit to 1 clears the Rx Data FIFO Overrun interrupt Phy
has attempted to write data to FIFO but FIFO was full
ICR
0A
rxcfEmptyClr
Setting this bit to 1 clears the Rx Control FIFO Empty interrupt
ICR
0A
txBurstDoneClr
Setting this bit to 1 clears the transmit burst done interrupt
ICR
0A
scramErrorClr
Setting this bit to 1 clears the tx scrambler underflow error interrupt
ICR
0A
rxBurstDoneClr
Setting this bit to 1 clears the receiver burst done interrupt
ICR
0A
syncDoneClr
Setting this bit to 1 clears the receiver sync done interrupt
ICR
0A
pilotUpdateClr
10
Setting this bit to 1 clears the receiver pilot update interrupt
ICR
0A
rsUpdateClr
11
Setting this bit to 1 clears the receiver Reed Solomon error update
interrupt
ICR
0A
berUpdateClr
12
Setting this bit to 1 clears the receiver Viterbi bit error rate update
interrupt
ICR
0A
fti0Clr
13
Setting this bit to 1 clears Frame Timer Interrupt 0
ICR
0A
fti1Clr
14
ICR
0A
fti2Clr
15
ICR
0A
fti3Clr
16
ICR
0A
fti4Clr
17
ICR
0A
fti5Clr
18
ICR
0A
illegalAccessClr
19
Setting this bit to 1 clears the illegal access interrupt
R
R
Table 14: Interrupt Clear Register (ICR) Description
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6.5 Frame Timer:

An OFDM frame timer is provided as a reference time base for the WMAN_Phy. The
periodicity of the frame timer is specified through three parameters as follows:
ftFrameLength the symbol value at which the frame timer will wrap
ftCpLength the cyclic prefix length used within the OFDM symbol
frameFinal the number of samples in the final symbol of the frame
The ftFrameLength symbol field is an 11-bit value which allows the maximum frame size
of 20 msto be achieved. The number of samples within each OFDM symbol varies
according to the cyclic prefix length specified in ftCPlength. The number of samples
depends on the cyclic prefix length. A table showing the correspondence between
ftCpLength and G, the ratio of cylic prefix time to useful time is shown in. .
G
ftCpLength
1/32
8
1/16
16
1/8
32
1/4
64
Table 15: Cyclic Prefix Lengths
In order to provide precise 2.5 ms to 20 ms frame sizes an additional frameFinal field
register is provided. This field specifies the final number of samples in the last partial
symbol of a frame. It is required due to the fact that there is not normally an integer
number of OFDM symbols in the required 2.5 to 20 ms frames due to the varying
channel bandwidth and cyclic prefix lengths of the target systems. In order to generate
the proper ftFrameLength and frameFinal register values for each combination of channel
bandwith, frame size and cyclic prefix length the following formulas and examples are
provided:
n = sampling factor
BW = nominal channel bandwidth (Hz)
Nfft = FFT size i.e 256
ft = frame time (seconds)
G = ratio of cyclic prefix time to useful time
Fs = sample frequency
Samplesperframe = number of samples per frame
Samplespersymbol = number of samples per symbol
fs = floor(BW*n/0.008)*0.008;
samplesperframe = fs*ft;
samplespersymbol = Nfft + G*Nfft;
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ftFrameLength = floor(samplesperframe/(Nfft + G*Nfft));

frameFinal = samplesperframe - ftFrameLength*samplespersymbol;
The following Matlab script shows an example calculation for 1.25 MHz channel
bandwidth with G= 1/32 and a 2.5 msec frame time:
n = 144/125;
BW = 1.25e6;
ft = 2.5e-3;
Nfft = 256;
G = 1/32;
fs = floor(BW*n/0.008)*0.008;
samplesperframe = fs*ft;
samplespersymbol = Nfft + G*Nfft;
ftFrameLength = floor(samplesperframe/(Nfft + G*Nfft));
frameFinal = samplesperframe - ftFrameLength*samplespersymbol;
ftFrameLength
frameFinal
Result:
ftFrameLength =13
frameFinal =168
The status of the frame timer can be read through the ftSample and ftSymbol fields in the
Frame Timer Status Register.
Six internal interrupts are provided to allow programmable frame-timing based interrupts
to the micro controller. The symbol and sample values for each of the frame timer
interrupts are specified through the FTINTR0-5 registers. Operation of these interrupts is
controlled through the interrupt registers.
The frame timer also has an external interrupt, ft_int. This signal uses the timer value
specified for frame timer interrupt 0 in order to generate a periodic pulse based external
interrupt. ft_int is enabled by setting the IER.ftIntEn bit high. . When enabled ft_int will
provide a 160 ns pulse (10 phy_clock cycles @ 100 MHz) whose period is equal to the
frame timer duration. Note that ft_int is not enabled, disabled or affected by the frame
timer 0 interrupt registers.
The frame timer can either be initialized to start at an arbitrary time (BS Mode) or can be
initialized during the Rx synchronization process (SS Mode). The frame timer can be
cleared and reset by setting the ftClr bit in theFTCR. The current value of the frame timer
can be read in the Frame Timer Status Register.
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It is also possible to synchronize or reset the frame timer using the BS_SYNC_IN
external signal. The rising edge of the BS_SYNC_IN signal is detected and used to
provide the reset to the frame timer. An additional output signal, BS_SYNC_OUT, is
also available which gives a 160 ns (10 phy_clock cycles @ 100 MHz) pulse whenever
the frame timer is reset, whether through external or internal means.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
FTCR
0B
R/W ftFrameLength
11
10:0 Symbol value at which the frame timer will wrap
FTCR
0B
R/W
ftCpLength
18:11 cyclic prefix length 8-bit number that specifies the CP length i.e 0,
8, 16, 32, 64
FTCR
0B
ftClr
FTCR
0B
R/W
frameFinal
10
FTSR
0C
ftSample
8:0
FTSR
0C
ftSymbol
11
19:9 Current value of the symbol field of the frame timer. The maximum
value of symbol field is set using ftFrameLength
FTINTR0
0D
R/W
sampInt0
8:0
FTINTR0
0D
R/W
symInt0
11
19:9 Symbol value at which Frame Timer Interrupt 0 will occur
FTINTR1
0E
R/W
sampInt1
8:0
FTINTR1
0E
R/W
symInt1
11
FTINTR2
0F
R/W
sampInt2
8:0
FTINTR2
0F
R/W
symInt2
11
FTINTR3
10
R/W
sampInt3
8:0
FTINTR3
10
R/W
symInt3
11
FTINTR4
11
R/W
sampInt4
8:0
FTINTR4
11
R/W
symInt4
11
FTINTR5
12
R/W
sampInt5
8:0
FTINTR5
12
R/W
symInt5
11
19
Clear frame timer by setting this bit high - this bit is self-clearing
28:20 Number of samples in the final symbol of the frame. <9.0> unsigned
Current value of the sample field of the frame timer. The maximum
value of the sample field is (255 + ftCpLength) before it wraps to
zero.
Sample value at which Frame Timer Interrupt 0 will occur
Table 16: Frame Timer Register (FTR) Description
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6.6 Preamble and AGC Memory Interface

The WMAN_PHY contains separate memories for the Receive and Transmit Preamble
patterns and the AGC output translation table. The use of Preamble memories allows the
phy to be programmable in terms of which preamble patterns it transmits and receives.
This feature allows flexibility in upgrading the preamble patterns should the standards
change and also allows proprietary preamble patterns to be applied. The AGC output
translation table allows the internal 8-bit monotonic agc output to be translated to a
programmable 10-bit field
The separate Rx and Tx preamble memories are defined as follows:
Rx Preamble memory
Size:
Bit Definition:
Tx Preamble memory
Size:
Bit Definition:
256 x 8 bits
[7:4] Subchannel Preamble
[3:0] Preamble 128
256 x 12 bits
[11:8] - Preamble 64
[7:4] - Subchannel Preamble
[3:0] - Preamble 128
Each 4-bit memory field consists of two, two-bit fields in signed integer format which
represent the real and imaginary components of the frequency domain represenation of
the preamble. Typical values are +1, -1 and 0 for each of the fields. The default values of
Preamble 64, Preamble 128 and Subchannel Preamble are shown in Appendix A.
The AGC translation memory is defined as follows:
Tx Preamble memory
Size:
256 x 10 bits
Bit Definition:
[21:12] - AGC Value(9:0)
Each field corresponds to a 10-bit mapping a particular 8-bit agc input.
The memories are written via a simple register interface. The Preamble Memory Control
Register (PMCR) is used to set up and initiate the filling of the preamble memory. In
order to write to either the Rx or Tx preamble memory, an enable bit (rxMemEn or
txMemEn) is set in the PMCR. In order to write to the AGC translation memory the
agcMemEn bit must be set in the PMCR. Note that it is possible to write to all three
preamble memories in parallel by simultaneously setting the all the enable bits high. In
this case the lower 8 bits (Subchannel Preamble and Preamble 128) of the Rx and Tx
preamble memories would have to be the same since the fields are shared in the PMDR.
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An address counter is used to drive the address of the preamble and agc translation
memories. The address counter is reset to 0 by setting the addCntRst bit in the PMCR
high then low. Subsequent writes will cause the address counter to automatically
increment. The data for the memories is written to from the Preamble Memory Data
Register (PMDR).
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
rxMemEn
PMCR
16
R/W
PMCR
16
R/W
0 Writes to to the receiver preamble memory are inhibited
PMCR
16
R/W
1 Writes to the receiver preamble memory are enabled
PMCR
16
R/W
PMCR
16
R/W
0 Writes to to the transmitter preamble memory are inhibited
PMCR
16
R/W
1 Writes to the transmitter preamble memory are enabled
PMCR
16
PMCR
16
PMCR
16
R/W
PMCR
16
R/W
0 Writes to to the AGC translation memory are inhibited
PMCR
16
R/W
1 Writes to the AGC translation memory are enabled
PMDR
17
wrMemVal
12
21:0 The value written to this address is applied to the selected Rx or Tx

preamble memory. The address counter is incremented after the
operation.
PMSR
18
addrStatus
7:0
txMemEn
addCntRst
Description
Rx Preamble Memory Enable
Tx Preamble Memory Enable
Address Counter Reset

Writing a 1 resets the 8-bit memory address counter. This bit clears
itself after the operation completes.
agcMemEn
AGC Translation Memory Enable
Address Counter Status Read only value which reflects the value
of the address counter
Table 17: Preamble Memory Control (PMCR) and Data Register (PMDR) Description
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7 Transmitter
7.1 Overview
The WMANY_Phy transmitter takes uncoded blocks of data and then scrambles, encodes
and modulates the data according to the 802.16 specification. The main blocks in the
transmitter are:
Transmit Channel Encoder consisting of:
Scrambler
Encoder: Reed Solomon Encoder
Serial Buffer
Convolutional Encoder
Puncturer
Interleaver
Modulator
IFFT
Transmit Front End consisting of:
Tx Buffer
Tx Interpolation Filter
Tx Test Tone Generator
Tx Analog Front End Interface
A block diagram of the transmitter is shown in Figure 10.
WMAN_PHY Transmitter
Tx Channel
Encoder:
Tx Data
Tx Front End
Scrambler
Puncturer
Modulator
Tx Control
256-pt
IFFT
Tx
Buffer
Int.
Filter
AFE Tx
Interface
Tx Status
Registers
Test
Circuitry
Tx Control
Registers
Encoder
Interleaver
Figure 10: Transmitter Block Diagram
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7.2 Transmitter Control Word and Register Description

Field
# of
Name
Word
Word
Name
Bits Slice
tx_cntl0
start
11
10:0
Burst start time (symbol number)
rate
13:11
Modulation and Code Rate Selection:
Description
000 BPSK, R=1/2

001 BPSK, R=
010 QPSK, R=1/2
011 QPSK, R=
100 QAM 16, R=1/2
101 QAM 16, R=3/4
110 QAM 64, R=2/3
111 QAM 64, R=3/4
tx_cntl1
length
18
31:14
Number of data bytes to transmit.
seqNum
3:0
Control sequence number Tag which can be used to identify a specific

control word
preType
5:4
Transmit preamble type:

00 No preamble
01 Short preamble (P128)
10 Long preamble (P64 + (P128 or Psub))
11 Reserved
midType
7:6
Burst midamble type (repetition interval)

00 No midamble
01 8 symbol midamble repetition interval
subChan
12:8
Specifies subchannel index

0000 16 subchannels with no RS encoding
00001 11111 as per Table 185(D2)
scramEn
13
Turn on/off scrambling for the burst

0 scrambler off
1 scrambler on
scramInit
14
Initialize scrambler at start of burst if set to 1
scramSeed
15
29:15
Transmit Scrambler Seed
intEn
30
Transmit Burst Interrupt Enable

0 Interrupt is disabled
1 - Enables an interrupt after the transmit burst has been sent. Note,
interrupt must still be enabled at IER
Table 18: Transmit Control Word Description
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
txBsSel
Description
TCR0
19
R/W
TCR0
19
R/W
BS/SS Mode Selection for Transmitter
TCR0
19
R/W
TCR0
19
R/W
txRst
TCR0
19
R/W
ifftScale
5:2
Selects number of scaling shifts to be performed in the IFFT on the

transmit data. Expected range is from 0 to 8
TCR0
19
R/W
ifftScalePre
9:6
Selects number of scaling shifts to be performed in the IFFT on the

transmit preamble. Expected range is from 0 to 8.
TCR0
19
R/W
ifftScaleSub
TCR1
1A
R/W
offsetSample
TCR1
1A
R/W
offsetSymbol
11
19:9 Selects number of symbols to offset the frame timer by.
TCR1
1A
R/W
pilotSeed
11
30:20 Pilot seed for initialization at symbol 0.
0 Subscriber Station
1 - Base Station
Transmitter is held in reset when set to 1
13:10 Selects number of scaling shifts to be performed in the IFFT on the

transmit subchannel preamble. Expected range is from 0 to 8.
8:0
Selects number of samples to offset the frame timer by.
Table 19: Transmit Control Register (TCR0,1) Description
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
TSR
1B
BurstSeqNum
3:0
Sequence number which caused txBurstDone Interrupt
TSR
1B
ScramSeqNum
7:4
Sequence number which caused txScramError Interrupt
Table 20: Transmit Status Register (TSR) Description
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7.3 Transmitter Timing

The timing of a transmit burst is normally dictated by the burst start time field in the Tx
Control Word. The TCW.start field gives the frame timer symbol number at which the
burst should be transmitted. A diagram of a transmit burst starting at frame timer symbol
0 is shown in Figure 11.
During ranging a subscriber station may be told by the base station to adjust the timing of
its transmit bursts. In order to accommodate ranging the transmit timing offset registers,
TCR1.offsetSymbol and TCR1.offsetSample, are provided. These allow all transmit
bursts to be offset by a integer number of symbols and samples. A diagram of a transmit
burst with TCR1.offsetSymbol =1 and TCR1.offsetSample =90 is shown in Figure 12.
2.5 ms Frame
Frame Timer
218
Pre
Tx Data from Phy
217
Data
Transmit Control Word issued to

generate preamble at symbol 0
TCR1.offsetSymbol = 0
TCR1.offsetSample = 0
Figure 11: Transmit Burst Timing no Offset

2.5 ms Frame
Frame Timer
Tx Data from Phy
218
Pre
217
Data
Transmit Control Word issued to

generate preamble at symbol 0
TCR1.offsetSymbol = 1
TCR1.offsetSample = 90
Figure 12: Transmit Burst Timing with Offset
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7.4 Transmit Channel Encoder

7.4.1
Scrambler
The scrambler performs data randomization on each uplink and downlink burst. The
scrambler consists of a 15-bit Linear Feedback Shift Register (LFSR) with feedback
polynomial 1 + x14 + x15. A diagram of the LFSR is shown in Figure 13. The state of the
LFSR is initialized at the start of every allocation. This is accomplished through the
scramInit and seed values of the Tx Control Word. In addition, the Scrambler performs
padding in cases where the amount of data to be transmitted does not make up a complete
OFDM symbol. In theses cases where RS-CC and CC coding is employed, the scrambler
will pad 0xFF to the end of the transmission block allocated with the exception of the last
byte which is reserved for the 0x00 Viterbi tail byte.
3 4
8 9
10 11 12 13 14 15
data out
data in
Figure 13: Scrambler LFSR
7.4.2
Encoder
The Encoder consists of the following blocks:

Reed-Solomon Encoder
Serial Buffer
Convolutional Encoder
Two types of coding are supported: Reed-Solomon + Convolutional Coding RS-CC or
Convolutional Coding CC. The type of coding provided for each symbol of transmit
data is determined by the rate and subChan fields of the Tx Control Word. The block
sizes and code rates used for different modulations are shown in Table 21.
tx_cntl0
rate
Modulation
0000
0001
0010
0011
BPSK
BPSK
QPSK
QPSK
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Uncoded
Block
Size
12
12
24
48
Coded
Block
Size
24
24
48
48
Overall
Coding
Rate
1/2
3/4
1/2
3/4
RS Code
(12,12,0)
(12,12,0)
(32,24,4)
(40,36,2)
CC
Code
Rate
1/2
3/4
2/3
5/6

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Comment
standard compliant
proprietary
standard compliant
standard compliant
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0100
0101
0110
0111
16-QAM
16-QAM
64-QAM
64-QAM
36
72
96
108
96
96
144
144
1/2
3/4
2/3
3/4
(64,48,8)
(80,72,4)
(108,96,6)
(120,108,6)
2/3
5/6
3/4
5/6
standard compliant
standard compliant
standard compliant
standard compliant
Table 21: Block Sizes per Modulation Format

The block descriptions are as follows:
Reed-Solomon Encoder:
The Reed Solomon encoder utilizes an RS(N=255,K=239, T=8) code. The field and
generator polynomials are as follows:
Code Generator Polynomial: g(x) = (x + 0) (x + 1) (x + 2) (x + 2T-1), =02HEX
Field Generator Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
Note, that the RS encoder is bypassed in subchannelization mode.
Serial Buffer:
A buffer is provided to serialize the bytes provided by the RS Encoder into bits.
Convolutional Encoder:
Each RS block is encoded by a binary convolution encoder with rate, R = , and
constraint rate, K=7, according to the generator polynomials, g0 = 133, g1 = 171. The
convolutional encoder produces two bits, X & Y as shown in Figure 14.
X
+
data in
+
Y
Figure 14: Convolutional Encoder
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7.4.3
Puncturer and Interleaver
In order to achieve different code rates, data from the convolutional encoder is punctured.
The puncture patterns used to provide the different rates are shown in . A 1 indicates the
bit is transmitted and a 0 indicates the bit is removed.
Rate
X
Y
1/2
1
1
2/3
10
11
3/4
101
110
5/6
10101
11010
Table 22: Puncture Patterns

Interleaving is performed through a two step permutation of a block of encoded input
data according to formulas defined in the 802.16 specification. The block sizes of the
interleaver depend on the modulation type i.e. BPSK, QPSK, 16-QAM & 64-QAM as
shown in Table 23.
Rate
BPSK
QPSK
16-QAM
64-QAM
16
subchannels
192
384
768
1152
8 subchannel
4 subchannels
2 subchannels
1 subchannel
96
192
384
576
48
96
192
288
24
48
96
144
12
24
48
73
Table 23: Interleaver Block Sizes

The Interleaver block is responsible for insertion of the preamble sequences before the
bits are fed to the Modulator. The preamble sequences are specified in the Preamble
Memory Data Register (PMDR) as described in section 6.6. The determination as to
whether preamble sequences or regular data are to be transmitted is made through the
preType field in the TCW.
In addition, the Interleaver performs the insertion of Pilot subcarriers into each data burst.
A LFSR with polynomial 1 + X9+X11, shown in Figure 15, is used to generate the pilot
sequence wk where k represents the OFDM symbol index. In DL mode the index k
represents the symbol index relative to the beginning of the downlink subframe. In UL
mode the index k represents the symbol index relative to the beginning of the burst. In
Initialization of the LFSR is dependent on whether the phy is in DL or UL mode.
In Dl mode the pilot initilization sequence is 11111111111. In UL mode the pilot
initialization sequence is 10101010101. The pilot initialization sequence is set through
TCR0.pilotSeed.
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3 4
8 9
10 11
wk
Figure 15: Pilot LFSR

The pilots are modulated onto the carriers using BPSK modulation as described below:
DL:
UL:
7.4.4
c-88 = c-38 = c63 = c88 = 1- 2wk and c-63 = c-13 = c13 = c38 = 1- 2wk
c-88 = c-38 = c13 = c38 = c63 = c88 =1- 2wk and c-63 = c-13 = 1- 2wk
Modulator
Data bits from the interleaver are mapped according to constellation diagrams provided in
the 802.16 specification. BPSK, QPSK, 16-QAM and 64-QAM are supported. The
constellation-mapped data is then modulated onto the allocated data subcarriers and
provided to the IFFT.
The Transmit Modulation Register, shown in Table 24, provides programmable scaling
control for the absolute value of a particular modulation constellation. Each 10 bit
register provides a signed <1.9> scale value relative to a +1 transmitted value. In the
case of BPSK, the preamble and pilot modulation constellations, and QPSK the scale
value is applied to the +/-1 output values. In the case of 16-QAM the scale value is
applied to the +/-3 and +/-1 output values. In the case of 64-QAM the scale value is
applied to the +/-7, +/-5, +/-3 and +/-1 output values.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
TMR0
1C
R/W
moduQAM64
10
TMR0
1C
R/W
moduQAM16
10
19:10 Modulation constellation scale value for +1 at QAM 16 - <1.9>

signed
TMR0
1C
R/W
moduQPSK
10
29:20 Modulation constellation scale value for +1 at QPSK - <1.9> signed
TMR1
1D
R/W
moduP64
10
TMR1
1D
R/W
moduP128
10
19:10 Modulation constellation scale value for preamble 128 - <1.9>

signed
TMR1
1D
R/W
moduPSub
10
29:20 Modulation constellation scale value for preamble subchannel <1.9> signed
REV 1.13
9:0
Description
9:0
Modulation constellation scale value for +1 at QAM 64 - <1.9>

signed
Modulation constellation scale value for preamble 64 - <1.9> signed

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TMR2
1E
R/W
moduPilot
10
TMR2
1E
R/W
moduBPSK
10
9:0
Modulation constellation scale value for pilot - <1.9> signed
19:10 Modulation constellation scale value for +1 at BPSK - <1.9> signed
Table 24: Transmit Modulation Register (TMR0-2) description

The scaling provided in the Transmit Modulation Registers is designed to provide the
normalization, c, required by the 802.16 specification to achieve equal average power for
all modulation types. The actual scaling level for each modulation constellation is a
combination of the normalization factor, c, and a backoff factor, bkoff used for prescaling of the IFFT input to reduce the potential for saturation and ensure the maximum
input value is less than 1.
An example showing the setting of the scale value for a
particular modulation constellation is shown below:
moduQAM64 = c * bkoff = (1/sqrt(42)) *0.92 = 0.136054
Typical scale control values for each modulation type are shown in Table 25 for reference
purposes.
Field Name
bkoff
Quantized Value
moduQAM64
moduQAM16
moduQPSK
moduP64
moduP128
moduPSub
moduPilot
moduBPSK
1/sqrt(42)
1/sqrt(10)
1/sqrt(2)
1
1/sqrt(2)
1/sqrt(2)
1
1
0.92
0.92
0.92
0.92
0.92
0.92
0.92
0.92
0.142578125
0.291015625
0.650390625
0.919921875
0.650390625
0.650390625
0.919921875
0.919921875
Table 25: Typical Transmit Modulation Scale Values
7.5 IFFT
The IFFT block is a radix-2 256-point pipelined FFT processor. It performs a 256-point
complex Inverse Fast Fourier Transform on the modulated subcarriers provided by
Modulator. The input and output precision of the IFFT is 10-bits. Note that the IFFT
block is not resource shared with the receiver
Two scaling parameters are provided in the IFFT. They are ifftScale which scales the
transmitted data and ifftScalePre which scales the preamble. Both values are
programmed through the TCR and are 4-bits with the maximum scale value being limited
to 8. The scale value basically controls a right shift on the decimal point of the IFFT
output and allows the range of the IFFT output to be increased. An example is shown in
Table 26 for a signal with <1.9> input precision. The default scale values were
determined through simulations of various typical 802.16 transmit bursts with the
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intention of achieving less than ?? saturation/clipping events in ??. The default values for
ifftScale and ifftScalePre has been set to 6 and 5 respectively.
Scale
Value
0
1
2
3
4
5
6
7
8
Input
Precision
1.9
Output
Precision
<1.9>
<2.8>
<3.7>
<4.6>
<5.5>
<6.4>
<7.3>
<8.2>
<9.1>
Table 26: IFFT Scaling Example
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7.6 Transmit Front End

7.6.1
Tx Buffer
The Tx Buffer is performs Cyclic Prefix insertion on the data output by IFFT in order to
form a proper OFDM symbol.. Cyclic prefix lengths of 1/64, 1/32, 1/16 and 1/8 are
supported.
7.6.2
Interpolation Filter
The interpolation filter is a 39-tap halfband filter with approximately 60 dB stopband

attenuation and 0.01 dB ripple. The passband corner lies at 0.42 Fs. The frequency
response is shown in Figure 16.
Magnitude Response (dB)
20
-20
-40
-60
)
B
d(
e
d
uti
n
g
a
M
-80
-100
-120
-140
-160
-180
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Frequency ( rad/sample)
0.7
0.8
0.9
Figure 16: Frequency Response of 39-tap Halfband Tx Interpolation Filter

7.6.3
Tx FIFO
The Tx FIFO resolves the asynchronous clock domain boundary between the fixed 100
MHz Phy clock (phy_clk) and the variable rate AFE clock (fe_clk). The transmitter has
been designed such that the Tx FIFO pulls data as required to meet the ADC clock rate.
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7.7 Transmit Test Circuitry

Test tone generation allows a variable frequency test tone to be provided on the output of
the transmit I&Q ADCs. Test Tone 0 is a sinusoid with frequency ranging from 250 kHz
to 5 MHz in steps of 250 kHz. Test Tone 1 is a sinusoid with frequency ranging from
500 kHz to 10 MHz in steps of 500 kHz. . The Transmit Test Register (TTR) is used to
enable/disable the tones and also control the I and Q relationships of the two tones.
Note that only one tone or the other is enabled at any time.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
sbSel
TTR
1F
R/W
TTR
1F
R/W
00 - Reserved
TTR
1F
R/W
01 - Lower Sideband (I=Sin, Q=Cos)
TTR
1F
R/W
10 - Upper Sideband (I=Cos, Q Sin)
TTR
1F
R/W
11 - Dual Sideband (I=Sin, Q=Sin)
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W step500kHzSel
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
ttfSel
9:4
Selects the frequency of the test tones - see Table 21 for tfSel
selection table
TTR
1F
R/W
adLpbkEn
10
Enables Analog/Digital Loopback of Rx I&Q data to TX I&Q data.

When this loopback is enabled, analog I&Q signals can be applied
to the Rx I&Q ports and fed back to the TX I&Q ports
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
R/W
TTR
1F
0 - data from the tx_core
TTR
1F
1 - data from the TDR register
testToneEn
1:0
Description
Selects the sidebands which are generated
Enables test tones to be generated

0 Tone Generator disabled
1 Tone Generator enabled
Selects between 250 kHz and 500 kHz step size for the tone
generator
0 f=250 kHz to 5 Mhz in 250 kHz steps
1 f=500 kHz to 10 Mhz in 500 kHz steps
0 Loopback disabled
1 - Loopback enabled
digLpbkEn
11
Enables Digital Loopback of Tx I&Q digital outpu data to Rx I&Q

inputs
0 Digital Loopback Disabled
1- Digital Loopback Enabled
txTdrRegsSel
12
Selects source of data to be applied to the I & Q DACs
Table 27: Transmit Test Register (TTR) Description
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
TDR
20
R/W
Idac
10
9:0
In-phase DAC value value to placed on the output of the I DAC

when txOutRegsSel = 1
TDR
20
R/W
Reserved
15:10
TDR
20
R/W
Qdac
10
25:16 Quadrature DAC value value to be placed on the output of the Q

DAC when txOutRegsSel = 1
Table 28: Transmit DAC Register(TDR) Description

Test Tone
Frequency
Selection
(ttfsel integer)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Test Tone
Frequency
Selection
(ttfsel(5:0) Hex)
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x10
0x11
0x12
0x13
0x14
Output Frequency,
250 kHz step
Output Frequency
500 kHz step
250 kHz
500 kHz
750 kHz
1000 kHz
1250 kHz
1500 kHz
1750 kHz
2000 kHz
2250 kHz
2500 kHz
2750 kHz
3000 kHz
3250 kHz
3500 kHz
3750 kHz
4000 kHz
4250 kHz
4500 kHz
4750 kHz
5000 kHz
500 kHz
1000 kHz
1500 kHz
2000 kHz
2500 kHz
3000 kHz
3500 kHz
4000 kHz
4500 kHz
5000 kHz
5500 kHz
6000 kHz
6500 kHz
7000 kHz
7500 kHz
8000 kHz
8500 kHz
9000 kHz
9500 kHz
10000 kHz
Table 29: Transmit Test Tone Selection Table
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8 Receiver
8.1 Overview
The WMANY_Phy receiver takes sampled data from the AFE and then filters,
synchronizes, demodulates, decodes and descrambles the data according to the 802.16
specification. The main blocks in the transmitter are:
Receive Front End
Rx Analog Front End Interface
Automatic Gain Control (AGC) Wi-Lan Specific
Rx Decimation Filter
Frequency Correction
CP Removal
Synchronization and Automatic Frequency Control (AFC) Wi-Lan Specific
FFT
Timing Correction
Channel Decoder consisting of:
Channel Estimator
Deinterleaver
Depuncturer
Decoder: Viterbi Decoder
Reed-Solomon Decoder
Descrambler
A block diagram of the receiver is shown in Figure 17
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WMAN_PHY Receiver
Rx Channel
Decoder:
Rx Data
Rx Front End
Descrambler Depuncturer
Sync &
AFC
Chanel Est.
Rx Control
Decimation
Filter
AFE Rx
Interface
256-pt
FFT
Rx Status
Registers
Rx Control
Registers
Encoder
Deinterleaver
Timing
Corr.
Frequency
Corr.
AGC
Figure 17: Receiver Block Diagram
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8.2 Receiver Control Word & Register Description

Field
# of
Name
Word
Word
Name
Bits Slice
rx_cntl0
seqNum
3:0
Control Sequence Number
start
11
14:4
Burst start time (symbol number)
rate
17:15
Modulation and Code Rate Selection:
Description
000 BPSK, R=1/2

001 BPSK, R=
010 QPSK, R=1/2
011 QPSK, R=
100 QAM 16, R=1/2
101 QAM 16, R=3/4
110 QAM 64, R=2/3
111 QAM 64, R=3/4
length
11
28:18
Length of burst in symbols
preType
30:29
Receive Preamble Type - Long preamble signals a search for long

preamble will occur. Short preamble means a new channel estimate will be
calculated, No preamble sends the data straight through
00 No preamble
01 Short preamble (P128)
10 Long preamble (P64 + (P128 or Psub))
11 Reserved
rx_cntl1
subChan
4:0
Specifies subchannel index

0000 16 subchannels with no RS encoding
00001 11111 as per Table 185(D2)
scramEn
Turn on/off descrambling for the burst

0 descrambler off
1 descrambler on
scramInit
Initialize descrambler at start of burst

0 dont initialize
1 - initialize
scramSeed
midType
15
2
21:7
23:22
Descrambler seed for initialization

Burst midamble type (repetition interval)
00 No midamble
rx_cntl2
clearTrack
24
Clears the timing and frequency tracking loops at the end of the burst.
intEn
25
Generate an interrupt at end of burst
searchWin
11
10:0
unlockAGC
11
adjustTime
12
Length of time in symbols from the start of the search before searchFailed
is asserted. Needed for contention slots
AGC is locked during a successful search. This bit will unlock the AGC at
the end of the burst
This bit enables adjustment of the frame timer during synchronization
Table 30: Receive Control Word Description
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
RCR0
21
R/W
fftScale
3:0
RCR0
21
R/W
fftScalePre
7:4
RCR0
21
R/W
chnInterpEn
RCR0
RCR0
RCR0
21
21
21
R/W
R/W
R/W
feedFwdEn
RCR0
RCR0
RCR0
21
21
21
R/W
R/W
R/W
rxRst
10
RCR1
22
R/W
demapScale
5:0
RCR1
RCR1
22
22
R/W
R/W
demapK64
demapK16
10
10
RCR2
23
R/W
syncThresh
RCR2
23
R/W
syncMinPwr
15
RCR2
23
R/W
guard
RCR3
RCR3
RCR3
RCR3
RCR3
RCR3
24
24
24
24
24
24
R/W
R/W
R/W
R/W
R/W
R/W
timeEn
timeLoopA
timeLoopB
timeFactor
8
8
12
Description
Selects number of scaling shifts to be performed in the FFT on the

receive data. Expected range is from 0 to 8.
Selects number of scaling shifts to be performed in the FFT on the
receive preamble . Expected range is from 0 to 8.
Enables interpolation between even carriers in the channel
estimation
0 = disable
1 = enable
Enables feed forward correction where the average phase of the
pilot subcarriers is used to adjust the phase on the other subcarriers.
0 = disable
1 = enable
Holds receiver in reset when set to 1
Demapper soft bit scaling factor - <3.3> unsigned value which is

used for prescaling the soft bits.
15:6 Demapper slicing point for QAM64 - <1.9> signed
25:16 Demapper slicing point for QAM16 - <1.9> signed
5:0
Specifies the percentage of power that the matched filter has to

achieve in order to signal a synchronization hit <2.4> unsigned
20:6 Specifies the minimum power that the matched filter has to achieve
in order to signal a synchronization hit - <3.12> unsigned
28:21 Guard time inside of the cyclic prefix - <8.0> unsigned. Guard is
the number of samples of the CP which is included in the OFDM
symbol sent to the FFT
0
Enables timing correction

0 = disable
1 = enable
8:1 Loop filter A coefficient - <1.7> signed
16:9 Loop filter B coefficient - <1.7> signed
28:17 Frequency offset (freqency domain) to timing offset conversion
factor <1.11> signed
Table 31: Receive Control Registers (RCR0-3) Description
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Register Addr
Name (hex) R/W
Field
Name
freqEn
# of
Bits Slice Description
RCR4
RCR4
RCR4
RCR4
25
25
25
25
R/W
R/W
R/W
R/W
P64FreqEn
RCR4
RCR4
RCR4
25
25
25
R/W
R/W
R/W
P128FreqEn
RCR4
RCR4
RCR4
25
25
25
R/W
R/W
R/W
freqFactor
RCR4
25
R/W
pilotAmplitude
RCR5
26
R/W
agcLockTime
RCR5
RCR5
RCR5
26
26
26
R/W
R/W
R/W
agcDelay
agcVal
agcOverrideEn
6
8
1
RCR5
26
R/W
agc6BitSel
RCR5
RCR5
RCR5
RCR5
RCR5
RCR5
RCR5
RCR5
26
26
26
26
26
26
26
26
R/W
agcAvgSel
R/W
R/W
R/W
R/W
R/W agcTableTestEn
R/W
R/W
RCR6
27
R/W
agcOffset
Enables frequency tracking correction

0 = disabled
1 = enabled
1
1 Enables preamble 64 to be used for frequency offset estimation.
Can be used simultaneously with P128FreqEn.
0 = disabled
1 = enabled
1
2 Enables preamble 128 to be used for frequency offset estimation.
Can be used simultaneously with P64FreqEn.
0 = disabled
1 = enabled
8
10:3 Pilot offset (time domain) to frequency offset conversion factor <3.5> signed
10 20:11 Expected amplitude of pilot carriers that is used for the pilot error
calculation - <1.9> signed
8:0 Value of the sync counter at which AGC is locked during a long
preamble search - <9.0> unsigned
14:9 Number of samples between AGC updates - <6.0> unsigned
22:15 AGC value to apply to AGC output - <8.0> unsigned
23 Overrides internally generated AGC output value and outputs
agcVal above
24 Selects 6-bit mode for AGC operation, otherwise 8-bit mode. The
attenuation is incremented in 1 dB steps for 6-bit mode and 1/2 dB
steps for 8-bit mode. The most significant bit of the AGC value is
not used in 6-bit mode so the range is reduced.
26:25 Sets the number of samples to average final agc value.
00 = no averaging
01 = average 2 samples
10 = average 4 samples
11 = reserved
27 Enables test mode where agc outputs attenuation table value.
0 = disabled
1 = enabled
7:0 AGC attenuation offset to apply after AGC lock - <8.0> signed.
Table 32: Receive Control Registers (RCR4-6) Description
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
RSR0
28
burstSeqNum
3:0
RSR0
28
attenuation
11:4 Value of sync attenuation output
Sequence number which caused rxBurstDone interrupt
RSR0
28
syncFifoEmpty
12
Synchronization FIFO has not received any data from the ADC
RSR1
29
syncSeqNum
3:0
Sequence number of the last command that updated the sync status
registers (RSR1 - RSR4) and caused rxSyncDone interrupt
RSR1
29
searchFailed
RSR1
29
p128Time
13:5 Sync counter value of matched filter p128 hit <9.0> unsigned
RSR2
2A
power
29
28:0 Average power over 256 samples of Preamble 128. <3.26>

unsigned
RSR3
2B
phi64
15
14:0 Arctangent of Preamble 64 correlation. <3.12> signed
RSR3
2B
mag64
15
29:15 Magnitude of Preamble 64 correlation. <3.12> unsigned
RSR4
2C
phi128
15
14:0 Arctangent of Preamble 128 correlation. <3.12> signed
RSR4
2C
mag128
15
29:15 Magnitude of Preamble 128 correlation. <3.12> unsigned
RSR5
2D
pilotSeqNum
3:0
RSR5
2D
phiPilot
15
18:4 Angle of the weighted averages of the received pilots after channel
correction <3.12> signed
RSR6
2E
pilotError
20
19:0 Noise power of pilots
RSR6
2E
maxCarrier
RSR6
2E
pilotShift
27:20 Index of the subcarrier with the maximum power for the symbol
directly following a long preamble
31:28 Shift value used in calculating pilot error. <4.0> unsigned
RSR7
2F
pilotPower
20
19:0 Calculated pilot power per symbol. <10.10> signed
RSR8
30
berSeqNum
3:0
RSR8
30
ber
16
19:4 Bit Error Rate Indicates number of bit errors in the received packet
RSR8
30
rsSeqNum
23:20 Sequence number which caused rxRsUpdate interrupt
RSR8
30
rsError
31:24 Number of errors corrected by the Reed-Solomon decoder
RSR9
31
p64Sample
8:0
RSR9
31
p64Symbol
11
19:9 Symbol in frame time when first P64 was detected. <11.0>
unsigned
Synchronization search failed
Sequence number of the last command that updated the pilot status
registers (RSR5,RSR6) and caused rxPilotUpdate interrupt
Sequence number which caused the ber interrupt
Sample in frame time when first P64 was detected. <9.0> unsigned
Table 33: Receive Status Registers (RSR0-8) Description
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8.3 AFE Rx Interface, Rx FIFO, AGC & Decimation Filters

8.3.1
AFE Rx Interface & Rx FIFO
The AFE Rx interface provides the interface between the 10-bit I&Q data from the
ADCs and the AGC, Rx FIFO and Decimation filters. The control signals for the
ADCs i.e. adc_2s_cmp_sel, adc_out_en_n, adc_pd, bandgap_pd & vref_pd are set
through the MCR. The 10-bit in-phase and quadrature data, rx_I and rx_q, is fed directly
to the Rx FIFO where it is resynchronized to the phy_clk domain. After
resynchronization the I&Q data is sent directly to the AGC and then the decimation
filters.
fe_clk
Decimation
Filter
AGC
IADC
Rx FIFO
rx_i(9:0)
DO(9:0)
OMODE
OUTDIS
MCR
adc_2s_cmp_sel
adc_out_en_n
adc_pd
bandgap_pd
vref_pd
PDADC
PDBGR
PDVR
QADC
PDVR
PDBGR
PDADC
OUTDIS
OMODE
rx_q(9:0)
DO(9:0)
Figure 18: ADC Interface & Rx FIFO

The Rx FIFO resynchronizes the I&Q data from the variable fe_clk clock domain to the
100 MHz phy_clk clock domain.
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8.3.2
AGC
8.3.2.1 Overview
Relevant Control Words
Rx_cntl0
unlockAGC
the end of the burst Note, this function actually provided by the SYNC
circuit
Relevant Control Registers

RCR
agcLockTime
agcDelay
agcVal
agcOverrideEn
agc6BitSel
agcAvgSel
agcTableTestEn
agcOffset
Relevant Status Registers
RSR
attenuation
Value of the sync counter at which AGC is locked during a long preamble
search - <9.0> unsigned
Number of samples between AGC updates - <6.0> unsigned
AGC value to apply to AGC output - <8.0> unsigned
Overrides internally generated AGC output value and outputs agcVal above
Selects 6-bit mode for AGC operation, otherwise 8-bit mode. The
attenuation is incremented in 1 dB steps for 6-bit mode and 1/2 dB steps
for 8-bit mode. The msb and lsb of the AGC value are not used in 6-bit
mode so the range is reduced.
Sets the number of samples to average final agc value
00 no averaging
10 average2 samples
10 average 4 samples
11 reserved
Enables test mode where agc outputs attenuation table value.
AGC attenuation offset to apply after AGC lock - <8.0> signed.
Value of sync attenuation output
The AGC is implemented as a table based look up table and is designed to lock in on the
optimum gain during the long preamble sequence of the OFDM transmission. A system
level block diagram of the AGC is shown in Figure 19.
The AGC generates an internal 8/6-bit output, currentAtten which selects an attenuation
level for the I&Q input signals before the ADCs. The AGC output represents a range of
0 to 127 dB attenuation in dB steps in 8-bit mode and a range of 0 to 64 dB in 1 dB
steps in 6-bit mode. Note that in 6-bit mode, the msb and lsb of the 8-bit AGC output
word are set to 0 and should not be used. If the AGC value is less than zero, then it is set
to zero. If the internal AGC value is greater than 2ÂGC_BITS-1 then the AGC value is set
to 2ÂGC_BITS-1.
The internal 8-bit agc value is used to address an 256x10-bit agc translation RAM. This
RAM is used to translate the monotonic 8-bt agc value to a programmable 10-bit output
field. Each 8-bit AGC value is used address an individual memory location whose 10-bit
value is then read and place in a register to provide a 10-bit agc output. The use of a 10bit programmable output field allows the agc circuit to interface to different chipsets
which may have their gains distributed over several chips. Note that the agc translation
RAM is loaded through the preamble memory interface using the PMDR and PMCR
registers.
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fe_clk
AGC
IADC
Rx FIFO
rx_i(9:0)
MCR
DO(9:0)
rx_i
Attenuator
+ Filter
ADC
control
QADC
rx_q
rx_q(9:0)
Attenuator
+ Filter
DO(9:0)
agc_stb
currentAtten (7:0)
agcDelay
agcVal(7:0) RCR5
agcOverrideEn
agc6bitSel
AGC
Translation
Memory
agc(9:0)
SOC
Figure 19: AGC System Level Block Diagram
Operation of the AGC is as follows:
AGC is unlocked at reset and at the end of a rx burst when an Rx control word
command has the unlock bit set.
AGC is locked agcLockTime samples after the first successful synchronization
(P64_Hit) to to a the P64 preamble. The maximum value of agcLockTime is 128
with the typical value being 64 samples.
While the AGC is unlocked the average power, P32, over 32 fe_clk samples is
compared to the 10 attenuation compare values. The index of the maximum
compare value of which the P32 is greater is used to adjust the AGC value from a
list of 11 values of attenuation.
Each AGC iteration requires agcDelay fe_clk clock cycles. This consists of 32
fixed cycles for performing the average power calculation and an additional
number of cycles to account for additional delays in the system. . The additional
delay is used to account for the following:
o Attenuator setting time, att_time
o ADC pipeline delay, adc_delay
o Internal pipeline delays, int_delay
The total number of fe_clk clock cycles available for AGC updates (agc_cycles)
is dictated by the shortest possible OFDM symbol and is:
agc_cycles = 2((G)*256 + *(64 + agcLockTime ) + 19
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Note that G is the cyclic prefix ratio and the 19 additional clock cycles in the
equation is due to the delay through the decimation filter as the SYNC block
which controls the AGC circuit resides after the decimation filter. For a worst
case situation where agcLockTime = 64 and G= 1/32, agc_cycles = 291.
The total number of agc iterations, agc_iter, is dependent on agcDelay and on agc_cycles
which is the total number of cycles available as follows:
agc_iter = round(agc_cycles/agcDelay);
A reference calculation is given below for the current ASIC implementation under the
wrost case scenario i.e. minimum cyclic prefix ratio:
att_time = 4 clock cycles
adc_delay = 7 clock cycles
int_delay = 5 clock cycles
// Attenuator + Filter delay

// Delay due to ADC pipeline
// Delay due to Rx FIFO
agcDelay = 32 + 4 + 7 + 5 = 48
agc_iter = round(291/48) = 6
Therefore in the worst case a maximum of 6 agc iterations are possible.
A symbol timing diagram is provided in Figure 20 which shows the approximate timing
of the AGC estimation during the short preamble. In this case agcLockTime was set to
64.
AGC Locked
AGC Unlocked
CP
P64
P64_Hit
P64
P64
P64
CP
P128
P128
CP
Data 0
agcLockTime
Figure 20: AGC Timing

It is also possible to apply an offset to the output of the AGC. The agcOffset register in
RCR6 is an 8-bit signed offset which is applied to the output of the AGC after it has been
locked. The agc output is calculated as follows:
CurrentAtten = agc_int + agc_offset
Note that the agc output saturation to zero or 2ÂGC_BITS-1 occurs after the offset is added.
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Finally, it is also possible to provide an extra agc iteration which is the average of the last
0, 2 or 4 AGC outputs . This is controlled through the agcAvgSel bit in RCR5. For
instance if in normal operation (agcAvgSel =0) the agc operates with 7 iterations, in
averaging mode with agcAvgSel =1 (2 samples averaged) an 8th iteration is produced
whose value is the average of the last 2 outputs. This potentially provides a means of
smoothing the agc output in situations where variability in agc estimates is encountered.
8.3.2.2 AGC Algorithm Description
The algorithm utilized in the AGC circuit compares the power estimationvalue to a table
of power compare values. The power compare values in the phy are specified by writing
a series of registers as outlined in Table 34. Depending on the magnitude of the P16 value
compared to the power compare value (powerCompareVect), an attenuation estimate is
derived based on the previous attenuation estimate and the current power comparison
threshold . Note that the table of attenuation values (attenVect) is specified by writing
the AAR registers as described in Table 34 .
The basic AGC algorithm is outlined below:minAtten_ = 0;
maxAtten_ = (1<<AGC_BITS)-1;
if (AGC_LOCKED=0) {
if (P32 > powerCompareVect[0]) currentAtten_ += attenVect_[0];
else if (P32 > powerCompareVect [1]) currentAtten_ += attenVect_[1];
else currentAtten_ += attenVect_[10];
if (currentAtten_ < minAtten_)
currentAtten_ = minAtten_;
if (currentAtten_ > maxAtten_)
currentAtten_ = maxAtten_;
}
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if (AGC_LOCKED=1) && AGC_LOCKED_DEL == 0 {

AGC_LOCKED_DEL = 1;
If agc_avg == 0
currentAtten = currentAtten + agcOffset;
If agc_avg == 1
currentAtten = (currentAtten(0) + currentAtten (-1))/2 + agcOffset;
If agc_avg == 2
currentAtten = (currentAtten(0) + currentAtten (-1))/4 + agcOffset;
}
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
APCR0
42
R/W
apc0
16
15:0 AGC Power Compare Value 0 - <3.13> unsigned
APCR0
42
R/W
apc1
16
APCR1
43
R/W
apc2
16
APCR1
43
R/W
apc3
16
APCR2
44
R/W
apc4
16
APCR2
44
R/W
apc5
16
APCR3
45
R/W
apc6
16
APCR3
45
R/W
apc7
16
APCR4
46
R/W
apc8
16
APCR4
46
R/W
apc9
16
APCR5
47
R/W
apc10
16
APCR5
47
R/W
apc11
16
AAR0
48
R/W
aac0
7:0
AAR0
48
R/W
aac1
15:8 AGC Attenuator Value 1 - <8.0> signed
AAR0
48
R/W
aac2
AAR0
48
R/W
aac3
AAR1
49
R/W
aac4
7:0
AAR1
49
R/W
aac5
AAR1
49
R/W
aac6
AAR1
49
R/W
aac7
AAR2
4A
R/W
aac8
AAR2
4A
R/W
aac9
AAR2
4A
R/W
aac10
AAR2
4A
R/W
aac11
AAR3
4B
R/W
aac12
7:0
7:0
AGC Attenuator Value 0 - <8.0> signed
Table 34: AGC Power Compare (APCR0-4) and AGC Attenuatior (AAR0-2) Register
Descriptions
8.3.2.3 AGC External Timing
The agc block provides an external 8/6-bit output which is used to control external
attenuators or variable gain amplifiers. An additional strobe signal, agc_stb is provided
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which allows the agc value to be clocked into an external device. A timing diagram is
shown in Figure 33. The strobe signal is active high, comes one phy_clock cycle after
the agc output is valid and has a duration of 3 phy_clock cycles.
phy_clk
agc(7:0)
new agc value
new agc value
agc_stb
Figure 21: AGC External Timing Diagram
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8.3.3
Decimation Filter
The decimation filter is a 39-tap halfband filter with approximately 60 dB stopband

attenuation and 0.01 dB ripple. The passband corner lies at 0.42 Fs. The frequency
response is shown in Figure 22.
Magnitude Response (dB)
20
-20
-40
-60
)
B
d(
e
d
uti
n
g
a
M
-80
-100
-120
-140
-160
-180
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Frequency ( rad/sample)
0.7
0.8
0.9
Figure 22: Frequency Response of 39-tap Halfband Rx Decimation Filter
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8.4 Frequency Correction

rx_cntl1
clearTrack
Clears the timing and frequency tracking loops at the end of the burst. This
is needed for base station operation

RCR3
timeEn
RCR3
RCR3
RCR4
timeLoopA
timeLoopB
freqEn
RCR4
freqFactor
RCR4
pilotAmplitude
Enables timing tracking correction

0=disable
1=enalble
Loop filter A coefficient <2.6> signed
Loop filter B coefficient <2.6> signed
Enables frequency tracking correction
0=disable
1=enable
Pilot offset (time domain) to frequency offset conversion factor <3.5>
signed
Expected amplitude of pilot carriers that is used for the pilot error
calculation - <1.9> signed

RSR3
RSR3
RSR4
RSR4
8.4.1
phi64
mag64
phi128
mag128
Arctangent of Preamble 64 correlation. <3.12> signed

Magnitude of Preamble 64 correlation. <3.12> unsigned
Arctangent of Preamble 128 correlation. <3.12> signed
Magnitude of Preamble 128 correlation. <3.12> unsigned
Overview
The frequency correction block compensates for the remaining frequency offset error
after AFC correction using the external VCTCXO. A system block diagram of the
frequency correction block is shown in Figure 23. The pilot data from the demapper is
used to provide a phase error estimate to a timing loop filter by subtracting the actual
pilot amplitude from the expected pilot amplitude as specified by RCR4.pilotAmplitude.
The timing loop filter is a phase lock loop whose loop bandwidth is controlled by the
RCR3.timeLoopA,B parameters.
The timeLoopA,B parameters are calculated as
follows:
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Freq_Corr
ADC data
from AGC
Sync
Freq.
Correction
FFT
Tim_Corr
Ch_Est
Demapper
Coarse/fine
Freq. estimates
freqFactor
freqEn
phi64,
mag64
phi128,
mag128
Frequency Loop
Filter
Timing Loop
Filter
Phase Error
Estimation
Pilot data
pilotAmplitude
Cordic ATAN
timeEn
timeLoopA
timeLoopB
Figure 23: Freq_Corr Block Diagram
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8.5 Timing Recovery, Synchronization & AFC

rx_cntl0
preType
Rx_cntl2
searchWin
Rx_cntl0
unlockAGC
Receive Preamble Type - Long preamble signals a search for long

preamble will occur. Short preamble means a new channel estimate will be
caluclated, No preamble sends the data straight through
00 - No preamble
01 - Short preamble
10 - Long preamble (P64+(P128 or Psub))
11 - Reserved
Length of time in symbols from the start of the search before searchFailed
is asserted. Needed for contention slots
the end of the burst

RCR2
syncThresh
syncMinPwr
guard
Specifies the percentage of power that the matched filter has to achieve in
order to signal a synchronization hit <2.4> unsigned
Specifies the minimum power that the matched filter has to achieve in order
to signal a synchronization hit - <3.12> unsigned
Guard time inside of the cyclic prefix - <8.0> unsigned. Guard is the
number of samples of the CP which is included in the OFDM symbol sent
to the FFT

RSR1
syncSeqNum
RSR1
RSR1
RSR2
RSR9
RSR9
searchFailed
p128Time
power
p64Sample
p64Symbol
8.5.1
Sequence number of the last command that updated the sync status
registers (RSR1 - RSR4) and caused rxSyncDone interrupt
Synchronization search failed
Sync counter value of matched filter p128 hit <9.0> unsigned
Average power over 256 samples of Preamble 128. <3.26> unsigned
Sample in frame time when first P64 was detected. <9.0> unsigned
Symbol in frame time when first P64 was detected. <11.0> unsigned
Overview
Timing Recovery, synchronization and AFC are performed in the SYNC block.
Synchronization and timing recovery establishes the symbol timing in the phy. AFC
involves estimation of the frequency offset which is used to modify the frequency of an
external VCTCXO for coarse frequency adjustment and is used internally for frequency
correction.
The SYNC block consists of the following subblocks:
Timing Recovery State Machine
Matched Filter
Correlator
Power Calculator
A block diagram of the SYNC block is shown in Figure 24.
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Timing
Recovery
State
Machine
Data In
Compute
Correlations
Freq. Estimates
(to Freq. Corr.)
Data Out
FFT Control
AGC Control
Status Registers
Compute
Power
P64CR0-7
Matched
Filter
P128CR0-7
Control Registers
Control Word
Figure 24: SYNC Block Diagram

Input data from the Frequency Correction block is fed to the SYNC block which contains
the Timing Recovery State machine, Matched Filter, Correlator and Power Calculator
Blocks. The Matched Filter is used to search for the Preamble 64 and 128 sequences in
the long preamble. The matched filter coefficients are programmable through the
P64CR0-7 and P128Cr0-7 registers which are described in Table 35 through Table 38.
The initial search for synchronization is controlled through the rx_cntl0.preType and
rx_cntl0.searchWin fields in the receive control word.
Once a valid preamble has been detected the information is fed to the timing recovery
state machine. The state machine also uses additional information on the power of the
signal to determine whether a valid synchronization has been achieved. The Compute
Power block calculates the average power of the input signal over 16 and 256 samples.
This information in addition to the parameters RCR2.syncThresh and
RCR2.syncMinPower is used by the state machine to determine when a valid preamble
has been detected. The values of the syncThresh and syncMinPowerparameters in the
control registers are constants that are determined through system simulation. Further
details are provided in the phy programmermanual.
The RCR3.guard parameter provides the extra guard time in samples in the OFDM
symbol which is passed to the FFT. It is typically set to (cyclic prefix length)/4
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The timing recovery state machine processes the information from the Compute Power
and Matched Filter blocks and provides timing and synchronization control for the rest of
the receiver. Specifically, the control of the upstream AGC and downstream FFT blocks
is provided by this block. In addition, various status registers and interrupts are updated
under the control of this state machine. The approximate sequencing for the various
timing recovery and control functions provided by the SYNC block is shown in Figure 25
for a typical OFDM symbol.
Unlock
AGC
AGC FFT FFT

Lock Reset Reset
CP
Start of
Sync. Acq.
P64
P64
P64
P64
Coarse
Freq. Est.
CP
P128
P128
CP
Data0
Fine
Freq. Est.
Figure 25: Sequencing of Timing Recovery Operations in SYNC block

The SYNC block also contains a correlator which is used to provide the correlation
estimates between the two received P64 and P128 preambles in the long preamble
sequence. This correlation is used to provide an estimate of the frequency offset for AFC
and also provides feedback to the frequency and timing correction blocks where
frequency and timing correction occur. A coarse frequency estimate is provided from the
Frequency Correction block by RSR3.phi64 which is the arctangent of the P64 cross
correlation. A fine frequency estimate is provided from the Frequency Correction block
by RSR3.phi128 which is the arctangent of the P128 cross correlation.
In order to support initial ranging in the BS, the RSR9.p64Sample and RSR9.p64Symbol
status registers are provided. Initial ranging uses a UL burst with a long preamble in the
contention slot so the BS can calculate the amount of time delay in the channel between
the SS and BS. This information is then to the SS so that it can adjust its timing
accordingly.
8.5.2
P64 and P128 Matched Filter Coefficient Registers
A programmable matched filter is used in the detection of the P64 and P128 preamble
sequences. The coefficients of the filter are loaded through P64CR0-7 and P128CR0-7.
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
p64Coeff0
3:0
Description
P64CR0
32
R/W
P64CR0
32
R/W
Coefficient 0 of the Preamble 64 Matched filter
P64CR0
32
R/W
P64CR0
32
R/W
p64Coeff1
P64CR0
32
R/W
P64Coeff2
11:8 Coefficient 2 of the P64 Matched Filter
P64CR0
32
R/W
P64Coeff3
P64CR0
32
R/W
P64Coeff4
P64CR0
32
R/W
P64Coeff5
P64CR0
32
R/W
P64Coeff6
P64CR0
32
R/W
P64Coeff7
P64CR1
33
R/W
p64Coeff8
3:0
Coefficient 8 of the P64 Matched Filter
P64CR1
33
R/W
p64Coeff9
7:4
P64CR1
33
R/W
p64Coeff10
P64CR1
33
R/W
p64Coeff11
P64CR1
33
R/W
p64Coeff12
P64CR1
33
R/W
p64Coeff13
P64CR1
33
R/W
p64Coeff14
P64CR1
33
R/W
P64Coeff15
P64CR2
34
R/W
p64Coeff16
3:0
P64CR2
34
R/W
p64Coeff17
7:4
P64CR2
34
R/W
p64Coeff18
P64CR2
34
R/W
p64Coeff19
P64CR2
34
R/W
p64Coeff20
P64CR2
34
R/W
p64Coeff21
P64CR2
34
R/W
p64Coeff22
P64CR2
34
R/W
P64Coeff23
P64CR3
35
R/W
p64Coeff24
3:0
P64CR3
35
R/W
p64Coeff25
7:4
P64CR3
35
R/W
p64Coeff26
P64CR3
35
R/W
p64Coeff27
P64CR3
35
R/W
p64Coeff28
P64CR3
35
R/W
p64Coeff29
P64CR3
35
R/W
p64Coeff30
P64CR3
35
R/W
P64Coeff31
Bits 1:0 Real coefficient, +/- 1 or 0

Bits 3:2 Imag coefficient, +/-1 or 0
7:4
Table 35: Preamble 64 Coefficient Registers (P64CR0-3) Description
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
P64CR4
36
R/W
p64Coeff32
3:0
P64CR4
36
R/W
p64Coeff33
P64CR4
36
R/W
p64Coeff34
7:4
P64CR4
36
R/W
p64Coeff35
P64CR4
36
P64CR4
36
R/W
p64Coeff36
R/W
p64Coeff37
P64CR4
36
R/W
p64Coeff38
P64CR4
36
R/W
P64Coeff39
P64CR5
37
R/W
p64Coeff40
3:0
P64CR5
37
R/W
p64Coeff41
7:4
P64CR5
37
R/W
p64Coeff42
11:8
P64CR5
37
R/W
p64Coeff43
P64CR5
37
R/W
p64Coeff44
P64CR5
37
R/W
p64Coeff45
P64CR5
37
R/W
p64Coeff46
P64CR5
37
R/W
P64Coeff47
P64CR6
38
R/W
p64Coeff48
3:0
P64CR6
38
R/W
p64Coeff49
7:4
P64CR6
38
R/W
p64Coeff50
11:8
P64CR6
38
R/W
p64Coeff51
P64CR6
38
R/W
p64Coeff52
P64CR6
38
R/W
p64Coeff53
P64CR6
38
R/W
p64Coeff54
P64CR6
38
R/W
P64Coeff55
P64CR7
39
R/W
p64Coeff56
3:0
P64CR7
39
R/W
p64Coeff57
7:4
P64CR7
39
R/W
p64Coeff58
11:8
P64CR7
39
R/W
p64Coeff59
P64CR7
39
R/W
p64Coeff60
P64CR7
39
R/W
p64Coeff61
P64CR7
39
R/W
p64Coeff62
P64CR7
39
R/W
p64Coeff63
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
p128Coeff0
3:0
Description
P128CR0
3A
R/W
Coefficient 0 of the Preamble 128 Matched filter
P128CR0
3A
R/W
Bits 1:0 Real coefficient, +/- 1 or 0
P128CR0
3A
R/W
Bits 3:2 Imag coefficient, +/-1 or 0
P128CR0
3A
R/W
p128Coeff1
7:4
P128CR0
3A
R/W
P128Coeff2
P128CR0
3A
R/W
P128Coeff3
P128CR0
3A
R/W
P128Coeff4
P128CR0
3A
R/W
P128Coeff5
P128CR0
3A
R/W
P128Coeff6
P128CR0
3A
R/W
P128Coeff7
P128CR1
3B
R/W
p128Coeff8
P128CR1
3B
R/W
p128Coeff9
P128CR1
3B
R/W
p128Coeff10
P128CR1
3B
R/W
p128Coeff11
P128CR1
3B
R/W
p128Coeff12
P128CR1
3B
R/W
p128Coeff13
P128CR1
3B
R/W
p128Coeff14
P128CR1
3B
R/W
P128Coeff15
P128CR2
3C
R/W
p128Coeff16
P128CR2
3C
R/W
p128Coeff17
P128CR2
3C
R/W
p128Coeff18
P128CR2
3C
R/W
P128CR2
3C
P128CR2
3C
P128CR2
3C
R/W
p128Coeff22
P128CR2
3C
R/W
P128Coeff23
P128CR3
3D
R/W
p128Coeff24
3:0
P128CR3
3D
R/W
p128Coeff25
7:4
P128CR3
3D
R/W
p128Coeff26
P128CR3
3D
R/W
p128Coeff27
P128CR3
3D
R/W
p128Coeff28
P128CR3
3D
R/W
p128Coeff29
P128CR3
3D
R/W
p128Coeff30
P128CR3
3D
R/W
P128Coeff31
3:0
7:4
3:0
7:4
p128Coeff19
R/W
p128Coeff20
R/W
p128Coeff21
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
P128CR4
3E
R/W
p128Coeff32
3:0
P128CR4
3E
R/W
p128Coeff33
P128CR4
3E
R/W
p128Coeff34
7:4
P128CR4
3E
R/W
p128Coeff35
P128CR4
3E
P128CR4
3E
R/W
p128Coeff36
R/W
p128Coeff37
P128CR4
3E
R/W
p128Coeff38
P128CR4
3E
R/W
P128Coeff39
P128CR5
3F
R/W
p128Coeff40
3:0
P128CR5
3F
R/W
p128Coeff41
7:4
P128CR5
3F
R/W
p128Coeff42
11:8
P128CR5
3F
R/W
p128Coeff43
P128CR5
3F
R/W
p128Coeff44
P128CR5
3F
R/W
p128Coeff45
P128CR5
3F
R/W
p128Coeff46
P128CR5
3F
R/W
P128Coeff47
P128CR6
40
R/W
p128Coeff48
3:0
P128CR6
40
R/W
p128Coeff49
7:4
P128CR6
40
R/W
p128Coeff50
11:8
P128CR6
40
R/W
p128Coeff51
P128CR6
40
R/W
p128Coeff52
P128CR6
40
R/W
p128Coeff53
P128CR6
40
R/W
p128Coeff54
P128CR6
40
R/W
p128Coeff55
P128CR7
41
R/W
p128Coeff56
3:0
P128CR7
41
R/W
p128Coeff57
7:4
P128CR7
41
R/W
p128Coeff58
11:8
P128CR7
41
R/W
p128Coeff59
P128CR7
41
R/W
p128Coeff60
P128CR7
41
R/W
p128Coeff61
P128CR7
41
R/W
p128Coeff62
P128CR7
41
R/W
p128Coeff63
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8.6 FFT
RCR0
fftScale
fftScalePre
Selects number of scaling shifts to be performed in the FFT on the receive

data. Expected range is from 0 to 8.
Selects number of scaling shifts to be performed in the FFT on the receive
preamble . Expected range is from 0 to 8.
8.7 Timing Correction

RCR3
timeFactor
Frequency offset (freqency domain) to timing offset conversion factor

<2.10> signed
Timing correction compensates for the remaining timing offset error after AFC
correction. The algorithm operates on a per-sample basis, using freq as a reference base.
The incoming samples are rotated based on the received OFDM symbol count and the
subcarrier index. The block diagram of the timing correction block is shown in Figure
26.
FFT data
R(k)
Cordic
Rotator
freq
Ktime factor
Timing Offset
Compensated Data
Subcarrier Index (-128:127)

x
Figure 26: Timing Correction Block Diagram
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8.8 Channel Estimator

RCR0
chnInterpEn
Enables interpolation between even carriers in the channel estimation
The channel estimator uses apriori knowledge of what the transmitted preamble is to
create an estimate of the channel. The channel estimator algorithm consists of two parts,
an initial estimation based on the received preamble, and a filtering (interpolation)
computation to fill in subcarriers that do not have any transmitted power. The channel
estimate is only performed for transmitted subcarriers, these are the subcarriers in the
range 100 to 100.
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8.9
Channel Decoder
8.9.1
Block Description
The main sub-blocks of the channel decoder are shown below in Figure 27.
De-Interleaver /
De-Puncturer
Demapper
Viterbi
Decoder
RS
Decoder
Descrambler
Figure 27: Channel Decoder Sub-blocks

8.9.1.1 Demapper Sub-block
RCR1
demapScale
demapK64
demapK16
Demapper soft bit scaling factor - <3.3> unsigned value which is used for
prescaling the soft bits.
Demapper slicing point for QAM64 - <1.9> signed
Demapper slicing point for QAM16 - <1.9> signed
The demapper block is responsible for channel compensation and soft data generation.
The soft data are generated using a Log Likelihood Ratio (LLR) algorithm. The
functional block diagram of the demapper sub-block is show in Figure 28. Note that the
actual implementation of the demapper integrates several functional blocks into one
algorithm which optimizes hardware usage.
Input Data
Channel Estimate
Channel Power
Rotation
Compensated
Scaling
Data
Slicer
Quantizer
Soft Data Values
<<
demapScale
demapK64,K16
Figure 28: Demapper Sub-Block

The functional steps of the demapper block are as follows:
1) The input data is de-rotated by the channel estimate to form compensated data.
2) The channel power is computed.
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3) The compensated data is sliced using the constellation selected by the modulation
rate. The channel power is used in the slicing operation to produce log likelihood
ratio soft value data.
4) A left shift based on the scale input using saturation is performed.
5) A bit-reduction quantization using rounding is performed to reduce the soft values
from the shifter to the specified softbit precision.
6) The soft data values of softbit width are passed to the de-interleaver for further
processing.
Field Name
Register Value
(Decimal quantized)
demapScale
demapK64
demapK16
1.5
0.1640625
0.16796875
Table 39: Typical Demap Scale Values

8.9.1.2 De-Interleaver / De-Puncturer Sub-block
This block de-interleaves and de-punctures the incoming soft data values from the
demapper according to the IEEE 802.16 specification. This block produces two soft data
values of softbits width.
Soft Data
Code
Rate
Bit X
De-Interleaver
De-Puncturer
Bit Y
Figure 29: De-Interleaver / De-Puncturer Sub-block

8.9.1.3 Viterbi Decoder Sub-block
The Viterbi sub-block performs a Viterbi decoding operation on the incoming soft data
values according to the 802.16 generator polynomials, with g0 = 1338, g1 = 1718, and rate
R = 1/2. This block accepts two soft data values of width softbits from the preceding deinterleaver / de-puncturer block and produces an output data bitstream.
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Bit A
Bit B
Bit Output
Viterbi
Decoder
BER
Figure 30: Viterbi Sub-block

The Viterbi decoder requires an init signal at the start of a packet. At the end a packet a
flush signal is required in order to flush the remaining data bits out of the decoder. These
signals are provided by the decoder control sub-block.
8.9.1.4 Reed Solomon Decoder Sub-block

The Reed-Solomon decoder is an error correcting decoder optimized for
RS(N=255,K=239) and corrects up to T = (N-K)/2 = 8 symbol errors. The complete code
is formed from the K data symbols and the (N-K) parity symbols. Symbols sizes equal to
8-bits are supported.
The field and generator polynomials supported are as follows:
Code Generator Polynomial: g(x) = (x + 0) (x + 1) (x + 2) (x + 2T-1), =02HEX
Field Generator Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
These polynomials are specified by the IEEE 802.16 standard.
The decoder supports the shortened codes specified in Table 21 as per the 802.16
specifications.
8.9.1.5 Descrambler Sub-block

The descrambler sub-block is responsible for descrambling of the data bits received from
the Viterbi decoder.
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BIT_IN
BIT_OUT
Descrambler
BIT_VALID
BIT_OUT_VALID
Figure 31: Descrambler Sub-block
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8.10 Receive Test Circuitry

The receiver has several test circuits to enable lab debugging. The circuits are as follows:
Receive I&Q Averaging circuit- used to provide averages of the incoming I&Q
Data
Symbol Error Display (SED) output of the estimated channel magnitude and
phase through an interface to a serial DAC
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8.10.1 Receive I&Q Averaging

The receive averaging functions are controlled through the Receive Averaging Control
Register (RACR) as shown inTable 40.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
rxAvgEn
Description
RACR
4C
R/W
RACR
4C
R/W
Enable averaging of the samples from the I & Q ADCs
RACR
4C
R/W
RACR
4C
rxAvgClr
Clears the I&Q averages when set to 1. The bit is automatically set
to 0 after the clear operation
RACR
4C
R/W
rxSamples
4:2
The exponent value used to calculate the number of samples over

which the I&Q averages should be calculated.
RACR
4C
R/W
0 Disable
1 - Enable
Total number of samples = 2^rxSamples
Table 40: Receive AveragingControl Register (RACR) Description

The Receive I&Q averaging circuit provides a non-overlapping or boxcar average of the
incoming I&Q data samples. The averaging is performed continuously on each set of
2rxSamples input words. The output of the averaging circuit is provided in the RAVGR
register for I samples, rxAvgI, and Q samples, rxAvgQ.
Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
Description
RAVGR
4D
rxAvgQ
16
15:0 Average of samples from the Q ADC
RAVGR
4D
rxAvgI
16
31:16 Average of samples from the I ADC
Table 41: Receive I&Q Averaging Register (RAVGR) Description

8.10.2 Symbol Error Display (SED)
SED provides the ability for real-time monitoring of the estimated channel magnitude and
phase. The SED functions are controlled through the SED control register (SEDR) as
shown in .
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Register Addr
Name
(hex) R/W
Field
# of
Name
Bits Slice
sedEn
SEDR
4E
R/W
SEDR
4E
R/W
0 = disabled
SEDR
4E
R/W
1 = enabled
SEDR
4E
R/W
SEDR
4E
R/W
00 = phy_clk/2
SEDR
4E
R/W
01 = phy_clk/4
SEDR
4E
R/W
10 = phy_clk/6
SEDR
4E
R/W
11 = phy_clk/8
SEDR
4E
R/W
ctrlField
6:3
SEDR
4E
R/W
overrideEn
SEDR
4E
R/W
SEDR
4E
R/W
SEDR
4E
R/W
clkSel
Description
2:1
Enables output signals for the symbol error display
Selects clock to be used for the SED.
Value to output in the control field of the serial output.

Enables overrideData to be output on the symbol error display
0 = output receiver data
1 = output testData
overrideData
12
19:8 Data to be output when overrideEn is active.
Figure 32: SED Register (SEDR)

The magnitude and phase information is fed to a serial DAC through a three wire serial
interface as shown in Figure 33. This interface is compatible with a TI TLV5616 12-bit
serial DAC. The three wire interface consists of the following signals:
sed_clk
sed_data
phy_clk/2,4, 6 or 8
Serial data, 16-bits per sample consisting of 4 control bits and 12
data bits
Frame synchronization signal for serial data
sed_fs
The 4-bit control field is provided by SEDR.ctrlField and this corresponds to the 4 msbs
(D15:12) of the serial output. Depending on the mode of operation the 12-bit data field is
provided either by the magnitude/phase estimate output circuitry or through
SEDR.overrideData The SED output is enabled through SEDR.sedEn and the override
mode is controlled by SEDR.overrideEn.
sed_clk
sed_data
D15
D14
D13,..,D2
D1
D0
XX
D0
D1
D13,..,D2
D1
D0
XX
D15
D14
sed_fs
Figure 33: SED Timing Diagram
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The format of the magnitude and phase output is shown in Figure 34. When the SED
function is enabled by setting SEDR.sedEn = 1 a repeating output of the magnitude and
phase estimate for the current burst is generated. The magnitude and phase fields are
comprised of 201 samples which corresponds to the 201 frequency carriers. The most
negative frequency carrier is sent out first in time. Each pair of magnitude and phase
fields is delineated by a maximum positive full-scale then a maximum negative full-scale
pulse. Magnitude information is normalized to a 40 dB range with 0 dB being set to midrail and 20 dB being set to the half negative full-scale rail. The magnitude/phase output
boundary is delineated by half-scale negative pulse followed by a half-scale negative
pulse. Phase information is normalized to a +/- 180 degree range over half the full-scale
range with 0 degrees corresponding to the mid-rail.
half positive
full-scale
180 deg,
20 dB
max positive
full-scale
Channel Magnitude
Channel Magnitude -repeated
0 deg,
0 dB
-20 dB
max negative
full-scal
Channel Phase
-180 deg,
half negative
full-scale
Figure 34: SED Channel Estimate Magnitude & Phase Timing Diagram
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Appendix A: Preamble Memory Coefficients

Preamble 64 Coefficients:
P64Real = {
0, 0, 0, 0, -1,
-1, 0, 0, 0, -1,
-1, 0, 0, 0, 1,
-1, 0, 0, 0, -1,
-1, 0, 0, 0, 1,
-1, 0, 0, 0, -1,
-1, 0, 0, 0, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
1, 0, 0, 0, 1,
1, 0, 0, 0, 1,
-1, 0, 0, 0, 1,
1, 0, 0, 0, -1,
1, 0, 0, 0, -1,
-1, 0, 0, 0, -1,
};
P64Imag = {
0, 0, 0, 0, -1,
-1, 0, 0, 0, 1,
1, 0, 0, 0, -1,
1, 0, 0, 0, -1,
-1, 0, 0, 0, -1,
1, 0, 0, 0, 1,
1, 0, 0, 0, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
1, 0, 0, 0, 1,
1, 0, 0, 0, 1,
1, 0, 0, 0, 1,
-1, 0, 0, 0, 1,
-1, 0, 0, 0, -1,
1, 0, 0, 0, 1,
};
REV 1.13
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, -1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, -1, 0, 0, 0,
0, -1, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, -1, 0, 0, 0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, 1, 0, 0, 0,
0, 1, 0, 0, 0, -1, 0, 0, 0,
0, 1, 0, 0, 0, -1, 0, 0, 0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0, -1,
0, -1,
0, -1,
0, 1,
0, 1,
0, -1,
0, 0,
0, 0,
0, 0,
0, 0,
0, -1,
0, 1,
0, 1,
0, -1,
0, 1,
0, 1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0, 1, 0, 0, 0,
0, 1, 0, 0, 0,
0, 1, 0, 0, 0,
0, -1, 0, 0, 0,
0, -1, 0, 0, 0,
0, -1, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 1, 0, 0, 0,
0, 1, 0, 0, 0,
0, -1, 0, 0, 0,
0, 1, 0, 0, 0,
0, -1, 0, 0, 0,
0, 1, 0, 0, 0,
0, -1, 0, 0, 0,

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Preamble 128 Coefficients:

P128Real = {
0, 0, 1, 0, -1, 0, 1, 0, 1, 0, 1, 0, 1, 0, -1, 0,
-1, 0, 1, 0, -1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
-1, 0, 1, 0, 1, 0, -1, 0, -1, 0, -1, 0, 1, 0, -1, 0,
-1, 0, -1, 0, -1, 0, 1, 0, 1, 0, -1, 0, 1, 0, 1, 0,
-1, 0, 1, 0, 1, 0, 1, 0, 1, 0, -1, 0, -1, 0, 1, 0,
-1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, 1, 0, -1, 0,
-1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, -1, 0,
1, 0, -1, 0, 1, 0, 1, 0, 1, 0, -1, 0, -1, 0, 1, 0,
1, 0, -1, 0, 1, 0, -1, 0, 1, 0, 1, 0, 1, 0, -1, 0,
-1, 0, 1, 0, 1, 0, -1, 0, 1, 0, -1, 0, 1, 0, 1, 0,
1, 0, -1, 0, -1, 0, 1, 0, 1, 0, 1, 0, 1, 0, -1, 0,
1, 0, -1, 0, -1, 0, 1, 0, 1, 0, 1, 0, -1, 0, -1, 0,
-1, 0, 1, 0, -1, 0, 1, 0, 1, 0, -1, 0, -1, 0, -1, 0,
};
P128Imag = {
0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, -1, 0, 1, 0,
1, 0, -1, 0, -1, 0, -1, 0, 1, 0, -1, 0, -1, 0, -1, 0,
-1, 0, 1, 0, 1, 0, -1, 0, 1, 0, -1, 0, -1, 0, -1, 0,
-1, 0, -1, 0, 1, 0, -1, 0, -1, 0, 1, 0, 1, 0, 1, 0,
1, 0, 1, 0, 1, 0, 1, 0, -1, 0, 1, 0, 1, 0, -1, 0,
-1, 0, 1, 0, -1, 0, 1, 0, 1, 0, 1, 0, 1, 0, -1, 0,
-1, 0, 1, 0, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 0, -1, 0,
-1, 0, 1, 0, -1, 0, 1, 0, 1, 0, -1, 0, -1, 0, -1, 0,
-1, 0, -1, 0, -1, 0, 1, 0, -1, 0, 1, 0, 1, 0, -1, 0,
-1, 0, -1, 0, -1, 0, -1, 0, -1, 0, 1, 0, -1, 0, 1, 0,
1, 0, -1, 0, -1, 0, -1, 0, 1, 0, -1, 0, 1, 0, -1, 0,
1, 0, 1, 0, 1, 0, -1, 0, -1, 0, 1, 0, -1, 0, 1, 0,
-1, 0, 1, 0, -1, 0, -1, 0, -1, 0, 1, 0, 1, 0, -1, 0,
};
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Preamble Subchannel Coefficients:

PSubReal = {
0, 1, 1,-1, 1,-1, 1, 1, 1,-1,-1, 1,-1, 1, 1, 1,
1, 1,-1,-1, 1, 1, 1,-1, 1, 1,-1,-1, 1,-1, 1,-1,
-1,-1, 1, 1,-1, 1, 1,-1,-1,-1,-1, 1, 1,-1,-1,-1,
1,-1,-1,-1,-1, 1,-1, 1,-1,-1,-1, 1, 1,-1, 1,-1,
1, 1, 1, 1,-1,-1, 1, 1, 1,-1, 1, 1, 1, 1,-1, 1,
-1, 1, 1, 1,-1,-1, 1,-1,-1,-1,-1,-1,-1, 1, 1,-1,
-1,-1, 1,-1,-1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1,-1, 1,-1, 1, 1, 1,-1,-1, 1,-1, 1, 1, 1, 1,
1,-1,-1, 1, 1, 1,-1, 1, 1, 1, 1,-1, 1,-1, 1, 1,
1,-1,-1, 1,-1,-1, 1, 1, 1, 1,-1,-1, 1, 1, 1,-1,
1, 1, 1, 1,-1, 1,-1, 1, 1, 1,-1,-1, 1,-1, 1,-1,
-1,-1,-1, 1, 1,-1,-1,-1, 1,-1,-1, 1, 1,-1, 1,-1,
1, 1, 1,-1,-1, 1,-1, 1,-1,-1,-1,-1, 1, 1,-1,-1,
-1, 1, -1, -1
};
PSubImag = {
0, 1, 1,-1, 1, 1, 1, 1, 1,-1,-1,-1,-1,-1, 1,-1,
1, 1,-1,-1, 1,-1, 1,-1, 1, 1,-1,-1, 1,-1,-1,-1,
-1,-1, 1, 1, 1, 1,-1,-1, 1,-1,-1, 1, 1,-1, 1,-1,
1,-1,-1,-1,-1, 1,-1,-1,-1,-1,-1, 1, 1, 1, 1, 1,
1,-1, 1, 1,-1,-1, 1,-1, 1,-1, 1, 1, 1, 1,-1, 1,
1, 1, 1, 1,-1,-1,-1,-1,-1,-1, 1,-1,-1, 1, 1,-1,
1,-1, 1,-1,-1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1,-1, 1, 1, 1, 1, 1,-1,-1,-1,-1,-1, 1,-1, 1,
1,-1,-1, 1,-1, 1,-1, 1, 1, 1, 1,-1, 1, 1, 1, 1,
1,-1,-1,-1,-1,-1, 1,-1, 1, 1,-1,-1, 1,-1, 1,-1,
1, 1, 1, 1,-1, 1, 1, 1, 1, 1,-1,-1,-1,-1,-1,-1,
1,-1,-1, 1, 1,-1, 1,-1, 1,-1,-1, 1, 1,-1, 1, 1,
1, 1, 1,-1,-1,-1,-1,-1,-1, 1,-1,-1, 1, 1,-1, 1,
-1, 1,-1,-1
};Appendix B: Transmit Interpolation Filter Coefficients
Coefficient
C19
C18,C20
C17,C21
REV 1.13
Normalized
Integer
0.5
0.316376
0
16384
10367
0

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C16,C22
C15,C23
C14,C24
C13,C25
C12,C26
C11,C27
C10,C28
C9,C29
C8,C30
C7,C31
C6,C32
C5,C33
C4,C34
C3,C35
C2,C36
C1,C37
C0,C38
REV 1.13
-0.1001
0
0.054199
0
-0.03296
0
0.020538
0
-0.0127
0
0.008324
0
-0.00391
0
0.001831
0
-0.00061
-3280
0
1776
0
-1080
0
673
0
-416
0
240
0
-128
0
60
0
-20

1/7/05
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802.16 OFDM Phy

802.16 OFDM Phy Technical Description

RESTRICTED PROPRIETARY INFORMATION

802.16 OFDM Phy Technical Description

802.16 OFDM Phy Technical Description

802.16 OFDM Phy Technical Description

802.16 OFDM Phy Technical Description

Fixed-point numbers are specified as follows:

802.16 OFDM Phy Technical Description

Rx Front End: Rx_FE

Figure 1: WMAN_PHY System Block Diagram

802.16 OFDM Phy Technical Description

The WMAN_PHY will support the following features:

Table 1: IEEE 802.16 Modulation Modes

802.16 OFDM Phy Technical Description

Table 2: Max Data Rates for Supported Channel Bandwidths

Assumes R=5/6 for coding rate at Viterbi decoder

802.16 OFDM Phy Technical Description

Note that a Downlink subframe consists of a single Downlink PDU

See section 8.3.4.1 of 802.16Revd-D2

802.16 OFDM Phy Technical Description

802.16 OFDM Phy Technical Description

4 Top Level Interface Description

ARC Clock (160 MHz)

Lock Detect active high

Lock Detect active low

Table 3: WMAN_PHY Top Level Interface

802.16 OFDM Phy Technical Description

4.2 802.16 SOC System Block Diagram

802.16 OFDM Phy Technical Description

Figure 2: 802.16 SOC System Block Diagram

802.16 OFDM Phy Technical Description

4.3 Register Description

FIFO Control Register

FIFO Status Register

Interrupt Enable Register

Interrupt Status Register

Interrupt Information Register

Interrupt Clear Register

Frame Timer Control Register

Frame Timer Status Register

Frame Timer Interrupt 0

Frame Timer Interrupt 1

Frame Timer Interrupt 2

Frame Timer Interrupt 3

Frame Timer Interrupt 4

Frame Timer Interrupt 5

Miscellaneous Control Register

Delay Timer Control Register 0

Delay Timer Control Register 1

Preamble Memory Control Register

Preamble Memory Data Register

Preamble Memory Status Register

Transmit Control Register 0

Transmit Control Register 1

Transmit Status Register

Transmit Modulation Register 0

Transmit Modulation Register 1

Transmit Modulation Register 2

Transmit Test Register

Table 4: WMAN_PHY Register Description: 0x00 - 0x1F

802.16 OFDM Phy Technical Description

Transmit DAC Register